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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/socket.h> | |
12 | #include <linux/in.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
8ceee660 BH |
14 | #include <linux/ip.h> |
15 | #include <linux/tcp.h> | |
16 | #include <linux/udp.h> | |
70c71606 | 17 | #include <linux/prefetch.h> |
6eb07caf | 18 | #include <linux/moduleparam.h> |
8ceee660 BH |
19 | #include <net/ip.h> |
20 | #include <net/checksum.h> | |
21 | #include "net_driver.h" | |
8ceee660 | 22 | #include "efx.h" |
744093c9 | 23 | #include "nic.h" |
3273c2e8 | 24 | #include "selftest.h" |
8ceee660 BH |
25 | #include "workarounds.h" |
26 | ||
27 | /* Number of RX descriptors pushed at once. */ | |
28 | #define EFX_RX_BATCH 8 | |
29 | ||
62b330ba SH |
30 | /* Maximum size of a buffer sharing a page */ |
31 | #define EFX_RX_HALF_PAGE ((PAGE_SIZE >> 1) - sizeof(struct efx_rx_page_state)) | |
32 | ||
8ceee660 BH |
33 | /* Size of buffer allocated for skb header area. */ |
34 | #define EFX_SKB_HEADERS 64u | |
35 | ||
36 | /* | |
37 | * rx_alloc_method - RX buffer allocation method | |
38 | * | |
39 | * This driver supports two methods for allocating and using RX buffers: | |
40 | * each RX buffer may be backed by an skb or by an order-n page. | |
41 | * | |
4afb7527 | 42 | * When GRO is in use then the second method has a lower overhead, |
8ceee660 BH |
43 | * since we don't have to allocate then free skbs on reassembled frames. |
44 | * | |
45 | * Values: | |
46 | * - RX_ALLOC_METHOD_AUTO = 0 | |
47 | * - RX_ALLOC_METHOD_SKB = 1 | |
48 | * - RX_ALLOC_METHOD_PAGE = 2 | |
49 | * | |
50 | * The heuristic for %RX_ALLOC_METHOD_AUTO is a simple hysteresis count | |
51 | * controlled by the parameters below. | |
52 | * | |
53 | * - Since pushing and popping descriptors are separated by the rx_queue | |
54 | * size, so the watermarks should be ~rxd_size. | |
4afb7527 | 55 | * - The performance win by using page-based allocation for GRO is less |
56 | * than the performance hit of using page-based allocation of non-GRO, | |
8ceee660 BH |
57 | * so the watermarks should reflect this. |
58 | * | |
59 | * Per channel we maintain a single variable, updated by each channel: | |
60 | * | |
4afb7527 | 61 | * rx_alloc_level += (gro_performed ? RX_ALLOC_FACTOR_GRO : |
8ceee660 BH |
62 | * RX_ALLOC_FACTOR_SKB) |
63 | * Per NAPI poll interval, we constrain rx_alloc_level to 0..MAX (which | |
64 | * limits the hysteresis), and update the allocation strategy: | |
65 | * | |
4afb7527 | 66 | * rx_alloc_method = (rx_alloc_level > RX_ALLOC_LEVEL_GRO ? |
8ceee660 BH |
67 | * RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB) |
68 | */ | |
c3c63365 | 69 | static int rx_alloc_method = RX_ALLOC_METHOD_AUTO; |
8ceee660 | 70 | |
4afb7527 | 71 | #define RX_ALLOC_LEVEL_GRO 0x2000 |
8ceee660 | 72 | #define RX_ALLOC_LEVEL_MAX 0x3000 |
4afb7527 | 73 | #define RX_ALLOC_FACTOR_GRO 1 |
8ceee660 BH |
74 | #define RX_ALLOC_FACTOR_SKB (-2) |
75 | ||
76 | /* This is the percentage fill level below which new RX descriptors | |
77 | * will be added to the RX descriptor ring. | |
78 | */ | |
79 | static unsigned int rx_refill_threshold = 90; | |
80 | ||
81 | /* This is the percentage fill level to which an RX queue will be refilled | |
82 | * when the "RX refill threshold" is reached. | |
83 | */ | |
84 | static unsigned int rx_refill_limit = 95; | |
85 | ||
86 | /* | |
87 | * RX maximum head room required. | |
88 | * | |
89 | * This must be at least 1 to prevent overflow and at least 2 to allow | |
62b330ba | 90 | * pipelined receives. |
8ceee660 | 91 | */ |
62b330ba | 92 | #define EFX_RXD_HEAD_ROOM 2 |
8ceee660 | 93 | |
a526f140 SH |
94 | /* Offset of ethernet header within page */ |
95 | static inline unsigned int efx_rx_buf_offset(struct efx_nic *efx, | |
96 | struct efx_rx_buffer *buf) | |
55668611 BH |
97 | { |
98 | /* Offset is always within one page, so we don't need to consider | |
99 | * the page order. | |
100 | */ | |
06e63c57 | 101 | return ((unsigned int) buf->dma_addr & (PAGE_SIZE - 1)) + |
0beaca2c | 102 | efx->type->rx_buffer_hash_size; |
55668611 BH |
103 | } |
104 | static inline unsigned int efx_rx_buf_size(struct efx_nic *efx) | |
105 | { | |
106 | return PAGE_SIZE << efx->rx_buffer_order; | |
107 | } | |
8ceee660 | 108 | |
a526f140 | 109 | static u8 *efx_rx_buf_eh(struct efx_nic *efx, struct efx_rx_buffer *buf) |
39c9cf07 | 110 | { |
db339569 | 111 | if (buf->flags & EFX_RX_BUF_PAGE) |
a526f140 SH |
112 | return page_address(buf->u.page) + efx_rx_buf_offset(efx, buf); |
113 | else | |
0beaca2c | 114 | return (u8 *)buf->u.skb->data + efx->type->rx_buffer_hash_size; |
a526f140 SH |
115 | } |
116 | ||
117 | static inline u32 efx_rx_buf_hash(const u8 *eh) | |
118 | { | |
119 | /* The ethernet header is always directly after any hash. */ | |
39c9cf07 | 120 | #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) || NET_IP_ALIGN % 4 == 0 |
a526f140 | 121 | return __le32_to_cpup((const __le32 *)(eh - 4)); |
39c9cf07 | 122 | #else |
a526f140 | 123 | const u8 *data = eh - 4; |
0beaca2c BH |
124 | return (u32)data[0] | |
125 | (u32)data[1] << 8 | | |
126 | (u32)data[2] << 16 | | |
127 | (u32)data[3] << 24; | |
39c9cf07 BH |
128 | #endif |
129 | } | |
130 | ||
8ceee660 | 131 | /** |
f7d6f379 | 132 | * efx_init_rx_buffers_skb - create EFX_RX_BATCH skb-based RX buffers |
8ceee660 BH |
133 | * |
134 | * @rx_queue: Efx RX queue | |
8ceee660 | 135 | * |
f7d6f379 SH |
136 | * This allocates EFX_RX_BATCH skbs, maps them for DMA, and populates a |
137 | * struct efx_rx_buffer for each one. Return a negative error code or 0 | |
138 | * on success. May fail having only inserted fewer than EFX_RX_BATCH | |
139 | * buffers. | |
8ceee660 | 140 | */ |
f7d6f379 | 141 | static int efx_init_rx_buffers_skb(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
142 | { |
143 | struct efx_nic *efx = rx_queue->efx; | |
144 | struct net_device *net_dev = efx->net_dev; | |
f7d6f379 | 145 | struct efx_rx_buffer *rx_buf; |
8ba5366a | 146 | struct sk_buff *skb; |
8ceee660 | 147 | int skb_len = efx->rx_buffer_len; |
f7d6f379 | 148 | unsigned index, count; |
8ceee660 | 149 | |
f7d6f379 | 150 | for (count = 0; count < EFX_RX_BATCH; ++count) { |
ecc910f5 | 151 | index = rx_queue->added_count & rx_queue->ptr_mask; |
f7d6f379 | 152 | rx_buf = efx_rx_buffer(rx_queue, index); |
8ceee660 | 153 | |
8ba5366a SH |
154 | rx_buf->u.skb = skb = netdev_alloc_skb(net_dev, skb_len); |
155 | if (unlikely(!skb)) | |
f7d6f379 | 156 | return -ENOMEM; |
8ceee660 | 157 | |
ff3bc1e7 | 158 | /* Adjust the SKB for padding */ |
8ba5366a | 159 | skb_reserve(skb, NET_IP_ALIGN); |
f7d6f379 | 160 | rx_buf->len = skb_len - NET_IP_ALIGN; |
db339569 | 161 | rx_buf->flags = 0; |
f7d6f379 SH |
162 | |
163 | rx_buf->dma_addr = pci_map_single(efx->pci_dev, | |
a526f140 | 164 | skb->data, rx_buf->len, |
f7d6f379 SH |
165 | PCI_DMA_FROMDEVICE); |
166 | if (unlikely(pci_dma_mapping_error(efx->pci_dev, | |
167 | rx_buf->dma_addr))) { | |
8ba5366a SH |
168 | dev_kfree_skb_any(skb); |
169 | rx_buf->u.skb = NULL; | |
f7d6f379 SH |
170 | return -EIO; |
171 | } | |
8ceee660 | 172 | |
f7d6f379 SH |
173 | ++rx_queue->added_count; |
174 | ++rx_queue->alloc_skb_count; | |
8ceee660 BH |
175 | } |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | /** | |
f7d6f379 | 181 | * efx_init_rx_buffers_page - create EFX_RX_BATCH page-based RX buffers |
8ceee660 BH |
182 | * |
183 | * @rx_queue: Efx RX queue | |
8ceee660 | 184 | * |
f7d6f379 SH |
185 | * This allocates memory for EFX_RX_BATCH receive buffers, maps them for DMA, |
186 | * and populates struct efx_rx_buffers for each one. Return a negative error | |
187 | * code or 0 on success. If a single page can be split between two buffers, | |
188 | * then the page will either be inserted fully, or not at at all. | |
8ceee660 | 189 | */ |
f7d6f379 | 190 | static int efx_init_rx_buffers_page(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
191 | { |
192 | struct efx_nic *efx = rx_queue->efx; | |
f7d6f379 SH |
193 | struct efx_rx_buffer *rx_buf; |
194 | struct page *page; | |
62b330ba SH |
195 | void *page_addr; |
196 | struct efx_rx_page_state *state; | |
f7d6f379 SH |
197 | dma_addr_t dma_addr; |
198 | unsigned index, count; | |
199 | ||
200 | /* We can split a page between two buffers */ | |
201 | BUILD_BUG_ON(EFX_RX_BATCH & 1); | |
202 | ||
203 | for (count = 0; count < EFX_RX_BATCH; ++count) { | |
204 | page = alloc_pages(__GFP_COLD | __GFP_COMP | GFP_ATOMIC, | |
205 | efx->rx_buffer_order); | |
206 | if (unlikely(page == NULL)) | |
8ceee660 | 207 | return -ENOMEM; |
f7d6f379 SH |
208 | dma_addr = pci_map_page(efx->pci_dev, page, 0, |
209 | efx_rx_buf_size(efx), | |
8ceee660 | 210 | PCI_DMA_FROMDEVICE); |
8d8bb39b | 211 | if (unlikely(pci_dma_mapping_error(efx->pci_dev, dma_addr))) { |
f7d6f379 | 212 | __free_pages(page, efx->rx_buffer_order); |
8ceee660 BH |
213 | return -EIO; |
214 | } | |
62b330ba SH |
215 | page_addr = page_address(page); |
216 | state = page_addr; | |
217 | state->refcnt = 0; | |
218 | state->dma_addr = dma_addr; | |
219 | ||
220 | page_addr += sizeof(struct efx_rx_page_state); | |
221 | dma_addr += sizeof(struct efx_rx_page_state); | |
f7d6f379 SH |
222 | |
223 | split: | |
ecc910f5 | 224 | index = rx_queue->added_count & rx_queue->ptr_mask; |
f7d6f379 | 225 | rx_buf = efx_rx_buffer(rx_queue, index); |
62b330ba | 226 | rx_buf->dma_addr = dma_addr + EFX_PAGE_IP_ALIGN; |
8ba5366a | 227 | rx_buf->u.page = page; |
f7d6f379 | 228 | rx_buf->len = efx->rx_buffer_len - EFX_PAGE_IP_ALIGN; |
db339569 | 229 | rx_buf->flags = EFX_RX_BUF_PAGE; |
f7d6f379 SH |
230 | ++rx_queue->added_count; |
231 | ++rx_queue->alloc_page_count; | |
62b330ba | 232 | ++state->refcnt; |
f7d6f379 | 233 | |
62b330ba | 234 | if ((~count & 1) && (efx->rx_buffer_len <= EFX_RX_HALF_PAGE)) { |
f7d6f379 SH |
235 | /* Use the second half of the page */ |
236 | get_page(page); | |
237 | dma_addr += (PAGE_SIZE >> 1); | |
238 | page_addr += (PAGE_SIZE >> 1); | |
239 | ++count; | |
240 | goto split; | |
8ceee660 BH |
241 | } |
242 | } | |
243 | ||
8ceee660 BH |
244 | return 0; |
245 | } | |
246 | ||
4d566063 BH |
247 | static void efx_unmap_rx_buffer(struct efx_nic *efx, |
248 | struct efx_rx_buffer *rx_buf) | |
8ceee660 | 249 | { |
db339569 | 250 | if ((rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.page) { |
62b330ba SH |
251 | struct efx_rx_page_state *state; |
252 | ||
8ba5366a | 253 | state = page_address(rx_buf->u.page); |
62b330ba | 254 | if (--state->refcnt == 0) { |
f7d6f379 | 255 | pci_unmap_page(efx->pci_dev, |
62b330ba | 256 | state->dma_addr, |
55668611 BH |
257 | efx_rx_buf_size(efx), |
258 | PCI_DMA_FROMDEVICE); | |
8ceee660 | 259 | } |
db339569 | 260 | } else if (!(rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.skb) { |
8ceee660 BH |
261 | pci_unmap_single(efx->pci_dev, rx_buf->dma_addr, |
262 | rx_buf->len, PCI_DMA_FROMDEVICE); | |
263 | } | |
264 | } | |
265 | ||
4d566063 BH |
266 | static void efx_free_rx_buffer(struct efx_nic *efx, |
267 | struct efx_rx_buffer *rx_buf) | |
8ceee660 | 268 | { |
db339569 | 269 | if ((rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.page) { |
8ba5366a SH |
270 | __free_pages(rx_buf->u.page, efx->rx_buffer_order); |
271 | rx_buf->u.page = NULL; | |
db339569 | 272 | } else if (!(rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.skb) { |
8ba5366a SH |
273 | dev_kfree_skb_any(rx_buf->u.skb); |
274 | rx_buf->u.skb = NULL; | |
8ceee660 BH |
275 | } |
276 | } | |
277 | ||
4d566063 BH |
278 | static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue, |
279 | struct efx_rx_buffer *rx_buf) | |
8ceee660 BH |
280 | { |
281 | efx_unmap_rx_buffer(rx_queue->efx, rx_buf); | |
282 | efx_free_rx_buffer(rx_queue->efx, rx_buf); | |
283 | } | |
284 | ||
24455800 SH |
285 | /* Attempt to resurrect the other receive buffer that used to share this page, |
286 | * which had previously been passed up to the kernel and freed. */ | |
287 | static void efx_resurrect_rx_buffer(struct efx_rx_queue *rx_queue, | |
288 | struct efx_rx_buffer *rx_buf) | |
289 | { | |
8ba5366a | 290 | struct efx_rx_page_state *state = page_address(rx_buf->u.page); |
24455800 | 291 | struct efx_rx_buffer *new_buf; |
62b330ba SH |
292 | unsigned fill_level, index; |
293 | ||
294 | /* +1 because efx_rx_packet() incremented removed_count. +1 because | |
295 | * we'd like to insert an additional descriptor whilst leaving | |
296 | * EFX_RXD_HEAD_ROOM for the non-recycle path */ | |
297 | fill_level = (rx_queue->added_count - rx_queue->removed_count + 2); | |
ecc910f5 | 298 | if (unlikely(fill_level > rx_queue->max_fill)) { |
62b330ba SH |
299 | /* We could place "state" on a list, and drain the list in |
300 | * efx_fast_push_rx_descriptors(). For now, this will do. */ | |
301 | return; | |
302 | } | |
24455800 | 303 | |
62b330ba | 304 | ++state->refcnt; |
8ba5366a | 305 | get_page(rx_buf->u.page); |
24455800 | 306 | |
ecc910f5 | 307 | index = rx_queue->added_count & rx_queue->ptr_mask; |
24455800 | 308 | new_buf = efx_rx_buffer(rx_queue, index); |
62b330ba | 309 | new_buf->dma_addr = rx_buf->dma_addr ^ (PAGE_SIZE >> 1); |
8ba5366a | 310 | new_buf->u.page = rx_buf->u.page; |
24455800 | 311 | new_buf->len = rx_buf->len; |
db339569 | 312 | new_buf->flags = EFX_RX_BUF_PAGE; |
24455800 SH |
313 | ++rx_queue->added_count; |
314 | } | |
315 | ||
316 | /* Recycle the given rx buffer directly back into the rx_queue. There is | |
317 | * always room to add this buffer, because we've just popped a buffer. */ | |
318 | static void efx_recycle_rx_buffer(struct efx_channel *channel, | |
319 | struct efx_rx_buffer *rx_buf) | |
320 | { | |
321 | struct efx_nic *efx = channel->efx; | |
f7d12cdc | 322 | struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel); |
24455800 SH |
323 | struct efx_rx_buffer *new_buf; |
324 | unsigned index; | |
325 | ||
db339569 BH |
326 | rx_buf->flags &= EFX_RX_BUF_PAGE; |
327 | ||
328 | if ((rx_buf->flags & EFX_RX_BUF_PAGE) && | |
329 | efx->rx_buffer_len <= EFX_RX_HALF_PAGE && | |
8ba5366a | 330 | page_count(rx_buf->u.page) == 1) |
62b330ba | 331 | efx_resurrect_rx_buffer(rx_queue, rx_buf); |
24455800 | 332 | |
ecc910f5 | 333 | index = rx_queue->added_count & rx_queue->ptr_mask; |
24455800 SH |
334 | new_buf = efx_rx_buffer(rx_queue, index); |
335 | ||
336 | memcpy(new_buf, rx_buf, sizeof(*new_buf)); | |
8ba5366a | 337 | rx_buf->u.page = NULL; |
24455800 SH |
338 | ++rx_queue->added_count; |
339 | } | |
340 | ||
8ceee660 BH |
341 | /** |
342 | * efx_fast_push_rx_descriptors - push new RX descriptors quickly | |
343 | * @rx_queue: RX descriptor queue | |
8ceee660 BH |
344 | * This will aim to fill the RX descriptor queue up to |
345 | * @rx_queue->@fast_fill_limit. If there is insufficient atomic | |
90d683af SH |
346 | * memory to do so, a slow fill will be scheduled. |
347 | * | |
348 | * The caller must provide serialisation (none is used here). In practise, | |
349 | * this means this function must run from the NAPI handler, or be called | |
350 | * when NAPI is disabled. | |
8ceee660 | 351 | */ |
90d683af | 352 | void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue) |
8ceee660 | 353 | { |
ba1e8a35 | 354 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); |
f7d6f379 SH |
355 | unsigned fill_level; |
356 | int space, rc = 0; | |
8ceee660 | 357 | |
90d683af | 358 | /* Calculate current fill level, and exit if we don't need to fill */ |
8ceee660 | 359 | fill_level = (rx_queue->added_count - rx_queue->removed_count); |
ecc910f5 | 360 | EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries); |
8ceee660 | 361 | if (fill_level >= rx_queue->fast_fill_trigger) |
24455800 | 362 | goto out; |
8ceee660 BH |
363 | |
364 | /* Record minimum fill level */ | |
b3475645 | 365 | if (unlikely(fill_level < rx_queue->min_fill)) { |
8ceee660 BH |
366 | if (fill_level) |
367 | rx_queue->min_fill = fill_level; | |
b3475645 | 368 | } |
8ceee660 | 369 | |
8ceee660 BH |
370 | space = rx_queue->fast_fill_limit - fill_level; |
371 | if (space < EFX_RX_BATCH) | |
24455800 | 372 | goto out; |
8ceee660 | 373 | |
62776d03 BH |
374 | netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev, |
375 | "RX queue %d fast-filling descriptor ring from" | |
376 | " level %d to level %d using %s allocation\n", | |
ba1e8a35 BH |
377 | efx_rx_queue_index(rx_queue), fill_level, |
378 | rx_queue->fast_fill_limit, | |
62776d03 | 379 | channel->rx_alloc_push_pages ? "page" : "skb"); |
8ceee660 BH |
380 | |
381 | do { | |
f7d6f379 SH |
382 | if (channel->rx_alloc_push_pages) |
383 | rc = efx_init_rx_buffers_page(rx_queue); | |
384 | else | |
385 | rc = efx_init_rx_buffers_skb(rx_queue); | |
386 | if (unlikely(rc)) { | |
387 | /* Ensure that we don't leave the rx queue empty */ | |
388 | if (rx_queue->added_count == rx_queue->removed_count) | |
389 | efx_schedule_slow_fill(rx_queue); | |
390 | goto out; | |
8ceee660 BH |
391 | } |
392 | } while ((space -= EFX_RX_BATCH) >= EFX_RX_BATCH); | |
393 | ||
62776d03 BH |
394 | netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev, |
395 | "RX queue %d fast-filled descriptor ring " | |
ba1e8a35 | 396 | "to level %d\n", efx_rx_queue_index(rx_queue), |
62776d03 | 397 | rx_queue->added_count - rx_queue->removed_count); |
8ceee660 BH |
398 | |
399 | out: | |
24455800 SH |
400 | if (rx_queue->notified_count != rx_queue->added_count) |
401 | efx_nic_notify_rx_desc(rx_queue); | |
8ceee660 BH |
402 | } |
403 | ||
90d683af | 404 | void efx_rx_slow_fill(unsigned long context) |
8ceee660 | 405 | { |
90d683af | 406 | struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context; |
8ceee660 | 407 | |
90d683af | 408 | /* Post an event to cause NAPI to run and refill the queue */ |
2ae75dac | 409 | efx_nic_generate_fill_event(rx_queue); |
8ceee660 | 410 | ++rx_queue->slow_fill_count; |
8ceee660 BH |
411 | } |
412 | ||
4d566063 BH |
413 | static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue, |
414 | struct efx_rx_buffer *rx_buf, | |
db339569 | 415 | int len, bool *leak_packet) |
8ceee660 BH |
416 | { |
417 | struct efx_nic *efx = rx_queue->efx; | |
418 | unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding; | |
419 | ||
420 | if (likely(len <= max_len)) | |
421 | return; | |
422 | ||
423 | /* The packet must be discarded, but this is only a fatal error | |
424 | * if the caller indicated it was | |
425 | */ | |
db339569 | 426 | rx_buf->flags |= EFX_RX_PKT_DISCARD; |
8ceee660 BH |
427 | |
428 | if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) { | |
62776d03 BH |
429 | if (net_ratelimit()) |
430 | netif_err(efx, rx_err, efx->net_dev, | |
431 | " RX queue %d seriously overlength " | |
432 | "RX event (0x%x > 0x%x+0x%x). Leaking\n", | |
ba1e8a35 | 433 | efx_rx_queue_index(rx_queue), len, max_len, |
62776d03 | 434 | efx->type->rx_buffer_padding); |
8ceee660 BH |
435 | /* If this buffer was skb-allocated, then the meta |
436 | * data at the end of the skb will be trashed. So | |
437 | * we have no choice but to leak the fragment. | |
438 | */ | |
db339569 | 439 | *leak_packet = !(rx_buf->flags & EFX_RX_BUF_PAGE); |
8ceee660 BH |
440 | efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY); |
441 | } else { | |
62776d03 BH |
442 | if (net_ratelimit()) |
443 | netif_err(efx, rx_err, efx->net_dev, | |
444 | " RX queue %d overlength RX event " | |
445 | "(0x%x > 0x%x)\n", | |
ba1e8a35 | 446 | efx_rx_queue_index(rx_queue), len, max_len); |
8ceee660 BH |
447 | } |
448 | ||
ba1e8a35 | 449 | efx_rx_queue_channel(rx_queue)->n_rx_overlength++; |
8ceee660 BH |
450 | } |
451 | ||
61321d92 BH |
452 | /* Pass a received packet up through GRO. GRO can handle pages |
453 | * regardless of checksum state and skbs with a good checksum. | |
8ceee660 | 454 | */ |
4afb7527 | 455 | static void efx_rx_packet_gro(struct efx_channel *channel, |
345056af | 456 | struct efx_rx_buffer *rx_buf, |
db339569 | 457 | const u8 *eh) |
8ceee660 | 458 | { |
da3bc071 | 459 | struct napi_struct *napi = &channel->napi_str; |
18e1d2be | 460 | gro_result_t gro_result; |
8ceee660 | 461 | |
db339569 | 462 | if (rx_buf->flags & EFX_RX_BUF_PAGE) { |
39c9cf07 | 463 | struct efx_nic *efx = channel->efx; |
8ba5366a | 464 | struct page *page = rx_buf->u.page; |
1241e951 | 465 | struct sk_buff *skb; |
8ceee660 | 466 | |
8ba5366a | 467 | rx_buf->u.page = NULL; |
1241e951 BH |
468 | |
469 | skb = napi_get_frags(napi); | |
76620aaf | 470 | if (!skb) { |
1241e951 BH |
471 | put_page(page); |
472 | return; | |
76620aaf HX |
473 | } |
474 | ||
39c9cf07 | 475 | if (efx->net_dev->features & NETIF_F_RXHASH) |
a526f140 | 476 | skb->rxhash = efx_rx_buf_hash(eh); |
39c9cf07 | 477 | |
70350b06 BH |
478 | skb_fill_page_desc(skb, 0, page, |
479 | efx_rx_buf_offset(efx, rx_buf), rx_buf->len); | |
76620aaf HX |
480 | |
481 | skb->len = rx_buf->len; | |
482 | skb->data_len = rx_buf->len; | |
483 | skb->truesize += rx_buf->len; | |
db339569 BH |
484 | skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ? |
485 | CHECKSUM_UNNECESSARY : CHECKSUM_NONE); | |
8ceee660 | 486 | |
3eadb7b0 BH |
487 | skb_record_rx_queue(skb, channel->channel); |
488 | ||
18e1d2be | 489 | gro_result = napi_gro_frags(napi); |
8ceee660 | 490 | } else { |
8ba5366a | 491 | struct sk_buff *skb = rx_buf->u.skb; |
8ceee660 | 492 | |
db339569 | 493 | EFX_BUG_ON_PARANOID(!(rx_buf->flags & EFX_RX_PKT_CSUMMED)); |
8ba5366a | 494 | rx_buf->u.skb = NULL; |
ff3bc1e7 | 495 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1241e951 BH |
496 | |
497 | gro_result = napi_gro_receive(napi, skb); | |
8ceee660 | 498 | } |
18e1d2be BH |
499 | |
500 | if (gro_result == GRO_NORMAL) { | |
501 | channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB; | |
502 | } else if (gro_result != GRO_DROP) { | |
4afb7527 | 503 | channel->rx_alloc_level += RX_ALLOC_FACTOR_GRO; |
18e1d2be BH |
504 | channel->irq_mod_score += 2; |
505 | } | |
8ceee660 BH |
506 | } |
507 | ||
8ceee660 | 508 | void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index, |
db339569 | 509 | unsigned int len, u16 flags) |
8ceee660 BH |
510 | { |
511 | struct efx_nic *efx = rx_queue->efx; | |
ba1e8a35 | 512 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); |
8ceee660 | 513 | struct efx_rx_buffer *rx_buf; |
dc8cfa55 | 514 | bool leak_packet = false; |
8ceee660 BH |
515 | |
516 | rx_buf = efx_rx_buffer(rx_queue, index); | |
db339569 | 517 | rx_buf->flags |= flags; |
8ceee660 BH |
518 | |
519 | /* This allows the refill path to post another buffer. | |
520 | * EFX_RXD_HEAD_ROOM ensures that the slot we are using | |
521 | * isn't overwritten yet. | |
522 | */ | |
523 | rx_queue->removed_count++; | |
524 | ||
525 | /* Validate the length encoded in the event vs the descriptor pushed */ | |
db339569 | 526 | efx_rx_packet__check_len(rx_queue, rx_buf, len, &leak_packet); |
8ceee660 | 527 | |
62776d03 BH |
528 | netif_vdbg(efx, rx_status, efx->net_dev, |
529 | "RX queue %d received id %x at %llx+%x %s%s\n", | |
ba1e8a35 | 530 | efx_rx_queue_index(rx_queue), index, |
62776d03 | 531 | (unsigned long long)rx_buf->dma_addr, len, |
db339569 BH |
532 | (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "", |
533 | (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : ""); | |
8ceee660 BH |
534 | |
535 | /* Discard packet, if instructed to do so */ | |
db339569 | 536 | if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) { |
8ceee660 | 537 | if (unlikely(leak_packet)) |
24455800 | 538 | channel->n_skbuff_leaks++; |
8ceee660 | 539 | else |
24455800 SH |
540 | efx_recycle_rx_buffer(channel, rx_buf); |
541 | ||
542 | /* Don't hold off the previous receive */ | |
543 | rx_buf = NULL; | |
544 | goto out; | |
8ceee660 BH |
545 | } |
546 | ||
547 | /* Release card resources - assumes all RX buffers consumed in-order | |
548 | * per RX queue | |
549 | */ | |
550 | efx_unmap_rx_buffer(efx, rx_buf); | |
551 | ||
552 | /* Prefetch nice and early so data will (hopefully) be in cache by | |
553 | * the time we look at it. | |
554 | */ | |
a526f140 | 555 | prefetch(efx_rx_buf_eh(efx, rx_buf)); |
8ceee660 BH |
556 | |
557 | /* Pipeline receives so that we give time for packet headers to be | |
558 | * prefetched into cache. | |
559 | */ | |
a526f140 | 560 | rx_buf->len = len - efx->type->rx_buffer_hash_size; |
24455800 | 561 | out: |
ba1e8a35 | 562 | if (channel->rx_pkt) |
db339569 | 563 | __efx_rx_packet(channel, channel->rx_pkt); |
ba1e8a35 | 564 | channel->rx_pkt = rx_buf; |
8ceee660 BH |
565 | } |
566 | ||
1ddceb4c BH |
567 | static void efx_rx_deliver(struct efx_channel *channel, |
568 | struct efx_rx_buffer *rx_buf) | |
569 | { | |
570 | struct sk_buff *skb; | |
571 | ||
572 | /* We now own the SKB */ | |
573 | skb = rx_buf->u.skb; | |
574 | rx_buf->u.skb = NULL; | |
575 | ||
576 | /* Set the SKB flags */ | |
577 | skb_checksum_none_assert(skb); | |
578 | ||
579 | /* Pass the packet up */ | |
580 | netif_receive_skb(skb); | |
581 | ||
582 | /* Update allocation strategy method */ | |
583 | channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB; | |
584 | } | |
585 | ||
8ceee660 | 586 | /* Handle a received packet. Second half: Touches packet payload. */ |
db339569 | 587 | void __efx_rx_packet(struct efx_channel *channel, struct efx_rx_buffer *rx_buf) |
8ceee660 BH |
588 | { |
589 | struct efx_nic *efx = channel->efx; | |
a526f140 | 590 | u8 *eh = efx_rx_buf_eh(efx, rx_buf); |
604f6049 | 591 | |
3273c2e8 BH |
592 | /* If we're in loopback test, then pass the packet directly to the |
593 | * loopback layer, and free the rx_buf here | |
594 | */ | |
595 | if (unlikely(efx->loopback_selftest)) { | |
a526f140 | 596 | efx_loopback_rx_packet(efx, eh, rx_buf->len); |
3273c2e8 | 597 | efx_free_rx_buffer(efx, rx_buf); |
d96d7dc9 | 598 | return; |
3273c2e8 BH |
599 | } |
600 | ||
db339569 | 601 | if (!(rx_buf->flags & EFX_RX_BUF_PAGE)) { |
1ddceb4c | 602 | struct sk_buff *skb = rx_buf->u.skb; |
8ba5366a SH |
603 | |
604 | prefetch(skb_shinfo(skb)); | |
8ceee660 | 605 | |
8ba5366a SH |
606 | skb_reserve(skb, efx->type->rx_buffer_hash_size); |
607 | skb_put(skb, rx_buf->len); | |
8ceee660 | 608 | |
39c9cf07 | 609 | if (efx->net_dev->features & NETIF_F_RXHASH) |
a526f140 | 610 | skb->rxhash = efx_rx_buf_hash(eh); |
39c9cf07 | 611 | |
8ceee660 BH |
612 | /* Move past the ethernet header. rx_buf->data still points |
613 | * at the ethernet header */ | |
8ba5366a | 614 | skb->protocol = eth_type_trans(skb, efx->net_dev); |
3eadb7b0 | 615 | |
8ba5366a | 616 | skb_record_rx_queue(skb, channel->channel); |
8ceee660 BH |
617 | } |
618 | ||
abfe9039 | 619 | if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM))) |
db339569 | 620 | rx_buf->flags &= ~EFX_RX_PKT_CSUMMED; |
ab3cf6d0 | 621 | |
db339569 BH |
622 | if (likely(rx_buf->flags & (EFX_RX_BUF_PAGE | EFX_RX_PKT_CSUMMED))) |
623 | efx_rx_packet_gro(channel, rx_buf, eh); | |
1ddceb4c BH |
624 | else |
625 | efx_rx_deliver(channel, rx_buf); | |
8ceee660 BH |
626 | } |
627 | ||
628 | void efx_rx_strategy(struct efx_channel *channel) | |
629 | { | |
630 | enum efx_rx_alloc_method method = rx_alloc_method; | |
631 | ||
4afb7527 | 632 | /* Only makes sense to use page based allocation if GRO is enabled */ |
da3bc071 | 633 | if (!(channel->efx->net_dev->features & NETIF_F_GRO)) { |
8ceee660 BH |
634 | method = RX_ALLOC_METHOD_SKB; |
635 | } else if (method == RX_ALLOC_METHOD_AUTO) { | |
636 | /* Constrain the rx_alloc_level */ | |
637 | if (channel->rx_alloc_level < 0) | |
638 | channel->rx_alloc_level = 0; | |
639 | else if (channel->rx_alloc_level > RX_ALLOC_LEVEL_MAX) | |
640 | channel->rx_alloc_level = RX_ALLOC_LEVEL_MAX; | |
641 | ||
642 | /* Decide on the allocation method */ | |
4afb7527 | 643 | method = ((channel->rx_alloc_level > RX_ALLOC_LEVEL_GRO) ? |
8ceee660 BH |
644 | RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB); |
645 | } | |
646 | ||
647 | /* Push the option */ | |
648 | channel->rx_alloc_push_pages = (method == RX_ALLOC_METHOD_PAGE); | |
649 | } | |
650 | ||
651 | int efx_probe_rx_queue(struct efx_rx_queue *rx_queue) | |
652 | { | |
653 | struct efx_nic *efx = rx_queue->efx; | |
ecc910f5 | 654 | unsigned int entries; |
8ceee660 BH |
655 | int rc; |
656 | ||
ecc910f5 SH |
657 | /* Create the smallest power-of-two aligned ring */ |
658 | entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE); | |
659 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
660 | rx_queue->ptr_mask = entries - 1; | |
661 | ||
62776d03 | 662 | netif_dbg(efx, probe, efx->net_dev, |
ecc910f5 SH |
663 | "creating RX queue %d size %#x mask %#x\n", |
664 | efx_rx_queue_index(rx_queue), efx->rxq_entries, | |
665 | rx_queue->ptr_mask); | |
8ceee660 BH |
666 | |
667 | /* Allocate RX buffers */ | |
c2e4e25a | 668 | rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer), |
ecc910f5 | 669 | GFP_KERNEL); |
8831da7b BH |
670 | if (!rx_queue->buffer) |
671 | return -ENOMEM; | |
8ceee660 | 672 | |
152b6a62 | 673 | rc = efx_nic_probe_rx(rx_queue); |
8831da7b BH |
674 | if (rc) { |
675 | kfree(rx_queue->buffer); | |
676 | rx_queue->buffer = NULL; | |
677 | } | |
8ceee660 BH |
678 | return rc; |
679 | } | |
680 | ||
bc3c90a2 | 681 | void efx_init_rx_queue(struct efx_rx_queue *rx_queue) |
8ceee660 | 682 | { |
ecc910f5 | 683 | struct efx_nic *efx = rx_queue->efx; |
8ceee660 BH |
684 | unsigned int max_fill, trigger, limit; |
685 | ||
62776d03 | 686 | netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev, |
ba1e8a35 | 687 | "initialising RX queue %d\n", efx_rx_queue_index(rx_queue)); |
8ceee660 BH |
688 | |
689 | /* Initialise ptr fields */ | |
690 | rx_queue->added_count = 0; | |
691 | rx_queue->notified_count = 0; | |
692 | rx_queue->removed_count = 0; | |
693 | rx_queue->min_fill = -1U; | |
8ceee660 BH |
694 | |
695 | /* Initialise limit fields */ | |
ecc910f5 | 696 | max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM; |
8ceee660 BH |
697 | trigger = max_fill * min(rx_refill_threshold, 100U) / 100U; |
698 | limit = max_fill * min(rx_refill_limit, 100U) / 100U; | |
699 | ||
700 | rx_queue->max_fill = max_fill; | |
701 | rx_queue->fast_fill_trigger = trigger; | |
702 | rx_queue->fast_fill_limit = limit; | |
703 | ||
704 | /* Set up RX descriptor ring */ | |
9f2cb71c | 705 | rx_queue->enabled = true; |
152b6a62 | 706 | efx_nic_init_rx(rx_queue); |
8ceee660 BH |
707 | } |
708 | ||
709 | void efx_fini_rx_queue(struct efx_rx_queue *rx_queue) | |
710 | { | |
711 | int i; | |
712 | struct efx_rx_buffer *rx_buf; | |
713 | ||
62776d03 | 714 | netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev, |
ba1e8a35 | 715 | "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue)); |
8ceee660 | 716 | |
9f2cb71c BH |
717 | /* A flush failure might have left rx_queue->enabled */ |
718 | rx_queue->enabled = false; | |
719 | ||
90d683af | 720 | del_timer_sync(&rx_queue->slow_fill); |
152b6a62 | 721 | efx_nic_fini_rx(rx_queue); |
8ceee660 BH |
722 | |
723 | /* Release RX buffers NB start at index 0 not current HW ptr */ | |
724 | if (rx_queue->buffer) { | |
ecc910f5 | 725 | for (i = 0; i <= rx_queue->ptr_mask; i++) { |
8ceee660 BH |
726 | rx_buf = efx_rx_buffer(rx_queue, i); |
727 | efx_fini_rx_buffer(rx_queue, rx_buf); | |
728 | } | |
729 | } | |
8ceee660 BH |
730 | } |
731 | ||
732 | void efx_remove_rx_queue(struct efx_rx_queue *rx_queue) | |
733 | { | |
62776d03 | 734 | netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev, |
ba1e8a35 | 735 | "destroying RX queue %d\n", efx_rx_queue_index(rx_queue)); |
8ceee660 | 736 | |
152b6a62 | 737 | efx_nic_remove_rx(rx_queue); |
8ceee660 BH |
738 | |
739 | kfree(rx_queue->buffer); | |
740 | rx_queue->buffer = NULL; | |
8ceee660 BH |
741 | } |
742 | ||
8ceee660 BH |
743 | |
744 | module_param(rx_alloc_method, int, 0644); | |
745 | MODULE_PARM_DESC(rx_alloc_method, "Allocation method used for RX buffers"); | |
746 | ||
747 | module_param(rx_refill_threshold, uint, 0444); | |
748 | MODULE_PARM_DESC(rx_refill_threshold, | |
749 | "RX descriptor ring fast/slow fill threshold (%)"); | |
750 |