sfc: Make initial fill of RX descriptors synchronous
[deliverable/linux.git] / drivers / net / ethernet / sfc / rx.c
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2005-2013 Solarflare Communications Inc.
8ceee660
BH
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/socket.h>
12#include <linux/in.h>
5a0e3ad6 13#include <linux/slab.h>
8ceee660 14#include <linux/ip.h>
c47b2d9d 15#include <linux/ipv6.h>
8ceee660
BH
16#include <linux/tcp.h>
17#include <linux/udp.h>
70c71606 18#include <linux/prefetch.h>
6eb07caf 19#include <linux/moduleparam.h>
2768935a 20#include <linux/iommu.h>
8ceee660
BH
21#include <net/ip.h>
22#include <net/checksum.h>
23#include "net_driver.h"
8ceee660 24#include "efx.h"
add72477 25#include "filter.h"
744093c9 26#include "nic.h"
3273c2e8 27#include "selftest.h"
8ceee660
BH
28#include "workarounds.h"
29
1648a23f
DP
30/* Preferred number of descriptors to fill at once */
31#define EFX_RX_PREFERRED_BATCH 8U
8ceee660 32
2768935a
DP
33/* Number of RX buffers to recycle pages for. When creating the RX page recycle
34 * ring, this number is divided by the number of buffers per page to calculate
35 * the number of pages to store in the RX page recycle ring.
36 */
37#define EFX_RECYCLE_RING_SIZE_IOMMU 4096
1648a23f 38#define EFX_RECYCLE_RING_SIZE_NOIOMMU (2 * EFX_RX_PREFERRED_BATCH)
62b330ba 39
8ceee660 40/* Size of buffer allocated for skb header area. */
d4ef5b6f 41#define EFX_SKB_HEADERS 128u
8ceee660 42
8ceee660
BH
43/* This is the percentage fill level below which new RX descriptors
44 * will be added to the RX descriptor ring.
45 */
64235187 46static unsigned int rx_refill_threshold;
8ceee660 47
85740cdf
BH
48/* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
49#define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \
50 EFX_RX_USR_BUF_SIZE)
51
8ceee660
BH
52/*
53 * RX maximum head room required.
54 *
85740cdf
BH
55 * This must be at least 1 to prevent overflow, plus one packet-worth
56 * to allow pipelined receives.
8ceee660 57 */
85740cdf 58#define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
8ceee660 59
b184f16b 60static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf)
39c9cf07 61{
b184f16b 62 return page_address(buf->page) + buf->page_offset;
a526f140
SH
63}
64
43a3739d 65static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh)
a526f140 66{
43a3739d
JC
67#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
68 return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset));
39c9cf07 69#else
43a3739d 70 const u8 *data = eh + efx->rx_packet_hash_offset;
0beaca2c
BH
71 return (u32)data[0] |
72 (u32)data[1] << 8 |
73 (u32)data[2] << 16 |
74 (u32)data[3] << 24;
39c9cf07
BH
75#endif
76}
77
85740cdf
BH
78static inline struct efx_rx_buffer *
79efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
80{
81 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
82 return efx_rx_buffer(rx_queue, 0);
83 else
84 return rx_buf + 1;
85}
86
2768935a
DP
87static inline void efx_sync_rx_buffer(struct efx_nic *efx,
88 struct efx_rx_buffer *rx_buf,
89 unsigned int len)
90{
91 dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len,
92 DMA_FROM_DEVICE);
93}
94
1648a23f
DP
95void efx_rx_config_page_split(struct efx_nic *efx)
96{
2ec03014 97 efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align,
950c54df 98 EFX_RX_BUF_ALIGNMENT);
1648a23f
DP
99 efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
100 ((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
101 efx->rx_page_buf_step);
102 efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
103 efx->rx_bufs_per_page;
104 efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
105 efx->rx_bufs_per_page);
106}
107
2768935a
DP
108/* Check the RX page recycle ring for a page that can be reused. */
109static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
110{
111 struct efx_nic *efx = rx_queue->efx;
112 struct page *page;
113 struct efx_rx_page_state *state;
114 unsigned index;
115
116 index = rx_queue->page_remove & rx_queue->page_ptr_mask;
117 page = rx_queue->page_ring[index];
118 if (page == NULL)
119 return NULL;
120
121 rx_queue->page_ring[index] = NULL;
122 /* page_remove cannot exceed page_add. */
123 if (rx_queue->page_remove != rx_queue->page_add)
124 ++rx_queue->page_remove;
125
126 /* If page_count is 1 then we hold the only reference to this page. */
127 if (page_count(page) == 1) {
128 ++rx_queue->page_recycle_count;
129 return page;
130 } else {
131 state = page_address(page);
132 dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
133 PAGE_SIZE << efx->rx_buffer_order,
134 DMA_FROM_DEVICE);
135 put_page(page);
136 ++rx_queue->page_recycle_failed;
137 }
138
139 return NULL;
140}
141
8ceee660 142/**
97d48a10 143 * efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
8ceee660
BH
144 *
145 * @rx_queue: Efx RX queue
8ceee660 146 *
1648a23f
DP
147 * This allocates a batch of pages, maps them for DMA, and populates
148 * struct efx_rx_buffers for each one. Return a negative error code or
149 * 0 on success. If a single page can be used for multiple buffers,
150 * then the page will either be inserted fully, or not at all.
8ceee660 151 */
cce28794 152static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic)
8ceee660
BH
153{
154 struct efx_nic *efx = rx_queue->efx;
f7d6f379
SH
155 struct efx_rx_buffer *rx_buf;
156 struct page *page;
b590ace0 157 unsigned int page_offset;
62b330ba 158 struct efx_rx_page_state *state;
f7d6f379
SH
159 dma_addr_t dma_addr;
160 unsigned index, count;
161
1648a23f
DP
162 count = 0;
163 do {
2768935a
DP
164 page = efx_reuse_page(rx_queue);
165 if (page == NULL) {
cce28794
JC
166 page = alloc_pages(__GFP_COLD | __GFP_COMP |
167 (atomic ? GFP_ATOMIC : GFP_KERNEL),
2768935a
DP
168 efx->rx_buffer_order);
169 if (unlikely(page == NULL))
170 return -ENOMEM;
171 dma_addr =
172 dma_map_page(&efx->pci_dev->dev, page, 0,
173 PAGE_SIZE << efx->rx_buffer_order,
174 DMA_FROM_DEVICE);
175 if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
176 dma_addr))) {
177 __free_pages(page, efx->rx_buffer_order);
178 return -EIO;
179 }
180 state = page_address(page);
181 state->dma_addr = dma_addr;
182 } else {
183 state = page_address(page);
184 dma_addr = state->dma_addr;
8ceee660 185 }
62b330ba 186
62b330ba 187 dma_addr += sizeof(struct efx_rx_page_state);
b590ace0 188 page_offset = sizeof(struct efx_rx_page_state);
f7d6f379 189
1648a23f
DP
190 do {
191 index = rx_queue->added_count & rx_queue->ptr_mask;
192 rx_buf = efx_rx_buffer(rx_queue, index);
2ec03014 193 rx_buf->dma_addr = dma_addr + efx->rx_ip_align;
1648a23f 194 rx_buf->page = page;
2ec03014 195 rx_buf->page_offset = page_offset + efx->rx_ip_align;
1648a23f 196 rx_buf->len = efx->rx_dma_len;
179ea7f0 197 rx_buf->flags = 0;
1648a23f
DP
198 ++rx_queue->added_count;
199 get_page(page);
200 dma_addr += efx->rx_page_buf_step;
201 page_offset += efx->rx_page_buf_step;
202 } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
179ea7f0
BH
203
204 rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
1648a23f 205 } while (++count < efx->rx_pages_per_batch);
8ceee660 206
8ceee660
BH
207 return 0;
208}
209
2768935a
DP
210/* Unmap a DMA-mapped page. This function is only called for the final RX
211 * buffer in a page.
212 */
4d566063 213static void efx_unmap_rx_buffer(struct efx_nic *efx,
2768935a 214 struct efx_rx_buffer *rx_buf)
8ceee660 215{
2768935a
DP
216 struct page *page = rx_buf->page;
217
218 if (page) {
219 struct efx_rx_page_state *state = page_address(page);
220 dma_unmap_page(&efx->pci_dev->dev,
221 state->dma_addr,
222 PAGE_SIZE << efx->rx_buffer_order,
223 DMA_FROM_DEVICE);
8ceee660
BH
224 }
225}
226
2768935a 227static void efx_free_rx_buffer(struct efx_rx_buffer *rx_buf)
8ceee660 228{
97d48a10 229 if (rx_buf->page) {
2768935a 230 put_page(rx_buf->page);
97d48a10 231 rx_buf->page = NULL;
8ceee660
BH
232 }
233}
234
2768935a
DP
235/* Attempt to recycle the page if there is an RX recycle ring; the page can
236 * only be added if this is the final RX buffer, to prevent pages being used in
237 * the descriptor ring and appearing in the recycle ring simultaneously.
238 */
239static void efx_recycle_rx_page(struct efx_channel *channel,
240 struct efx_rx_buffer *rx_buf)
8ceee660 241{
2768935a
DP
242 struct page *page = rx_buf->page;
243 struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
244 struct efx_nic *efx = rx_queue->efx;
245 unsigned index;
8ceee660 246
2768935a 247 /* Only recycle the page after processing the final buffer. */
179ea7f0 248 if (!(rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE))
62b330ba 249 return;
24455800 250
2768935a
DP
251 index = rx_queue->page_add & rx_queue->page_ptr_mask;
252 if (rx_queue->page_ring[index] == NULL) {
253 unsigned read_index = rx_queue->page_remove &
254 rx_queue->page_ptr_mask;
24455800 255
2768935a
DP
256 /* The next slot in the recycle ring is available, but
257 * increment page_remove if the read pointer currently
258 * points here.
259 */
260 if (read_index == index)
261 ++rx_queue->page_remove;
262 rx_queue->page_ring[index] = page;
263 ++rx_queue->page_add;
264 return;
265 }
266 ++rx_queue->page_recycle_full;
267 efx_unmap_rx_buffer(efx, rx_buf);
268 put_page(rx_buf->page);
24455800
SH
269}
270
2768935a
DP
271static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
272 struct efx_rx_buffer *rx_buf)
273{
274 /* Release the page reference we hold for the buffer. */
275 if (rx_buf->page)
276 put_page(rx_buf->page);
277
278 /* If this is the last buffer in a page, unmap and free it. */
179ea7f0 279 if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
2768935a
DP
280 efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
281 efx_free_rx_buffer(rx_buf);
282 }
283 rx_buf->page = NULL;
284}
285
286/* Recycle the pages that are used by buffers that have just been received. */
734d4e15
BH
287static void efx_recycle_rx_pages(struct efx_channel *channel,
288 struct efx_rx_buffer *rx_buf,
289 unsigned int n_frags)
24455800 290{
f7d12cdc 291 struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
24455800 292
85740cdf 293 do {
2768935a 294 efx_recycle_rx_page(channel, rx_buf);
85740cdf
BH
295 rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
296 } while (--n_frags);
24455800
SH
297}
298
734d4e15
BH
299static void efx_discard_rx_packet(struct efx_channel *channel,
300 struct efx_rx_buffer *rx_buf,
301 unsigned int n_frags)
302{
303 struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
304
305 efx_recycle_rx_pages(channel, rx_buf, n_frags);
306
307 do {
308 efx_free_rx_buffer(rx_buf);
309 rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
310 } while (--n_frags);
311}
312
8ceee660
BH
313/**
314 * efx_fast_push_rx_descriptors - push new RX descriptors quickly
315 * @rx_queue: RX descriptor queue
49ce9c2c 316 *
8ceee660 317 * This will aim to fill the RX descriptor queue up to
da9ca505 318 * @rx_queue->@max_fill. If there is insufficient atomic
90d683af
SH
319 * memory to do so, a slow fill will be scheduled.
320 *
321 * The caller must provide serialisation (none is used here). In practise,
322 * this means this function must run from the NAPI handler, or be called
323 * when NAPI is disabled.
8ceee660 324 */
cce28794 325void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic)
8ceee660 326{
1648a23f
DP
327 struct efx_nic *efx = rx_queue->efx;
328 unsigned int fill_level, batch_size;
f7d6f379 329 int space, rc = 0;
8ceee660 330
d8aec745
BH
331 if (!rx_queue->refill_enabled)
332 return;
333
90d683af 334 /* Calculate current fill level, and exit if we don't need to fill */
8ceee660 335 fill_level = (rx_queue->added_count - rx_queue->removed_count);
ecc910f5 336 EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
8ceee660 337 if (fill_level >= rx_queue->fast_fill_trigger)
24455800 338 goto out;
8ceee660
BH
339
340 /* Record minimum fill level */
b3475645 341 if (unlikely(fill_level < rx_queue->min_fill)) {
8ceee660
BH
342 if (fill_level)
343 rx_queue->min_fill = fill_level;
b3475645 344 }
8ceee660 345
1648a23f 346 batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
da9ca505 347 space = rx_queue->max_fill - fill_level;
1648a23f 348 EFX_BUG_ON_PARANOID(space < batch_size);
8ceee660 349
62776d03
BH
350 netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
351 "RX queue %d fast-filling descriptor ring from"
97d48a10 352 " level %d to level %d\n",
ba1e8a35 353 efx_rx_queue_index(rx_queue), fill_level,
97d48a10
AR
354 rx_queue->max_fill);
355
8ceee660
BH
356
357 do {
cce28794 358 rc = efx_init_rx_buffers(rx_queue, atomic);
f7d6f379
SH
359 if (unlikely(rc)) {
360 /* Ensure that we don't leave the rx queue empty */
361 if (rx_queue->added_count == rx_queue->removed_count)
362 efx_schedule_slow_fill(rx_queue);
363 goto out;
8ceee660 364 }
1648a23f 365 } while ((space -= batch_size) >= batch_size);
8ceee660 366
62776d03
BH
367 netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
368 "RX queue %d fast-filled descriptor ring "
ba1e8a35 369 "to level %d\n", efx_rx_queue_index(rx_queue),
62776d03 370 rx_queue->added_count - rx_queue->removed_count);
8ceee660
BH
371
372 out:
24455800
SH
373 if (rx_queue->notified_count != rx_queue->added_count)
374 efx_nic_notify_rx_desc(rx_queue);
8ceee660
BH
375}
376
90d683af 377void efx_rx_slow_fill(unsigned long context)
8ceee660 378{
90d683af 379 struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
8ceee660 380
90d683af 381 /* Post an event to cause NAPI to run and refill the queue */
2ae75dac 382 efx_nic_generate_fill_event(rx_queue);
8ceee660 383 ++rx_queue->slow_fill_count;
8ceee660
BH
384}
385
4d566063
BH
386static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
387 struct efx_rx_buffer *rx_buf,
97d48a10 388 int len)
8ceee660
BH
389{
390 struct efx_nic *efx = rx_queue->efx;
391 unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
392
393 if (likely(len <= max_len))
394 return;
395
396 /* The packet must be discarded, but this is only a fatal error
397 * if the caller indicated it was
398 */
db339569 399 rx_buf->flags |= EFX_RX_PKT_DISCARD;
8ceee660
BH
400
401 if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
62776d03
BH
402 if (net_ratelimit())
403 netif_err(efx, rx_err, efx->net_dev,
404 " RX queue %d seriously overlength "
405 "RX event (0x%x > 0x%x+0x%x). Leaking\n",
ba1e8a35 406 efx_rx_queue_index(rx_queue), len, max_len,
62776d03 407 efx->type->rx_buffer_padding);
8ceee660
BH
408 efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
409 } else {
62776d03
BH
410 if (net_ratelimit())
411 netif_err(efx, rx_err, efx->net_dev,
412 " RX queue %d overlength RX event "
413 "(0x%x > 0x%x)\n",
ba1e8a35 414 efx_rx_queue_index(rx_queue), len, max_len);
8ceee660
BH
415 }
416
ba1e8a35 417 efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
8ceee660
BH
418}
419
61321d92
BH
420/* Pass a received packet up through GRO. GRO can handle pages
421 * regardless of checksum state and skbs with a good checksum.
8ceee660 422 */
85740cdf
BH
423static void
424efx_rx_packet_gro(struct efx_channel *channel, struct efx_rx_buffer *rx_buf,
425 unsigned int n_frags, u8 *eh)
8ceee660 426{
da3bc071 427 struct napi_struct *napi = &channel->napi_str;
18e1d2be 428 gro_result_t gro_result;
97d48a10 429 struct efx_nic *efx = channel->efx;
97d48a10 430 struct sk_buff *skb;
8ceee660 431
97d48a10 432 skb = napi_get_frags(napi);
85740cdf
BH
433 if (unlikely(!skb)) {
434 while (n_frags--) {
435 put_page(rx_buf->page);
436 rx_buf->page = NULL;
437 rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
438 }
97d48a10
AR
439 return;
440 }
76620aaf 441
97d48a10 442 if (efx->net_dev->features & NETIF_F_RXHASH)
43a3739d 443 skb->rxhash = efx_rx_buf_hash(efx, eh);
97d48a10
AR
444 skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
445 CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
8ceee660 446
85740cdf
BH
447 for (;;) {
448 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
449 rx_buf->page, rx_buf->page_offset,
450 rx_buf->len);
451 rx_buf->page = NULL;
452 skb->len += rx_buf->len;
453 if (skb_shinfo(skb)->nr_frags == n_frags)
454 break;
3eadb7b0 455
85740cdf
BH
456 rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
457 }
458
459 skb->data_len = skb->len;
460 skb->truesize += n_frags * efx->rx_buffer_truesize;
461
462 skb_record_rx_queue(skb, channel->rx_queue.core_index);
8ceee660 463
85740cdf 464 gro_result = napi_gro_frags(napi);
97d48a10
AR
465 if (gro_result != GRO_DROP)
466 channel->irq_mod_score += 2;
467}
1241e951 468
85740cdf 469/* Allocate and construct an SKB around page fragments */
97d48a10
AR
470static struct sk_buff *efx_rx_mk_skb(struct efx_channel *channel,
471 struct efx_rx_buffer *rx_buf,
85740cdf 472 unsigned int n_frags,
97d48a10
AR
473 u8 *eh, int hdr_len)
474{
475 struct efx_nic *efx = channel->efx;
476 struct sk_buff *skb;
18e1d2be 477
97d48a10
AR
478 /* Allocate an SKB to store the headers */
479 skb = netdev_alloc_skb(efx->net_dev, hdr_len + EFX_PAGE_SKB_ALIGN);
480 if (unlikely(skb == NULL))
481 return NULL;
482
483 EFX_BUG_ON_PARANOID(rx_buf->len < hdr_len);
484
485 skb_reserve(skb, EFX_PAGE_SKB_ALIGN);
85740cdf 486 memcpy(__skb_put(skb, hdr_len), eh, hdr_len);
97d48a10 487
85740cdf 488 /* Append the remaining page(s) onto the frag list */
97d48a10 489 if (rx_buf->len > hdr_len) {
85740cdf
BH
490 rx_buf->page_offset += hdr_len;
491 rx_buf->len -= hdr_len;
492
493 for (;;) {
494 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
495 rx_buf->page, rx_buf->page_offset,
496 rx_buf->len);
497 rx_buf->page = NULL;
498 skb->len += rx_buf->len;
499 skb->data_len += rx_buf->len;
500 if (skb_shinfo(skb)->nr_frags == n_frags)
501 break;
502
503 rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
504 }
97d48a10
AR
505 } else {
506 __free_pages(rx_buf->page, efx->rx_buffer_order);
85740cdf
BH
507 rx_buf->page = NULL;
508 n_frags = 0;
18e1d2be 509 }
97d48a10 510
85740cdf 511 skb->truesize += n_frags * efx->rx_buffer_truesize;
97d48a10
AR
512
513 /* Move past the ethernet header */
514 skb->protocol = eth_type_trans(skb, efx->net_dev);
515
516 return skb;
8ceee660
BH
517}
518
8ceee660 519void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
85740cdf 520 unsigned int n_frags, unsigned int len, u16 flags)
8ceee660
BH
521{
522 struct efx_nic *efx = rx_queue->efx;
ba1e8a35 523 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
8ceee660 524 struct efx_rx_buffer *rx_buf;
8ceee660
BH
525
526 rx_buf = efx_rx_buffer(rx_queue, index);
179ea7f0 527 rx_buf->flags |= flags;
8ceee660 528
85740cdf
BH
529 /* Validate the number of fragments and completed length */
530 if (n_frags == 1) {
3dced740
BH
531 if (!(flags & EFX_RX_PKT_PREFIX_LEN))
532 efx_rx_packet__check_len(rx_queue, rx_buf, len);
85740cdf 533 } else if (unlikely(n_frags > EFX_RX_MAX_FRAGS) ||
e8c68c0a
JC
534 unlikely(len <= (n_frags - 1) * efx->rx_dma_len) ||
535 unlikely(len > n_frags * efx->rx_dma_len) ||
85740cdf
BH
536 unlikely(!efx->rx_scatter)) {
537 /* If this isn't an explicit discard request, either
538 * the hardware or the driver is broken.
539 */
540 WARN_ON(!(len == 0 && rx_buf->flags & EFX_RX_PKT_DISCARD));
541 rx_buf->flags |= EFX_RX_PKT_DISCARD;
542 }
8ceee660 543
62776d03 544 netif_vdbg(efx, rx_status, efx->net_dev,
85740cdf 545 "RX queue %d received ids %x-%x len %d %s%s\n",
ba1e8a35 546 efx_rx_queue_index(rx_queue), index,
85740cdf 547 (index + n_frags - 1) & rx_queue->ptr_mask, len,
db339569
BH
548 (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
549 (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : "");
8ceee660 550
85740cdf
BH
551 /* Discard packet, if instructed to do so. Process the
552 * previous receive first.
553 */
db339569 554 if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) {
85740cdf 555 efx_rx_flush_packet(channel);
734d4e15 556 efx_discard_rx_packet(channel, rx_buf, n_frags);
85740cdf 557 return;
8ceee660
BH
558 }
559
3dced740 560 if (n_frags == 1 && !(flags & EFX_RX_PKT_PREFIX_LEN))
85740cdf
BH
561 rx_buf->len = len;
562
2768935a
DP
563 /* Release and/or sync the DMA mapping - assumes all RX buffers
564 * consumed in-order per RX queue.
8ceee660 565 */
2768935a 566 efx_sync_rx_buffer(efx, rx_buf, rx_buf->len);
8ceee660
BH
567
568 /* Prefetch nice and early so data will (hopefully) be in cache by
569 * the time we look at it.
570 */
5036b7c7 571 prefetch(efx_rx_buf_va(rx_buf));
8ceee660 572
43a3739d
JC
573 rx_buf->page_offset += efx->rx_prefix_size;
574 rx_buf->len -= efx->rx_prefix_size;
85740cdf
BH
575
576 if (n_frags > 1) {
577 /* Release/sync DMA mapping for additional fragments.
578 * Fix length for last fragment.
579 */
580 unsigned int tail_frags = n_frags - 1;
581
582 for (;;) {
583 rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
584 if (--tail_frags == 0)
585 break;
e8c68c0a 586 efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
85740cdf 587 }
e8c68c0a 588 rx_buf->len = len - (n_frags - 1) * efx->rx_dma_len;
2768935a 589 efx_sync_rx_buffer(efx, rx_buf, rx_buf->len);
85740cdf 590 }
b74e3e8c 591
734d4e15 592 /* All fragments have been DMA-synced, so recycle pages. */
2768935a 593 rx_buf = efx_rx_buffer(rx_queue, index);
734d4e15 594 efx_recycle_rx_pages(channel, rx_buf, n_frags);
2768935a 595
8ceee660
BH
596 /* Pipeline receives so that we give time for packet headers to be
597 * prefetched into cache.
598 */
ff734ef4 599 efx_rx_flush_packet(channel);
85740cdf
BH
600 channel->rx_pkt_n_frags = n_frags;
601 channel->rx_pkt_index = index;
8ceee660
BH
602}
603
97d48a10 604static void efx_rx_deliver(struct efx_channel *channel, u8 *eh,
85740cdf
BH
605 struct efx_rx_buffer *rx_buf,
606 unsigned int n_frags)
1ddceb4c
BH
607{
608 struct sk_buff *skb;
97d48a10 609 u16 hdr_len = min_t(u16, rx_buf->len, EFX_SKB_HEADERS);
1ddceb4c 610
85740cdf 611 skb = efx_rx_mk_skb(channel, rx_buf, n_frags, eh, hdr_len);
97d48a10 612 if (unlikely(skb == NULL)) {
2768935a 613 efx_free_rx_buffer(rx_buf);
97d48a10
AR
614 return;
615 }
616 skb_record_rx_queue(skb, channel->rx_queue.core_index);
1ddceb4c
BH
617
618 /* Set the SKB flags */
619 skb_checksum_none_assert(skb);
c99dffc4
JC
620 if (likely(rx_buf->flags & EFX_RX_PKT_CSUMMED))
621 skb->ip_summed = CHECKSUM_UNNECESSARY;
1ddceb4c 622
c31e5f9f 623 if (channel->type->receive_skb)
4a74dc65 624 if (channel->type->receive_skb(channel, skb))
97d48a10 625 return;
4a74dc65
BH
626
627 /* Pass the packet up */
628 netif_receive_skb(skb);
1ddceb4c
BH
629}
630
8ceee660 631/* Handle a received packet. Second half: Touches packet payload. */
85740cdf 632void __efx_rx_packet(struct efx_channel *channel)
8ceee660
BH
633{
634 struct efx_nic *efx = channel->efx;
85740cdf
BH
635 struct efx_rx_buffer *rx_buf =
636 efx_rx_buffer(&channel->rx_queue, channel->rx_pkt_index);
b74e3e8c 637 u8 *eh = efx_rx_buf_va(rx_buf);
604f6049 638
3dced740
BH
639 /* Read length from the prefix if necessary. This already
640 * excludes the length of the prefix itself.
641 */
642 if (rx_buf->flags & EFX_RX_PKT_PREFIX_LEN)
643 rx_buf->len = le16_to_cpup((__le16 *)
644 (eh + efx->rx_packet_len_offset));
645
3273c2e8
BH
646 /* If we're in loopback test, then pass the packet directly to the
647 * loopback layer, and free the rx_buf here
648 */
649 if (unlikely(efx->loopback_selftest)) {
a526f140 650 efx_loopback_rx_packet(efx, eh, rx_buf->len);
2768935a 651 efx_free_rx_buffer(rx_buf);
85740cdf 652 goto out;
3273c2e8
BH
653 }
654
abfe9039 655 if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
db339569 656 rx_buf->flags &= ~EFX_RX_PKT_CSUMMED;
ab3cf6d0 657
e79255de 658 if ((rx_buf->flags & EFX_RX_PKT_TCP) && !channel->type->receive_skb)
85740cdf 659 efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh);
1ddceb4c 660 else
85740cdf
BH
661 efx_rx_deliver(channel, eh, rx_buf, channel->rx_pkt_n_frags);
662out:
663 channel->rx_pkt_n_frags = 0;
8ceee660
BH
664}
665
666int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
667{
668 struct efx_nic *efx = rx_queue->efx;
ecc910f5 669 unsigned int entries;
8ceee660
BH
670 int rc;
671
ecc910f5
SH
672 /* Create the smallest power-of-two aligned ring */
673 entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
674 EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
675 rx_queue->ptr_mask = entries - 1;
676
62776d03 677 netif_dbg(efx, probe, efx->net_dev,
ecc910f5
SH
678 "creating RX queue %d size %#x mask %#x\n",
679 efx_rx_queue_index(rx_queue), efx->rxq_entries,
680 rx_queue->ptr_mask);
8ceee660
BH
681
682 /* Allocate RX buffers */
c2e4e25a 683 rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
ecc910f5 684 GFP_KERNEL);
8831da7b
BH
685 if (!rx_queue->buffer)
686 return -ENOMEM;
8ceee660 687
152b6a62 688 rc = efx_nic_probe_rx(rx_queue);
8831da7b
BH
689 if (rc) {
690 kfree(rx_queue->buffer);
691 rx_queue->buffer = NULL;
692 }
2768935a 693
8ceee660
BH
694 return rc;
695}
696
debd0034 697static void efx_init_rx_recycle_ring(struct efx_nic *efx,
698 struct efx_rx_queue *rx_queue)
2768935a
DP
699{
700 unsigned int bufs_in_recycle_ring, page_ring_size;
701
702 /* Set the RX recycle ring size */
703#ifdef CONFIG_PPC64
704 bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU;
705#else
636d73da 706 if (iommu_present(&pci_bus_type))
2768935a
DP
707 bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU;
708 else
709 bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_NOIOMMU;
710#endif /* CONFIG_PPC64 */
711
712 page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring /
713 efx->rx_bufs_per_page);
714 rx_queue->page_ring = kcalloc(page_ring_size,
715 sizeof(*rx_queue->page_ring), GFP_KERNEL);
716 rx_queue->page_ptr_mask = page_ring_size - 1;
717}
718
bc3c90a2 719void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
8ceee660 720{
ecc910f5 721 struct efx_nic *efx = rx_queue->efx;
64235187 722 unsigned int max_fill, trigger, max_trigger;
8ceee660 723
62776d03 724 netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
ba1e8a35 725 "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
8ceee660
BH
726
727 /* Initialise ptr fields */
728 rx_queue->added_count = 0;
729 rx_queue->notified_count = 0;
730 rx_queue->removed_count = 0;
731 rx_queue->min_fill = -1U;
2768935a
DP
732 efx_init_rx_recycle_ring(efx, rx_queue);
733
734 rx_queue->page_remove = 0;
735 rx_queue->page_add = rx_queue->page_ptr_mask + 1;
736 rx_queue->page_recycle_count = 0;
737 rx_queue->page_recycle_failed = 0;
738 rx_queue->page_recycle_full = 0;
8ceee660
BH
739
740 /* Initialise limit fields */
ecc910f5 741 max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
1648a23f
DP
742 max_trigger =
743 max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
64235187
DR
744 if (rx_refill_threshold != 0) {
745 trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
746 if (trigger > max_trigger)
747 trigger = max_trigger;
748 } else {
749 trigger = max_trigger;
750 }
8ceee660
BH
751
752 rx_queue->max_fill = max_fill;
753 rx_queue->fast_fill_trigger = trigger;
d8aec745 754 rx_queue->refill_enabled = true;
8ceee660
BH
755
756 /* Set up RX descriptor ring */
152b6a62 757 efx_nic_init_rx(rx_queue);
8ceee660
BH
758}
759
760void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
761{
762 int i;
2768935a 763 struct efx_nic *efx = rx_queue->efx;
8ceee660
BH
764 struct efx_rx_buffer *rx_buf;
765
62776d03 766 netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
ba1e8a35 767 "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
8ceee660 768
90d683af 769 del_timer_sync(&rx_queue->slow_fill);
8ceee660 770
2768935a 771 /* Release RX buffers from the current read ptr to the write ptr */
8ceee660 772 if (rx_queue->buffer) {
2768935a
DP
773 for (i = rx_queue->removed_count; i < rx_queue->added_count;
774 i++) {
775 unsigned index = i & rx_queue->ptr_mask;
776 rx_buf = efx_rx_buffer(rx_queue, index);
8ceee660
BH
777 efx_fini_rx_buffer(rx_queue, rx_buf);
778 }
779 }
2768935a
DP
780
781 /* Unmap and release the pages in the recycle ring. Remove the ring. */
782 for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
783 struct page *page = rx_queue->page_ring[i];
784 struct efx_rx_page_state *state;
785
786 if (page == NULL)
787 continue;
788
789 state = page_address(page);
790 dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
791 PAGE_SIZE << efx->rx_buffer_order,
792 DMA_FROM_DEVICE);
793 put_page(page);
794 }
795 kfree(rx_queue->page_ring);
796 rx_queue->page_ring = NULL;
8ceee660
BH
797}
798
799void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
800{
62776d03 801 netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
ba1e8a35 802 "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
8ceee660 803
152b6a62 804 efx_nic_remove_rx(rx_queue);
8ceee660
BH
805
806 kfree(rx_queue->buffer);
807 rx_queue->buffer = NULL;
8ceee660
BH
808}
809
8ceee660 810
8ceee660
BH
811module_param(rx_refill_threshold, uint, 0444);
812MODULE_PARM_DESC(rx_refill_threshold,
64235187 813 "RX descriptor ring refill threshold (%)");
8ceee660 814
add72477
BH
815#ifdef CONFIG_RFS_ACCEL
816
817int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
818 u16 rxq_index, u32 flow_id)
819{
820 struct efx_nic *efx = netdev_priv(net_dev);
821 struct efx_channel *channel;
822 struct efx_filter_spec spec;
add72477 823 const __be16 *ports;
c47b2d9d 824 __be16 ether_type;
add72477
BH
825 int nhoff;
826 int rc;
827
c47b2d9d
BH
828 /* The core RPS/RFS code has already parsed and validated
829 * VLAN, IP and transport headers. We assume they are in the
830 * header area.
831 */
add72477
BH
832
833 if (skb->protocol == htons(ETH_P_8021Q)) {
c47b2d9d
BH
834 const struct vlan_hdr *vh =
835 (const struct vlan_hdr *)skb->data;
add72477 836
c47b2d9d
BH
837 /* We can't filter on the IP 5-tuple and the vlan
838 * together, so just strip the vlan header and filter
839 * on the IP part.
add72477 840 */
c47b2d9d
BH
841 EFX_BUG_ON_PARANOID(skb_headlen(skb) < sizeof(*vh));
842 ether_type = vh->h_vlan_encapsulated_proto;
843 nhoff = sizeof(struct vlan_hdr);
844 } else {
845 ether_type = skb->protocol;
846 nhoff = 0;
add72477
BH
847 }
848
c47b2d9d 849 if (ether_type != htons(ETH_P_IP) && ether_type != htons(ETH_P_IPV6))
add72477 850 return -EPROTONOSUPPORT;
add72477
BH
851
852 efx_filter_init_rx(&spec, EFX_FILTER_PRI_HINT,
853 efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0,
854 rxq_index);
c47b2d9d
BH
855 spec.match_flags =
856 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
857 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
858 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
859 spec.ether_type = ether_type;
860
861 if (ether_type == htons(ETH_P_IP)) {
862 const struct iphdr *ip =
863 (const struct iphdr *)(skb->data + nhoff);
864
865 EFX_BUG_ON_PARANOID(skb_headlen(skb) < nhoff + sizeof(*ip));
866 if (ip_is_fragment(ip))
867 return -EPROTONOSUPPORT;
868 spec.ip_proto = ip->protocol;
869 spec.rem_host[0] = ip->saddr;
870 spec.loc_host[0] = ip->daddr;
871 EFX_BUG_ON_PARANOID(skb_headlen(skb) < nhoff + 4 * ip->ihl + 4);
872 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
873 } else {
874 const struct ipv6hdr *ip6 =
875 (const struct ipv6hdr *)(skb->data + nhoff);
876
877 EFX_BUG_ON_PARANOID(skb_headlen(skb) <
878 nhoff + sizeof(*ip6) + 4);
879 spec.ip_proto = ip6->nexthdr;
880 memcpy(spec.rem_host, &ip6->saddr, sizeof(ip6->saddr));
881 memcpy(spec.loc_host, &ip6->daddr, sizeof(ip6->daddr));
882 ports = (const __be16 *)(ip6 + 1);
883 }
884
885 spec.rem_port = ports[0];
886 spec.loc_port = ports[1];
add72477
BH
887
888 rc = efx->type->filter_rfs_insert(efx, &spec);
889 if (rc < 0)
890 return rc;
891
892 /* Remember this so we can check whether to expire the filter later */
893 efx->rps_flow_id[rc] = flow_id;
894 channel = efx_get_channel(efx, skb_get_rx_queue(skb));
895 ++channel->rfs_filters_added;
896
c47b2d9d
BH
897 if (ether_type == htons(ETH_P_IP))
898 netif_info(efx, rx_status, efx->net_dev,
899 "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d]\n",
900 (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
901 spec.rem_host, ntohs(ports[0]), spec.loc_host,
902 ntohs(ports[1]), rxq_index, flow_id, rc);
903 else
904 netif_info(efx, rx_status, efx->net_dev,
905 "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d]\n",
906 (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
907 spec.rem_host, ntohs(ports[0]), spec.loc_host,
908 ntohs(ports[1]), rxq_index, flow_id, rc);
add72477
BH
909
910 return rc;
911}
912
913bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned int quota)
914{
915 bool (*expire_one)(struct efx_nic *efx, u32 flow_id, unsigned int index);
916 unsigned int index, size;
917 u32 flow_id;
918
919 if (!spin_trylock_bh(&efx->filter_lock))
920 return false;
921
922 expire_one = efx->type->filter_rfs_expire_one;
923 index = efx->rps_expire_index;
924 size = efx->type->max_rx_ip_filters;
925 while (quota--) {
926 flow_id = efx->rps_flow_id[index];
927 if (expire_one(efx, flow_id, index))
928 netif_info(efx, rx_status, efx->net_dev,
929 "expired filter %d [flow %u]\n",
930 index, flow_id);
931 if (++index == size)
932 index = 0;
933 }
934 efx->rps_expire_index = index;
935
936 spin_unlock_bh(&efx->filter_lock);
937 return true;
938}
939
940#endif /* CONFIG_RFS_ACCEL */
b883d0bd
BH
941
942/**
943 * efx_filter_is_mc_recipient - test whether spec is a multicast recipient
944 * @spec: Specification to test
945 *
946 * Return: %true if the specification is a non-drop RX filter that
947 * matches a local MAC address I/G bit value of 1 or matches a local
948 * IPv4 or IPv6 address value in the respective multicast address
949 * range. Otherwise %false.
950 */
951bool efx_filter_is_mc_recipient(const struct efx_filter_spec *spec)
952{
953 if (!(spec->flags & EFX_FILTER_FLAG_RX) ||
954 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP)
955 return false;
956
957 if (spec->match_flags &
958 (EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_MAC_IG) &&
959 is_multicast_ether_addr(spec->loc_mac))
960 return true;
961
962 if ((spec->match_flags &
963 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
964 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
965 if (spec->ether_type == htons(ETH_P_IP) &&
966 ipv4_is_multicast(spec->loc_host[0]))
967 return true;
968 if (spec->ether_type == htons(ETH_P_IPV6) &&
969 ((const u8 *)spec->loc_host)[0] == 0xff)
970 return true;
971 }
972
973 return false;
974}
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