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afd4aea0 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
afd4aea0 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d614cfbc | 16 | #include <linux/random.h> |
afd4aea0 BH |
17 | #include "net_driver.h" |
18 | #include "bitfield.h" | |
19 | #include "efx.h" | |
20 | #include "nic.h" | |
21 | #include "mac.h" | |
22 | #include "spi.h" | |
23 | #include "regs.h" | |
24 | #include "io.h" | |
25 | #include "phy.h" | |
26 | #include "workarounds.h" | |
27 | #include "mcdi.h" | |
28 | #include "mcdi_pcol.h" | |
29 | ||
30 | /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ | |
31 | ||
32 | static void siena_init_wol(struct efx_nic *efx); | |
33 | ||
34 | ||
35 | static void siena_push_irq_moderation(struct efx_channel *channel) | |
36 | { | |
37 | efx_dword_t timer_cmd; | |
38 | ||
9e393b30 BH |
39 | BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_CZ_TC_TIMER_VAL_WIDTH)); |
40 | ||
afd4aea0 BH |
41 | if (channel->irq_moderation) |
42 | EFX_POPULATE_DWORD_2(timer_cmd, | |
43 | FRF_CZ_TC_TIMER_MODE, | |
44 | FFE_CZ_TIMER_MODE_INT_HLDOFF, | |
45 | FRF_CZ_TC_TIMER_VAL, | |
46 | channel->irq_moderation - 1); | |
47 | else | |
48 | EFX_POPULATE_DWORD_2(timer_cmd, | |
49 | FRF_CZ_TC_TIMER_MODE, | |
50 | FFE_CZ_TIMER_MODE_DIS, | |
51 | FRF_CZ_TC_TIMER_VAL, 0); | |
52 | efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, | |
53 | channel->channel); | |
54 | } | |
55 | ||
56 | static void siena_push_multicast_hash(struct efx_nic *efx) | |
57 | { | |
58 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
59 | ||
60 | efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH, | |
61 | efx->multicast_hash.byte, sizeof(efx->multicast_hash), | |
62 | NULL, 0, NULL); | |
63 | } | |
64 | ||
65 | static int siena_mdio_write(struct net_device *net_dev, | |
66 | int prtad, int devad, u16 addr, u16 value) | |
67 | { | |
68 | struct efx_nic *efx = netdev_priv(net_dev); | |
69 | uint32_t status; | |
70 | int rc; | |
71 | ||
72 | rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad, | |
73 | addr, value, &status); | |
74 | if (rc) | |
75 | return rc; | |
76 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
77 | return -EIO; | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
82 | static int siena_mdio_read(struct net_device *net_dev, | |
83 | int prtad, int devad, u16 addr) | |
84 | { | |
85 | struct efx_nic *efx = netdev_priv(net_dev); | |
86 | uint16_t value; | |
87 | uint32_t status; | |
88 | int rc; | |
89 | ||
90 | rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad, | |
91 | addr, &value, &status); | |
92 | if (rc) | |
93 | return rc; | |
94 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
95 | return -EIO; | |
96 | ||
97 | return (int)value; | |
98 | } | |
99 | ||
100 | /* This call is responsible for hooking in the MAC and PHY operations */ | |
101 | static int siena_probe_port(struct efx_nic *efx) | |
102 | { | |
103 | int rc; | |
104 | ||
105 | /* Hook in PHY operations table */ | |
106 | efx->phy_op = &efx_mcdi_phy_ops; | |
107 | ||
108 | /* Set up MDIO structure for PHY */ | |
109 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
110 | efx->mdio.mdio_read = siena_mdio_read; | |
111 | efx->mdio.mdio_write = siena_mdio_write; | |
112 | ||
7a6b8f6f | 113 | /* Fill out MDIO structure, loopback modes, and initial link state */ |
afd4aea0 BH |
114 | rc = efx->phy_op->probe(efx); |
115 | if (rc != 0) | |
116 | return rc; | |
117 | ||
afd4aea0 BH |
118 | /* Allocate buffer for stats */ |
119 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, | |
120 | MC_CMD_MAC_NSTATS * sizeof(u64)); | |
121 | if (rc) | |
122 | return rc; | |
62776d03 BH |
123 | netif_dbg(efx, probe, efx->net_dev, |
124 | "stats buffer at %llx (virt %p phys %llx)\n", | |
125 | (u64)efx->stats_buffer.dma_addr, | |
126 | efx->stats_buffer.addr, | |
127 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
afd4aea0 BH |
128 | |
129 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
d215697f | 134 | static void siena_remove_port(struct efx_nic *efx) |
afd4aea0 | 135 | { |
ff3b00a0 | 136 | efx->phy_op->remove(efx); |
afd4aea0 BH |
137 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
138 | } | |
139 | ||
140 | static const struct efx_nic_register_test siena_register_tests[] = { | |
141 | { FR_AZ_ADR_REGION, | |
4cddca54 | 142 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
afd4aea0 BH |
143 | { FR_CZ_USR_EV_CFG, |
144 | EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, | |
145 | { FR_AZ_RX_CFG, | |
146 | EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, | |
147 | { FR_AZ_TX_CFG, | |
148 | EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, | |
149 | { FR_AZ_TX_RESERVED, | |
150 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, | |
151 | { FR_AZ_SRM_TX_DC_CFG, | |
152 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, | |
153 | { FR_AZ_RX_DC_CFG, | |
154 | EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, | |
155 | { FR_AZ_RX_DC_PF_WM, | |
156 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, | |
157 | { FR_BZ_DP_CTRL, | |
158 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, | |
159 | { FR_BZ_RX_RSS_TKEY, | |
160 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
161 | { FR_CZ_RX_RSS_IPV6_REG1, | |
162 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
163 | { FR_CZ_RX_RSS_IPV6_REG2, | |
164 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
165 | { FR_CZ_RX_RSS_IPV6_REG3, | |
166 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, | |
167 | }; | |
168 | ||
169 | static int siena_test_registers(struct efx_nic *efx) | |
170 | { | |
171 | return efx_nic_test_registers(efx, siena_register_tests, | |
172 | ARRAY_SIZE(siena_register_tests)); | |
173 | } | |
174 | ||
175 | /************************************************************************** | |
176 | * | |
177 | * Device reset | |
178 | * | |
179 | ************************************************************************** | |
180 | */ | |
181 | ||
0e2a9c7c BH |
182 | static enum reset_type siena_map_reset_reason(enum reset_type reason) |
183 | { | |
184 | return RESET_TYPE_ALL; | |
185 | } | |
186 | ||
187 | static int siena_map_reset_flags(u32 *flags) | |
188 | { | |
189 | enum { | |
190 | SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER | | |
191 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | | |
192 | ETH_RESET_PHY), | |
193 | SIENA_RESET_MC = (SIENA_RESET_PORT | | |
194 | ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT), | |
195 | }; | |
196 | ||
197 | if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) { | |
198 | *flags &= ~SIENA_RESET_MC; | |
199 | return RESET_TYPE_WORLD; | |
200 | } | |
201 | ||
202 | if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) { | |
203 | *flags &= ~SIENA_RESET_PORT; | |
204 | return RESET_TYPE_ALL; | |
205 | } | |
206 | ||
207 | /* no invisible reset implemented */ | |
208 | ||
209 | return -EINVAL; | |
210 | } | |
211 | ||
afd4aea0 BH |
212 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) |
213 | { | |
8b2103ad SH |
214 | int rc; |
215 | ||
216 | /* Recover from a failed assertion pre-reset */ | |
217 | rc = efx_mcdi_handle_assertion(efx); | |
218 | if (rc) | |
219 | return rc; | |
afd4aea0 BH |
220 | |
221 | if (method == RESET_TYPE_WORLD) | |
222 | return efx_mcdi_reset_mc(efx); | |
223 | else | |
224 | return efx_mcdi_reset_port(efx); | |
225 | } | |
226 | ||
227 | static int siena_probe_nvconfig(struct efx_nic *efx) | |
228 | { | |
7e300bc8 | 229 | return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL); |
afd4aea0 BH |
230 | } |
231 | ||
232 | static int siena_probe_nic(struct efx_nic *efx) | |
233 | { | |
234 | struct siena_nic_data *nic_data; | |
3db1cd5c | 235 | bool already_attached = false; |
d42a8f46 | 236 | efx_oword_t reg; |
afd4aea0 BH |
237 | int rc; |
238 | ||
239 | /* Allocate storage for hardware specific data */ | |
240 | nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); | |
241 | if (!nic_data) | |
242 | return -ENOMEM; | |
243 | efx->nic_data = nic_data; | |
244 | ||
245 | if (efx_nic_fpga_ver(efx) != 0) { | |
62776d03 BH |
246 | netif_err(efx, probe, efx->net_dev, |
247 | "Siena FPGA not supported\n"); | |
afd4aea0 BH |
248 | rc = -ENODEV; |
249 | goto fail1; | |
250 | } | |
251 | ||
d42a8f46 | 252 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); |
3df95ce9 | 253 | efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; |
d42a8f46 | 254 | |
afd4aea0 BH |
255 | efx_mcdi_init(efx); |
256 | ||
257 | /* Recover from a failed assertion before probing */ | |
258 | rc = efx_mcdi_handle_assertion(efx); | |
259 | if (rc) | |
86c432ca | 260 | goto fail1; |
afd4aea0 | 261 | |
afd4aea0 BH |
262 | /* Let the BMC know that the driver is now in charge of link and |
263 | * filter settings. We must do this before we reset the NIC */ | |
264 | rc = efx_mcdi_drv_attach(efx, true, &already_attached); | |
265 | if (rc) { | |
62776d03 BH |
266 | netif_err(efx, probe, efx->net_dev, |
267 | "Unable to register driver with MCPU\n"); | |
afd4aea0 BH |
268 | goto fail2; |
269 | } | |
270 | if (already_attached) | |
271 | /* Not a fatal error */ | |
62776d03 BH |
272 | netif_err(efx, probe, efx->net_dev, |
273 | "Host already registered with MCPU\n"); | |
afd4aea0 BH |
274 | |
275 | /* Now we can reset the NIC */ | |
276 | rc = siena_reset_hw(efx, RESET_TYPE_ALL); | |
277 | if (rc) { | |
62776d03 | 278 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
afd4aea0 BH |
279 | goto fail3; |
280 | } | |
281 | ||
282 | siena_init_wol(efx); | |
283 | ||
284 | /* Allocate memory for INT_KER */ | |
285 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
286 | if (rc) | |
287 | goto fail4; | |
288 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
289 | ||
62776d03 BH |
290 | netif_dbg(efx, probe, efx->net_dev, |
291 | "INT_KER at %llx (virt %p phys %llx)\n", | |
292 | (unsigned long long)efx->irq_status.dma_addr, | |
293 | efx->irq_status.addr, | |
294 | (unsigned long long)virt_to_phys(efx->irq_status.addr)); | |
afd4aea0 BH |
295 | |
296 | /* Read in the non-volatile configuration */ | |
297 | rc = siena_probe_nvconfig(efx); | |
298 | if (rc == -EINVAL) { | |
62776d03 BH |
299 | netif_err(efx, probe, efx->net_dev, |
300 | "NVRAM is invalid therefore using defaults\n"); | |
afd4aea0 BH |
301 | efx->phy_type = PHY_TYPE_NONE; |
302 | efx->mdio.prtad = MDIO_PRTAD_NONE; | |
303 | } else if (rc) { | |
304 | goto fail5; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | ||
309 | fail5: | |
310 | efx_nic_free_buffer(efx, &efx->irq_status); | |
311 | fail4: | |
312 | fail3: | |
313 | efx_mcdi_drv_attach(efx, false, NULL); | |
314 | fail2: | |
315 | fail1: | |
316 | kfree(efx->nic_data); | |
317 | return rc; | |
318 | } | |
319 | ||
320 | /* This call performs hardware-specific global initialisation, such as | |
321 | * defining the descriptor cache sizes and number of RSS channels. | |
322 | * It does not set up any buffers, descriptor rings or event queues. | |
323 | */ | |
324 | static int siena_init_nic(struct efx_nic *efx) | |
325 | { | |
326 | efx_oword_t temp; | |
327 | int rc; | |
328 | ||
329 | /* Recover from a failed assertion post-reset */ | |
330 | rc = efx_mcdi_handle_assertion(efx); | |
331 | if (rc) | |
332 | return rc; | |
333 | ||
334 | /* Squash TX of packets of 16 bytes or less */ | |
335 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); | |
336 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); | |
337 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); | |
338 | ||
339 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
340 | * descriptors (which is bad). | |
341 | */ | |
342 | efx_reado(efx, &temp, FR_AZ_TX_CFG); | |
343 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); | |
344 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); | |
345 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); | |
346 | ||
347 | efx_reado(efx, &temp, FR_AZ_RX_CFG); | |
348 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); | |
349 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
350 | /* Enable hash insertion. This is broken for the 'Falcon' hash |
351 | * if IPv6 hashing is also enabled, so also select Toeplitz | |
352 | * TCP/IPv4 and IPv4 hashes. */ | |
353 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1); | |
354 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1); | |
355 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1); | |
afd4aea0 BH |
356 | efx_writeo(efx, &temp, FR_AZ_RX_CFG); |
357 | ||
477e54eb BH |
358 | /* Set hash key for IPv4 */ |
359 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
360 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | |
361 | ||
d614cfbc | 362 | /* Enable IPv6 RSS */ |
5d3a6fca | 363 | BUILD_BUG_ON(sizeof(efx->rx_hash_key) < |
d614cfbc BH |
364 | 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || |
365 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); | |
5d3a6fca | 366 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); |
d614cfbc | 367 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); |
5d3a6fca | 368 | memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp)); |
d614cfbc BH |
369 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); |
370 | EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, | |
371 | FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); | |
5d3a6fca | 372 | memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp), |
d614cfbc BH |
373 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); |
374 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); | |
375 | ||
afd4aea0 BH |
376 | /* Enable event logging */ |
377 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); | |
378 | if (rc) | |
379 | return rc; | |
380 | ||
381 | /* Set destination of both TX and RX Flush events */ | |
382 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); | |
383 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); | |
384 | ||
385 | EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); | |
386 | efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); | |
387 | ||
388 | efx_nic_init_common(efx); | |
389 | return 0; | |
390 | } | |
391 | ||
392 | static void siena_remove_nic(struct efx_nic *efx) | |
393 | { | |
394 | efx_nic_free_buffer(efx, &efx->irq_status); | |
395 | ||
396 | siena_reset_hw(efx, RESET_TYPE_ALL); | |
397 | ||
398 | /* Relinquish the device back to the BMC */ | |
399 | if (efx_nic_has_mc(efx)) | |
400 | efx_mcdi_drv_attach(efx, false, NULL); | |
401 | ||
402 | /* Tear down the private nic state */ | |
86c432ca | 403 | kfree(efx->nic_data); |
afd4aea0 BH |
404 | efx->nic_data = NULL; |
405 | } | |
406 | ||
a659b2a9 | 407 | #define STATS_GENERATION_INVALID ((__force __le64)(-1)) |
afd4aea0 BH |
408 | |
409 | static int siena_try_update_nic_stats(struct efx_nic *efx) | |
410 | { | |
a659b2a9 | 411 | __le64 *dma_stats; |
afd4aea0 | 412 | struct efx_mac_stats *mac_stats; |
a659b2a9 | 413 | __le64 generation_start, generation_end; |
afd4aea0 BH |
414 | |
415 | mac_stats = &efx->mac_stats; | |
43d620c8 | 416 | dma_stats = efx->stats_buffer.addr; |
afd4aea0 BH |
417 | |
418 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; | |
419 | if (generation_end == STATS_GENERATION_INVALID) | |
420 | return 0; | |
421 | rmb(); | |
422 | ||
423 | #define MAC_STAT(M, D) \ | |
a659b2a9 | 424 | mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D]) |
afd4aea0 BH |
425 | |
426 | MAC_STAT(tx_bytes, TX_BYTES); | |
427 | MAC_STAT(tx_bad_bytes, TX_BAD_BYTES); | |
428 | mac_stats->tx_good_bytes = (mac_stats->tx_bytes - | |
429 | mac_stats->tx_bad_bytes); | |
430 | MAC_STAT(tx_packets, TX_PKTS); | |
431 | MAC_STAT(tx_bad, TX_BAD_FCS_PKTS); | |
432 | MAC_STAT(tx_pause, TX_PAUSE_PKTS); | |
433 | MAC_STAT(tx_control, TX_CONTROL_PKTS); | |
434 | MAC_STAT(tx_unicast, TX_UNICAST_PKTS); | |
435 | MAC_STAT(tx_multicast, TX_MULTICAST_PKTS); | |
436 | MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS); | |
437 | MAC_STAT(tx_lt64, TX_LT64_PKTS); | |
438 | MAC_STAT(tx_64, TX_64_PKTS); | |
439 | MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS); | |
440 | MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS); | |
441 | MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS); | |
442 | MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS); | |
443 | MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS); | |
444 | MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS); | |
445 | MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS); | |
446 | mac_stats->tx_collision = 0; | |
447 | MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS); | |
448 | MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS); | |
449 | MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS); | |
450 | MAC_STAT(tx_deferred, TX_DEFERRED_PKTS); | |
451 | MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS); | |
452 | mac_stats->tx_collision = (mac_stats->tx_single_collision + | |
453 | mac_stats->tx_multiple_collision + | |
454 | mac_stats->tx_excessive_collision + | |
455 | mac_stats->tx_late_collision); | |
456 | MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS); | |
457 | MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS); | |
458 | MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS); | |
459 | MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS); | |
460 | MAC_STAT(rx_bytes, RX_BYTES); | |
461 | MAC_STAT(rx_bad_bytes, RX_BAD_BYTES); | |
462 | mac_stats->rx_good_bytes = (mac_stats->rx_bytes - | |
463 | mac_stats->rx_bad_bytes); | |
464 | MAC_STAT(rx_packets, RX_PKTS); | |
465 | MAC_STAT(rx_good, RX_GOOD_PKTS); | |
1cdc2cfc | 466 | MAC_STAT(rx_bad, RX_BAD_FCS_PKTS); |
afd4aea0 BH |
467 | MAC_STAT(rx_pause, RX_PAUSE_PKTS); |
468 | MAC_STAT(rx_control, RX_CONTROL_PKTS); | |
469 | MAC_STAT(rx_unicast, RX_UNICAST_PKTS); | |
470 | MAC_STAT(rx_multicast, RX_MULTICAST_PKTS); | |
471 | MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS); | |
472 | MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS); | |
473 | MAC_STAT(rx_64, RX_64_PKTS); | |
474 | MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS); | |
475 | MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS); | |
476 | MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS); | |
477 | MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS); | |
478 | MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS); | |
479 | MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS); | |
480 | MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS); | |
481 | mac_stats->rx_bad_lt64 = 0; | |
482 | mac_stats->rx_bad_64_to_15xx = 0; | |
483 | mac_stats->rx_bad_15xx_to_jumbo = 0; | |
484 | MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS); | |
485 | MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS); | |
486 | mac_stats->rx_missed = 0; | |
487 | MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS); | |
488 | MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS); | |
489 | MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS); | |
490 | MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS); | |
491 | MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS); | |
492 | mac_stats->rx_good_lt64 = 0; | |
493 | ||
a659b2a9 SH |
494 | efx->n_rx_nodesc_drop_cnt = |
495 | le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]); | |
afd4aea0 BH |
496 | |
497 | #undef MAC_STAT | |
498 | ||
499 | rmb(); | |
500 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; | |
501 | if (generation_end != generation_start) | |
502 | return -EAGAIN; | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | static void siena_update_nic_stats(struct efx_nic *efx) | |
508 | { | |
aabc5649 BH |
509 | int retry; |
510 | ||
511 | /* If we're unlucky enough to read statistics wduring the DMA, wait | |
512 | * up to 10ms for it to finish (typically takes <500us) */ | |
513 | for (retry = 0; retry < 100; ++retry) { | |
514 | if (siena_try_update_nic_stats(efx) == 0) | |
515 | return; | |
516 | udelay(100); | |
517 | } | |
518 | ||
519 | /* Use the old values instead */ | |
afd4aea0 BH |
520 | } |
521 | ||
522 | static void siena_start_nic_stats(struct efx_nic *efx) | |
523 | { | |
a659b2a9 | 524 | __le64 *dma_stats = efx->stats_buffer.addr; |
afd4aea0 BH |
525 | |
526 | dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID; | |
527 | ||
528 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, | |
529 | MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0); | |
530 | } | |
531 | ||
532 | static void siena_stop_nic_stats(struct efx_nic *efx) | |
533 | { | |
534 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0); | |
535 | } | |
536 | ||
afd4aea0 BH |
537 | /************************************************************************** |
538 | * | |
539 | * Wake on LAN | |
540 | * | |
541 | ************************************************************************** | |
542 | */ | |
543 | ||
544 | static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
545 | { | |
546 | struct siena_nic_data *nic_data = efx->nic_data; | |
547 | ||
548 | wol->supported = WAKE_MAGIC; | |
549 | if (nic_data->wol_filter_id != -1) | |
550 | wol->wolopts = WAKE_MAGIC; | |
551 | else | |
552 | wol->wolopts = 0; | |
553 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
554 | } | |
555 | ||
556 | ||
557 | static int siena_set_wol(struct efx_nic *efx, u32 type) | |
558 | { | |
559 | struct siena_nic_data *nic_data = efx->nic_data; | |
560 | int rc; | |
561 | ||
562 | if (type & ~WAKE_MAGIC) | |
563 | return -EINVAL; | |
564 | ||
565 | if (type & WAKE_MAGIC) { | |
566 | if (nic_data->wol_filter_id != -1) | |
567 | efx_mcdi_wol_filter_remove(efx, | |
568 | nic_data->wol_filter_id); | |
02ebc268 | 569 | rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr, |
afd4aea0 BH |
570 | &nic_data->wol_filter_id); |
571 | if (rc) | |
572 | goto fail; | |
573 | ||
574 | pci_wake_from_d3(efx->pci_dev, true); | |
575 | } else { | |
576 | rc = efx_mcdi_wol_filter_reset(efx); | |
577 | nic_data->wol_filter_id = -1; | |
578 | pci_wake_from_d3(efx->pci_dev, false); | |
579 | if (rc) | |
580 | goto fail; | |
581 | } | |
582 | ||
583 | return 0; | |
584 | fail: | |
62776d03 BH |
585 | netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n", |
586 | __func__, type, rc); | |
afd4aea0 BH |
587 | return rc; |
588 | } | |
589 | ||
590 | ||
591 | static void siena_init_wol(struct efx_nic *efx) | |
592 | { | |
593 | struct siena_nic_data *nic_data = efx->nic_data; | |
594 | int rc; | |
595 | ||
596 | rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); | |
597 | ||
598 | if (rc != 0) { | |
599 | /* If it failed, attempt to get into a synchronised | |
600 | * state with MC by resetting any set WoL filters */ | |
601 | efx_mcdi_wol_filter_reset(efx); | |
602 | nic_data->wol_filter_id = -1; | |
603 | } else if (nic_data->wol_filter_id != -1) { | |
604 | pci_wake_from_d3(efx->pci_dev, true); | |
605 | } | |
606 | } | |
607 | ||
608 | ||
609 | /************************************************************************** | |
610 | * | |
611 | * Revision-dependent attributes used by efx.c and nic.c | |
612 | * | |
613 | ************************************************************************** | |
614 | */ | |
615 | ||
6c8c2513 | 616 | const struct efx_nic_type siena_a0_nic_type = { |
afd4aea0 BH |
617 | .probe = siena_probe_nic, |
618 | .remove = siena_remove_nic, | |
619 | .init = siena_init_nic, | |
620 | .fini = efx_port_dummy_op_void, | |
621 | .monitor = NULL, | |
0e2a9c7c BH |
622 | .map_reset_reason = siena_map_reset_reason, |
623 | .map_reset_flags = siena_map_reset_flags, | |
afd4aea0 BH |
624 | .reset = siena_reset_hw, |
625 | .probe_port = siena_probe_port, | |
626 | .remove_port = siena_remove_port, | |
627 | .prepare_flush = efx_port_dummy_op_void, | |
628 | .update_stats = siena_update_nic_stats, | |
629 | .start_stats = siena_start_nic_stats, | |
630 | .stop_stats = siena_stop_nic_stats, | |
631 | .set_id_led = efx_mcdi_set_id_led, | |
632 | .push_irq_moderation = siena_push_irq_moderation, | |
633 | .push_multicast_hash = siena_push_multicast_hash, | |
634 | .reconfigure_port = efx_mcdi_phy_reconfigure, | |
635 | .get_wol = siena_get_wol, | |
636 | .set_wol = siena_set_wol, | |
637 | .resume_wol = siena_init_wol, | |
638 | .test_registers = siena_test_registers, | |
2e803407 | 639 | .test_nvram = efx_mcdi_nvram_test_all, |
afd4aea0 BH |
640 | .default_mac_ops = &efx_mcdi_mac_operations, |
641 | ||
642 | .revision = EFX_REV_SIENA_A0, | |
86c432ca BH |
643 | .mem_map_size = (FR_CZ_MC_TREG_SMEM + |
644 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS), | |
afd4aea0 BH |
645 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
646 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
647 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
648 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
649 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
650 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), | |
39c9cf07 | 651 | .rx_buffer_hash_size = 0x10, |
afd4aea0 BH |
652 | .rx_buffer_padding = 0, |
653 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
654 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
655 | * interrupt handler only supports 32 | |
656 | * channels */ | |
657 | .tx_dc_base = 0x88000, | |
658 | .rx_dc_base = 0x68000, | |
39c9cf07 | 659 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
b4187e42 | 660 | NETIF_F_RXHASH | NETIF_F_NTUPLE), |
afd4aea0 | 661 | }; |