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net/mlx5_core: Print resource number on QP/SRQ async events
[deliverable/linux.git] / drivers / net / ethernet / sfc / siena_sriov.c
CommitLineData
cd2d5b52 1/****************************************************************************
f7a6d2c4
BH		 2 * Driver for Solarflare network controllers and boards
3 * Copyright 2010-2012 Solarflare Communications Inc.
cd2d5b52
BH		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9#include <linux/pci.h>
10#include <linux/module.h>
11#include "net_driver.h"
12#include "efx.h"
13#include "nic.h"
14#include "io.h"
15#include "mcdi.h"
16#include "filter.h"
17#include "mcdi_pcol.h"
8b8a95a1 18#include "farch_regs.h"
cd2d5b52
BH		 19#include "vfdi.h"
20
21/* Number of longs required to track all the VIs in a VF */
22#define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX)
23
45078374
BH		 24/* Maximum number of RX queues supported */
25#define VF_MAX_RX_QUEUES 63
26
cd2d5b52
BH		 27/**
28 * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour
29 * @VF_TX_FILTER_OFF: Disabled
30 * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only
31 * 2 TX queues allowed per VF.
32 * @VF_TX_FILTER_ON: Enabled
33 */
34enum efx_vf_tx_filter_mode {
35 VF_TX_FILTER_OFF,
36 VF_TX_FILTER_AUTO,
37 VF_TX_FILTER_ON,
38};
39
40/**
41 * struct efx_vf - Back-end resource and protocol state for a PCI VF
42 * @efx: The Efx NIC owning this VF
43 * @pci_rid: The PCI requester ID for this VF
44 * @pci_name: The PCI name (formatted address) of this VF
45 * @index: Index of VF within its port and PF.
46 * @req: VFDI incoming request work item. Incoming USR_EV events are received
47 * by the NAPI handler, but must be handled by executing MCDI requests
48 * inside a work item.
49 * @req_addr: VFDI incoming request DMA address (in VF's PCI address space).
50 * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member.
51 * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member.
52 * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by
53 * @status_lock
54 * @busy: VFDI request queued to be processed or being processed. Receiving
55 * a VFDI request when @busy is set is an error condition.
56 * @buf: Incoming VFDI requests are DMA from the VF into this buffer.
57 * @buftbl_base: Buffer table entries for this VF start at this index.
58 * @rx_filtering: Receive filtering has been requested by the VF driver.
59 * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request.
60 * @rx_filter_qid: VF relative qid for RX filter requested by VF.
61 * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported.
62 * @tx_filter_mode: Transmit MAC filtering mode.
63 * @tx_filter_id: Transmit MAC filter ID.
64 * @addr: The MAC address and outer vlan tag of the VF.
65 * @status_addr: VF DMA address of page for &struct vfdi_status updates.
66 * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr,
67 * @peer_page_addrs and @peer_page_count from simultaneous
68 * updates by the VM and consumption by
327c685e 69 * efx_siena_sriov_update_vf_addr()
cd2d5b52
BH		 70 * @peer_page_addrs: Pointer to an array of guest pages for local addresses.
71 * @peer_page_count: Number of entries in @peer_page_count.
72 * @evq0_addrs: Array of guest pages backing evq0.
73 * @evq0_count: Number of entries in @evq0_addrs.
74 * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler
75 * to wait for flush completions.
76 * @txq_lock: Mutex for TX queue allocation.
77 * @txq_mask: Mask of initialized transmit queues.
78 * @txq_count: Number of initialized transmit queues.
79 * @rxq_mask: Mask of initialized receive queues.
80 * @rxq_count: Number of initialized receive queues.
81 * @rxq_retry_mask: Mask or receive queues that need to be flushed again
82 * due to flush failure.
83 * @rxq_retry_count: Number of receive queues in @rxq_retry_mask.
84 * @reset_work: Work item to schedule a VF reset.
85 */
86struct efx_vf {
87 struct efx_nic *efx;
88 unsigned int pci_rid;
89 char pci_name[13]; /* dddd:bb:dd.f */
90 unsigned int index;
91 struct work_struct req;
92 u64 req_addr;
93 int req_type;
94 unsigned req_seqno;
95 unsigned msg_seqno;
96 bool busy;
97 struct efx_buffer buf;
98 unsigned buftbl_base;
99 bool rx_filtering;
100 enum efx_filter_flags rx_filter_flags;
101 unsigned rx_filter_qid;
102 int rx_filter_id;
103 enum efx_vf_tx_filter_mode tx_filter_mode;
104 int tx_filter_id;
105 struct vfdi_endpoint addr;
106 u64 status_addr;
107 struct mutex status_lock;
108 u64 *peer_page_addrs;
109 unsigned peer_page_count;
110 u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) /
111 EFX_BUF_SIZE];
112 unsigned evq0_count;
113 wait_queue_head_t flush_waitq;
114 struct mutex txq_lock;
115 unsigned long txq_mask[VI_MASK_LENGTH];
116 unsigned txq_count;
117 unsigned long rxq_mask[VI_MASK_LENGTH];
118 unsigned rxq_count;
119 unsigned long rxq_retry_mask[VI_MASK_LENGTH];
120 atomic_t rxq_retry_count;
121 struct work_struct reset_work;
122};
123
124struct efx_memcpy_req {
125 unsigned int from_rid;
126 void *from_buf;
127 u64 from_addr;
128 unsigned int to_rid;
129 u64 to_addr;
130 unsigned length;
131};
132
133/**
134 * struct efx_local_addr - A MAC address on the vswitch without a VF.
135 *
136 * Siena does not have a switch, so VFs can't transmit data to each
137 * other. Instead the VFs must be made aware of the local addresses
138 * on the vswitch, so that they can arrange for an alternative
139 * software datapath to be used.
140 *
141 * @link: List head for insertion into efx->local_addr_list.
142 * @addr: Ethernet address
143 */
144struct efx_local_addr {
145 struct list_head link;
146 u8 addr[ETH_ALEN];
147};
148
149/**
150 * struct efx_endpoint_page - Page of vfdi_endpoint structures
151 *
152 * @link: List head for insertion into efx->local_page_list.
153 * @ptr: Pointer to page.
154 * @addr: DMA address of page.
155 */
156struct efx_endpoint_page {
157 struct list_head link;
158 void *ptr;
159 dma_addr_t addr;
160};
161
162/* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */
163#define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \
164 ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid))
165#define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \
166 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
167 (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
168#define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \
169 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
170 (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
171
172#define EFX_FIELD_MASK(_field) \
173 ((1 << _field ## _WIDTH) - 1)
174
175/* VFs can only use this many transmit channels */
176static unsigned int vf_max_tx_channels = 2;
177module_param(vf_max_tx_channels, uint, 0444);
178MODULE_PARM_DESC(vf_max_tx_channels,
179 "Limit the number of TX channels VFs can use");
180
181static int max_vfs = -1;
182module_param(max_vfs, int, 0444);
183MODULE_PARM_DESC(max_vfs,
184 "Reduce the number of VFs initialized by the driver");
185
186/* Workqueue used by VFDI communication. We can't use the global
187 * workqueue because it may be running the VF driver's probe()
188 * routine, which will be blocked there waiting for a VFDI response.
189 */
190static struct workqueue_struct *vfdi_workqueue;
191
192static unsigned abs_index(struct efx_vf *vf, unsigned index)
193{
194 return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index;
195}
196
327c685e
SS		 197static int efx_siena_sriov_cmd(struct efx_nic *efx, bool enable,
198 unsigned *vi_scale_out, unsigned *vf_total_out)
cd2d5b52 199{
59cfc479
BH		 200 MCDI_DECLARE_BUF(inbuf, MC_CMD_SRIOV_IN_LEN);
201 MCDI_DECLARE_BUF(outbuf, MC_CMD_SRIOV_OUT_LEN);
cd2d5b52
BH		 202 unsigned vi_scale, vf_total;
203 size_t outlen;
204 int rc;
205
206 MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0);
207 MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE);
208 MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count);
209
210 rc = efx_mcdi_rpc(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN,
211 outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen);
212 if (rc)
213 return rc;
214 if (outlen < MC_CMD_SRIOV_OUT_LEN)
215 return -EIO;
216
217 vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL);
218 vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE);
219 if (vi_scale > EFX_VI_SCALE_MAX)
220 return -EOPNOTSUPP;
221
222 if (vi_scale_out)
223 *vi_scale_out = vi_scale;
224 if (vf_total_out)
225 *vf_total_out = vf_total;
226
227 return 0;
228}
229
327c685e 230static void efx_siena_sriov_usrev(struct efx_nic *efx, bool enabled)
cd2d5b52 231{
2dc313ec 232 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 233 efx_oword_t reg;
234
235 EFX_POPULATE_OWORD_2(reg,
236 FRF_CZ_USREV_DIS, enabled ? 0 : 1,
2dc313ec 237 FRF_CZ_DFLT_EVQ, nic_data->vfdi_channel->channel);
cd2d5b52
BH		 238 efx_writeo(efx, &reg, FR_CZ_USR_EV_CFG);
239}
240
327c685e
SS		 241static int efx_siena_sriov_memcpy(struct efx_nic *efx,
242 struct efx_memcpy_req *req,
243 unsigned int count)
cd2d5b52 244{
c5bb0e98
BH		 245 MCDI_DECLARE_BUF(inbuf, MCDI_CTL_SDU_LEN_MAX_V1);
246 MCDI_DECLARE_STRUCT_PTR(record);
247 unsigned int index, used;
338f74df
BH		 248 u64 from_addr;
249 u32 from_rid;
cd2d5b52
BH		 250 int rc;
251
252 mb(); /* Finish writing source/reading dest before DMA starts */
253
c5bb0e98 254 if (WARN_ON(count > MC_CMD_MEMCPY_IN_RECORD_MAXNUM))
cd2d5b52 255 return -ENOBUFS;
c5bb0e98 256 used = MC_CMD_MEMCPY_IN_LEN(count);
cd2d5b52 257
c5bb0e98
BH		 258 for (index = 0; index < count; index++) {
259 record = MCDI_ARRAY_STRUCT_PTR(inbuf, MEMCPY_IN_RECORD, index);
260 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_NUM_RECORDS,
261 count);
cd2d5b52
BH		 262 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID,
263 req->to_rid);
338f74df
BH		 264 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR,
265 req->to_addr);
cd2d5b52
BH		 266 if (req->from_buf == NULL) {
267 from_rid = req->from_rid;
338f74df 268 from_addr = req->from_addr;
cd2d5b52 269 } else {
d0c2ee99
BH		 270 if (WARN_ON(used + req->length >
271 MCDI_CTL_SDU_LEN_MAX_V1)) {
cd2d5b52
BH		 272 rc = -ENOBUFS;
273 goto out;
274 }
275
276 from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE;
338f74df 277 from_addr = used;
c5bb0e98
BH		 278 memcpy(_MCDI_PTR(inbuf, used), req->from_buf,
279 req->length);
cd2d5b52
BH		 280 used += req->length;
281 }
282
283 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid);
338f74df
BH		 284 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR,
285 from_addr);
cd2d5b52
BH		 286 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH,
287 req->length);
288
289 ++req;
cd2d5b52
BH		 290 }
291
292 rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL);
293out:
cd2d5b52
BH		 294 mb(); /* Don't write source/read dest before DMA is complete */
295
296 return rc;
297}
298
299/* The TX filter is entirely controlled by this driver, and is modified
300 * underneath the feet of the VF
301 */
327c685e 302static void efx_siena_sriov_reset_tx_filter(struct efx_vf *vf)
cd2d5b52
BH		 303{
304 struct efx_nic *efx = vf->efx;
305 struct efx_filter_spec filter;
306 u16 vlan;
307 int rc;
308
309 if (vf->tx_filter_id != -1) {
310 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
311 vf->tx_filter_id);
312 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n",
313 vf->pci_name, vf->tx_filter_id);
314 vf->tx_filter_id = -1;
315 }
316
317 if (is_zero_ether_addr(vf->addr.mac_addr))
318 return;
319
320 /* Turn on TX filtering automatically if not explicitly
321 * enabled or disabled.
322 */
323 if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2)
324 vf->tx_filter_mode = VF_TX_FILTER_ON;
325
326 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
327 efx_filter_init_tx(&filter, abs_index(vf, 0));
328 rc = efx_filter_set_eth_local(&filter,
329 vlan ? vlan : EFX_FILTER_VID_UNSPEC,
330 vf->addr.mac_addr);
331 BUG_ON(rc);
332
333 rc = efx_filter_insert_filter(efx, &filter, true);
334 if (rc < 0) {
335 netif_warn(efx, hw, efx->net_dev,
336 "Unable to migrate tx filter for vf %s\n",
337 vf->pci_name);
338 } else {
339 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n",
340 vf->pci_name, rc);
341 vf->tx_filter_id = rc;
342 }
343}
344
345/* The RX filter is managed here on behalf of the VF driver */
327c685e 346static void efx_siena_sriov_reset_rx_filter(struct efx_vf *vf)
cd2d5b52
BH		 347{
348 struct efx_nic *efx = vf->efx;
349 struct efx_filter_spec filter;
350 u16 vlan;
351 int rc;
352
353 if (vf->rx_filter_id != -1) {
354 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
355 vf->rx_filter_id);
356 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n",
357 vf->pci_name, vf->rx_filter_id);
358 vf->rx_filter_id = -1;
359 }
360
361 if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr))
362 return;
363
364 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
365 efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED,
366 vf->rx_filter_flags,
367 abs_index(vf, vf->rx_filter_qid));
368 rc = efx_filter_set_eth_local(&filter,
369 vlan ? vlan : EFX_FILTER_VID_UNSPEC,
370 vf->addr.mac_addr);
371 BUG_ON(rc);
372
373 rc = efx_filter_insert_filter(efx, &filter, true);
374 if (rc < 0) {
375 netif_warn(efx, hw, efx->net_dev,
376 "Unable to insert rx filter for vf %s\n",
377 vf->pci_name);
378 } else {
379 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n",
380 vf->pci_name, rc);
381 vf->rx_filter_id = rc;
382 }
383}
384
327c685e 385static void __efx_siena_sriov_update_vf_addr(struct efx_vf *vf)
cd2d5b52 386{
2dc313ec
SS		 387 struct efx_nic *efx = vf->efx;
388 struct siena_nic_data *nic_data = efx->nic_data;
389
327c685e
SS		 390 efx_siena_sriov_reset_tx_filter(vf);
391 efx_siena_sriov_reset_rx_filter(vf);
2dc313ec 392 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 393}
394
395/* Push the peer list to this VF. The caller must hold status_lock to interlock
396 * with VFDI requests, and they must be serialised against manipulation of
397 * local_page_list, either by acquiring local_lock or by running from
327c685e 398 * efx_siena_sriov_peer_work()
cd2d5b52 399 */
327c685e 400static void __efx_siena_sriov_push_vf_status(struct efx_vf *vf)
cd2d5b52
BH		 401{
402 struct efx_nic *efx = vf->efx;
2dc313ec
SS		 403 struct siena_nic_data *nic_data = efx->nic_data;
404 struct vfdi_status *status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 405 struct efx_memcpy_req copy[4];
406 struct efx_endpoint_page *epp;
407 unsigned int pos, count;
408 unsigned data_offset;
409 efx_qword_t event;
410
411 WARN_ON(!mutex_is_locked(&vf->status_lock));
412 WARN_ON(!vf->status_addr);
413
414 status->local = vf->addr;
415 status->generation_end = ++status->generation_start;
416
417 memset(copy, '\0', sizeof(copy));
418 /* Write generation_start */
419 copy[0].from_buf = &status->generation_start;
420 copy[0].to_rid = vf->pci_rid;
421 copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status,
422 generation_start);
423 copy[0].length = sizeof(status->generation_start);
424 /* DMA the rest of the structure (excluding the generations). This
425 * assumes that the non-generation portion of vfdi_status is in
426 * one chunk starting at the version member.
427 */
428 data_offset = offsetof(struct vfdi_status, version);
429 copy[1].from_rid = efx->pci_dev->devfn;
2dc313ec 430 copy[1].from_addr = nic_data->vfdi_status.dma_addr + data_offset;
cd2d5b52
BH		 431 copy[1].to_rid = vf->pci_rid;
432 copy[1].to_addr = vf->status_addr + data_offset;
433 copy[1].length = status->length - data_offset;
434
435 /* Copy the peer pages */
436 pos = 2;
437 count = 0;
2dc313ec 438 list_for_each_entry(epp, &nic_data->local_page_list, link) {
cd2d5b52
BH		 439 if (count == vf->peer_page_count) {
440 /* The VF driver will know they need to provide more
441 * pages because peer_addr_count is too large.
442 */
443 break;
444 }
445 copy[pos].from_buf = NULL;
446 copy[pos].from_rid = efx->pci_dev->devfn;
447 copy[pos].from_addr = epp->addr;
448 copy[pos].to_rid = vf->pci_rid;
449 copy[pos].to_addr = vf->peer_page_addrs[count];
450 copy[pos].length = EFX_PAGE_SIZE;
451
452 if (++pos == ARRAY_SIZE(copy)) {
327c685e 453 efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
cd2d5b52
BH		 454 pos = 0;
455 }
456 ++count;
457 }
458
459 /* Write generation_end */
460 copy[pos].from_buf = &status->generation_end;
461 copy[pos].to_rid = vf->pci_rid;
462 copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status,
463 generation_end);
464 copy[pos].length = sizeof(status->generation_end);
327c685e 465 efx_siena_sriov_memcpy(efx, copy, pos + 1);
cd2d5b52
BH		 466
467 /* Notify the guest */
468 EFX_POPULATE_QWORD_3(event,
469 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
470 VFDI_EV_SEQ, (vf->msg_seqno & 0xff),
471 VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS);
472 ++vf->msg_seqno;
86094f7f
BH		 473 efx_farch_generate_event(efx,
474 EFX_VI_BASE + vf->index * efx_vf_size(efx),
475 &event);
cd2d5b52
BH		 476}
477
327c685e
SS		 478static void efx_siena_sriov_bufs(struct efx_nic *efx, unsigned offset,
479 u64 *addr, unsigned count)
cd2d5b52
BH		 480{
481 efx_qword_t buf;
482 unsigned pos;
483
484 for (pos = 0; pos < count; ++pos) {
485 EFX_POPULATE_QWORD_3(buf,
486 FRF_AZ_BUF_ADR_REGION, 0,
487 FRF_AZ_BUF_ADR_FBUF,
488 addr ? addr[pos] >> 12 : 0,
489 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
490 efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL,
491 &buf, offset + pos);
492 }
493}
494
495static bool bad_vf_index(struct efx_nic *efx, unsigned index)
496{
497 return index >= efx_vf_size(efx);
498}
499
500static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count)
501{
502 unsigned max_buf_count = max_entry_count *
503 sizeof(efx_qword_t) / EFX_BUF_SIZE;
504
505 return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count);
506}
507
508/* Check that VI specified by per-port index belongs to a VF.
509 * Optionally set VF index and VI index within the VF.
510 */
511static bool map_vi_index(struct efx_nic *efx, unsigned abs_index,
512 struct efx_vf **vf_out, unsigned *rel_index_out)
513{
514 unsigned vf_i;
515
516 if (abs_index < EFX_VI_BASE)
517 return true;
2c61c8a7 518 vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx);
cd2d5b52
BH		 519 if (vf_i >= efx->vf_init_count)
520 return true;
521
522 if (vf_out)
523 *vf_out = efx->vf + vf_i;
524 if (rel_index_out)
525 *rel_index_out = abs_index % efx_vf_size(efx);
526 return false;
527}
528
529static int efx_vfdi_init_evq(struct efx_vf *vf)
530{
531 struct efx_nic *efx = vf->efx;
532 struct vfdi_req *req = vf->buf.addr;
533 unsigned vf_evq = req->u.init_evq.index;
534 unsigned buf_count = req->u.init_evq.buf_count;
535 unsigned abs_evq = abs_index(vf, vf_evq);
536 unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq);
537 efx_oword_t reg;
538
539 if (bad_vf_index(efx, vf_evq) ||
540 bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) {
541 if (net_ratelimit())
542 netif_err(efx, hw, efx->net_dev,
543 "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n",
544 vf->pci_name, vf_evq, buf_count);
545 return VFDI_RC_EINVAL;
546 }
547
327c685e 548 efx_siena_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count);
cd2d5b52
BH		 549
550 EFX_POPULATE_OWORD_3(reg,
551 FRF_CZ_TIMER_Q_EN, 1,
552 FRF_CZ_HOST_NOTIFY_MODE, 0,
553 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
554 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
555 EFX_POPULATE_OWORD_3(reg,
556 FRF_AZ_EVQ_EN, 1,
557 FRF_AZ_EVQ_SIZE, __ffs(buf_count),
558 FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
559 efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
560
561 if (vf_evq == 0) {
562 memcpy(vf->evq0_addrs, req->u.init_evq.addr,
563 buf_count * sizeof(u64));
564 vf->evq0_count = buf_count;
565 }
566
567 return VFDI_RC_SUCCESS;
568}
569
570static int efx_vfdi_init_rxq(struct efx_vf *vf)
571{
572 struct efx_nic *efx = vf->efx;
573 struct vfdi_req *req = vf->buf.addr;
574 unsigned vf_rxq = req->u.init_rxq.index;
575 unsigned vf_evq = req->u.init_rxq.evq;
576 unsigned buf_count = req->u.init_rxq.buf_count;
577 unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq);
578 unsigned label;
579 efx_oword_t reg;
580
581 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) ||
45078374 582 vf_rxq >= VF_MAX_RX_QUEUES ||
cd2d5b52
BH		 583 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
584 if (net_ratelimit())
585 netif_err(efx, hw, efx->net_dev,
586 "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d "
587 "buf_count %d\n", vf->pci_name, vf_rxq,
588 vf_evq, buf_count);
589 return VFDI_RC_EINVAL;
590 }
591 if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask))
592 ++vf->rxq_count;
327c685e 593 efx_siena_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count);
cd2d5b52
BH		 594
595 label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL);
596 EFX_POPULATE_OWORD_6(reg,
597 FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl,
598 FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
599 FRF_AZ_RX_DESCQ_LABEL, label,
600 FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count),
601 FRF_AZ_RX_DESCQ_JUMBO,
602 !!(req->u.init_rxq.flags &
603 VFDI_RXQ_FLAG_SCATTER_EN),
604 FRF_AZ_RX_DESCQ_EN, 1);
605 efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
606 abs_index(vf, vf_rxq));
607
608 return VFDI_RC_SUCCESS;
609}
610
611static int efx_vfdi_init_txq(struct efx_vf *vf)
612{
613 struct efx_nic *efx = vf->efx;
614 struct vfdi_req *req = vf->buf.addr;
615 unsigned vf_txq = req->u.init_txq.index;
616 unsigned vf_evq = req->u.init_txq.evq;
617 unsigned buf_count = req->u.init_txq.buf_count;
618 unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq);
619 unsigned label, eth_filt_en;
620 efx_oword_t reg;
621
622 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) ||
623 vf_txq >= vf_max_tx_channels ||
624 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
625 if (net_ratelimit())
626 netif_err(efx, hw, efx->net_dev,
627 "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d "
628 "buf_count %d\n", vf->pci_name, vf_txq,
629 vf_evq, buf_count);
630 return VFDI_RC_EINVAL;
631 }
632
633 mutex_lock(&vf->txq_lock);
634 if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask))
635 ++vf->txq_count;
636 mutex_unlock(&vf->txq_lock);
327c685e 637 efx_siena_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count);
cd2d5b52
BH		 638
639 eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON;
640
641 label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL);
642 EFX_POPULATE_OWORD_8(reg,
643 FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U),
644 FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en,
645 FRF_AZ_TX_DESCQ_EN, 1,
646 FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl,
647 FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
648 FRF_AZ_TX_DESCQ_LABEL, label,
649 FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count),
650 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
651 efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
652 abs_index(vf, vf_txq));
653
654 return VFDI_RC_SUCCESS;
655}
656
657/* Returns true when efx_vfdi_fini_all_queues should wake */
658static bool efx_vfdi_flush_wake(struct efx_vf *vf)
659{
660 /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */
661 smp_mb();
662
663 return (!vf->txq_count && !vf->rxq_count) ||
664 atomic_read(&vf->rxq_retry_count);
665}
666
667static void efx_vfdi_flush_clear(struct efx_vf *vf)
668{
669 memset(vf->txq_mask, 0, sizeof(vf->txq_mask));
670 vf->txq_count = 0;
671 memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask));
672 vf->rxq_count = 0;
673 memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask));
674 atomic_set(&vf->rxq_retry_count, 0);
675}
676
677static int efx_vfdi_fini_all_queues(struct efx_vf *vf)
678{
679 struct efx_nic *efx = vf->efx;
680 efx_oword_t reg;
681 unsigned count = efx_vf_size(efx);
682 unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx);
683 unsigned timeout = HZ;
684 unsigned index, rxqs_count;
c5bb0e98 685 MCDI_DECLARE_BUF(inbuf, MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX);
cd2d5b52
BH		 686 int rc;
687
45078374
BH		 688 BUILD_BUG_ON(VF_MAX_RX_QUEUES >
689 MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
690
cd2d5b52 691 rtnl_lock();
d5e8cc6c 692 siena_prepare_flush(efx);
cd2d5b52
BH		 693 rtnl_unlock();
694
695 /* Flush all the initialized queues */
696 rxqs_count = 0;
697 for (index = 0; index < count; ++index) {
698 if (test_bit(index, vf->txq_mask)) {
699 EFX_POPULATE_OWORD_2(reg,
700 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
701 FRF_AZ_TX_FLUSH_DESCQ,
702 vf_offset + index);
703 efx_writeo(efx, &reg, FR_AZ_TX_FLUSH_DESCQ);
704 }
c5bb0e98
BH		 705 if (test_bit(index, vf->rxq_mask)) {
706 MCDI_SET_ARRAY_DWORD(
707 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
708 rxqs_count, vf_offset + index);
709 rxqs_count++;
710 }
cd2d5b52
BH		 711 }
712
713 atomic_set(&vf->rxq_retry_count, 0);
714 while (timeout && (vf->rxq_count || vf->txq_count)) {
c5bb0e98
BH		 715 rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
716 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(rxqs_count),
717 NULL, 0, NULL);
cd2d5b52
BH		 718 WARN_ON(rc < 0);
719
720 timeout = wait_event_timeout(vf->flush_waitq,
721 efx_vfdi_flush_wake(vf),
722 timeout);
723 rxqs_count = 0;
724 for (index = 0; index < count; ++index) {
725 if (test_and_clear_bit(index, vf->rxq_retry_mask)) {
726 atomic_dec(&vf->rxq_retry_count);
c5bb0e98
BH		 727 MCDI_SET_ARRAY_DWORD(
728 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
729 rxqs_count, vf_offset + index);
730 rxqs_count++;
cd2d5b52
BH		 731 }
732 }
733 }
734
735 rtnl_lock();
d5e8cc6c 736 siena_finish_flush(efx);
cd2d5b52
BH		 737 rtnl_unlock();
738
739 /* Irrespective of success/failure, fini the queues */
740 EFX_ZERO_OWORD(reg);
741 for (index = 0; index < count; ++index) {
742 efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
743 vf_offset + index);
744 efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
745 vf_offset + index);
746 efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL,
747 vf_offset + index);
748 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL,
749 vf_offset + index);
750 }
327c685e
SS		 751 efx_siena_sriov_bufs(efx, vf->buftbl_base, NULL,
752 EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx));
cd2d5b52
BH		 753 efx_vfdi_flush_clear(vf);
754
755 vf->evq0_count = 0;
756
757 return timeout ? 0 : VFDI_RC_ETIMEDOUT;
758}
759
760static int efx_vfdi_insert_filter(struct efx_vf *vf)
761{
762 struct efx_nic *efx = vf->efx;
2dc313ec 763 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 764 struct vfdi_req *req = vf->buf.addr;
765 unsigned vf_rxq = req->u.mac_filter.rxq;
766 unsigned flags;
767
768 if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) {
769 if (net_ratelimit())
770 netif_err(efx, hw, efx->net_dev,
771 "ERROR: Invalid INSERT_FILTER from %s: rxq %d "
772 "flags 0x%x\n", vf->pci_name, vf_rxq,
773 req->u.mac_filter.flags);
774 return VFDI_RC_EINVAL;
775 }
776
777 flags = 0;
778 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS)
779 flags |= EFX_FILTER_FLAG_RX_RSS;
780 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER)
781 flags |= EFX_FILTER_FLAG_RX_SCATTER;
782 vf->rx_filter_flags = flags;
783 vf->rx_filter_qid = vf_rxq;
784 vf->rx_filtering = true;
785
327c685e 786 efx_siena_sriov_reset_rx_filter(vf);
2dc313ec 787 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 788
789 return VFDI_RC_SUCCESS;
790}
791
792static int efx_vfdi_remove_all_filters(struct efx_vf *vf)
793{
2dc313ec
SS		 794 struct efx_nic *efx = vf->efx;
795 struct siena_nic_data *nic_data = efx->nic_data;
796
cd2d5b52 797 vf->rx_filtering = false;
327c685e 798 efx_siena_sriov_reset_rx_filter(vf);
2dc313ec 799 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 800
801 return VFDI_RC_SUCCESS;
802}
803
804static int efx_vfdi_set_status_page(struct efx_vf *vf)
805{
806 struct efx_nic *efx = vf->efx;
2dc313ec 807 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52 808 struct vfdi_req *req = vf->buf.addr;
01cb543d
BH		 809 u64 page_count = req->u.set_status_page.peer_page_count;
810 u64 max_page_count =
811 (EFX_PAGE_SIZE -
812 offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0]))
813 / sizeof(req->u.set_status_page.peer_page_addr[0]);
cd2d5b52 814
01cb543d 815 if (!req->u.set_status_page.dma_addr || page_count > max_page_count) {
cd2d5b52
BH		 816 if (net_ratelimit())
817 netif_err(efx, hw, efx->net_dev,
818 "ERROR: Invalid SET_STATUS_PAGE from %s\n",
819 vf->pci_name);
820 return VFDI_RC_EINVAL;
821 }
822
2dc313ec 823 mutex_lock(&nic_data->local_lock);
cd2d5b52
BH		 824 mutex_lock(&vf->status_lock);
825 vf->status_addr = req->u.set_status_page.dma_addr;
826
827 kfree(vf->peer_page_addrs);
828 vf->peer_page_addrs = NULL;
829 vf->peer_page_count = 0;
830
831 if (page_count) {
832 vf->peer_page_addrs = kcalloc(page_count, sizeof(u64),
833 GFP_KERNEL);
834 if (vf->peer_page_addrs) {
835 memcpy(vf->peer_page_addrs,
836 req->u.set_status_page.peer_page_addr,
837 page_count * sizeof(u64));
838 vf->peer_page_count = page_count;
839 }
840 }
841
327c685e 842 __efx_siena_sriov_push_vf_status(vf);
cd2d5b52 843 mutex_unlock(&vf->status_lock);
2dc313ec 844 mutex_unlock(&nic_data->local_lock);
cd2d5b52
BH		 845
846 return VFDI_RC_SUCCESS;
847}
848
849static int efx_vfdi_clear_status_page(struct efx_vf *vf)
850{
851 mutex_lock(&vf->status_lock);
852 vf->status_addr = 0;
853 mutex_unlock(&vf->status_lock);
854
855 return VFDI_RC_SUCCESS;
856}
857
858typedef int (*efx_vfdi_op_t)(struct efx_vf *vf);
859
860static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = {
861 [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq,
862 [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq,
863 [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq,
864 [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues,
865 [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter,
866 [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters,
867 [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page,
868 [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page,
869};
870
327c685e 871static void efx_siena_sriov_vfdi(struct work_struct *work)
cd2d5b52
BH		 872{
873 struct efx_vf *vf = container_of(work, struct efx_vf, req);
874 struct efx_nic *efx = vf->efx;
875 struct vfdi_req *req = vf->buf.addr;
876 struct efx_memcpy_req copy[2];
877 int rc;
878
879 /* Copy this page into the local address space */
880 memset(copy, '\0', sizeof(copy));
881 copy[0].from_rid = vf->pci_rid;
882 copy[0].from_addr = vf->req_addr;
883 copy[0].to_rid = efx->pci_dev->devfn;
884 copy[0].to_addr = vf->buf.dma_addr;
885 copy[0].length = EFX_PAGE_SIZE;
327c685e 886 rc = efx_siena_sriov_memcpy(efx, copy, 1);
cd2d5b52
BH		 887 if (rc) {
888 /* If we can't get the request, we can't reply to the caller */
889 if (net_ratelimit())
890 netif_err(efx, hw, efx->net_dev,
891 "ERROR: Unable to fetch VFDI request from %s rc %d\n",
892 vf->pci_name, -rc);
893 vf->busy = false;
894 return;
895 }
896
897 if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) {
898 rc = vfdi_ops[req->op](vf);
899 if (rc == 0) {
900 netif_dbg(efx, hw, efx->net_dev,
901 "vfdi request %d from %s ok\n",
902 req->op, vf->pci_name);
903 }
904 } else {
905 netif_dbg(efx, hw, efx->net_dev,
906 "ERROR: Unrecognised request %d from VF %s addr "
907 "%llx\n", req->op, vf->pci_name,
908 (unsigned long long)vf->req_addr);
909 rc = VFDI_RC_EOPNOTSUPP;
910 }
911
912 /* Allow subsequent VF requests */
913 vf->busy = false;
914 smp_wmb();
915
916 /* Respond to the request */
917 req->rc = rc;
918 req->op = VFDI_OP_RESPONSE;
919
920 memset(copy, '\0', sizeof(copy));
921 copy[0].from_buf = &req->rc;
922 copy[0].to_rid = vf->pci_rid;
923 copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc);
924 copy[0].length = sizeof(req->rc);
925 copy[1].from_buf = &req->op;
926 copy[1].to_rid = vf->pci_rid;
927 copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op);
928 copy[1].length = sizeof(req->op);
929
327c685e 930 (void)efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
cd2d5b52
BH		 931}
932
933
934
935/* After a reset the event queues inside the guests no longer exist. Fill the
936 * event ring in guest memory with VFDI reset events, then (re-initialise) the
937 * event queue to raise an interrupt. The guest driver will then recover.
938 */
327c685e
SS		 939static void efx_siena_sriov_reset_vf(struct efx_vf *vf,
940 struct efx_buffer *buffer)
cd2d5b52
BH		 941{
942 struct efx_nic *efx = vf->efx;
943 struct efx_memcpy_req copy_req[4];
944 efx_qword_t event;
945 unsigned int pos, count, k, buftbl, abs_evq;
946 efx_oword_t reg;
947 efx_dword_t ptr;
948 int rc;
949
950 BUG_ON(buffer->len != EFX_PAGE_SIZE);
951
952 if (!vf->evq0_count)
953 return;
954 BUG_ON(vf->evq0_count & (vf->evq0_count - 1));
955
956 mutex_lock(&vf->status_lock);
957 EFX_POPULATE_QWORD_3(event,
958 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
959 VFDI_EV_SEQ, vf->msg_seqno,
960 VFDI_EV_TYPE, VFDI_EV_TYPE_RESET);
961 vf->msg_seqno++;
962 for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event))
963 memcpy(buffer->addr + pos, &event, sizeof(event));
964
965 for (pos = 0; pos < vf->evq0_count; pos += count) {
966 count = min_t(unsigned, vf->evq0_count - pos,
967 ARRAY_SIZE(copy_req));
968 for (k = 0; k < count; k++) {
969 copy_req[k].from_buf = NULL;
970 copy_req[k].from_rid = efx->pci_dev->devfn;
971 copy_req[k].from_addr = buffer->dma_addr;
972 copy_req[k].to_rid = vf->pci_rid;
973 copy_req[k].to_addr = vf->evq0_addrs[pos + k];
974 copy_req[k].length = EFX_PAGE_SIZE;
975 }
327c685e 976 rc = efx_siena_sriov_memcpy(efx, copy_req, count);
cd2d5b52
BH		 977 if (rc) {
978 if (net_ratelimit())
979 netif_err(efx, hw, efx->net_dev,
980 "ERROR: Unable to notify %s of reset"
981 ": %d\n", vf->pci_name, -rc);
982 break;
983 }
984 }
985
986 /* Reinitialise, arm and trigger evq0 */
987 abs_evq = abs_index(vf, 0);
988 buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0);
327c685e 989 efx_siena_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count);
cd2d5b52
BH		 990
991 EFX_POPULATE_OWORD_3(reg,
992 FRF_CZ_TIMER_Q_EN, 1,
993 FRF_CZ_HOST_NOTIFY_MODE, 0,
994 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
995 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
996 EFX_POPULATE_OWORD_3(reg,
997 FRF_AZ_EVQ_EN, 1,
998 FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count),
999 FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
1000 efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
1001 EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0);
778cdaf6 1002 efx_writed(efx, &ptr, FR_BZ_EVQ_RPTR + FR_BZ_EVQ_RPTR_STEP * abs_evq);
cd2d5b52
BH		 1003
1004 mutex_unlock(&vf->status_lock);
1005}
1006
327c685e 1007static void efx_siena_sriov_reset_vf_work(struct work_struct *work)
cd2d5b52
BH		 1008{
1009 struct efx_vf *vf = container_of(work, struct efx_vf, req);
1010 struct efx_nic *efx = vf->efx;
1011 struct efx_buffer buf;
1012
0d19a540 1013 if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) {
327c685e 1014 efx_siena_sriov_reset_vf(vf, &buf);
cd2d5b52
BH		 1015 efx_nic_free_buffer(efx, &buf);
1016 }
1017}
1018
327c685e 1019static void efx_siena_sriov_handle_no_channel(struct efx_nic *efx)
cd2d5b52
BH		 1020{
1021 netif_err(efx, drv, efx->net_dev,
1022 "ERROR: IOV requires MSI-X and 1 additional interrupt"
1023 "vector. IOV disabled\n");
1024 efx->vf_count = 0;
1025}
1026
327c685e 1027static int efx_siena_sriov_probe_channel(struct efx_channel *channel)
cd2d5b52 1028{
2dc313ec
SS		 1029 struct siena_nic_data *nic_data = channel->efx->nic_data;
1030 nic_data->vfdi_channel = channel;
1031
cd2d5b52
BH		 1032 return 0;
1033}
1034
1035static void
327c685e
SS		 1036efx_siena_sriov_get_channel_name(struct efx_channel *channel,
1037 char *buf, size_t len)
cd2d5b52
BH		 1038{
1039 snprintf(buf, len, "%s-iov", channel->efx->name);
1040}
1041
327c685e
SS		 1042static const struct efx_channel_type efx_siena_sriov_channel_type = {
1043 .handle_no_channel = efx_siena_sriov_handle_no_channel,
1044 .pre_probe = efx_siena_sriov_probe_channel,
726ba0e1 1045 .post_remove = efx_channel_dummy_op_void,
327c685e 1046 .get_name = efx_siena_sriov_get_channel_name,
cd2d5b52
BH		 1047 /* no copy operation; channel must not be reallocated */
1048 .keep_eventq = true,
1049};
1050
327c685e 1051void efx_siena_sriov_probe(struct efx_nic *efx)
cd2d5b52
BH		 1052{
1053 unsigned count;
1054
1055 if (!max_vfs)
1056 return;
1057
327c685e 1058 if (efx_siena_sriov_cmd(efx, false, &efx->vi_scale, &count))
cd2d5b52
BH		 1059 return;
1060 if (count > 0 && count > max_vfs)
1061 count = max_vfs;
1062
1063 /* efx_nic_dimension_resources() will reduce vf_count as appopriate */
1064 efx->vf_count = count;
1065
327c685e 1066 efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_siena_sriov_channel_type;
cd2d5b52
BH		 1067}
1068
1069/* Copy the list of individual addresses into the vfdi_status.peers
1070 * array and auxillary pages, protected by %local_lock. Drop that lock
1071 * and then broadcast the address list to every VF.
1072 */
327c685e 1073static void efx_siena_sriov_peer_work(struct work_struct *data)
cd2d5b52 1074{
2dc313ec
SS		 1075 struct siena_nic_data *nic_data = container_of(data,
1076 struct siena_nic_data,
1077 peer_work);
1078 struct efx_nic *efx = nic_data->efx;
1079 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 1080 struct efx_vf *vf;
1081 struct efx_local_addr *local_addr;
1082 struct vfdi_endpoint *peer;
1083 struct efx_endpoint_page *epp;
1084 struct list_head pages;
1085 unsigned int peer_space;
1086 unsigned int peer_count;
1087 unsigned int pos;
1088
2dc313ec 1089 mutex_lock(&nic_data->local_lock);
cd2d5b52
BH		 1090
1091 /* Move the existing peer pages off %local_page_list */
1092 INIT_LIST_HEAD(&pages);
2dc313ec 1093 list_splice_tail_init(&nic_data->local_page_list, &pages);
cd2d5b52
BH		 1094
1095 /* Populate the VF addresses starting from entry 1 (entry 0 is
1096 * the PF address)
1097 */
1098 peer = vfdi_status->peers + 1;
1099 peer_space = ARRAY_SIZE(vfdi_status->peers) - 1;
1100 peer_count = 1;
1101 for (pos = 0; pos < efx->vf_count; ++pos) {
1102 vf = efx->vf + pos;
1103
1104 mutex_lock(&vf->status_lock);
1105 if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) {
1106 *peer++ = vf->addr;
1107 ++peer_count;
1108 --peer_space;
1109 BUG_ON(peer_space == 0);
1110 }
1111 mutex_unlock(&vf->status_lock);
1112 }
1113
1114 /* Fill the remaining addresses */
2dc313ec 1115 list_for_each_entry(local_addr, &nic_data->local_addr_list, link) {
cd84ff4d 1116 ether_addr_copy(peer->mac_addr, local_addr->addr);
cd2d5b52
BH		 1117 peer->tci = 0;
1118 ++peer;
1119 ++peer_count;
1120 if (--peer_space == 0) {
1121 if (list_empty(&pages)) {
1122 epp = kmalloc(sizeof(*epp), GFP_KERNEL);
1123 if (!epp)
1124 break;
1125 epp->ptr = dma_alloc_coherent(
1126 &efx->pci_dev->dev, EFX_PAGE_SIZE,
1127 &epp->addr, GFP_KERNEL);
1128 if (!epp->ptr) {
1129 kfree(epp);
1130 break;
1131 }
1132 } else {
1133 epp = list_first_entry(
1134 &pages, struct efx_endpoint_page, link);
1135 list_del(&epp->link);
1136 }
1137
2dc313ec 1138 list_add_tail(&epp->link, &nic_data->local_page_list);
cd2d5b52
BH		 1139 peer = (struct vfdi_endpoint *)epp->ptr;
1140 peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint);
1141 }
1142 }
1143 vfdi_status->peer_count = peer_count;
2dc313ec 1144 mutex_unlock(&nic_data->local_lock);
cd2d5b52
BH		 1145
1146 /* Free any now unused endpoint pages */
1147 while (!list_empty(&pages)) {
1148 epp = list_first_entry(
1149 &pages, struct efx_endpoint_page, link);
1150 list_del(&epp->link);
1151 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
1152 epp->ptr, epp->addr);
1153 kfree(epp);
1154 }
1155
1156 /* Finally, push the pages */
1157 for (pos = 0; pos < efx->vf_count; ++pos) {
1158 vf = efx->vf + pos;
1159
1160 mutex_lock(&vf->status_lock);
1161 if (vf->status_addr)
327c685e 1162 __efx_siena_sriov_push_vf_status(vf);
cd2d5b52
BH		 1163 mutex_unlock(&vf->status_lock);
1164 }
1165}
1166
327c685e 1167static void efx_siena_sriov_free_local(struct efx_nic *efx)
cd2d5b52 1168{
2dc313ec 1169 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1170 struct efx_local_addr *local_addr;
1171 struct efx_endpoint_page *epp;
1172
2dc313ec
SS		 1173 while (!list_empty(&nic_data->local_addr_list)) {
1174 local_addr = list_first_entry(&nic_data->local_addr_list,
cd2d5b52
BH		 1175 struct efx_local_addr, link);
1176 list_del(&local_addr->link);
1177 kfree(local_addr);
1178 }
1179
2dc313ec
SS		 1180 while (!list_empty(&nic_data->local_page_list)) {
1181 epp = list_first_entry(&nic_data->local_page_list,
cd2d5b52
BH		 1182 struct efx_endpoint_page, link);
1183 list_del(&epp->link);
1184 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
1185 epp->ptr, epp->addr);
1186 kfree(epp);
1187 }
1188}
1189
327c685e 1190static int efx_siena_sriov_vf_alloc(struct efx_nic *efx)
cd2d5b52
BH		 1191{
1192 unsigned index;
1193 struct efx_vf *vf;
1194
1195 efx->vf = kzalloc(sizeof(struct efx_vf) * efx->vf_count, GFP_KERNEL);
1196 if (!efx->vf)
1197 return -ENOMEM;
1198
1199 for (index = 0; index < efx->vf_count; ++index) {
1200 vf = efx->vf + index;
1201
1202 vf->efx = efx;
1203 vf->index = index;
1204 vf->rx_filter_id = -1;
1205 vf->tx_filter_mode = VF_TX_FILTER_AUTO;
1206 vf->tx_filter_id = -1;
327c685e
SS		 1207 INIT_WORK(&vf->req, efx_siena_sriov_vfdi);
1208 INIT_WORK(&vf->reset_work, efx_siena_sriov_reset_vf_work);
cd2d5b52
BH		 1209 init_waitqueue_head(&vf->flush_waitq);
1210 mutex_init(&vf->status_lock);
1211 mutex_init(&vf->txq_lock);
1212 }
1213
1214 return 0;
1215}
1216
327c685e 1217static void efx_siena_sriov_vfs_fini(struct efx_nic *efx)
cd2d5b52
BH		 1218{
1219 struct efx_vf *vf;
1220 unsigned int pos;
1221
1222 for (pos = 0; pos < efx->vf_count; ++pos) {
1223 vf = efx->vf + pos;
1224
1225 efx_nic_free_buffer(efx, &vf->buf);
1226 kfree(vf->peer_page_addrs);
1227 vf->peer_page_addrs = NULL;
1228 vf->peer_page_count = 0;
1229
1230 vf->evq0_count = 0;
1231 }
1232}
1233
327c685e 1234static int efx_siena_sriov_vfs_init(struct efx_nic *efx)
cd2d5b52
BH		 1235{
1236 struct pci_dev *pci_dev = efx->pci_dev;
2dc313ec 1237 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1238 unsigned index, devfn, sriov, buftbl_base;
1239 u16 offset, stride;
1240 struct efx_vf *vf;
1241 int rc;
1242
1243 sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV);
1244 if (!sriov)
1245 return -ENOENT;
1246
1247 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset);
1248 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride);
1249
2dc313ec 1250 buftbl_base = nic_data->vf_buftbl_base;
cd2d5b52
BH		 1251 devfn = pci_dev->devfn + offset;
1252 for (index = 0; index < efx->vf_count; ++index) {
1253 vf = efx->vf + index;
1254
1255 /* Reserve buffer entries */
1256 vf->buftbl_base = buftbl_base;
1257 buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx);
1258
1259 vf->pci_rid = devfn;
1260 snprintf(vf->pci_name, sizeof(vf->pci_name),
1261 "%04x:%02x:%02x.%d",
1262 pci_domain_nr(pci_dev->bus), pci_dev->bus->number,
1263 PCI_SLOT(devfn), PCI_FUNC(devfn));
1264
0d19a540
BH		 1265 rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE,
1266 GFP_KERNEL);
cd2d5b52
BH		 1267 if (rc)
1268 goto fail;
1269
1270 devfn += stride;
1271 }
1272
1273 return 0;
1274
1275fail:
327c685e 1276 efx_siena_sriov_vfs_fini(efx);
cd2d5b52
BH		 1277 return rc;
1278}
1279
327c685e 1280int efx_siena_sriov_init(struct efx_nic *efx)
cd2d5b52
BH		 1281{
1282 struct net_device *net_dev = efx->net_dev;
2dc313ec 1283 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1284 struct vfdi_status *vfdi_status;
1285 int rc;
1286
1287 /* Ensure there's room for vf_channel */
1288 BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE);
1289 /* Ensure that VI_BASE is aligned on VI_SCALE */
1290 BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1));
1291
1292 if (efx->vf_count == 0)
1293 return 0;
1294
327c685e 1295 rc = efx_siena_sriov_cmd(efx, true, NULL, NULL);
cd2d5b52
BH		 1296 if (rc)
1297 goto fail_cmd;
1298
2dc313ec
SS		 1299 rc = efx_nic_alloc_buffer(efx, &nic_data->vfdi_status,
1300 sizeof(*vfdi_status), GFP_KERNEL);
cd2d5b52
BH		 1301 if (rc)
1302 goto fail_status;
2dc313ec 1303 vfdi_status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 1304 memset(vfdi_status, 0, sizeof(*vfdi_status));
1305 vfdi_status->version = 1;
1306 vfdi_status->length = sizeof(*vfdi_status);
1307 vfdi_status->max_tx_channels = vf_max_tx_channels;
1308 vfdi_status->vi_scale = efx->vi_scale;
1309 vfdi_status->rss_rxq_count = efx->rss_spread;
1310 vfdi_status->peer_count = 1 + efx->vf_count;
1311 vfdi_status->timer_quantum_ns = efx->timer_quantum_ns;
1312
327c685e 1313 rc = efx_siena_sriov_vf_alloc(efx);
cd2d5b52
BH		 1314 if (rc)
1315 goto fail_alloc;
1316
2dc313ec 1317 mutex_init(&nic_data->local_lock);
327c685e 1318 INIT_WORK(&nic_data->peer_work, efx_siena_sriov_peer_work);
2dc313ec
SS		 1319 INIT_LIST_HEAD(&nic_data->local_addr_list);
1320 INIT_LIST_HEAD(&nic_data->local_page_list);
cd2d5b52 1321
327c685e 1322 rc = efx_siena_sriov_vfs_init(efx);
cd2d5b52
BH		 1323 if (rc)
1324 goto fail_vfs;
1325
1326 rtnl_lock();
cd84ff4d 1327 ether_addr_copy(vfdi_status->peers[0].mac_addr, net_dev->dev_addr);
cd2d5b52
BH		 1328 efx->vf_init_count = efx->vf_count;
1329 rtnl_unlock();
1330
327c685e 1331 efx_siena_sriov_usrev(efx, true);
cd2d5b52
BH		 1332
1333 /* At this point we must be ready to accept VFDI requests */
1334
1335 rc = pci_enable_sriov(efx->pci_dev, efx->vf_count);
1336 if (rc)
1337 goto fail_pci;
1338
1339 netif_info(efx, probe, net_dev,
1340 "enabled SR-IOV for %d VFs, %d VI per VF\n",
1341 efx->vf_count, efx_vf_size(efx));
1342 return 0;
1343
1344fail_pci:
327c685e 1345 efx_siena_sriov_usrev(efx, false);
cd2d5b52
BH		 1346 rtnl_lock();
1347 efx->vf_init_count = 0;
1348 rtnl_unlock();
327c685e 1349 efx_siena_sriov_vfs_fini(efx);
cd2d5b52 1350fail_vfs:
2dc313ec 1351 cancel_work_sync(&nic_data->peer_work);
327c685e 1352 efx_siena_sriov_free_local(efx);
cd2d5b52
BH		 1353 kfree(efx->vf);
1354fail_alloc:
2dc313ec 1355 efx_nic_free_buffer(efx, &nic_data->vfdi_status);
cd2d5b52 1356fail_status:
327c685e 1357 efx_siena_sriov_cmd(efx, false, NULL, NULL);
cd2d5b52
BH		 1358fail_cmd:
1359 return rc;
1360}
1361
327c685e 1362void efx_siena_sriov_fini(struct efx_nic *efx)
cd2d5b52
BH		 1363{
1364 struct efx_vf *vf;
1365 unsigned int pos;
2dc313ec 1366 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1367
1368 if (efx->vf_init_count == 0)
1369 return;
1370
1371 /* Disable all interfaces to reconfiguration */
2dc313ec 1372 BUG_ON(nic_data->vfdi_channel->enabled);
327c685e 1373 efx_siena_sriov_usrev(efx, false);
cd2d5b52
BH		 1374 rtnl_lock();
1375 efx->vf_init_count = 0;
1376 rtnl_unlock();
1377
1378 /* Flush all reconfiguration work */
1379 for (pos = 0; pos < efx->vf_count; ++pos) {
1380 vf = efx->vf + pos;
1381 cancel_work_sync(&vf->req);
1382 cancel_work_sync(&vf->reset_work);
1383 }
2dc313ec 1384 cancel_work_sync(&nic_data->peer_work);
cd2d5b52
BH		 1385
1386 pci_disable_sriov(efx->pci_dev);
1387
1388 /* Tear down back-end state */
327c685e
SS		 1389 efx_siena_sriov_vfs_fini(efx);
1390 efx_siena_sriov_free_local(efx);
cd2d5b52 1391 kfree(efx->vf);
2dc313ec 1392 efx_nic_free_buffer(efx, &nic_data->vfdi_status);
327c685e 1393 efx_siena_sriov_cmd(efx, false, NULL, NULL);
cd2d5b52
BH		 1394}
1395
327c685e 1396void efx_siena_sriov_event(struct efx_channel *channel, efx_qword_t *event)
cd2d5b52
BH		 1397{
1398 struct efx_nic *efx = channel->efx;
1399 struct efx_vf *vf;
1400 unsigned qid, seq, type, data;
1401
1402 qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID);
1403
1404 /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */
1405 BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0);
1406 seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ);
1407 type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE);
1408 data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA);
1409
1410 netif_vdbg(efx, hw, efx->net_dev,
1411 "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n",
1412 qid, seq, type, data);
1413
1414 if (map_vi_index(efx, qid, &vf, NULL))
1415 return;
1416 if (vf->busy)
1417 goto error;
1418
1419 if (type == VFDI_EV_TYPE_REQ_WORD0) {
1420 /* Resynchronise */
1421 vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
1422 vf->req_seqno = seq + 1;
1423 vf->req_addr = 0;
1424 } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type)
1425 goto error;
1426
1427 switch (vf->req_type) {
1428 case VFDI_EV_TYPE_REQ_WORD0:
1429 case VFDI_EV_TYPE_REQ_WORD1:
1430 case VFDI_EV_TYPE_REQ_WORD2:
1431 vf->req_addr |= (u64)data << (vf->req_type << 4);
1432 ++vf->req_type;
1433 return;
1434
1435 case VFDI_EV_TYPE_REQ_WORD3:
1436 vf->req_addr |= (u64)data << 48;
1437 vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
1438 vf->busy = true;
1439 queue_work(vfdi_workqueue, &vf->req);
1440 return;
1441 }
1442
1443error:
1444 if (net_ratelimit())
1445 netif_err(efx, hw, efx->net_dev,
1446 "ERROR: Screaming VFDI request from %s\n",
1447 vf->pci_name);
1448 /* Reset the request and sequence number */
1449 vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
1450 vf->req_seqno = seq + 1;
1451}
1452
327c685e 1453void efx_siena_sriov_flr(struct efx_nic *efx, unsigned vf_i)
cd2d5b52
BH		 1454{
1455 struct efx_vf *vf;
1456
1457 if (vf_i > efx->vf_init_count)
1458 return;
1459 vf = efx->vf + vf_i;
1460 netif_info(efx, hw, efx->net_dev,
1461 "FLR on VF %s\n", vf->pci_name);
1462
1463 vf->status_addr = 0;
1464 efx_vfdi_remove_all_filters(vf);
1465 efx_vfdi_flush_clear(vf);
1466
1467 vf->evq0_count = 0;
1468}
1469
327c685e 1470void efx_siena_sriov_mac_address_changed(struct efx_nic *efx)
cd2d5b52 1471{
2dc313ec
SS		 1472 struct siena_nic_data *nic_data = efx->nic_data;
1473 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 1474
1475 if (!efx->vf_init_count)
1476 return;
cd84ff4d
EC		 1477 ether_addr_copy(vfdi_status->peers[0].mac_addr,
1478 efx->net_dev->dev_addr);
2dc313ec 1479 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 1480}
1481
327c685e 1482void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
cd2d5b52
BH		 1483{
1484 struct efx_vf *vf;
1485 unsigned queue, qid;
1486
1487 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1488 if (map_vi_index(efx, queue, &vf, &qid))
1489 return;
1490 /* Ignore flush completions triggered by an FLR */
1491 if (!test_bit(qid, vf->txq_mask))
1492 return;
1493
1494 __clear_bit(qid, vf->txq_mask);
1495 --vf->txq_count;
1496
1497 if (efx_vfdi_flush_wake(vf))
1498 wake_up(&vf->flush_waitq);
1499}
1500
327c685e 1501void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
cd2d5b52
BH		 1502{
1503 struct efx_vf *vf;
1504 unsigned ev_failed, queue, qid;
1505
1506 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1507 ev_failed = EFX_QWORD_FIELD(*event,
1508 FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1509 if (map_vi_index(efx, queue, &vf, &qid))
1510 return;
1511 if (!test_bit(qid, vf->rxq_mask))
1512 return;
1513
1514 if (ev_failed) {
1515 set_bit(qid, vf->rxq_retry_mask);
1516 atomic_inc(&vf->rxq_retry_count);
1517 } else {
1518 __clear_bit(qid, vf->rxq_mask);
1519 --vf->rxq_count;
1520 }
1521 if (efx_vfdi_flush_wake(vf))
1522 wake_up(&vf->flush_waitq);
1523}
1524
1525/* Called from napi. Schedule the reset work item */
327c685e 1526void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq)
cd2d5b52
BH		 1527{
1528 struct efx_vf *vf;
1529 unsigned int rel;
1530
1531 if (map_vi_index(efx, dmaq, &vf, &rel))
1532 return;
1533
1534 if (net_ratelimit())
1535 netif_err(efx, hw, efx->net_dev,
1536 "VF %d DMA Q %d reports descriptor fetch error.\n",
1537 vf->index, rel);
1538 queue_work(vfdi_workqueue, &vf->reset_work);
1539}
1540
1541/* Reset all VFs */
327c685e 1542void efx_siena_sriov_reset(struct efx_nic *efx)
cd2d5b52
BH		 1543{
1544 unsigned int vf_i;
1545 struct efx_buffer buf;
1546 struct efx_vf *vf;
1547
1548 ASSERT_RTNL();
1549
1550 if (efx->vf_init_count == 0)
1551 return;
1552
327c685e
SS		 1553 efx_siena_sriov_usrev(efx, true);
1554 (void)efx_siena_sriov_cmd(efx, true, NULL, NULL);
cd2d5b52 1555
0d19a540 1556 if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO))
cd2d5b52
BH		 1557 return;
1558
1559 for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) {
1560 vf = efx->vf + vf_i;
327c685e 1561 efx_siena_sriov_reset_vf(vf, &buf);
cd2d5b52
BH		 1562 }
1563
1564 efx_nic_free_buffer(efx, &buf);
1565}
1566
1567int efx_init_sriov(void)
1568{
327c685e
SS		 1569 /* A single threaded workqueue is sufficient. efx_siena_sriov_vfdi() and
1570 * efx_siena_sriov_peer_work() spend almost all their time sleeping for
cd2d5b52
BH		 1571 * MCDI to complete anyway
1572 */
1573 vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi");
1574 if (!vfdi_workqueue)
1575 return -ENOMEM;
1576
1577 return 0;
1578}
1579
1580void efx_fini_sriov(void)
1581{
1582 destroy_workqueue(vfdi_workqueue);
1583}
1584
327c685e 1585int efx_siena_sriov_set_vf_mac(struct net_device *net_dev, int vf_i, u8 *mac)
cd2d5b52
BH		 1586{
1587 struct efx_nic *efx = netdev_priv(net_dev);
1588 struct efx_vf *vf;
1589
1590 if (vf_i >= efx->vf_init_count)
1591 return -EINVAL;
1592 vf = efx->vf + vf_i;
1593
1594 mutex_lock(&vf->status_lock);
cd84ff4d 1595 ether_addr_copy(vf->addr.mac_addr, mac);
327c685e 1596 __efx_siena_sriov_update_vf_addr(vf);
cd2d5b52
BH		 1597 mutex_unlock(&vf->status_lock);
1598
1599 return 0;
1600}
1601
327c685e
SS		 1602int efx_siena_sriov_set_vf_vlan(struct net_device *net_dev, int vf_i,
1603 u16 vlan, u8 qos)
cd2d5b52
BH		 1604{
1605 struct efx_nic *efx = netdev_priv(net_dev);
1606 struct efx_vf *vf;
1607 u16 tci;
1608
1609 if (vf_i >= efx->vf_init_count)
1610 return -EINVAL;
1611 vf = efx->vf + vf_i;
1612
1613 mutex_lock(&vf->status_lock);
1614 tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT);
1615 vf->addr.tci = htons(tci);
327c685e 1616 __efx_siena_sriov_update_vf_addr(vf);
cd2d5b52
BH		 1617 mutex_unlock(&vf->status_lock);
1618
1619 return 0;
1620}
1621
327c685e
SS		 1622int efx_siena_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf_i,
1623 bool spoofchk)
cd2d5b52
BH		 1624{
1625 struct efx_nic *efx = netdev_priv(net_dev);
1626 struct efx_vf *vf;
1627 int rc;
1628
1629 if (vf_i >= efx->vf_init_count)
1630 return -EINVAL;
1631 vf = efx->vf + vf_i;
1632
1633 mutex_lock(&vf->txq_lock);
1634 if (vf->txq_count == 0) {
1635 vf->tx_filter_mode =
1636 spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF;
1637 rc = 0;
1638 } else {
1639 /* This cannot be changed while TX queues are running */
1640 rc = -EBUSY;
1641 }
1642 mutex_unlock(&vf->txq_lock);
1643 return rc;
1644}
1645
327c685e
SS		 1646int efx_siena_sriov_get_vf_config(struct net_device *net_dev, int vf_i,
1647 struct ifla_vf_info *ivi)
cd2d5b52
BH		 1648{
1649 struct efx_nic *efx = netdev_priv(net_dev);
1650 struct efx_vf *vf;
1651 u16 tci;
1652
1653 if (vf_i >= efx->vf_init_count)
1654 return -EINVAL;
1655 vf = efx->vf + vf_i;
1656
1657 ivi->vf = vf_i;
cd84ff4d 1658 ether_addr_copy(ivi->mac, vf->addr.mac_addr);
ed616689
SC		 1659 ivi->max_tx_rate = 0;
1660 ivi->min_tx_rate = 0;
cd2d5b52
BH		 1661 tci = ntohs(vf->addr.tci);
1662 ivi->vlan = tci & VLAN_VID_MASK;
1663 ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7;
1664 ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON;
1665
1666 return 0;
1667}
1668
Linux kernel - Deliverables
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