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sfc: Own header for nic-specific sriov functions, single instance of netdev_ops and...
[deliverable/linux.git] / drivers / net / ethernet / sfc / siena_sriov.c
CommitLineData
cd2d5b52 1/****************************************************************************
f7a6d2c4
BH		 2 * Driver for Solarflare network controllers and boards
3 * Copyright 2010-2012 Solarflare Communications Inc.
cd2d5b52
BH		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9#include <linux/pci.h>
10#include <linux/module.h>
11#include "net_driver.h"
12#include "efx.h"
13#include "nic.h"
14#include "io.h"
15#include "mcdi.h"
16#include "filter.h"
17#include "mcdi_pcol.h"
8b8a95a1 18#include "farch_regs.h"
7fa8d547 19#include "siena_sriov.h"
cd2d5b52
BH		 20#include "vfdi.h"
21
22/* Number of longs required to track all the VIs in a VF */
23#define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX)
24
45078374
BH		 25/* Maximum number of RX queues supported */
26#define VF_MAX_RX_QUEUES 63
27
cd2d5b52
BH		 28/**
29 * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour
30 * @VF_TX_FILTER_OFF: Disabled
31 * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only
32 * 2 TX queues allowed per VF.
33 * @VF_TX_FILTER_ON: Enabled
34 */
35enum efx_vf_tx_filter_mode {
36 VF_TX_FILTER_OFF,
37 VF_TX_FILTER_AUTO,
38 VF_TX_FILTER_ON,
39};
40
41/**
42 * struct efx_vf - Back-end resource and protocol state for a PCI VF
43 * @efx: The Efx NIC owning this VF
44 * @pci_rid: The PCI requester ID for this VF
45 * @pci_name: The PCI name (formatted address) of this VF
46 * @index: Index of VF within its port and PF.
47 * @req: VFDI incoming request work item. Incoming USR_EV events are received
48 * by the NAPI handler, but must be handled by executing MCDI requests
49 * inside a work item.
50 * @req_addr: VFDI incoming request DMA address (in VF's PCI address space).
51 * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member.
52 * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member.
53 * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by
54 * @status_lock
55 * @busy: VFDI request queued to be processed or being processed. Receiving
56 * a VFDI request when @busy is set is an error condition.
57 * @buf: Incoming VFDI requests are DMA from the VF into this buffer.
58 * @buftbl_base: Buffer table entries for this VF start at this index.
59 * @rx_filtering: Receive filtering has been requested by the VF driver.
60 * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request.
61 * @rx_filter_qid: VF relative qid for RX filter requested by VF.
62 * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported.
63 * @tx_filter_mode: Transmit MAC filtering mode.
64 * @tx_filter_id: Transmit MAC filter ID.
65 * @addr: The MAC address and outer vlan tag of the VF.
66 * @status_addr: VF DMA address of page for &struct vfdi_status updates.
67 * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr,
68 * @peer_page_addrs and @peer_page_count from simultaneous
69 * updates by the VM and consumption by
327c685e 70 * efx_siena_sriov_update_vf_addr()
cd2d5b52
BH		 71 * @peer_page_addrs: Pointer to an array of guest pages for local addresses.
72 * @peer_page_count: Number of entries in @peer_page_count.
73 * @evq0_addrs: Array of guest pages backing evq0.
74 * @evq0_count: Number of entries in @evq0_addrs.
75 * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler
76 * to wait for flush completions.
77 * @txq_lock: Mutex for TX queue allocation.
78 * @txq_mask: Mask of initialized transmit queues.
79 * @txq_count: Number of initialized transmit queues.
80 * @rxq_mask: Mask of initialized receive queues.
81 * @rxq_count: Number of initialized receive queues.
82 * @rxq_retry_mask: Mask or receive queues that need to be flushed again
83 * due to flush failure.
84 * @rxq_retry_count: Number of receive queues in @rxq_retry_mask.
85 * @reset_work: Work item to schedule a VF reset.
86 */
87struct efx_vf {
88 struct efx_nic *efx;
89 unsigned int pci_rid;
90 char pci_name[13]; /* dddd:bb:dd.f */
91 unsigned int index;
92 struct work_struct req;
93 u64 req_addr;
94 int req_type;
95 unsigned req_seqno;
96 unsigned msg_seqno;
97 bool busy;
98 struct efx_buffer buf;
99 unsigned buftbl_base;
100 bool rx_filtering;
101 enum efx_filter_flags rx_filter_flags;
102 unsigned rx_filter_qid;
103 int rx_filter_id;
104 enum efx_vf_tx_filter_mode tx_filter_mode;
105 int tx_filter_id;
106 struct vfdi_endpoint addr;
107 u64 status_addr;
108 struct mutex status_lock;
109 u64 *peer_page_addrs;
110 unsigned peer_page_count;
111 u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) /
112 EFX_BUF_SIZE];
113 unsigned evq0_count;
114 wait_queue_head_t flush_waitq;
115 struct mutex txq_lock;
116 unsigned long txq_mask[VI_MASK_LENGTH];
117 unsigned txq_count;
118 unsigned long rxq_mask[VI_MASK_LENGTH];
119 unsigned rxq_count;
120 unsigned long rxq_retry_mask[VI_MASK_LENGTH];
121 atomic_t rxq_retry_count;
122 struct work_struct reset_work;
123};
124
125struct efx_memcpy_req {
126 unsigned int from_rid;
127 void *from_buf;
128 u64 from_addr;
129 unsigned int to_rid;
130 u64 to_addr;
131 unsigned length;
132};
133
134/**
135 * struct efx_local_addr - A MAC address on the vswitch without a VF.
136 *
137 * Siena does not have a switch, so VFs can't transmit data to each
138 * other. Instead the VFs must be made aware of the local addresses
139 * on the vswitch, so that they can arrange for an alternative
140 * software datapath to be used.
141 *
142 * @link: List head for insertion into efx->local_addr_list.
143 * @addr: Ethernet address
144 */
145struct efx_local_addr {
146 struct list_head link;
147 u8 addr[ETH_ALEN];
148};
149
150/**
151 * struct efx_endpoint_page - Page of vfdi_endpoint structures
152 *
153 * @link: List head for insertion into efx->local_page_list.
154 * @ptr: Pointer to page.
155 * @addr: DMA address of page.
156 */
157struct efx_endpoint_page {
158 struct list_head link;
159 void *ptr;
160 dma_addr_t addr;
161};
162
163/* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */
164#define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \
165 ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid))
166#define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \
167 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
168 (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
169#define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \
170 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
171 (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
172
173#define EFX_FIELD_MASK(_field) \
174 ((1 << _field ## _WIDTH) - 1)
175
176/* VFs can only use this many transmit channels */
177static unsigned int vf_max_tx_channels = 2;
178module_param(vf_max_tx_channels, uint, 0444);
179MODULE_PARM_DESC(vf_max_tx_channels,
180 "Limit the number of TX channels VFs can use");
181
182static int max_vfs = -1;
183module_param(max_vfs, int, 0444);
184MODULE_PARM_DESC(max_vfs,
185 "Reduce the number of VFs initialized by the driver");
186
187/* Workqueue used by VFDI communication. We can't use the global
188 * workqueue because it may be running the VF driver's probe()
189 * routine, which will be blocked there waiting for a VFDI response.
190 */
191static struct workqueue_struct *vfdi_workqueue;
192
193static unsigned abs_index(struct efx_vf *vf, unsigned index)
194{
195 return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index;
196}
197
327c685e
SS		 198static int efx_siena_sriov_cmd(struct efx_nic *efx, bool enable,
199 unsigned *vi_scale_out, unsigned *vf_total_out)
cd2d5b52 200{
59cfc479
BH		 201 MCDI_DECLARE_BUF(inbuf, MC_CMD_SRIOV_IN_LEN);
202 MCDI_DECLARE_BUF(outbuf, MC_CMD_SRIOV_OUT_LEN);
cd2d5b52
BH		 203 unsigned vi_scale, vf_total;
204 size_t outlen;
205 int rc;
206
207 MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0);
208 MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE);
209 MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count);
210
211 rc = efx_mcdi_rpc(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN,
212 outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen);
213 if (rc)
214 return rc;
215 if (outlen < MC_CMD_SRIOV_OUT_LEN)
216 return -EIO;
217
218 vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL);
219 vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE);
220 if (vi_scale > EFX_VI_SCALE_MAX)
221 return -EOPNOTSUPP;
222
223 if (vi_scale_out)
224 *vi_scale_out = vi_scale;
225 if (vf_total_out)
226 *vf_total_out = vf_total;
227
228 return 0;
229}
230
327c685e 231static void efx_siena_sriov_usrev(struct efx_nic *efx, bool enabled)
cd2d5b52 232{
2dc313ec 233 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 234 efx_oword_t reg;
235
236 EFX_POPULATE_OWORD_2(reg,
237 FRF_CZ_USREV_DIS, enabled ? 0 : 1,
2dc313ec 238 FRF_CZ_DFLT_EVQ, nic_data->vfdi_channel->channel);
cd2d5b52
BH		 239 efx_writeo(efx, &reg, FR_CZ_USR_EV_CFG);
240}
241
327c685e
SS		 242static int efx_siena_sriov_memcpy(struct efx_nic *efx,
243 struct efx_memcpy_req *req,
244 unsigned int count)
cd2d5b52 245{
c5bb0e98
BH		 246 MCDI_DECLARE_BUF(inbuf, MCDI_CTL_SDU_LEN_MAX_V1);
247 MCDI_DECLARE_STRUCT_PTR(record);
248 unsigned int index, used;
338f74df
BH		 249 u64 from_addr;
250 u32 from_rid;
cd2d5b52
BH		 251 int rc;
252
253 mb(); /* Finish writing source/reading dest before DMA starts */
254
c5bb0e98 255 if (WARN_ON(count > MC_CMD_MEMCPY_IN_RECORD_MAXNUM))
cd2d5b52 256 return -ENOBUFS;
c5bb0e98 257 used = MC_CMD_MEMCPY_IN_LEN(count);
cd2d5b52 258
c5bb0e98
BH		 259 for (index = 0; index < count; index++) {
260 record = MCDI_ARRAY_STRUCT_PTR(inbuf, MEMCPY_IN_RECORD, index);
261 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_NUM_RECORDS,
262 count);
cd2d5b52
BH		 263 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID,
264 req->to_rid);
338f74df
BH		 265 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR,
266 req->to_addr);
cd2d5b52
BH		 267 if (req->from_buf == NULL) {
268 from_rid = req->from_rid;
338f74df 269 from_addr = req->from_addr;
cd2d5b52 270 } else {
d0c2ee99
BH		 271 if (WARN_ON(used + req->length >
272 MCDI_CTL_SDU_LEN_MAX_V1)) {
cd2d5b52
BH		 273 rc = -ENOBUFS;
274 goto out;
275 }
276
277 from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE;
338f74df 278 from_addr = used;
c5bb0e98
BH		 279 memcpy(_MCDI_PTR(inbuf, used), req->from_buf,
280 req->length);
cd2d5b52
BH		 281 used += req->length;
282 }
283
284 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid);
338f74df
BH		 285 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR,
286 from_addr);
cd2d5b52
BH		 287 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH,
288 req->length);
289
290 ++req;
cd2d5b52
BH		 291 }
292
293 rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL);
294out:
cd2d5b52
BH		 295 mb(); /* Don't write source/read dest before DMA is complete */
296
297 return rc;
298}
299
300/* The TX filter is entirely controlled by this driver, and is modified
301 * underneath the feet of the VF
302 */
327c685e 303static void efx_siena_sriov_reset_tx_filter(struct efx_vf *vf)
cd2d5b52
BH		 304{
305 struct efx_nic *efx = vf->efx;
306 struct efx_filter_spec filter;
307 u16 vlan;
308 int rc;
309
310 if (vf->tx_filter_id != -1) {
311 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
312 vf->tx_filter_id);
313 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n",
314 vf->pci_name, vf->tx_filter_id);
315 vf->tx_filter_id = -1;
316 }
317
318 if (is_zero_ether_addr(vf->addr.mac_addr))
319 return;
320
321 /* Turn on TX filtering automatically if not explicitly
322 * enabled or disabled.
323 */
324 if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2)
325 vf->tx_filter_mode = VF_TX_FILTER_ON;
326
327 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
328 efx_filter_init_tx(&filter, abs_index(vf, 0));
329 rc = efx_filter_set_eth_local(&filter,
330 vlan ? vlan : EFX_FILTER_VID_UNSPEC,
331 vf->addr.mac_addr);
332 BUG_ON(rc);
333
334 rc = efx_filter_insert_filter(efx, &filter, true);
335 if (rc < 0) {
336 netif_warn(efx, hw, efx->net_dev,
337 "Unable to migrate tx filter for vf %s\n",
338 vf->pci_name);
339 } else {
340 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n",
341 vf->pci_name, rc);
342 vf->tx_filter_id = rc;
343 }
344}
345
346/* The RX filter is managed here on behalf of the VF driver */
327c685e 347static void efx_siena_sriov_reset_rx_filter(struct efx_vf *vf)
cd2d5b52
BH		 348{
349 struct efx_nic *efx = vf->efx;
350 struct efx_filter_spec filter;
351 u16 vlan;
352 int rc;
353
354 if (vf->rx_filter_id != -1) {
355 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
356 vf->rx_filter_id);
357 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n",
358 vf->pci_name, vf->rx_filter_id);
359 vf->rx_filter_id = -1;
360 }
361
362 if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr))
363 return;
364
365 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
366 efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED,
367 vf->rx_filter_flags,
368 abs_index(vf, vf->rx_filter_qid));
369 rc = efx_filter_set_eth_local(&filter,
370 vlan ? vlan : EFX_FILTER_VID_UNSPEC,
371 vf->addr.mac_addr);
372 BUG_ON(rc);
373
374 rc = efx_filter_insert_filter(efx, &filter, true);
375 if (rc < 0) {
376 netif_warn(efx, hw, efx->net_dev,
377 "Unable to insert rx filter for vf %s\n",
378 vf->pci_name);
379 } else {
380 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n",
381 vf->pci_name, rc);
382 vf->rx_filter_id = rc;
383 }
384}
385
327c685e 386static void __efx_siena_sriov_update_vf_addr(struct efx_vf *vf)
cd2d5b52 387{
2dc313ec
SS		 388 struct efx_nic *efx = vf->efx;
389 struct siena_nic_data *nic_data = efx->nic_data;
390
327c685e
SS		 391 efx_siena_sriov_reset_tx_filter(vf);
392 efx_siena_sriov_reset_rx_filter(vf);
2dc313ec 393 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 394}
395
396/* Push the peer list to this VF. The caller must hold status_lock to interlock
397 * with VFDI requests, and they must be serialised against manipulation of
398 * local_page_list, either by acquiring local_lock or by running from
327c685e 399 * efx_siena_sriov_peer_work()
cd2d5b52 400 */
327c685e 401static void __efx_siena_sriov_push_vf_status(struct efx_vf *vf)
cd2d5b52
BH		 402{
403 struct efx_nic *efx = vf->efx;
2dc313ec
SS		 404 struct siena_nic_data *nic_data = efx->nic_data;
405 struct vfdi_status *status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 406 struct efx_memcpy_req copy[4];
407 struct efx_endpoint_page *epp;
408 unsigned int pos, count;
409 unsigned data_offset;
410 efx_qword_t event;
411
412 WARN_ON(!mutex_is_locked(&vf->status_lock));
413 WARN_ON(!vf->status_addr);
414
415 status->local = vf->addr;
416 status->generation_end = ++status->generation_start;
417
418 memset(copy, '\0', sizeof(copy));
419 /* Write generation_start */
420 copy[0].from_buf = &status->generation_start;
421 copy[0].to_rid = vf->pci_rid;
422 copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status,
423 generation_start);
424 copy[0].length = sizeof(status->generation_start);
425 /* DMA the rest of the structure (excluding the generations). This
426 * assumes that the non-generation portion of vfdi_status is in
427 * one chunk starting at the version member.
428 */
429 data_offset = offsetof(struct vfdi_status, version);
430 copy[1].from_rid = efx->pci_dev->devfn;
2dc313ec 431 copy[1].from_addr = nic_data->vfdi_status.dma_addr + data_offset;
cd2d5b52
BH		 432 copy[1].to_rid = vf->pci_rid;
433 copy[1].to_addr = vf->status_addr + data_offset;
434 copy[1].length = status->length - data_offset;
435
436 /* Copy the peer pages */
437 pos = 2;
438 count = 0;
2dc313ec 439 list_for_each_entry(epp, &nic_data->local_page_list, link) {
cd2d5b52
BH		 440 if (count == vf->peer_page_count) {
441 /* The VF driver will know they need to provide more
442 * pages because peer_addr_count is too large.
443 */
444 break;
445 }
446 copy[pos].from_buf = NULL;
447 copy[pos].from_rid = efx->pci_dev->devfn;
448 copy[pos].from_addr = epp->addr;
449 copy[pos].to_rid = vf->pci_rid;
450 copy[pos].to_addr = vf->peer_page_addrs[count];
451 copy[pos].length = EFX_PAGE_SIZE;
452
453 if (++pos == ARRAY_SIZE(copy)) {
327c685e 454 efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
cd2d5b52
BH		 455 pos = 0;
456 }
457 ++count;
458 }
459
460 /* Write generation_end */
461 copy[pos].from_buf = &status->generation_end;
462 copy[pos].to_rid = vf->pci_rid;
463 copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status,
464 generation_end);
465 copy[pos].length = sizeof(status->generation_end);
327c685e 466 efx_siena_sriov_memcpy(efx, copy, pos + 1);
cd2d5b52
BH		 467
468 /* Notify the guest */
469 EFX_POPULATE_QWORD_3(event,
470 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
471 VFDI_EV_SEQ, (vf->msg_seqno & 0xff),
472 VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS);
473 ++vf->msg_seqno;
86094f7f
BH		 474 efx_farch_generate_event(efx,
475 EFX_VI_BASE + vf->index * efx_vf_size(efx),
476 &event);
cd2d5b52
BH		 477}
478
327c685e
SS		 479static void efx_siena_sriov_bufs(struct efx_nic *efx, unsigned offset,
480 u64 *addr, unsigned count)
cd2d5b52
BH		 481{
482 efx_qword_t buf;
483 unsigned pos;
484
485 for (pos = 0; pos < count; ++pos) {
486 EFX_POPULATE_QWORD_3(buf,
487 FRF_AZ_BUF_ADR_REGION, 0,
488 FRF_AZ_BUF_ADR_FBUF,
489 addr ? addr[pos] >> 12 : 0,
490 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
491 efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL,
492 &buf, offset + pos);
493 }
494}
495
496static bool bad_vf_index(struct efx_nic *efx, unsigned index)
497{
498 return index >= efx_vf_size(efx);
499}
500
501static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count)
502{
503 unsigned max_buf_count = max_entry_count *
504 sizeof(efx_qword_t) / EFX_BUF_SIZE;
505
506 return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count);
507}
508
509/* Check that VI specified by per-port index belongs to a VF.
510 * Optionally set VF index and VI index within the VF.
511 */
512static bool map_vi_index(struct efx_nic *efx, unsigned abs_index,
513 struct efx_vf **vf_out, unsigned *rel_index_out)
514{
515 unsigned vf_i;
516
517 if (abs_index < EFX_VI_BASE)
518 return true;
2c61c8a7 519 vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx);
cd2d5b52
BH		 520 if (vf_i >= efx->vf_init_count)
521 return true;
522
523 if (vf_out)
524 *vf_out = efx->vf + vf_i;
525 if (rel_index_out)
526 *rel_index_out = abs_index % efx_vf_size(efx);
527 return false;
528}
529
530static int efx_vfdi_init_evq(struct efx_vf *vf)
531{
532 struct efx_nic *efx = vf->efx;
533 struct vfdi_req *req = vf->buf.addr;
534 unsigned vf_evq = req->u.init_evq.index;
535 unsigned buf_count = req->u.init_evq.buf_count;
536 unsigned abs_evq = abs_index(vf, vf_evq);
537 unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq);
538 efx_oword_t reg;
539
540 if (bad_vf_index(efx, vf_evq) ||
541 bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) {
542 if (net_ratelimit())
543 netif_err(efx, hw, efx->net_dev,
544 "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n",
545 vf->pci_name, vf_evq, buf_count);
546 return VFDI_RC_EINVAL;
547 }
548
327c685e 549 efx_siena_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count);
cd2d5b52
BH		 550
551 EFX_POPULATE_OWORD_3(reg,
552 FRF_CZ_TIMER_Q_EN, 1,
553 FRF_CZ_HOST_NOTIFY_MODE, 0,
554 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
555 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
556 EFX_POPULATE_OWORD_3(reg,
557 FRF_AZ_EVQ_EN, 1,
558 FRF_AZ_EVQ_SIZE, __ffs(buf_count),
559 FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
560 efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
561
562 if (vf_evq == 0) {
563 memcpy(vf->evq0_addrs, req->u.init_evq.addr,
564 buf_count * sizeof(u64));
565 vf->evq0_count = buf_count;
566 }
567
568 return VFDI_RC_SUCCESS;
569}
570
571static int efx_vfdi_init_rxq(struct efx_vf *vf)
572{
573 struct efx_nic *efx = vf->efx;
574 struct vfdi_req *req = vf->buf.addr;
575 unsigned vf_rxq = req->u.init_rxq.index;
576 unsigned vf_evq = req->u.init_rxq.evq;
577 unsigned buf_count = req->u.init_rxq.buf_count;
578 unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq);
579 unsigned label;
580 efx_oword_t reg;
581
582 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) ||
45078374 583 vf_rxq >= VF_MAX_RX_QUEUES ||
cd2d5b52
BH		 584 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
585 if (net_ratelimit())
586 netif_err(efx, hw, efx->net_dev,
587 "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d "
588 "buf_count %d\n", vf->pci_name, vf_rxq,
589 vf_evq, buf_count);
590 return VFDI_RC_EINVAL;
591 }
592 if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask))
593 ++vf->rxq_count;
327c685e 594 efx_siena_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count);
cd2d5b52
BH		 595
596 label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL);
597 EFX_POPULATE_OWORD_6(reg,
598 FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl,
599 FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
600 FRF_AZ_RX_DESCQ_LABEL, label,
601 FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count),
602 FRF_AZ_RX_DESCQ_JUMBO,
603 !!(req->u.init_rxq.flags &
604 VFDI_RXQ_FLAG_SCATTER_EN),
605 FRF_AZ_RX_DESCQ_EN, 1);
606 efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
607 abs_index(vf, vf_rxq));
608
609 return VFDI_RC_SUCCESS;
610}
611
612static int efx_vfdi_init_txq(struct efx_vf *vf)
613{
614 struct efx_nic *efx = vf->efx;
615 struct vfdi_req *req = vf->buf.addr;
616 unsigned vf_txq = req->u.init_txq.index;
617 unsigned vf_evq = req->u.init_txq.evq;
618 unsigned buf_count = req->u.init_txq.buf_count;
619 unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq);
620 unsigned label, eth_filt_en;
621 efx_oword_t reg;
622
623 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) ||
624 vf_txq >= vf_max_tx_channels ||
625 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
626 if (net_ratelimit())
627 netif_err(efx, hw, efx->net_dev,
628 "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d "
629 "buf_count %d\n", vf->pci_name, vf_txq,
630 vf_evq, buf_count);
631 return VFDI_RC_EINVAL;
632 }
633
634 mutex_lock(&vf->txq_lock);
635 if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask))
636 ++vf->txq_count;
637 mutex_unlock(&vf->txq_lock);
327c685e 638 efx_siena_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count);
cd2d5b52
BH		 639
640 eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON;
641
642 label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL);
643 EFX_POPULATE_OWORD_8(reg,
644 FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U),
645 FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en,
646 FRF_AZ_TX_DESCQ_EN, 1,
647 FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl,
648 FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
649 FRF_AZ_TX_DESCQ_LABEL, label,
650 FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count),
651 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
652 efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
653 abs_index(vf, vf_txq));
654
655 return VFDI_RC_SUCCESS;
656}
657
658/* Returns true when efx_vfdi_fini_all_queues should wake */
659static bool efx_vfdi_flush_wake(struct efx_vf *vf)
660{
661 /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */
662 smp_mb();
663
664 return (!vf->txq_count && !vf->rxq_count) ||
665 atomic_read(&vf->rxq_retry_count);
666}
667
668static void efx_vfdi_flush_clear(struct efx_vf *vf)
669{
670 memset(vf->txq_mask, 0, sizeof(vf->txq_mask));
671 vf->txq_count = 0;
672 memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask));
673 vf->rxq_count = 0;
674 memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask));
675 atomic_set(&vf->rxq_retry_count, 0);
676}
677
678static int efx_vfdi_fini_all_queues(struct efx_vf *vf)
679{
680 struct efx_nic *efx = vf->efx;
681 efx_oword_t reg;
682 unsigned count = efx_vf_size(efx);
683 unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx);
684 unsigned timeout = HZ;
685 unsigned index, rxqs_count;
c5bb0e98 686 MCDI_DECLARE_BUF(inbuf, MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX);
cd2d5b52
BH		 687 int rc;
688
45078374
BH		 689 BUILD_BUG_ON(VF_MAX_RX_QUEUES >
690 MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
691
cd2d5b52 692 rtnl_lock();
d5e8cc6c 693 siena_prepare_flush(efx);
cd2d5b52
BH		 694 rtnl_unlock();
695
696 /* Flush all the initialized queues */
697 rxqs_count = 0;
698 for (index = 0; index < count; ++index) {
699 if (test_bit(index, vf->txq_mask)) {
700 EFX_POPULATE_OWORD_2(reg,
701 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
702 FRF_AZ_TX_FLUSH_DESCQ,
703 vf_offset + index);
704 efx_writeo(efx, &reg, FR_AZ_TX_FLUSH_DESCQ);
705 }
c5bb0e98
BH		 706 if (test_bit(index, vf->rxq_mask)) {
707 MCDI_SET_ARRAY_DWORD(
708 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
709 rxqs_count, vf_offset + index);
710 rxqs_count++;
711 }
cd2d5b52
BH		 712 }
713
714 atomic_set(&vf->rxq_retry_count, 0);
715 while (timeout && (vf->rxq_count || vf->txq_count)) {
c5bb0e98
BH		 716 rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
717 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(rxqs_count),
718 NULL, 0, NULL);
cd2d5b52
BH		 719 WARN_ON(rc < 0);
720
721 timeout = wait_event_timeout(vf->flush_waitq,
722 efx_vfdi_flush_wake(vf),
723 timeout);
724 rxqs_count = 0;
725 for (index = 0; index < count; ++index) {
726 if (test_and_clear_bit(index, vf->rxq_retry_mask)) {
727 atomic_dec(&vf->rxq_retry_count);
c5bb0e98
BH		 728 MCDI_SET_ARRAY_DWORD(
729 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
730 rxqs_count, vf_offset + index);
731 rxqs_count++;
cd2d5b52
BH		 732 }
733 }
734 }
735
736 rtnl_lock();
d5e8cc6c 737 siena_finish_flush(efx);
cd2d5b52
BH		 738 rtnl_unlock();
739
740 /* Irrespective of success/failure, fini the queues */
741 EFX_ZERO_OWORD(reg);
742 for (index = 0; index < count; ++index) {
743 efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
744 vf_offset + index);
745 efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
746 vf_offset + index);
747 efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL,
748 vf_offset + index);
749 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL,
750 vf_offset + index);
751 }
327c685e
SS		 752 efx_siena_sriov_bufs(efx, vf->buftbl_base, NULL,
753 EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx));
cd2d5b52
BH		 754 efx_vfdi_flush_clear(vf);
755
756 vf->evq0_count = 0;
757
758 return timeout ? 0 : VFDI_RC_ETIMEDOUT;
759}
760
761static int efx_vfdi_insert_filter(struct efx_vf *vf)
762{
763 struct efx_nic *efx = vf->efx;
2dc313ec 764 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 765 struct vfdi_req *req = vf->buf.addr;
766 unsigned vf_rxq = req->u.mac_filter.rxq;
767 unsigned flags;
768
769 if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) {
770 if (net_ratelimit())
771 netif_err(efx, hw, efx->net_dev,
772 "ERROR: Invalid INSERT_FILTER from %s: rxq %d "
773 "flags 0x%x\n", vf->pci_name, vf_rxq,
774 req->u.mac_filter.flags);
775 return VFDI_RC_EINVAL;
776 }
777
778 flags = 0;
779 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS)
780 flags |= EFX_FILTER_FLAG_RX_RSS;
781 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER)
782 flags |= EFX_FILTER_FLAG_RX_SCATTER;
783 vf->rx_filter_flags = flags;
784 vf->rx_filter_qid = vf_rxq;
785 vf->rx_filtering = true;
786
327c685e 787 efx_siena_sriov_reset_rx_filter(vf);
2dc313ec 788 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 789
790 return VFDI_RC_SUCCESS;
791}
792
793static int efx_vfdi_remove_all_filters(struct efx_vf *vf)
794{
2dc313ec
SS		 795 struct efx_nic *efx = vf->efx;
796 struct siena_nic_data *nic_data = efx->nic_data;
797
cd2d5b52 798 vf->rx_filtering = false;
327c685e 799 efx_siena_sriov_reset_rx_filter(vf);
2dc313ec 800 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 801
802 return VFDI_RC_SUCCESS;
803}
804
805static int efx_vfdi_set_status_page(struct efx_vf *vf)
806{
807 struct efx_nic *efx = vf->efx;
2dc313ec 808 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52 809 struct vfdi_req *req = vf->buf.addr;
01cb543d
BH		 810 u64 page_count = req->u.set_status_page.peer_page_count;
811 u64 max_page_count =
812 (EFX_PAGE_SIZE -
813 offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0]))
814 / sizeof(req->u.set_status_page.peer_page_addr[0]);
cd2d5b52 815
01cb543d 816 if (!req->u.set_status_page.dma_addr || page_count > max_page_count) {
cd2d5b52
BH		 817 if (net_ratelimit())
818 netif_err(efx, hw, efx->net_dev,
819 "ERROR: Invalid SET_STATUS_PAGE from %s\n",
820 vf->pci_name);
821 return VFDI_RC_EINVAL;
822 }
823
2dc313ec 824 mutex_lock(&nic_data->local_lock);
cd2d5b52
BH		 825 mutex_lock(&vf->status_lock);
826 vf->status_addr = req->u.set_status_page.dma_addr;
827
828 kfree(vf->peer_page_addrs);
829 vf->peer_page_addrs = NULL;
830 vf->peer_page_count = 0;
831
832 if (page_count) {
833 vf->peer_page_addrs = kcalloc(page_count, sizeof(u64),
834 GFP_KERNEL);
835 if (vf->peer_page_addrs) {
836 memcpy(vf->peer_page_addrs,
837 req->u.set_status_page.peer_page_addr,
838 page_count * sizeof(u64));
839 vf->peer_page_count = page_count;
840 }
841 }
842
327c685e 843 __efx_siena_sriov_push_vf_status(vf);
cd2d5b52 844 mutex_unlock(&vf->status_lock);
2dc313ec 845 mutex_unlock(&nic_data->local_lock);
cd2d5b52
BH		 846
847 return VFDI_RC_SUCCESS;
848}
849
850static int efx_vfdi_clear_status_page(struct efx_vf *vf)
851{
852 mutex_lock(&vf->status_lock);
853 vf->status_addr = 0;
854 mutex_unlock(&vf->status_lock);
855
856 return VFDI_RC_SUCCESS;
857}
858
859typedef int (*efx_vfdi_op_t)(struct efx_vf *vf);
860
861static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = {
862 [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq,
863 [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq,
864 [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq,
865 [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues,
866 [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter,
867 [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters,
868 [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page,
869 [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page,
870};
871
327c685e 872static void efx_siena_sriov_vfdi(struct work_struct *work)
cd2d5b52
BH		 873{
874 struct efx_vf *vf = container_of(work, struct efx_vf, req);
875 struct efx_nic *efx = vf->efx;
876 struct vfdi_req *req = vf->buf.addr;
877 struct efx_memcpy_req copy[2];
878 int rc;
879
880 /* Copy this page into the local address space */
881 memset(copy, '\0', sizeof(copy));
882 copy[0].from_rid = vf->pci_rid;
883 copy[0].from_addr = vf->req_addr;
884 copy[0].to_rid = efx->pci_dev->devfn;
885 copy[0].to_addr = vf->buf.dma_addr;
886 copy[0].length = EFX_PAGE_SIZE;
327c685e 887 rc = efx_siena_sriov_memcpy(efx, copy, 1);
cd2d5b52
BH		 888 if (rc) {
889 /* If we can't get the request, we can't reply to the caller */
890 if (net_ratelimit())
891 netif_err(efx, hw, efx->net_dev,
892 "ERROR: Unable to fetch VFDI request from %s rc %d\n",
893 vf->pci_name, -rc);
894 vf->busy = false;
895 return;
896 }
897
898 if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) {
899 rc = vfdi_ops[req->op](vf);
900 if (rc == 0) {
901 netif_dbg(efx, hw, efx->net_dev,
902 "vfdi request %d from %s ok\n",
903 req->op, vf->pci_name);
904 }
905 } else {
906 netif_dbg(efx, hw, efx->net_dev,
907 "ERROR: Unrecognised request %d from VF %s addr "
908 "%llx\n", req->op, vf->pci_name,
909 (unsigned long long)vf->req_addr);
910 rc = VFDI_RC_EOPNOTSUPP;
911 }
912
913 /* Allow subsequent VF requests */
914 vf->busy = false;
915 smp_wmb();
916
917 /* Respond to the request */
918 req->rc = rc;
919 req->op = VFDI_OP_RESPONSE;
920
921 memset(copy, '\0', sizeof(copy));
922 copy[0].from_buf = &req->rc;
923 copy[0].to_rid = vf->pci_rid;
924 copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc);
925 copy[0].length = sizeof(req->rc);
926 copy[1].from_buf = &req->op;
927 copy[1].to_rid = vf->pci_rid;
928 copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op);
929 copy[1].length = sizeof(req->op);
930
327c685e 931 (void)efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
cd2d5b52
BH		 932}
933
934
935
936/* After a reset the event queues inside the guests no longer exist. Fill the
937 * event ring in guest memory with VFDI reset events, then (re-initialise) the
938 * event queue to raise an interrupt. The guest driver will then recover.
939 */
327c685e
SS		 940static void efx_siena_sriov_reset_vf(struct efx_vf *vf,
941 struct efx_buffer *buffer)
cd2d5b52
BH		 942{
943 struct efx_nic *efx = vf->efx;
944 struct efx_memcpy_req copy_req[4];
945 efx_qword_t event;
946 unsigned int pos, count, k, buftbl, abs_evq;
947 efx_oword_t reg;
948 efx_dword_t ptr;
949 int rc;
950
951 BUG_ON(buffer->len != EFX_PAGE_SIZE);
952
953 if (!vf->evq0_count)
954 return;
955 BUG_ON(vf->evq0_count & (vf->evq0_count - 1));
956
957 mutex_lock(&vf->status_lock);
958 EFX_POPULATE_QWORD_3(event,
959 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
960 VFDI_EV_SEQ, vf->msg_seqno,
961 VFDI_EV_TYPE, VFDI_EV_TYPE_RESET);
962 vf->msg_seqno++;
963 for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event))
964 memcpy(buffer->addr + pos, &event, sizeof(event));
965
966 for (pos = 0; pos < vf->evq0_count; pos += count) {
967 count = min_t(unsigned, vf->evq0_count - pos,
968 ARRAY_SIZE(copy_req));
969 for (k = 0; k < count; k++) {
970 copy_req[k].from_buf = NULL;
971 copy_req[k].from_rid = efx->pci_dev->devfn;
972 copy_req[k].from_addr = buffer->dma_addr;
973 copy_req[k].to_rid = vf->pci_rid;
974 copy_req[k].to_addr = vf->evq0_addrs[pos + k];
975 copy_req[k].length = EFX_PAGE_SIZE;
976 }
327c685e 977 rc = efx_siena_sriov_memcpy(efx, copy_req, count);
cd2d5b52
BH		 978 if (rc) {
979 if (net_ratelimit())
980 netif_err(efx, hw, efx->net_dev,
981 "ERROR: Unable to notify %s of reset"
982 ": %d\n", vf->pci_name, -rc);
983 break;
984 }
985 }
986
987 /* Reinitialise, arm and trigger evq0 */
988 abs_evq = abs_index(vf, 0);
989 buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0);
327c685e 990 efx_siena_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count);
cd2d5b52
BH		 991
992 EFX_POPULATE_OWORD_3(reg,
993 FRF_CZ_TIMER_Q_EN, 1,
994 FRF_CZ_HOST_NOTIFY_MODE, 0,
995 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
996 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
997 EFX_POPULATE_OWORD_3(reg,
998 FRF_AZ_EVQ_EN, 1,
999 FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count),
1000 FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
1001 efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
1002 EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0);
778cdaf6 1003 efx_writed(efx, &ptr, FR_BZ_EVQ_RPTR + FR_BZ_EVQ_RPTR_STEP * abs_evq);
cd2d5b52
BH		 1004
1005 mutex_unlock(&vf->status_lock);
1006}
1007
327c685e 1008static void efx_siena_sriov_reset_vf_work(struct work_struct *work)
cd2d5b52
BH		 1009{
1010 struct efx_vf *vf = container_of(work, struct efx_vf, req);
1011 struct efx_nic *efx = vf->efx;
1012 struct efx_buffer buf;
1013
0d19a540 1014 if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) {
327c685e 1015 efx_siena_sriov_reset_vf(vf, &buf);
cd2d5b52
BH		 1016 efx_nic_free_buffer(efx, &buf);
1017 }
1018}
1019
327c685e 1020static void efx_siena_sriov_handle_no_channel(struct efx_nic *efx)
cd2d5b52
BH		 1021{
1022 netif_err(efx, drv, efx->net_dev,
1023 "ERROR: IOV requires MSI-X and 1 additional interrupt"
1024 "vector. IOV disabled\n");
1025 efx->vf_count = 0;
1026}
1027
327c685e 1028static int efx_siena_sriov_probe_channel(struct efx_channel *channel)
cd2d5b52 1029{
2dc313ec
SS		 1030 struct siena_nic_data *nic_data = channel->efx->nic_data;
1031 nic_data->vfdi_channel = channel;
1032
cd2d5b52
BH		 1033 return 0;
1034}
1035
1036static void
327c685e
SS		 1037efx_siena_sriov_get_channel_name(struct efx_channel *channel,
1038 char *buf, size_t len)
cd2d5b52
BH		 1039{
1040 snprintf(buf, len, "%s-iov", channel->efx->name);
1041}
1042
327c685e
SS		 1043static const struct efx_channel_type efx_siena_sriov_channel_type = {
1044 .handle_no_channel = efx_siena_sriov_handle_no_channel,
1045 .pre_probe = efx_siena_sriov_probe_channel,
726ba0e1 1046 .post_remove = efx_channel_dummy_op_void,
327c685e 1047 .get_name = efx_siena_sriov_get_channel_name,
cd2d5b52
BH		 1048 /* no copy operation; channel must not be reallocated */
1049 .keep_eventq = true,
1050};
1051
327c685e 1052void efx_siena_sriov_probe(struct efx_nic *efx)
cd2d5b52
BH		 1053{
1054 unsigned count;
1055
1056 if (!max_vfs)
1057 return;
1058
327c685e 1059 if (efx_siena_sriov_cmd(efx, false, &efx->vi_scale, &count))
cd2d5b52
BH		 1060 return;
1061 if (count > 0 && count > max_vfs)
1062 count = max_vfs;
1063
1064 /* efx_nic_dimension_resources() will reduce vf_count as appopriate */
1065 efx->vf_count = count;
1066
327c685e 1067 efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_siena_sriov_channel_type;
cd2d5b52
BH		 1068}
1069
1070/* Copy the list of individual addresses into the vfdi_status.peers
dbedd44e 1071 * array and auxiliary pages, protected by %local_lock. Drop that lock
cd2d5b52
BH		 1072 * and then broadcast the address list to every VF.
1073 */
327c685e 1074static void efx_siena_sriov_peer_work(struct work_struct *data)
cd2d5b52 1075{
2dc313ec
SS		 1076 struct siena_nic_data *nic_data = container_of(data,
1077 struct siena_nic_data,
1078 peer_work);
1079 struct efx_nic *efx = nic_data->efx;
1080 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 1081 struct efx_vf *vf;
1082 struct efx_local_addr *local_addr;
1083 struct vfdi_endpoint *peer;
1084 struct efx_endpoint_page *epp;
1085 struct list_head pages;
1086 unsigned int peer_space;
1087 unsigned int peer_count;
1088 unsigned int pos;
1089
2dc313ec 1090 mutex_lock(&nic_data->local_lock);
cd2d5b52
BH		 1091
1092 /* Move the existing peer pages off %local_page_list */
1093 INIT_LIST_HEAD(&pages);
2dc313ec 1094 list_splice_tail_init(&nic_data->local_page_list, &pages);
cd2d5b52
BH		 1095
1096 /* Populate the VF addresses starting from entry 1 (entry 0 is
1097 * the PF address)
1098 */
1099 peer = vfdi_status->peers + 1;
1100 peer_space = ARRAY_SIZE(vfdi_status->peers) - 1;
1101 peer_count = 1;
1102 for (pos = 0; pos < efx->vf_count; ++pos) {
1103 vf = efx->vf + pos;
1104
1105 mutex_lock(&vf->status_lock);
1106 if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) {
1107 *peer++ = vf->addr;
1108 ++peer_count;
1109 --peer_space;
1110 BUG_ON(peer_space == 0);
1111 }
1112 mutex_unlock(&vf->status_lock);
1113 }
1114
1115 /* Fill the remaining addresses */
2dc313ec 1116 list_for_each_entry(local_addr, &nic_data->local_addr_list, link) {
cd84ff4d 1117 ether_addr_copy(peer->mac_addr, local_addr->addr);
cd2d5b52
BH		 1118 peer->tci = 0;
1119 ++peer;
1120 ++peer_count;
1121 if (--peer_space == 0) {
1122 if (list_empty(&pages)) {
1123 epp = kmalloc(sizeof(*epp), GFP_KERNEL);
1124 if (!epp)
1125 break;
1126 epp->ptr = dma_alloc_coherent(
1127 &efx->pci_dev->dev, EFX_PAGE_SIZE,
1128 &epp->addr, GFP_KERNEL);
1129 if (!epp->ptr) {
1130 kfree(epp);
1131 break;
1132 }
1133 } else {
1134 epp = list_first_entry(
1135 &pages, struct efx_endpoint_page, link);
1136 list_del(&epp->link);
1137 }
1138
2dc313ec 1139 list_add_tail(&epp->link, &nic_data->local_page_list);
cd2d5b52
BH		 1140 peer = (struct vfdi_endpoint *)epp->ptr;
1141 peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint);
1142 }
1143 }
1144 vfdi_status->peer_count = peer_count;
2dc313ec 1145 mutex_unlock(&nic_data->local_lock);
cd2d5b52
BH		 1146
1147 /* Free any now unused endpoint pages */
1148 while (!list_empty(&pages)) {
1149 epp = list_first_entry(
1150 &pages, struct efx_endpoint_page, link);
1151 list_del(&epp->link);
1152 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
1153 epp->ptr, epp->addr);
1154 kfree(epp);
1155 }
1156
1157 /* Finally, push the pages */
1158 for (pos = 0; pos < efx->vf_count; ++pos) {
1159 vf = efx->vf + pos;
1160
1161 mutex_lock(&vf->status_lock);
1162 if (vf->status_addr)
327c685e 1163 __efx_siena_sriov_push_vf_status(vf);
cd2d5b52
BH		 1164 mutex_unlock(&vf->status_lock);
1165 }
1166}
1167
327c685e 1168static void efx_siena_sriov_free_local(struct efx_nic *efx)
cd2d5b52 1169{
2dc313ec 1170 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1171 struct efx_local_addr *local_addr;
1172 struct efx_endpoint_page *epp;
1173
2dc313ec
SS		 1174 while (!list_empty(&nic_data->local_addr_list)) {
1175 local_addr = list_first_entry(&nic_data->local_addr_list,
cd2d5b52
BH		 1176 struct efx_local_addr, link);
1177 list_del(&local_addr->link);
1178 kfree(local_addr);
1179 }
1180
2dc313ec
SS		 1181 while (!list_empty(&nic_data->local_page_list)) {
1182 epp = list_first_entry(&nic_data->local_page_list,
cd2d5b52
BH		 1183 struct efx_endpoint_page, link);
1184 list_del(&epp->link);
1185 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
1186 epp->ptr, epp->addr);
1187 kfree(epp);
1188 }
1189}
1190
327c685e 1191static int efx_siena_sriov_vf_alloc(struct efx_nic *efx)
cd2d5b52
BH		 1192{
1193 unsigned index;
1194 struct efx_vf *vf;
1195
1196 efx->vf = kzalloc(sizeof(struct efx_vf) * efx->vf_count, GFP_KERNEL);
1197 if (!efx->vf)
1198 return -ENOMEM;
1199
1200 for (index = 0; index < efx->vf_count; ++index) {
1201 vf = efx->vf + index;
1202
1203 vf->efx = efx;
1204 vf->index = index;
1205 vf->rx_filter_id = -1;
1206 vf->tx_filter_mode = VF_TX_FILTER_AUTO;
1207 vf->tx_filter_id = -1;
327c685e
SS		 1208 INIT_WORK(&vf->req, efx_siena_sriov_vfdi);
1209 INIT_WORK(&vf->reset_work, efx_siena_sriov_reset_vf_work);
cd2d5b52
BH		 1210 init_waitqueue_head(&vf->flush_waitq);
1211 mutex_init(&vf->status_lock);
1212 mutex_init(&vf->txq_lock);
1213 }
1214
1215 return 0;
1216}
1217
327c685e 1218static void efx_siena_sriov_vfs_fini(struct efx_nic *efx)
cd2d5b52
BH		 1219{
1220 struct efx_vf *vf;
1221 unsigned int pos;
1222
1223 for (pos = 0; pos < efx->vf_count; ++pos) {
1224 vf = efx->vf + pos;
1225
1226 efx_nic_free_buffer(efx, &vf->buf);
1227 kfree(vf->peer_page_addrs);
1228 vf->peer_page_addrs = NULL;
1229 vf->peer_page_count = 0;
1230
1231 vf->evq0_count = 0;
1232 }
1233}
1234
327c685e 1235static int efx_siena_sriov_vfs_init(struct efx_nic *efx)
cd2d5b52
BH		 1236{
1237 struct pci_dev *pci_dev = efx->pci_dev;
2dc313ec 1238 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1239 unsigned index, devfn, sriov, buftbl_base;
1240 u16 offset, stride;
1241 struct efx_vf *vf;
1242 int rc;
1243
1244 sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV);
1245 if (!sriov)
1246 return -ENOENT;
1247
1248 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset);
1249 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride);
1250
2dc313ec 1251 buftbl_base = nic_data->vf_buftbl_base;
cd2d5b52
BH		 1252 devfn = pci_dev->devfn + offset;
1253 for (index = 0; index < efx->vf_count; ++index) {
1254 vf = efx->vf + index;
1255
1256 /* Reserve buffer entries */
1257 vf->buftbl_base = buftbl_base;
1258 buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx);
1259
1260 vf->pci_rid = devfn;
1261 snprintf(vf->pci_name, sizeof(vf->pci_name),
1262 "%04x:%02x:%02x.%d",
1263 pci_domain_nr(pci_dev->bus), pci_dev->bus->number,
1264 PCI_SLOT(devfn), PCI_FUNC(devfn));
1265
0d19a540
BH		 1266 rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE,
1267 GFP_KERNEL);
cd2d5b52
BH		 1268 if (rc)
1269 goto fail;
1270
1271 devfn += stride;
1272 }
1273
1274 return 0;
1275
1276fail:
327c685e 1277 efx_siena_sriov_vfs_fini(efx);
cd2d5b52
BH		 1278 return rc;
1279}
1280
327c685e 1281int efx_siena_sriov_init(struct efx_nic *efx)
cd2d5b52
BH		 1282{
1283 struct net_device *net_dev = efx->net_dev;
2dc313ec 1284 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1285 struct vfdi_status *vfdi_status;
1286 int rc;
1287
1288 /* Ensure there's room for vf_channel */
1289 BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE);
1290 /* Ensure that VI_BASE is aligned on VI_SCALE */
1291 BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1));
1292
1293 if (efx->vf_count == 0)
1294 return 0;
1295
327c685e 1296 rc = efx_siena_sriov_cmd(efx, true, NULL, NULL);
cd2d5b52
BH		 1297 if (rc)
1298 goto fail_cmd;
1299
2dc313ec
SS		 1300 rc = efx_nic_alloc_buffer(efx, &nic_data->vfdi_status,
1301 sizeof(*vfdi_status), GFP_KERNEL);
cd2d5b52
BH		 1302 if (rc)
1303 goto fail_status;
2dc313ec 1304 vfdi_status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 1305 memset(vfdi_status, 0, sizeof(*vfdi_status));
1306 vfdi_status->version = 1;
1307 vfdi_status->length = sizeof(*vfdi_status);
1308 vfdi_status->max_tx_channels = vf_max_tx_channels;
1309 vfdi_status->vi_scale = efx->vi_scale;
1310 vfdi_status->rss_rxq_count = efx->rss_spread;
1311 vfdi_status->peer_count = 1 + efx->vf_count;
1312 vfdi_status->timer_quantum_ns = efx->timer_quantum_ns;
1313
327c685e 1314 rc = efx_siena_sriov_vf_alloc(efx);
cd2d5b52
BH		 1315 if (rc)
1316 goto fail_alloc;
1317
2dc313ec 1318 mutex_init(&nic_data->local_lock);
327c685e 1319 INIT_WORK(&nic_data->peer_work, efx_siena_sriov_peer_work);
2dc313ec
SS		 1320 INIT_LIST_HEAD(&nic_data->local_addr_list);
1321 INIT_LIST_HEAD(&nic_data->local_page_list);
cd2d5b52 1322
327c685e 1323 rc = efx_siena_sriov_vfs_init(efx);
cd2d5b52
BH		 1324 if (rc)
1325 goto fail_vfs;
1326
1327 rtnl_lock();
cd84ff4d 1328 ether_addr_copy(vfdi_status->peers[0].mac_addr, net_dev->dev_addr);
cd2d5b52
BH		 1329 efx->vf_init_count = efx->vf_count;
1330 rtnl_unlock();
1331
327c685e 1332 efx_siena_sriov_usrev(efx, true);
cd2d5b52
BH		 1333
1334 /* At this point we must be ready to accept VFDI requests */
1335
1336 rc = pci_enable_sriov(efx->pci_dev, efx->vf_count);
1337 if (rc)
1338 goto fail_pci;
1339
1340 netif_info(efx, probe, net_dev,
1341 "enabled SR-IOV for %d VFs, %d VI per VF\n",
1342 efx->vf_count, efx_vf_size(efx));
1343 return 0;
1344
1345fail_pci:
327c685e 1346 efx_siena_sriov_usrev(efx, false);
cd2d5b52
BH		 1347 rtnl_lock();
1348 efx->vf_init_count = 0;
1349 rtnl_unlock();
327c685e 1350 efx_siena_sriov_vfs_fini(efx);
cd2d5b52 1351fail_vfs:
2dc313ec 1352 cancel_work_sync(&nic_data->peer_work);
327c685e 1353 efx_siena_sriov_free_local(efx);
cd2d5b52
BH		 1354 kfree(efx->vf);
1355fail_alloc:
2dc313ec 1356 efx_nic_free_buffer(efx, &nic_data->vfdi_status);
cd2d5b52 1357fail_status:
327c685e 1358 efx_siena_sriov_cmd(efx, false, NULL, NULL);
cd2d5b52
BH		 1359fail_cmd:
1360 return rc;
1361}
1362
327c685e 1363void efx_siena_sriov_fini(struct efx_nic *efx)
cd2d5b52
BH		 1364{
1365 struct efx_vf *vf;
1366 unsigned int pos;
2dc313ec 1367 struct siena_nic_data *nic_data = efx->nic_data;
cd2d5b52
BH		 1368
1369 if (efx->vf_init_count == 0)
1370 return;
1371
1372 /* Disable all interfaces to reconfiguration */
2dc313ec 1373 BUG_ON(nic_data->vfdi_channel->enabled);
327c685e 1374 efx_siena_sriov_usrev(efx, false);
cd2d5b52
BH		 1375 rtnl_lock();
1376 efx->vf_init_count = 0;
1377 rtnl_unlock();
1378
1379 /* Flush all reconfiguration work */
1380 for (pos = 0; pos < efx->vf_count; ++pos) {
1381 vf = efx->vf + pos;
1382 cancel_work_sync(&vf->req);
1383 cancel_work_sync(&vf->reset_work);
1384 }
2dc313ec 1385 cancel_work_sync(&nic_data->peer_work);
cd2d5b52
BH		 1386
1387 pci_disable_sriov(efx->pci_dev);
1388
1389 /* Tear down back-end state */
327c685e
SS		 1390 efx_siena_sriov_vfs_fini(efx);
1391 efx_siena_sriov_free_local(efx);
cd2d5b52 1392 kfree(efx->vf);
2dc313ec 1393 efx_nic_free_buffer(efx, &nic_data->vfdi_status);
327c685e 1394 efx_siena_sriov_cmd(efx, false, NULL, NULL);
cd2d5b52
BH		 1395}
1396
327c685e 1397void efx_siena_sriov_event(struct efx_channel *channel, efx_qword_t *event)
cd2d5b52
BH		 1398{
1399 struct efx_nic *efx = channel->efx;
1400 struct efx_vf *vf;
1401 unsigned qid, seq, type, data;
1402
1403 qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID);
1404
1405 /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */
1406 BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0);
1407 seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ);
1408 type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE);
1409 data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA);
1410
1411 netif_vdbg(efx, hw, efx->net_dev,
1412 "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n",
1413 qid, seq, type, data);
1414
1415 if (map_vi_index(efx, qid, &vf, NULL))
1416 return;
1417 if (vf->busy)
1418 goto error;
1419
1420 if (type == VFDI_EV_TYPE_REQ_WORD0) {
1421 /* Resynchronise */
1422 vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
1423 vf->req_seqno = seq + 1;
1424 vf->req_addr = 0;
1425 } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type)
1426 goto error;
1427
1428 switch (vf->req_type) {
1429 case VFDI_EV_TYPE_REQ_WORD0:
1430 case VFDI_EV_TYPE_REQ_WORD1:
1431 case VFDI_EV_TYPE_REQ_WORD2:
1432 vf->req_addr |= (u64)data << (vf->req_type << 4);
1433 ++vf->req_type;
1434 return;
1435
1436 case VFDI_EV_TYPE_REQ_WORD3:
1437 vf->req_addr |= (u64)data << 48;
1438 vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
1439 vf->busy = true;
1440 queue_work(vfdi_workqueue, &vf->req);
1441 return;
1442 }
1443
1444error:
1445 if (net_ratelimit())
1446 netif_err(efx, hw, efx->net_dev,
1447 "ERROR: Screaming VFDI request from %s\n",
1448 vf->pci_name);
1449 /* Reset the request and sequence number */
1450 vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
1451 vf->req_seqno = seq + 1;
1452}
1453
327c685e 1454void efx_siena_sriov_flr(struct efx_nic *efx, unsigned vf_i)
cd2d5b52
BH		 1455{
1456 struct efx_vf *vf;
1457
1458 if (vf_i > efx->vf_init_count)
1459 return;
1460 vf = efx->vf + vf_i;
1461 netif_info(efx, hw, efx->net_dev,
1462 "FLR on VF %s\n", vf->pci_name);
1463
1464 vf->status_addr = 0;
1465 efx_vfdi_remove_all_filters(vf);
1466 efx_vfdi_flush_clear(vf);
1467
1468 vf->evq0_count = 0;
1469}
1470
327c685e 1471void efx_siena_sriov_mac_address_changed(struct efx_nic *efx)
cd2d5b52 1472{
2dc313ec
SS		 1473 struct siena_nic_data *nic_data = efx->nic_data;
1474 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr;
cd2d5b52
BH		 1475
1476 if (!efx->vf_init_count)
1477 return;
cd84ff4d
EC		 1478 ether_addr_copy(vfdi_status->peers[0].mac_addr,
1479 efx->net_dev->dev_addr);
2dc313ec 1480 queue_work(vfdi_workqueue, &nic_data->peer_work);
cd2d5b52
BH		 1481}
1482
327c685e 1483void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
cd2d5b52
BH		 1484{
1485 struct efx_vf *vf;
1486 unsigned queue, qid;
1487
1488 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1489 if (map_vi_index(efx, queue, &vf, &qid))
1490 return;
1491 /* Ignore flush completions triggered by an FLR */
1492 if (!test_bit(qid, vf->txq_mask))
1493 return;
1494
1495 __clear_bit(qid, vf->txq_mask);
1496 --vf->txq_count;
1497
1498 if (efx_vfdi_flush_wake(vf))
1499 wake_up(&vf->flush_waitq);
1500}
1501
327c685e 1502void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
cd2d5b52
BH		 1503{
1504 struct efx_vf *vf;
1505 unsigned ev_failed, queue, qid;
1506
1507 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1508 ev_failed = EFX_QWORD_FIELD(*event,
1509 FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1510 if (map_vi_index(efx, queue, &vf, &qid))
1511 return;
1512 if (!test_bit(qid, vf->rxq_mask))
1513 return;
1514
1515 if (ev_failed) {
1516 set_bit(qid, vf->rxq_retry_mask);
1517 atomic_inc(&vf->rxq_retry_count);
1518 } else {
1519 __clear_bit(qid, vf->rxq_mask);
1520 --vf->rxq_count;
1521 }
1522 if (efx_vfdi_flush_wake(vf))
1523 wake_up(&vf->flush_waitq);
1524}
1525
1526/* Called from napi. Schedule the reset work item */
327c685e 1527void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq)
cd2d5b52
BH		 1528{
1529 struct efx_vf *vf;
1530 unsigned int rel;
1531
1532 if (map_vi_index(efx, dmaq, &vf, &rel))
1533 return;
1534
1535 if (net_ratelimit())
1536 netif_err(efx, hw, efx->net_dev,
1537 "VF %d DMA Q %d reports descriptor fetch error.\n",
1538 vf->index, rel);
1539 queue_work(vfdi_workqueue, &vf->reset_work);
1540}
1541
1542/* Reset all VFs */
327c685e 1543void efx_siena_sriov_reset(struct efx_nic *efx)
cd2d5b52
BH		 1544{
1545 unsigned int vf_i;
1546 struct efx_buffer buf;
1547 struct efx_vf *vf;
1548
1549 ASSERT_RTNL();
1550
1551 if (efx->vf_init_count == 0)
1552 return;
1553
327c685e
SS		 1554 efx_siena_sriov_usrev(efx, true);
1555 (void)efx_siena_sriov_cmd(efx, true, NULL, NULL);
cd2d5b52 1556
0d19a540 1557 if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO))
cd2d5b52
BH		 1558 return;
1559
1560 for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) {
1561 vf = efx->vf + vf_i;
327c685e 1562 efx_siena_sriov_reset_vf(vf, &buf);
cd2d5b52
BH		 1563 }
1564
1565 efx_nic_free_buffer(efx, &buf);
1566}
1567
1568int efx_init_sriov(void)
1569{
327c685e
SS		 1570 /* A single threaded workqueue is sufficient. efx_siena_sriov_vfdi() and
1571 * efx_siena_sriov_peer_work() spend almost all their time sleeping for
cd2d5b52
BH		 1572 * MCDI to complete anyway
1573 */
1574 vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi");
1575 if (!vfdi_workqueue)
1576 return -ENOMEM;
cd2d5b52
BH		 1577 return 0;
1578}
1579
1580void efx_fini_sriov(void)
1581{
1582 destroy_workqueue(vfdi_workqueue);
1583}
1584
7fa8d547 1585int efx_siena_sriov_set_vf_mac(struct efx_nic *efx, int vf_i, u8 *mac)
cd2d5b52 1586{
cd2d5b52
BH		 1587 struct efx_vf *vf;
1588
1589 if (vf_i >= efx->vf_init_count)
1590 return -EINVAL;
1591 vf = efx->vf + vf_i;
1592
1593 mutex_lock(&vf->status_lock);
cd84ff4d 1594 ether_addr_copy(vf->addr.mac_addr, mac);
327c685e 1595 __efx_siena_sriov_update_vf_addr(vf);
cd2d5b52
BH		 1596 mutex_unlock(&vf->status_lock);
1597
1598 return 0;
1599}
1600
7fa8d547 1601int efx_siena_sriov_set_vf_vlan(struct efx_nic *efx, int vf_i,
327c685e 1602 u16 vlan, u8 qos)
cd2d5b52 1603{
cd2d5b52
BH		 1604 struct efx_vf *vf;
1605 u16 tci;
1606
1607 if (vf_i >= efx->vf_init_count)
1608 return -EINVAL;
1609 vf = efx->vf + vf_i;
1610
1611 mutex_lock(&vf->status_lock);
1612 tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT);
1613 vf->addr.tci = htons(tci);
327c685e 1614 __efx_siena_sriov_update_vf_addr(vf);
cd2d5b52
BH		 1615 mutex_unlock(&vf->status_lock);
1616
1617 return 0;
1618}
1619
7fa8d547 1620int efx_siena_sriov_set_vf_spoofchk(struct efx_nic *efx, int vf_i,
327c685e 1621 bool spoofchk)
cd2d5b52 1622{
cd2d5b52
BH		 1623 struct efx_vf *vf;
1624 int rc;
1625
1626 if (vf_i >= efx->vf_init_count)
1627 return -EINVAL;
1628 vf = efx->vf + vf_i;
1629
1630 mutex_lock(&vf->txq_lock);
1631 if (vf->txq_count == 0) {
1632 vf->tx_filter_mode =
1633 spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF;
1634 rc = 0;
1635 } else {
1636 /* This cannot be changed while TX queues are running */
1637 rc = -EBUSY;
1638 }
1639 mutex_unlock(&vf->txq_lock);
1640 return rc;
1641}
1642
7fa8d547 1643int efx_siena_sriov_get_vf_config(struct efx_nic *efx, int vf_i,
327c685e 1644 struct ifla_vf_info *ivi)
cd2d5b52 1645{
cd2d5b52
BH		 1646 struct efx_vf *vf;
1647 u16 tci;
1648
1649 if (vf_i >= efx->vf_init_count)
1650 return -EINVAL;
1651 vf = efx->vf + vf_i;
1652
1653 ivi->vf = vf_i;
cd84ff4d 1654 ether_addr_copy(ivi->mac, vf->addr.mac_addr);
ed616689
SC		 1655 ivi->max_tx_rate = 0;
1656 ivi->min_tx_rate = 0;
cd2d5b52
BH		 1657 tci = ntohs(vf->addr.tci);
1658 ivi->vlan = tci & VLAN_VID_MASK;
1659 ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7;
1660 ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON;
1661
1662 return 0;
1663}
1664
7fa8d547
SS		 1665bool efx_siena_sriov_wanted(struct efx_nic *efx)
1666{
1667 return efx->vf_count != 0;
1668}
Linux kernel - Deliverables
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