projects / deliverable / linux.git / blame
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| 8ceee660 BH |
1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards | |
| 3 | * Copyright 2005 Fen Systems Ltd. | |
| 0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
| 8ceee660 BH |
5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License version 2 as published | |
| 8 | * by the Free Software Foundation, incorporated herein by reference. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef EFX_SPI_H | |
| 12 | #define EFX_SPI_H | |
| 13 | ||
| 14 | #include "net_driver.h" | |
| 15 | ||
| 16 | /************************************************************************** | |
| 17 | * | |
| 18 | * Basic SPI command set and bit definitions | |
| 19 | * | |
| 20 | *************************************************************************/ | |
| 21 | ||
| 4a5b504d BH |
22 | #define SPI_WRSR 0x01 /* Write status register */ |
| 23 | #define SPI_WRITE 0x02 /* Write data to memory array */ | |
| 24 | #define SPI_READ 0x03 /* Read data from memory array */ | |
| 25 | #define SPI_WRDI 0x04 /* Reset write enable latch */ | |
| 26 | #define SPI_RDSR 0x05 /* Read status register */ | |
| 27 | #define SPI_WREN 0x06 /* Set write enable latch */ | |
| f4150724 | 28 | #define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */ |
| 4a5b504d BH |
29 | |
| 30 | #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */ | |
| 31 | #define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */ | |
| 32 | #define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */ | |
| 33 | #define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */ | |
| 34 | #define SPI_STATUS_WEN 0x02 /* State of the write enable latch */ | |
| 35 | #define SPI_STATUS_NRDY 0x01 /* Device busy flag */ | |
| 36 | ||
| 37 | /** | |
| 38 | * struct efx_spi_device - an Efx SPI (Serial Peripheral Interface) device | |
| 4a5b504d BH |
39 | * @device_id: Controller's id for the device |
| 40 | * @size: Size (in bytes) | |
| 41 | * @addr_len: Number of address bytes in read/write commands | |
| 42 | * @munge_address: Flag whether addresses should be munged. | |
| 43 | * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) | |
| 44 | * use bit 3 of the command byte as address bit A8, rather | |
| 45 | * than having a two-byte address. If this flag is set, then | |
| 46 | * commands should be munged in this way. | |
| f4150724 BH |
47 | * @erase_command: Erase command (or 0 if sector erase not needed). |
| 48 | * @erase_size: Erase sector size (in bytes) | |
| 49 | * Erase commands affect sectors with this size and alignment. | |
| 50 | * This must be a power of two. | |
| 4a5b504d BH |
51 | * @block_size: Write block size (in bytes). |
| 52 | * Write commands are limited to blocks with this size and alignment. | |
| 8ceee660 | 53 | */ |
| 4a5b504d | 54 | struct efx_spi_device { |
| 4a5b504d BH |
55 | int device_id; |
| 56 | unsigned int size; | |
| 57 | unsigned int addr_len; | |
| 58 | unsigned int munge_address:1; | |
| f4150724 BH |
59 | u8 erase_command; |
| 60 | unsigned int erase_size; | |
| 4a5b504d BH |
61 | unsigned int block_size; |
| 62 | }; | |
| 63 | ||
| 4de92180 BH |
64 | static inline bool efx_spi_present(const struct efx_spi_device *spi) |
| 65 | { | |
| 66 | return spi->size != 0; | |
| 67 | } | |
| 68 | ||
| 76884835 BH |
69 | int falcon_spi_cmd(struct efx_nic *efx, |
| 70 | const struct efx_spi_device *spi, unsigned int command, | |
| 9c636baf | 71 | int address, const void *in, void *out, size_t len); |
| 76884835 BH |
72 | int falcon_spi_wait_write(struct efx_nic *efx, |
| 73 | const struct efx_spi_device *spi); | |
| 74 | int falcon_spi_read(struct efx_nic *efx, | |
| 75 | const struct efx_spi_device *spi, loff_t start, | |
| 4a5b504d | 76 | size_t len, size_t *retlen, u8 *buffer); |
| 76884835 BH |
77 | int falcon_spi_write(struct efx_nic *efx, |
| 78 | const struct efx_spi_device *spi, loff_t start, | |
| 4a5b504d | 79 | size_t len, size_t *retlen, const u8 *buffer); |
| 8ceee660 | 80 | |
| 0a95f563 BH |
81 | /* |
| 82 | * SFC4000 flash is partitioned into: | |
| 83 | * 0-0x400 chip and board config (see falcon_hwdefs.h) | |
| 84 | * 0x400-0x8000 unused (or may contain VPD if EEPROM not present) | |
| 85 | * 0x8000-end boot code (mapped to PCI expansion ROM) | |
| 86 | * SFC4000 small EEPROM (size < 0x400) is used for VPD only. | |
| 87 | * SFC4000 large EEPROM (size >= 0x400) is partitioned into: | |
| 88 | * 0-0x400 chip and board config | |
| 89 | * configurable VPD | |
| 90 | * 0x800-0x1800 boot config | |
| 91 | * Aside from the chip and board config, all of these are optional and may | |
| 92 | * be absent or truncated depending on the devices used. | |
| 93 | */ | |
| 94 | #define FALCON_NVCONFIG_END 0x400U | |
| f4150724 | 95 | #define FALCON_FLASH_BOOTCODE_START 0x8000U |
| 0a95f563 BH |
96 | #define EFX_EEPROM_BOOTCONFIG_START 0x800U |
| 97 | #define EFX_EEPROM_BOOTCONFIG_END 0x1800U | |
| 98 | ||
| 8ceee660 | 99 | #endif /* EFX_SPI_H */ |