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Merge tag 'tag-sh-for-4.6' of git://git.libc.org/linux-sh
[deliverable/linux.git] / drivers / net / ethernet / smsc / smc911x.h
CommitLineData
0a0c72c9
DM		 1/*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
0ab75ae8 18 . along with this program; if not, see <http://www.gnu.org/licenses/>.
0a0c72c9
DM		 19 .
20 . Information contained in this file was obtained from the LAN9118
21 . manual from SMC. To get a copy, if you really want one, you can find
22 . information under www.smsc.com.
23 .
24 . Authors
25 . Dustin McIntire <dustin@sensoria.com>
26 .
27 ---------------------------------------------------------------------------*/
28#ifndef _SMC911X_H_
29#define _SMC911X_H_
30
12c03f59 31#include <linux/smc911x.h>
0a0c72c9
DM		 32/*
33 * Use the DMA feature on PXA chips
34 */
35#ifdef CONFIG_ARCH_PXA
36 #define SMC_USE_PXA_DMA 1
37 #define SMC_USE_16BIT 0
38 #define SMC_USE_32BIT 1
726d722e 39 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
d0c4581b 40#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
726d722e
MB		 41 #define SMC_USE_16BIT 0
42 #define SMC_USE_32BIT 1
43 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
a8eb7ca0 44#elif defined(CONFIG_ARCH_OMAP3)
07555c98
RK		 45 #define SMC_USE_16BIT 0
46 #define SMC_USE_32BIT 1
47 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
48 #define SMC_MEM_RESERVED 1
088ef950 49#elif defined(CONFIG_ARCH_OMAP2)
07555c98
RK		 50 #define SMC_USE_16BIT 0
51 #define SMC_USE_32BIT 1
52 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
53 #define SMC_MEM_RESERVED 1
12c03f59
MD		 54#else
55/*
56 * Default configuration
57 */
58
59#define SMC_DYNAMIC_BUS_CONFIG
0a0c72c9
DM		 60#endif
61
d766a4ed
DB		 62#ifdef SMC_USE_PXA_DMA
63#define SMC_USE_DMA
64#endif
65
699559f8
MD		 66/* store this information for the driver.. */
67struct smc911x_local {
68 /*
69 * If I have to wait until the DMA is finished and ready to reload a
70 * packet, I will store the skbuff here. Then, the DMA will send it
71 * out and free it.
72 */
73 struct sk_buff *pending_tx_skb;
74
75 /* version/revision of the SMC911x chip */
76 u16 version;
77 u16 revision;
78
79 /* FIFO sizes */
80 int tx_fifo_kb;
81 int tx_fifo_size;
82 int rx_fifo_size;
83 int afc_cfg;
84
85 /* Contains the current active receive/phy mode */
86 int ctl_rfduplx;
87 int ctl_rspeed;
88
89 u32 msg_enable;
90 u32 phy_type;
91 struct mii_if_info mii;
92
93 /* work queue */
94 struct work_struct phy_configure;
699559f8
MD		 95
96 int tx_throttle;
97 spinlock_t lock;
98
99 struct net_device *netdev;
100
101#ifdef SMC_USE_DMA
102 /* DMA needs the physical address of the chip */
103 u_long physaddr;
79d3b59a
RJ		 104 struct dma_chan *rxdma;
105 struct dma_chan *txdma;
699559f8
MD		 106 int rxdma_active;
107 int txdma_active;
108 struct sk_buff *current_rx_skb;
109 struct sk_buff *current_tx_skb;
110 struct device *dev;
111#endif
112 void __iomem *base;
12c03f59
MD		 113#ifdef SMC_DYNAMIC_BUS_CONFIG
114 struct smc911x_platdata cfg;
115#endif
699559f8 116};
0a0c72c9
DM		 117
118/*
119 * Define the bus width specific IO macros
120 */
121
12c03f59
MD		 122#ifdef SMC_DYNAMIC_BUS_CONFIG
123static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
124{
125 void __iomem *ioaddr = lp->base + reg;
126
127 if (lp->cfg.flags & SMC911X_USE_32BIT)
128 return readl(ioaddr);
129
130 if (lp->cfg.flags & SMC911X_USE_16BIT)
131 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
132
133 BUG();
134}
135
136static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
137 int reg)
138{
139 void __iomem *ioaddr = lp->base + reg;
140
141 if (lp->cfg.flags & SMC911X_USE_32BIT) {
142 writel(value, ioaddr);
143 return;
144 }
145
146 if (lp->cfg.flags & SMC911X_USE_16BIT) {
147 writew(value & 0xffff, ioaddr);
148 writew(value >> 16, ioaddr + 2);
149 return;
150 }
151
152 BUG();
153}
154
155static inline void SMC_insl(struct smc911x_local *lp, int reg,
156 void *addr, unsigned int count)
157{
158 void __iomem *ioaddr = lp->base + reg;
159
160 if (lp->cfg.flags & SMC911X_USE_32BIT) {
2925f6c0 161 ioread32_rep(ioaddr, addr, count);
12c03f59
MD		 162 return;
163 }
164
165 if (lp->cfg.flags & SMC911X_USE_16BIT) {
2925f6c0 166 ioread16_rep(ioaddr, addr, count * 2);
12c03f59
MD		 167 return;
168 }
169
170 BUG();
171}
172
173static inline void SMC_outsl(struct smc911x_local *lp, int reg,
174 void *addr, unsigned int count)
175{
176 void __iomem *ioaddr = lp->base + reg;
177
178 if (lp->cfg.flags & SMC911X_USE_32BIT) {
2925f6c0 179 iowrite32_rep(ioaddr, addr, count);
12c03f59
MD		 180 return;
181 }
182
183 if (lp->cfg.flags & SMC911X_USE_16BIT) {
2925f6c0 184 iowrite16_rep(ioaddr, addr, count * 2);
12c03f59
MD		 185 return;
186 }
187
188 BUG();
189}
190#else
0a0c72c9 191#if SMC_USE_16BIT
699559f8
MD		 192#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
193#define SMC_outl(v, lp, r) \
0a0c72c9 194 do{ \
699559f8
MD		 195 writew(v & 0xFFFF, (lp)->base + (r)); \
196 writew(v >> 16, (lp)->base + (r) + 2); \
0a0c72c9 197 } while (0)
2925f6c0
ML		 198#define SMC_insl(lp, r, p, l) ioread16_rep((short*)((lp)->base + (r)), p, l*2)
199#define SMC_outsl(lp, r, p, l) iowrite16_rep((short*)((lp)->base + (r)), p, l*2)
0a0c72c9
DM		 200
201#elif SMC_USE_32BIT
699559f8
MD		 202#define SMC_inl(lp, r) readl((lp)->base + (r))
203#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
2925f6c0
ML		 204#define SMC_insl(lp, r, p, l) ioread32_rep((int*)((lp)->base + (r)), p, l)
205#define SMC_outsl(lp, r, p, l) iowrite32_rep((int*)((lp)->base + (r)), p, l)
0a0c72c9
DM		 206
207#endif /* SMC_USE_16BIT */
12c03f59
MD		 208#endif /* SMC_DYNAMIC_BUS_CONFIG */
209
0a0c72c9 210
b173079f 211#ifdef SMC_USE_PXA_DMA
afb5b5c9 212
0a0c72c9
DM		 213/*
214 * Use a DMA for RX and TX packets.
215 */
216#include <linux/dma-mapping.h>
0a0c72c9
DM		 217
218static dma_addr_t rx_dmabuf, tx_dmabuf;
219static int rx_dmalen, tx_dmalen;
79d3b59a
RJ		 220static void smc911x_rx_dma_irq(void *data);
221static void smc911x_tx_dma_irq(void *data);
d5498bef 222
0a0c72c9
DM		 223#ifdef SMC_insl
224#undef SMC_insl
699559f8
MD		 225#define SMC_insl(lp, r, p, l) \
226 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
0a0c72c9
DM		 227
228static inline void
699559f8 229smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
79d3b59a 230 int reg, struct dma_chan *dma, u_char *buf, int len)
0a0c72c9 231{
79d3b59a
RJ		 232 struct dma_async_tx_descriptor *tx;
233
0a0c72c9
DM		 234 /* 64 bit alignment is required for memory to memory DMA */
235 if ((long)buf & 4) {
699559f8 236 *((u32 *)buf) = SMC_inl(lp, reg);
0a0c72c9
DM		 237 buf += 4;
238 len--;
239 }
240
241 len *= 4;
699559f8 242 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
0a0c72c9 243 rx_dmalen = len;
79d3b59a
RJ		 244 tx = dmaengine_prep_slave_single(dma, rx_dmabuf, rx_dmalen,
245 DMA_DEV_TO_MEM, 0);
246 if (tx) {
247 tx->callback = smc911x_rx_dma_irq;
248 tx->callback_param = lp;
249 dmaengine_submit(tx);
250 dma_async_issue_pending(dma);
251 }
0a0c72c9
DM		 252}
253#endif
254
0a0c72c9
DM		 255#ifdef SMC_outsl
256#undef SMC_outsl
699559f8
MD		 257#define SMC_outsl(lp, r, p, l) \
258 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
0a0c72c9
DM		 259
260static inline void
699559f8 261smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
79d3b59a 262 int reg, struct dma_chan *dma, u_char *buf, int len)
0a0c72c9 263{
79d3b59a
RJ		 264 struct dma_async_tx_descriptor *tx;
265
0a0c72c9
DM		 266 /* 64 bit alignment is required for memory to memory DMA */
267 if ((long)buf & 4) {
699559f8 268 SMC_outl(*((u32 *)buf), lp, reg);
0a0c72c9
DM		 269 buf += 4;
270 len--;
271 }
272
273 len *= 4;
699559f8 274 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
0a0c72c9 275 tx_dmalen = len;
79d3b59a
RJ		 276 tx = dmaengine_prep_slave_single(dma, tx_dmabuf, tx_dmalen,
277 DMA_DEV_TO_MEM, 0);
278 if (tx) {
279 tx->callback = smc911x_tx_dma_irq;
280 tx->callback_param = lp;
281 dmaengine_submit(tx);
282 dma_async_issue_pending(dma);
283 }
0a0c72c9
DM		 284}
285#endif
0a0c72c9
DM		 286#endif /* SMC_USE_PXA_DMA */
287
288
289/* Chip Parameters and Register Definitions */
290
291#define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
292
293#define SMC911X_IO_EXTENT 0x100
294
295#define SMC911X_EEPROM_LEN 7
296
297/* Below are the register offsets and bit definitions
298 * of the Lan911x memory space
299 */
300#define RX_DATA_FIFO (0x00)
301
302#define TX_DATA_FIFO (0x20)
303#define TX_CMD_A_INT_ON_COMP_ (0x80000000)
304#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
305#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
306#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
307#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
308#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
309#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
310#define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
311#define TX_CMD_A_BUF_SIZE_ (0x000007FF)
312#define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
313#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
314#define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
315#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
316
317#define RX_STATUS_FIFO (0x40)
318#define RX_STS_PKT_LEN_ (0x3FFF0000)
319#define RX_STS_ES_ (0x00008000)
320#define RX_STS_BCST_ (0x00002000)
321#define RX_STS_LEN_ERR_ (0x00001000)
322#define RX_STS_RUNT_ERR_ (0x00000800)
323#define RX_STS_MCAST_ (0x00000400)
324#define RX_STS_TOO_LONG_ (0x00000080)
325#define RX_STS_COLL_ (0x00000040)
326#define RX_STS_ETH_TYPE_ (0x00000020)
327#define RX_STS_WDOG_TMT_ (0x00000010)
328#define RX_STS_MII_ERR_ (0x00000008)
329#define RX_STS_DRIBBLING_ (0x00000004)
330#define RX_STS_CRC_ERR_ (0x00000002)
331#define RX_STATUS_FIFO_PEEK (0x44)
332#define TX_STATUS_FIFO (0x48)
333#define TX_STS_TAG_ (0xFFFF0000)
334#define TX_STS_ES_ (0x00008000)
335#define TX_STS_LOC_ (0x00000800)
336#define TX_STS_NO_CARR_ (0x00000400)
337#define TX_STS_LATE_COLL_ (0x00000200)
338#define TX_STS_MANY_COLL_ (0x00000100)
339#define TX_STS_COLL_CNT_ (0x00000078)
340#define TX_STS_MANY_DEFER_ (0x00000004)
341#define TX_STS_UNDERRUN_ (0x00000002)
342#define TX_STS_DEFERRED_ (0x00000001)
343#define TX_STATUS_FIFO_PEEK (0x4C)
344#define ID_REV (0x50)
345#define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
346#define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
347
348#define INT_CFG (0x54)
349#define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
350#define INT_CFG_INT_DEAS_CLR_ (0x00004000)
351#define INT_CFG_INT_DEAS_STS_ (0x00002000)
352#define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
353#define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
354#define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
355#define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
356
357#define INT_STS (0x58)
358#define INT_STS_SW_INT_ (0x80000000) /* R/WC */
359#define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
360#define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
361#define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
362#define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
363#define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
364#define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
365#define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
366#define INT_STS_PHY_INT_ (0x00040000) /* RO */
367#define INT_STS_PME_INT_ (0x00020000) /* R/WC */
368#define INT_STS_TXSO_ (0x00010000) /* R/WC */
369#define INT_STS_RWT_ (0x00008000) /* R/WC */
370#define INT_STS_RXE_ (0x00004000) /* R/WC */
371#define INT_STS_TXE_ (0x00002000) /* R/WC */
372//#define INT_STS_ERX_ (0x00001000) /* R/WC */
373#define INT_STS_TDFU_ (0x00000800) /* R/WC */
374#define INT_STS_TDFO_ (0x00000400) /* R/WC */
375#define INT_STS_TDFA_ (0x00000200) /* R/WC */
376#define INT_STS_TSFF_ (0x00000100) /* R/WC */
377#define INT_STS_TSFL_ (0x00000080) /* R/WC */
378//#define INT_STS_RXDF_ (0x00000040) /* R/WC */
379#define INT_STS_RDFO_ (0x00000040) /* R/WC */
380#define INT_STS_RDFL_ (0x00000020) /* R/WC */
381#define INT_STS_RSFF_ (0x00000010) /* R/WC */
382#define INT_STS_RSFL_ (0x00000008) /* R/WC */
383#define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
384#define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
385#define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
386
387#define INT_EN (0x5C)
388#define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
389#define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
390#define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
391#define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
392//#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
393#define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
394#define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
395#define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
396#define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
397#define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
398#define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
399#define INT_EN_RWT_EN_ (0x00008000) /* R/W */
400#define INT_EN_RXE_EN_ (0x00004000) /* R/W */
401#define INT_EN_TXE_EN_ (0x00002000) /* R/W */
402//#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
403#define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
404#define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
405#define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
406#define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
407#define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
408//#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
409#define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
410#define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
411#define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
412#define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
413#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
414#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
415#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
416
417#define BYTE_TEST (0x64)
418#define FIFO_INT (0x68)
419#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
420#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
421#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
422#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
423
424#define RX_CFG (0x6C)
425#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
426#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
427#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
428#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
429#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
430#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
431#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
432//#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
433
434#define TX_CFG (0x70)
435//#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
436//#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
437#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
438#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
439#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
440#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
441#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
442
443#define HW_CFG (0x74)
444#define HW_CFG_TTM_ (0x00200000) /* R/W */
445#define HW_CFG_SF_ (0x00100000) /* R/W */
446#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
447#define HW_CFG_TR_ (0x00003000) /* R/W */
448#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
449#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
450#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
451#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
452#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
453#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
454#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
455#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
456#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
457#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
458
459#define RX_DP_CTRL (0x78)
460#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
461#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
462
463#define RX_FIFO_INF (0x7C)
464#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
465#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
466
467#define TX_FIFO_INF (0x80)
468#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
469#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
470
471#define PMT_CTRL (0x84)
472#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
473#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
474#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
475#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
476#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
477#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
478#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
479#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
480#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
481#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
482#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
483#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
484#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
485#define PMT_CTRL_READY_ (0x00000001) /* RO */
486
487#define GPIO_CFG (0x88)
488#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
489#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
490#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
491#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
492#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
493#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
494#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
495#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
496#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
497#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
498#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
499#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
500#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
501#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
502#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
503#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
504#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
505#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
506
507#define GPT_CFG (0x8C)
508#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
509#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
510
511#define GPT_CNT (0x90)
512#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
513
514#define ENDIAN (0x98)
515#define FREE_RUN (0x9C)
516#define RX_DROP (0xA0)
517#define MAC_CSR_CMD (0xA4)
518#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
519#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
520#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
521
522#define MAC_CSR_DATA (0xA8)
523#define AFC_CFG (0xAC)
524#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
525#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
526#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
527#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
528#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
529#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
530#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
531
532#define E2P_CMD (0xB0)
533#define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
534#define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
535#define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
536#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
537#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
538#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
539#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
540#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
541#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
542#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
543#define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
544#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
545#define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
546
547#define E2P_DATA (0xB4)
548#define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
549/* end of LAN register offsets and bit definitions */
550
551/*
552 ****************************************************************************
553 ****************************************************************************
554 * MAC Control and Status Register (Indirect Address)
555 * Offset (through the MAC_CSR CMD and DATA port)
556 ****************************************************************************
557 ****************************************************************************
558 *
559 */
560#define MAC_CR (0x01) /* R/W */
561
562/* MAC_CR - MAC Control Register */
563#define MAC_CR_RXALL_ (0x80000000)
564// TODO: delete this bit? It is not described in the data sheet.
565#define MAC_CR_HBDIS_ (0x10000000)
566#define MAC_CR_RCVOWN_ (0x00800000)
567#define MAC_CR_LOOPBK_ (0x00200000)
568#define MAC_CR_FDPX_ (0x00100000)
569#define MAC_CR_MCPAS_ (0x00080000)
570#define MAC_CR_PRMS_ (0x00040000)
571#define MAC_CR_INVFILT_ (0x00020000)
572#define MAC_CR_PASSBAD_ (0x00010000)
573#define MAC_CR_HFILT_ (0x00008000)
574#define MAC_CR_HPFILT_ (0x00002000)
575#define MAC_CR_LCOLL_ (0x00001000)
576#define MAC_CR_BCAST_ (0x00000800)
577#define MAC_CR_DISRTY_ (0x00000400)
578#define MAC_CR_PADSTR_ (0x00000100)
579#define MAC_CR_BOLMT_MASK_ (0x000000C0)
580#define MAC_CR_DFCHK_ (0x00000020)
581#define MAC_CR_TXEN_ (0x00000008)
582#define MAC_CR_RXEN_ (0x00000004)
583
584#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
585#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
586#define HASHH (0x04) /* R/W */
587#define HASHL (0x05) /* R/W */
588
589#define MII_ACC (0x06) /* R/W */
590#define MII_ACC_PHY_ADDR_ (0x0000F800)
591#define MII_ACC_MIIRINDA_ (0x000007C0)
592#define MII_ACC_MII_WRITE_ (0x00000002)
593#define MII_ACC_MII_BUSY_ (0x00000001)
594
595#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
596
597#define FLOW (0x08) /* R/W */
598#define FLOW_FCPT_ (0xFFFF0000)
599#define FLOW_FCPASS_ (0x00000004)
600#define FLOW_FCEN_ (0x00000002)
601#define FLOW_FCBSY_ (0x00000001)
602
603#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
604#define VLAN1_VTI1_ (0x0000ffff)
605
606#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
607#define VLAN2_VTI2_ (0x0000ffff)
608
609#define WUFF (0x0B) /* WO */
610
611#define WUCSR (0x0C) /* R/W */
612#define WUCSR_GUE_ (0x00000200)
613#define WUCSR_WUFR_ (0x00000040)
614#define WUCSR_MPR_ (0x00000020)
615#define WUCSR_WAKE_EN_ (0x00000004)
616#define WUCSR_MPEN_ (0x00000002)
617
618/*
619 ****************************************************************************
620 * Chip Specific MII Defines
621 ****************************************************************************
622 *
623 * Phy register offsets and bit definitions
624 *
625 */
626
627#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
628//#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
629#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
630//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
631//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
632//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
633//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
634//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
635//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
636//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
637#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
638
639#define PHY_INT_SRC ((u32)29)
640#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
641#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
642#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
643#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
644#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
645#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
646#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
647
648#define PHY_INT_MASK ((u32)30)
649#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
650#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
651#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
652#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
653#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
654#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
655#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
656
657#define PHY_SPECIAL ((u32)31)
658#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
659#define PHY_SPECIAL_RES_ ((u16)0x0040)
660#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
661#define PHY_SPECIAL_SPD_ ((u16)0x001C)
662#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
663#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
664#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
665#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
666
667#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
668
669/* Chip ID values */
c6dcb827
GL		 670#define CHIP_9115 0x0115
671#define CHIP_9116 0x0116
672#define CHIP_9117 0x0117
673#define CHIP_9118 0x0118
07555c98 674#define CHIP_9211 0x9211
c6dcb827
GL		 675#define CHIP_9215 0x115A
676#define CHIP_9217 0x117A
677#define CHIP_9218 0x118A
0a0c72c9
DM		 678
679struct chip_id {
680 u16 id;
681 char *name;
682};
d5498bef 683
0a0c72c9
DM		 684static const struct chip_id chip_ids[] = {
685 { CHIP_9115, "LAN9115" },
686 { CHIP_9116, "LAN9116" },
687 { CHIP_9117, "LAN9117" },
688 { CHIP_9118, "LAN9118" },
07555c98 689 { CHIP_9211, "LAN9211" },
c6dcb827
GL		 690 { CHIP_9215, "LAN9215" },
691 { CHIP_9217, "LAN9217" },
692 { CHIP_9218, "LAN9218" },
0a0c72c9
DM		 693 { 0, NULL },
694};
695
696#define IS_REV_A(x) ((x & 0xFFFF)==0)
697
698/*
699 * Macros to abstract register access according to the data bus
700 * capabilities. Please use those and not the in/out primitives.
701 */
702/* FIFO read/write macros */
699559f8
MD		 703#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
704#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
705#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
706#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
0a0c72c9
DM		 707
708
709/* I/O mapped register read/write macros */
699559f8
MD		 710#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
711#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
712#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
713#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
714#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
715#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
716#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
717#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
718#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
719#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
720#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
721#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
722#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
723#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
724#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
725#define SMC_SET_FIFO_TDA(lp, x) \
0a0c72c9
DM		 726 do { \
727 unsigned long __flags; \
728 int __mask; \
729 local_irq_save(__flags); \
699559f8
MD		 730 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
731 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
0a0c72c9
DM		 732 local_irq_restore(__flags); \
733 } while (0)
699559f8 734#define SMC_SET_FIFO_TSL(lp, x) \
0a0c72c9
DM		 735 do { \
736 unsigned long __flags; \
737 int __mask; \
738 local_irq_save(__flags); \
699559f8
MD		 739 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
740 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
0a0c72c9
DM		 741 local_irq_restore(__flags); \
742 } while (0)
699559f8 743#define SMC_SET_FIFO_RSA(lp, x) \
0a0c72c9
DM		 744 do { \
745 unsigned long __flags; \
746 int __mask; \
747 local_irq_save(__flags); \
699559f8
MD		 748 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
749 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
0a0c72c9
DM		 750 local_irq_restore(__flags); \
751 } while (0)
699559f8 752#define SMC_SET_FIFO_RSL(lp, x) \
0a0c72c9
DM		 753 do { \
754 unsigned long __flags; \
755 int __mask; \
756 local_irq_save(__flags); \
699559f8
MD		 757 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
758 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
0a0c72c9
DM		 759 local_irq_restore(__flags); \
760 } while (0)
699559f8
MD		 761#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
762#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
763#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
764#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
765#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
766#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
767#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
768#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
769#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
770#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
771#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
772#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
773#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
774#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
775#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
776#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
777#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
778#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
779#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
780#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
781#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
782#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
783#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
784#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
785#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
786#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
787#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
788#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
789#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
790#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
0a0c72c9
DM		 791
792/* MAC register read/write macros */
699559f8 793#define SMC_GET_MAC_CSR(lp,a,v) \
0a0c72c9 794 do { \
699559f8
MD		 795 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
796 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
0a0c72c9 797 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
699559f8
MD		 798 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
799 v = SMC_GET_MAC_DATA((lp)); \
0a0c72c9 800 } while (0)
699559f8 801#define SMC_SET_MAC_CSR(lp,a,v) \
0a0c72c9 802 do { \
699559f8
MD		 803 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
804 SMC_SET_MAC_DATA((lp), v); \
805 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
806 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
0a0c72c9 807 } while (0)
699559f8
MD		 808#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
809#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
810#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
811#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
812#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
813#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
814#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
815#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
816#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
817#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
818#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
819#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
820#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
821#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
822#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
823#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
824#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
825#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
826#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
827#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
828#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
829#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
830#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
0a0c72c9
DM		 831
832/* PHY register read/write macros */
699559f8 833#define SMC_GET_MII(lp,a,phy,v) \
0a0c72c9
DM		 834 do { \
835 u32 __v; \
836 do { \
699559f8 837 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9 838 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8 839 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0a0c72c9
DM		 840 MII_ACC_MII_BUSY_); \
841 do { \
699559f8 842 SMC_GET_MII_ACC( (lp), __v); \
0a0c72c9 843 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8 844 SMC_GET_MII_DATA((lp), v); \
0a0c72c9 845 } while (0)
699559f8 846#define SMC_SET_MII(lp,a,phy,v) \
0a0c72c9
DM		 847 do { \
848 u32 __v; \
849 do { \
699559f8 850 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9 851 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8
MD		 852 SMC_SET_MII_DATA((lp), v); \
853 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0a0c72c9
DM		 854 MII_ACC_MII_BUSY_ | \
855 MII_ACC_MII_WRITE_ ); \
856 do { \
699559f8 857 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9
DM		 858 } while ( __v & MII_ACC_MII_BUSY_ ); \
859 } while (0)
699559f8
MD		 860#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
861#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
862#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
863#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
864#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
865#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
866#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
867#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
868#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
869#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
870#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
871#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
872#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
873#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
874#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
875#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
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DM		 876
877
878
879/* Misc read/write macros */
880
881#ifndef SMC_GET_MAC_ADDR
699559f8 882#define SMC_GET_MAC_ADDR(lp, addr) \
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DM		 883 do { \
884 unsigned int __v; \
885 \
699559f8 886 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
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DM		 887 addr[0] = __v; addr[1] = __v >> 8; \
888 addr[2] = __v >> 16; addr[3] = __v >> 24; \
699559f8 889 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
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DM		 890 addr[4] = __v; addr[5] = __v >> 8; \
891 } while (0)
892#endif
893
699559f8 894#define SMC_SET_MAC_ADDR(lp, addr) \
0a0c72c9 895 do { \
699559f8 896 SMC_SET_MAC_CSR((lp), ADDRL, \
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DM		 897 addr[0] | \
898 (addr[1] << 8) | \
899 (addr[2] << 16) | \
900 (addr[3] << 24)); \
699559f8 901 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
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DM		 902 } while (0)
903
904
699559f8 905#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
0a0c72c9 906 do { \
699559f8
MD		 907 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
908 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
909 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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DM		 910 } while (0)
911
912#endif /* _SMC911X_H_ */
Linux kernel - Deliverables
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