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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
0ab75ae8 | 21 | . along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
22 | . |
23 | . Information contained in this file was obtained from the LAN91C111 | |
24 | . manual from SMC. To get a copy, if you really want one, you can find | |
25 | . information under www.smsc.com. | |
26 | . | |
27 | . Authors | |
28 | . Erik Stahlman <erik@vt.edu> | |
29 | . Daris A Nevil <dnevil@snmc.com> | |
2f82af08 | 30 | . Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
31 | . |
32 | ---------------------------------------------------------------------------*/ | |
33 | #ifndef _SMC91X_H_ | |
34 | #define _SMC91X_H_ | |
35 | ||
d24c8f24 | 36 | #include <linux/dmaengine.h> |
3e947943 | 37 | #include <linux/smc91x.h> |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Define your architecture specific bus configuration parameters here. | |
41 | */ | |
42 | ||
b70661c7 | 43 | #if defined(CONFIG_ARM) |
1da177e4 | 44 | |
38fd6c38 EM |
45 | #include <asm/mach-types.h> |
46 | ||
47 | /* Now the bus width is specified in the platform data | |
48 | * pretend here to support all I/O access types | |
49 | */ | |
50 | #define SMC_CAN_USE_8BIT 1 | |
1da177e4 | 51 | #define SMC_CAN_USE_16BIT 1 |
38fd6c38 | 52 | #define SMC_CAN_USE_32BIT 1 |
1da177e4 LT |
53 | #define SMC_NOWAIT 1 |
54 | ||
3aed74cd | 55 | #define SMC_IO_SHIFT (lp->io_shift) |
1da177e4 | 56 | |
38fd6c38 | 57 | #define SMC_inb(a, r) readb((a) + (r)) |
1da177e4 | 58 | #define SMC_inw(a, r) readw((a) + (r)) |
38fd6c38 EM |
59 | #define SMC_inl(a, r) readl((a) + (r)) |
60 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
61 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
1da177e4 LT |
62 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
63 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
38fd6c38 EM |
64 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
65 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 66 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 67 | |
38fd6c38 EM |
68 | /* We actually can't write halfwords properly if not word aligned */ |
69 | static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) | |
70 | { | |
b70661c7 AB |
71 | if ((machine_is_mainstone() || machine_is_stargate2() || |
72 | machine_is_pxa_idp()) && reg & 2) { | |
1da177e4 LT |
73 | unsigned int v = val << 16; |
74 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
75 | writel(v, ioaddr + (reg & ~2)); | |
76 | } else { | |
77 | writew(val, ioaddr + reg); | |
78 | } | |
79 | } | |
80 | ||
1da177e4 LT |
81 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
82 | ||
83 | #define SMC_CAN_USE_8BIT 0 | |
84 | #define SMC_CAN_USE_16BIT 1 | |
85 | #define SMC_CAN_USE_32BIT 0 | |
86 | ||
87 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
88 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
89 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
90 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
91 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
92 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
93 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
94 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
95 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
96 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
97 | ||
9ded96f2 | 98 | #define SMC_IRQ_FLAGS (0) |
1da177e4 | 99 | |
1da177e4 LT |
100 | #elif defined(CONFIG_M32R) |
101 | ||
102 | #define SMC_CAN_USE_8BIT 0 | |
103 | #define SMC_CAN_USE_16BIT 1 | |
104 | #define SMC_CAN_USE_32BIT 0 | |
105 | ||
59dc76a4 | 106 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
f3ac9fbf HT |
107 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
108 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
109 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
110 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
111 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 112 | |
9ded96f2 | 113 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
114 | |
115 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
116 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
117 | ||
b920de1b DH |
118 | #elif defined(CONFIG_MN10300) |
119 | ||
120 | /* | |
121 | * MN10300/AM33 configuration | |
122 | */ | |
123 | ||
2f2a2132 | 124 | #include <unit/smc91111.h> |
b920de1b | 125 | |
6321b54a MS |
126 | #elif defined(CONFIG_ATARI) |
127 | ||
128 | #define SMC_CAN_USE_8BIT 1 | |
129 | #define SMC_CAN_USE_16BIT 1 | |
130 | #define SMC_CAN_USE_32BIT 1 | |
131 | #define SMC_NOWAIT 1 | |
132 | ||
133 | #define SMC_inb(a, r) readb((a) + (r)) | |
134 | #define SMC_inw(a, r) readw((a) + (r)) | |
135 | #define SMC_inl(a, r) readl((a) + (r)) | |
136 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
137 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
138 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
139 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
140 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
141 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
142 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
143 | ||
144 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
145 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
146 | ||
717ea4b3 GU |
147 | #elif defined(CONFIG_COLDFIRE) |
148 | ||
149 | #define SMC_CAN_USE_8BIT 0 | |
150 | #define SMC_CAN_USE_16BIT 1 | |
151 | #define SMC_CAN_USE_32BIT 0 | |
152 | #define SMC_NOWAIT 1 | |
153 | ||
154 | static inline void mcf_insw(void *a, unsigned char *p, int l) | |
155 | { | |
156 | u16 *wp = (u16 *) p; | |
157 | while (l-- > 0) | |
158 | *wp++ = readw(a); | |
159 | } | |
160 | ||
161 | static inline void mcf_outsw(void *a, unsigned char *p, int l) | |
162 | { | |
163 | u16 *wp = (u16 *) p; | |
164 | while (l-- > 0) | |
165 | writew(*wp++, a); | |
166 | } | |
167 | ||
168 | #define SMC_inw(a, r) _swapw(readw((a) + (r))) | |
169 | #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r)) | |
170 | #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) | |
171 | #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) | |
172 | ||
cf68ca1e | 173 | #define SMC_IRQ_FLAGS 0 |
717ea4b3 | 174 | |
f147d0b3 YS |
175 | #elif defined(CONFIG_H8300) |
176 | #define SMC_CAN_USE_8BIT 1 | |
177 | #define SMC_CAN_USE_16BIT 0 | |
178 | #define SMC_CAN_USE_32BIT 0 | |
179 | #define SMC_NOWAIT 0 | |
180 | ||
181 | #define SMC_inb(a, r) ioread8((a) + (r)) | |
182 | #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) | |
183 | #define SMC_insb(a, r, p, l) ioread8_rep((a) + (r), p, l) | |
184 | #define SMC_outsb(a, r, p, l) iowrite8_rep((a) + (r), p, l) | |
185 | ||
1da177e4 LT |
186 | #else |
187 | ||
b920de1b DH |
188 | /* |
189 | * Default configuration | |
190 | */ | |
191 | ||
1da177e4 LT |
192 | #define SMC_CAN_USE_8BIT 1 |
193 | #define SMC_CAN_USE_16BIT 1 | |
194 | #define SMC_CAN_USE_32BIT 1 | |
195 | #define SMC_NOWAIT 1 | |
196 | ||
d1c5ea33 MD |
197 | #define SMC_IO_SHIFT (lp->io_shift) |
198 | ||
4ba73aa1 WD |
199 | #define SMC_inb(a, r) ioread8((a) + (r)) |
200 | #define SMC_inw(a, r) ioread16((a) + (r)) | |
201 | #define SMC_inl(a, r) ioread32((a) + (r)) | |
202 | #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) | |
203 | #define SMC_outw(v, a, r) iowrite16(v, (a) + (r)) | |
204 | #define SMC_outl(v, a, r) iowrite32(v, (a) + (r)) | |
205 | #define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l) | |
206 | #define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l) | |
207 | #define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l) | |
208 | #define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l) | |
1da177e4 LT |
209 | |
210 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
211 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
212 | ||
213 | #endif | |
214 | ||
073ac8fd RK |
215 | |
216 | /* store this information for the driver.. */ | |
217 | struct smc_local { | |
218 | /* | |
219 | * If I have to wait until memory is available to send a | |
220 | * packet, I will store the skbuff here, until I get the | |
221 | * desired memory. Then, I'll send it out and free it. | |
222 | */ | |
223 | struct sk_buff *pending_tx_skb; | |
224 | struct tasklet_struct tx_task; | |
225 | ||
7d2911c4 TL |
226 | struct gpio_desc *power_gpio; |
227 | struct gpio_desc *reset_gpio; | |
228 | ||
073ac8fd RK |
229 | /* version/revision of the SMC91x chip */ |
230 | int version; | |
231 | ||
232 | /* Contains the current active transmission mode */ | |
233 | int tcr_cur_mode; | |
234 | ||
235 | /* Contains the current active receive mode */ | |
236 | int rcr_cur_mode; | |
237 | ||
238 | /* Contains the current active receive/phy mode */ | |
239 | int rpc_cur_mode; | |
240 | int ctl_rfduplx; | |
241 | int ctl_rspeed; | |
242 | ||
243 | u32 msg_enable; | |
244 | u32 phy_type; | |
245 | struct mii_if_info mii; | |
246 | ||
247 | /* work queue */ | |
248 | struct work_struct phy_configure; | |
249 | struct net_device *dev; | |
250 | int work_pending; | |
251 | ||
252 | spinlock_t lock; | |
253 | ||
52256c0e | 254 | #ifdef CONFIG_ARCH_PXA |
073ac8fd RK |
255 | /* DMA needs the physical address of the chip */ |
256 | u_long physaddr; | |
257 | struct device *device; | |
258 | #endif | |
d24c8f24 | 259 | struct dma_chan *dma_chan; |
073ac8fd RK |
260 | void __iomem *base; |
261 | void __iomem *datacs; | |
3e947943 | 262 | |
15919886 EM |
263 | /* the low address lines on some platforms aren't connected... */ |
264 | int io_shift; | |
265 | ||
3e947943 | 266 | struct smc91x_platdata cfg; |
073ac8fd RK |
267 | }; |
268 | ||
fa6d3be0 EM |
269 | #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) |
270 | #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) | |
271 | #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) | |
073ac8fd | 272 | |
52256c0e | 273 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
274 | /* |
275 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
276 | * always happening in irq context so no need to worry about races. TX is | |
277 | * different and probably not worth it for that reason, and not as critical | |
278 | * as RX which can overrun memory and lose packets. | |
279 | */ | |
280 | #include <linux/dma-mapping.h> | |
d24c8f24 | 281 | #include <linux/dma/pxa-dma.h> |
1da177e4 LT |
282 | |
283 | #ifdef SMC_insl | |
284 | #undef SMC_insl | |
285 | #define SMC_insl(a, r, p, l) \ | |
073ac8fd | 286 | smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) |
d24c8f24 RJ |
287 | static inline void |
288 | smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len) | |
289 | { | |
290 | dma_addr_t dmabuf; | |
291 | struct dma_async_tx_descriptor *tx; | |
292 | dma_cookie_t cookie; | |
293 | enum dma_status status; | |
294 | struct dma_tx_state state; | |
295 | ||
296 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); | |
297 | tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len, | |
298 | DMA_DEV_TO_MEM, 0); | |
299 | if (tx) { | |
300 | cookie = dmaengine_submit(tx); | |
301 | dma_async_issue_pending(lp->dma_chan); | |
302 | do { | |
303 | status = dmaengine_tx_status(lp->dma_chan, cookie, | |
304 | &state); | |
305 | cpu_relax(); | |
306 | } while (status != DMA_COMPLETE && status != DMA_ERROR && | |
307 | state.residue); | |
308 | dmaengine_terminate_all(lp->dma_chan); | |
309 | } | |
310 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); | |
311 | } | |
312 | ||
1da177e4 | 313 | static inline void |
073ac8fd | 314 | smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
315 | u_char *buf, int len) |
316 | { | |
d24c8f24 RJ |
317 | struct dma_slave_config config; |
318 | int ret; | |
1da177e4 LT |
319 | |
320 | /* fallback if no DMA available */ | |
d24c8f24 | 321 | if (!lp->dma_chan) { |
1da177e4 LT |
322 | readsl(ioaddr + reg, buf, len); |
323 | return; | |
324 | } | |
325 | ||
326 | /* 64 bit alignment is required for memory to memory DMA */ | |
327 | if ((long)buf & 4) { | |
328 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
329 | buf += 4; | |
330 | len--; | |
331 | } | |
332 | ||
d24c8f24 RJ |
333 | memset(&config, 0, sizeof(config)); |
334 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
335 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
336 | config.src_addr = lp->physaddr + reg; | |
337 | config.dst_addr = lp->physaddr + reg; | |
338 | config.src_maxburst = 32; | |
339 | config.dst_maxburst = 32; | |
340 | ret = dmaengine_slave_config(lp->dma_chan, &config); | |
341 | if (ret) { | |
342 | dev_err(lp->device, "dma channel configuration failed: %d\n", | |
343 | ret); | |
344 | return; | |
345 | } | |
346 | ||
1da177e4 | 347 | len *= 4; |
d24c8f24 | 348 | smc_pxa_dma_inpump(lp, buf, len); |
1da177e4 LT |
349 | } |
350 | #endif | |
351 | ||
352 | #ifdef SMC_insw | |
353 | #undef SMC_insw | |
354 | #define SMC_insw(a, r, p, l) \ | |
073ac8fd | 355 | smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) |
1da177e4 | 356 | static inline void |
073ac8fd | 357 | smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
358 | u_char *buf, int len) |
359 | { | |
d24c8f24 RJ |
360 | struct dma_slave_config config; |
361 | int ret; | |
1da177e4 LT |
362 | |
363 | /* fallback if no DMA available */ | |
d24c8f24 | 364 | if (!lp->dma_chan) { |
1da177e4 LT |
365 | readsw(ioaddr + reg, buf, len); |
366 | return; | |
367 | } | |
368 | ||
369 | /* 64 bit alignment is required for memory to memory DMA */ | |
370 | while ((long)buf & 6) { | |
371 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
372 | buf += 2; | |
373 | len--; | |
374 | } | |
375 | ||
d24c8f24 RJ |
376 | memset(&config, 0, sizeof(config)); |
377 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
378 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
379 | config.src_addr = lp->physaddr + reg; | |
380 | config.dst_addr = lp->physaddr + reg; | |
381 | config.src_maxburst = 32; | |
382 | config.dst_maxburst = 32; | |
383 | ret = dmaengine_slave_config(lp->dma_chan, &config); | |
384 | if (ret) { | |
385 | dev_err(lp->device, "dma channel configuration failed: %d\n", | |
386 | ret); | |
387 | return; | |
388 | } | |
389 | ||
1da177e4 | 390 | len *= 2; |
d24c8f24 | 391 | smc_pxa_dma_inpump(lp, buf, len); |
1da177e4 LT |
392 | } |
393 | #endif | |
394 | ||
52256c0e | 395 | #endif /* CONFIG_ARCH_PXA */ |
1da177e4 LT |
396 | |
397 | ||
09779c6d NP |
398 | /* |
399 | * Everything a particular hardware setup needs should have been defined | |
400 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
401 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
402 | * use of them. | |
403 | */ | |
404 | ||
405 | #if ! SMC_CAN_USE_32BIT | |
406 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
407 | #define SMC_outl(x, ioaddr, reg) BUG() | |
408 | #define SMC_insl(a, r, p, l) BUG() | |
409 | #define SMC_outsl(a, r, p, l) BUG() | |
410 | #endif | |
411 | ||
412 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
413 | #define SMC_insl(a, r, p, l) BUG() | |
414 | #define SMC_outsl(a, r, p, l) BUG() | |
415 | #endif | |
416 | ||
417 | #if ! SMC_CAN_USE_16BIT | |
418 | ||
419 | /* | |
420 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
421 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
422 | */ | |
423 | #define SMC_outw(x, ioaddr, reg) \ | |
424 | do { \ | |
425 | unsigned int __val16 = (x); \ | |
426 | SMC_outb( __val16, ioaddr, reg ); \ | |
427 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
428 | } while (0) | |
429 | #define SMC_inw(ioaddr, reg) \ | |
430 | ({ \ | |
431 | unsigned int __val16; \ | |
432 | __val16 = SMC_inb( ioaddr, reg ); \ | |
433 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
434 | __val16; \ | |
435 | }) | |
436 | ||
437 | #define SMC_insw(a, r, p, l) BUG() | |
438 | #define SMC_outsw(a, r, p, l) BUG() | |
439 | ||
440 | #endif | |
441 | ||
442 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
443 | #define SMC_insw(a, r, p, l) BUG() | |
444 | #define SMC_outsw(a, r, p, l) BUG() | |
445 | #endif | |
446 | ||
447 | #if ! SMC_CAN_USE_8BIT | |
448 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
449 | #define SMC_outb(x, ioaddr, reg) BUG() | |
450 | #define SMC_insb(a, r, p, l) BUG() | |
451 | #define SMC_outsb(a, r, p, l) BUG() | |
452 | #endif | |
453 | ||
454 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
455 | #define SMC_insb(a, r, p, l) BUG() | |
456 | #define SMC_outsb(a, r, p, l) BUG() | |
457 | #endif | |
458 | ||
459 | #ifndef SMC_CAN_USE_DATACS | |
460 | #define SMC_CAN_USE_DATACS 0 | |
461 | #endif | |
462 | ||
1da177e4 LT |
463 | #ifndef SMC_IO_SHIFT |
464 | #define SMC_IO_SHIFT 0 | |
465 | #endif | |
09779c6d NP |
466 | |
467 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 468 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
469 | #endif |
470 | ||
471 | #ifndef SMC_INTERRUPT_PREAMBLE | |
472 | #define SMC_INTERRUPT_PREAMBLE | |
473 | #endif | |
474 | ||
475 | ||
476 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
477 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
478 | #define SMC_DATA_EXTENT (4) | |
479 | ||
480 | /* | |
481 | . Bank Select Register: | |
482 | . | |
483 | . yyyy yyyy 0000 00xx | |
484 | . xx = bank number | |
485 | . yyyy yyyy = 0x33, for identification purposes. | |
486 | */ | |
487 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
488 | ||
489 | ||
490 | // Transmit Control Register | |
491 | /* BANK 0 */ | |
cfdfa865 | 492 | #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) |
1da177e4 LT |
493 | #define TCR_ENABLE 0x0001 // When 1 we can transmit |
494 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
495 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
496 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
497 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
498 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
499 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
500 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
501 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
502 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
503 | ||
504 | #define TCR_CLEAR 0 /* do NOTHING */ | |
505 | /* the default settings for the TCR register : */ | |
506 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
507 | ||
508 | ||
509 | // EPH Status Register | |
510 | /* BANK 0 */ | |
cfdfa865 | 511 | #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) |
1da177e4 LT |
512 | #define ES_TX_SUC 0x0001 // Last TX was successful |
513 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
514 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
515 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
516 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
517 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
518 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
519 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
520 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
521 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
522 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
523 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
524 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
525 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
526 | ||
527 | ||
528 | // Receive Control Register | |
529 | /* BANK 0 */ | |
cfdfa865 | 530 | #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) |
1da177e4 LT |
531 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted |
532 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
533 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
534 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
535 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
536 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
537 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
538 | #define RCR_SOFTRST 0x8000 // resets the chip | |
539 | ||
540 | /* the normal settings for the RCR register : */ | |
541 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
542 | #define RCR_CLEAR 0x0 // set it to a base state | |
543 | ||
544 | ||
545 | // Counter Register | |
546 | /* BANK 0 */ | |
cfdfa865 | 547 | #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) |
1da177e4 LT |
548 | |
549 | ||
550 | // Memory Information Register | |
551 | /* BANK 0 */ | |
cfdfa865 | 552 | #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) |
1da177e4 LT |
553 | |
554 | ||
555 | // Receive/Phy Control Register | |
556 | /* BANK 0 */ | |
cfdfa865 | 557 | #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) |
1da177e4 LT |
558 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. |
559 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
560 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
561 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
562 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
1da177e4 LT |
563 | |
564 | #ifndef RPC_LSA_DEFAULT | |
565 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
566 | #endif | |
567 | #ifndef RPC_LSB_DEFAULT | |
568 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
569 | #endif | |
570 | ||
b0dbcf51 | 571 | #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX) |
1da177e4 LT |
572 | |
573 | ||
574 | /* Bank 0 0x0C is reserved */ | |
575 | ||
576 | // Bank Select Register | |
577 | /* All Banks */ | |
578 | #define BSR_REG 0x000E | |
579 | ||
580 | ||
581 | // Configuration Reg | |
582 | /* BANK 1 */ | |
cfdfa865 | 583 | #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) |
1da177e4 LT |
584 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy |
585 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
586 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
587 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
588 | ||
589 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
590 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
591 | ||
592 | ||
593 | // Base Address Register | |
594 | /* BANK 1 */ | |
cfdfa865 | 595 | #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) |
1da177e4 LT |
596 | |
597 | ||
598 | // Individual Address Registers | |
599 | /* BANK 1 */ | |
cfdfa865 MD |
600 | #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) |
601 | #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) | |
602 | #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) | |
1da177e4 LT |
603 | |
604 | ||
605 | // General Purpose Register | |
606 | /* BANK 1 */ | |
cfdfa865 | 607 | #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) |
1da177e4 LT |
608 | |
609 | ||
610 | // Control Register | |
611 | /* BANK 1 */ | |
cfdfa865 | 612 | #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) |
1da177e4 LT |
613 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received |
614 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
615 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
616 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
617 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
618 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
619 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
620 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
621 | ||
622 | ||
623 | // MMU Command Register | |
624 | /* BANK 2 */ | |
cfdfa865 | 625 | #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) |
1da177e4 LT |
626 | #define MC_BUSY 1 // When 1 the last release has not completed |
627 | #define MC_NOP (0<<5) // No Op | |
628 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
629 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
630 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
631 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
632 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
633 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
634 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
635 | ||
636 | ||
637 | // Packet Number Register | |
638 | /* BANK 2 */ | |
cfdfa865 | 639 | #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) |
1da177e4 LT |
640 | |
641 | ||
642 | // Allocation Result Register | |
643 | /* BANK 2 */ | |
cfdfa865 | 644 | #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) |
1da177e4 LT |
645 | #define AR_FAILED 0x80 // Alocation Failed |
646 | ||
647 | ||
648 | // TX FIFO Ports Register | |
649 | /* BANK 2 */ | |
cfdfa865 | 650 | #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
651 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty |
652 | ||
653 | // RX FIFO Ports Register | |
654 | /* BANK 2 */ | |
cfdfa865 | 655 | #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) |
1da177e4 LT |
656 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty |
657 | ||
cfdfa865 | 658 | #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
659 | |
660 | // Pointer Register | |
661 | /* BANK 2 */ | |
cfdfa865 | 662 | #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) |
1da177e4 LT |
663 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area |
664 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
665 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
666 | ||
667 | ||
668 | // Data Register | |
669 | /* BANK 2 */ | |
cfdfa865 | 670 | #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) |
1da177e4 LT |
671 | |
672 | ||
673 | // Interrupt Status/Acknowledge Register | |
674 | /* BANK 2 */ | |
cfdfa865 | 675 | #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) |
1da177e4 LT |
676 | |
677 | ||
678 | // Interrupt Mask Register | |
679 | /* BANK 2 */ | |
cfdfa865 | 680 | #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) |
1da177e4 LT |
681 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt |
682 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
683 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
684 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
685 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
686 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
687 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
688 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
689 | ||
690 | ||
691 | // Multicast Table Registers | |
692 | /* BANK 3 */ | |
cfdfa865 MD |
693 | #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) |
694 | #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) | |
695 | #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) | |
696 | #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) | |
1da177e4 LT |
697 | |
698 | ||
699 | // Management Interface Register (MII) | |
700 | /* BANK 3 */ | |
cfdfa865 | 701 | #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) |
1da177e4 LT |
702 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup |
703 | #define MII_MDOE 0x0008 // MII Output Enable | |
704 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
705 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
706 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
707 | ||
708 | ||
709 | // Revision Register | |
710 | /* BANK 3 */ | |
711 | /* ( hi: chip id low: rev # ) */ | |
cfdfa865 | 712 | #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) |
1da177e4 LT |
713 | |
714 | ||
715 | // Early RCV Register | |
716 | /* BANK 3 */ | |
717 | /* this is NOT on SMC9192 */ | |
cfdfa865 | 718 | #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) |
1da177e4 LT |
719 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received |
720 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
721 | ||
722 | ||
723 | // External Register | |
724 | /* BANK 7 */ | |
cfdfa865 | 725 | #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) |
1da177e4 LT |
726 | |
727 | ||
728 | #define CHIP_9192 3 | |
729 | #define CHIP_9194 4 | |
730 | #define CHIP_9195 5 | |
731 | #define CHIP_9196 6 | |
732 | #define CHIP_91100 7 | |
733 | #define CHIP_91100FD 8 | |
734 | #define CHIP_91111FD 9 | |
735 | ||
736 | static const char * chip_ids[ 16 ] = { | |
737 | NULL, NULL, NULL, | |
738 | /* 3 */ "SMC91C90/91C92", | |
739 | /* 4 */ "SMC91C94", | |
740 | /* 5 */ "SMC91C95", | |
741 | /* 6 */ "SMC91C96", | |
742 | /* 7 */ "SMC91C100", | |
743 | /* 8 */ "SMC91C100FD", | |
744 | /* 9 */ "SMC91C11xFD", | |
745 | NULL, NULL, NULL, | |
746 | NULL, NULL, NULL}; | |
747 | ||
748 | ||
1da177e4 LT |
749 | /* |
750 | . Receive status bits | |
751 | */ | |
752 | #define RS_ALGNERR 0x8000 | |
753 | #define RS_BRODCAST 0x4000 | |
754 | #define RS_BADCRC 0x2000 | |
755 | #define RS_ODDFRAME 0x1000 | |
756 | #define RS_TOOLONG 0x0800 | |
757 | #define RS_TOOSHORT 0x0400 | |
758 | #define RS_MULTICAST 0x0001 | |
759 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
760 | ||
761 | ||
762 | /* | |
763 | * PHY IDs | |
764 | * LAN83C183 == LAN91C111 Internal PHY | |
765 | */ | |
766 | #define PHY_LAN83C183 0x0016f840 | |
767 | #define PHY_LAN83C180 0x02821c50 | |
768 | ||
769 | /* | |
770 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
771 | * | |
772 | * Generic PHY registers can be found in <linux/mii.h> | |
773 | * | |
774 | * These phy registers are specific to our on-board phy. | |
775 | */ | |
776 | ||
777 | // PHY Configuration Register 1 | |
778 | #define PHY_CFG1_REG 0x10 | |
779 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
780 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
781 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
782 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
783 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
784 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
785 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
786 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
787 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
788 | #define PHY_CFG1_TLVL_MASK 0x003C | |
789 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
790 | ||
791 | ||
792 | // PHY Configuration Register 2 | |
793 | #define PHY_CFG2_REG 0x11 | |
794 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
795 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
796 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
797 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
798 | ||
799 | // PHY Status Output (and Interrupt status) Register | |
800 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
801 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
802 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
803 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
804 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
805 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
806 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
807 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
808 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
809 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
810 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
811 | ||
812 | // PHY Interrupt/Status Mask Register | |
813 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
814 | // Uses the same bit definitions as PHY_INT_REG | |
815 | ||
816 | ||
817 | /* | |
818 | * SMC91C96 ethernet config and status registers. | |
819 | * These are in the "attribute" space. | |
820 | */ | |
821 | #define ECOR 0x8000 | |
822 | #define ECOR_RESET 0x80 | |
823 | #define ECOR_LEVEL_IRQ 0x40 | |
824 | #define ECOR_WR_ATTRIB 0x04 | |
825 | #define ECOR_ENABLE 0x01 | |
826 | ||
827 | #define ECSR 0x8002 | |
828 | #define ECSR_IOIS8 0x20 | |
829 | #define ECSR_PWRDWN 0x04 | |
830 | #define ECSR_INT 0x02 | |
831 | ||
832 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
833 | ||
834 | ||
835 | /* | |
836 | * Macros to abstract register access according to the data bus | |
837 | * capabilities. Please use those and not the in/out primitives. | |
838 | * Note: the following macros do *not* select the bank -- this must | |
839 | * be done separately as needed in the main code. The SMC_REG() macro | |
840 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
841 | * |
842 | * Note: despite inline functions being safer, everything leading to this | |
843 | * should preferably be macros to let BUG() display the line number in | |
844 | * the core source code since we're interested in the top call site | |
845 | * not in any inline function location. | |
1da177e4 LT |
846 | */ |
847 | ||
848 | #if SMC_DEBUG > 0 | |
cfdfa865 | 849 | #define SMC_REG(lp, reg, bank) \ |
1da177e4 | 850 | ({ \ |
cfdfa865 | 851 | int __b = SMC_CURRENT_BANK(lp); \ |
1da177e4 | 852 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ |
6389aa45 BB |
853 | pr_err("%s: bank reg screwed (0x%04x)\n", \ |
854 | CARDNAME, __b); \ | |
1da177e4 LT |
855 | BUG(); \ |
856 | } \ | |
857 | reg<<SMC_IO_SHIFT; \ | |
858 | }) | |
859 | #else | |
cfdfa865 | 860 | #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) |
1da177e4 LT |
861 | #endif |
862 | ||
09779c6d NP |
863 | /* |
864 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
865 | * aligned to a 32 bit boundary. I tell you that does exist! | |
866 | * Fortunately the affected register accesses can be easily worked around | |
25985edc | 867 | * since we can write zeroes to the preceding 16 bits without adverse |
09779c6d NP |
868 | * effects and use a 32-bit access. |
869 | * | |
870 | * Enforce it on any 32-bit capable setup for now. | |
871 | */ | |
3e947943 | 872 | #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) |
09779c6d | 873 | |
cfdfa865 | 874 | #define SMC_GET_PN(lp) \ |
3e947943 | 875 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ |
cfdfa865 | 876 | : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) |
09779c6d | 877 | |
cfdfa865 | 878 | #define SMC_SET_PN(lp, x) \ |
09779c6d | 879 | do { \ |
3e947943 | 880 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 881 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ |
3e947943 | 882 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 883 | SMC_outb(x, ioaddr, PN_REG(lp)); \ |
09779c6d | 884 | else \ |
cfdfa865 | 885 | SMC_outw(x, ioaddr, PN_REG(lp)); \ |
09779c6d NP |
886 | } while (0) |
887 | ||
cfdfa865 | 888 | #define SMC_GET_AR(lp) \ |
3e947943 | 889 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ |
cfdfa865 | 890 | : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) |
09779c6d | 891 | |
cfdfa865 | 892 | #define SMC_GET_TXFIFO(lp) \ |
3e947943 | 893 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ |
cfdfa865 | 894 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) |
09779c6d | 895 | |
cfdfa865 | 896 | #define SMC_GET_RXFIFO(lp) \ |
3e947943 | 897 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ |
cfdfa865 | 898 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) |
09779c6d | 899 | |
cfdfa865 | 900 | #define SMC_GET_INT(lp) \ |
3e947943 | 901 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ |
cfdfa865 | 902 | : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) |
09779c6d | 903 | |
cfdfa865 | 904 | #define SMC_ACK_INT(lp, x) \ |
1da177e4 | 905 | do { \ |
3e947943 | 906 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 907 | SMC_outb(x, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
908 | else { \ |
909 | unsigned long __flags; \ | |
910 | int __mask; \ | |
911 | local_irq_save(__flags); \ | |
cfdfa865 MD |
912 | __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ |
913 | SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ | |
09779c6d NP |
914 | local_irq_restore(__flags); \ |
915 | } \ | |
916 | } while (0) | |
917 | ||
cfdfa865 | 918 | #define SMC_GET_INT_MASK(lp) \ |
3e947943 | 919 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ |
cfdfa865 | 920 | : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) |
09779c6d | 921 | |
cfdfa865 | 922 | #define SMC_SET_INT_MASK(lp, x) \ |
09779c6d | 923 | do { \ |
3e947943 | 924 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 925 | SMC_outb(x, ioaddr, IM_REG(lp)); \ |
09779c6d | 926 | else \ |
cfdfa865 | 927 | SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
928 | } while (0) |
929 | ||
cfdfa865 | 930 | #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) |
09779c6d | 931 | |
cfdfa865 | 932 | #define SMC_SELECT_BANK(lp, x) \ |
09779c6d | 933 | do { \ |
3e947943 | 934 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
09779c6d NP |
935 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ |
936 | else \ | |
937 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
938 | } while (0) | |
939 | ||
cfdfa865 | 940 | #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) |
09779c6d | 941 | |
cfdfa865 | 942 | #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) |
09779c6d | 943 | |
cfdfa865 | 944 | #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) |
09779c6d | 945 | |
cfdfa865 | 946 | #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) |
09779c6d | 947 | |
cfdfa865 | 948 | #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) |
09779c6d | 949 | |
cfdfa865 | 950 | #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) |
09779c6d | 951 | |
cfdfa865 | 952 | #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) |
09779c6d | 953 | |
cfdfa865 | 954 | #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) |
09779c6d | 955 | |
357fe2c6 VS |
956 | #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp)) |
957 | ||
958 | #define SMC_SET_GP(lp, x) \ | |
959 | do { \ | |
960 | if (SMC_MUST_ALIGN_WRITE(lp)) \ | |
961 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \ | |
962 | else \ | |
963 | SMC_outw(x, ioaddr, GP_REG(lp)); \ | |
964 | } while (0) | |
965 | ||
cfdfa865 | 966 | #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) |
09779c6d | 967 | |
cfdfa865 | 968 | #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) |
09779c6d | 969 | |
cfdfa865 | 970 | #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) |
09779c6d | 971 | |
cfdfa865 | 972 | #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 973 | |
cfdfa865 | 974 | #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 975 | |
cfdfa865 | 976 | #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) |
09779c6d | 977 | |
cfdfa865 | 978 | #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) |
09779c6d | 979 | |
cfdfa865 | 980 | #define SMC_SET_PTR(lp, x) \ |
09779c6d | 981 | do { \ |
3e947943 | 982 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 983 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ |
09779c6d | 984 | else \ |
cfdfa865 | 985 | SMC_outw(x, ioaddr, PTR_REG(lp)); \ |
1da177e4 | 986 | } while (0) |
1da177e4 | 987 | |
cfdfa865 | 988 | #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) |
09779c6d | 989 | |
cfdfa865 | 990 | #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) |
09779c6d | 991 | |
cfdfa865 | 992 | #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) |
09779c6d | 993 | |
cfdfa865 | 994 | #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) |
09779c6d | 995 | |
cfdfa865 | 996 | #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) |
09779c6d | 997 | |
cfdfa865 | 998 | #define SMC_SET_RPC(lp, x) \ |
09779c6d | 999 | do { \ |
3e947943 | 1000 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1001 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ |
09779c6d | 1002 | else \ |
cfdfa865 | 1003 | SMC_outw(x, ioaddr, RPC_REG(lp)); \ |
09779c6d NP |
1004 | } while (0) |
1005 | ||
cfdfa865 | 1006 | #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) |
09779c6d | 1007 | |
cfdfa865 | 1008 | #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) |
1da177e4 LT |
1009 | |
1010 | #ifndef SMC_GET_MAC_ADDR | |
cfdfa865 | 1011 | #define SMC_GET_MAC_ADDR(lp, addr) \ |
1da177e4 LT |
1012 | do { \ |
1013 | unsigned int __v; \ | |
cfdfa865 | 1014 | __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ |
1da177e4 | 1015 | addr[0] = __v; addr[1] = __v >> 8; \ |
cfdfa865 | 1016 | __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ |
1da177e4 | 1017 | addr[2] = __v; addr[3] = __v >> 8; \ |
cfdfa865 | 1018 | __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ |
1da177e4 LT |
1019 | addr[4] = __v; addr[5] = __v >> 8; \ |
1020 | } while (0) | |
1021 | #endif | |
1022 | ||
cfdfa865 | 1023 | #define SMC_SET_MAC_ADDR(lp, addr) \ |
1da177e4 | 1024 | do { \ |
cfdfa865 MD |
1025 | SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ |
1026 | SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ | |
1027 | SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ | |
1da177e4 LT |
1028 | } while (0) |
1029 | ||
cfdfa865 | 1030 | #define SMC_SET_MCAST(lp, x) \ |
1da177e4 LT |
1031 | do { \ |
1032 | const unsigned char *mt = (x); \ | |
cfdfa865 MD |
1033 | SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ |
1034 | SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ | |
1035 | SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ | |
1036 | SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ | |
1da177e4 LT |
1037 | } while (0) |
1038 | ||
cfdfa865 | 1039 | #define SMC_PUT_PKT_HDR(lp, status, length) \ |
1da177e4 | 1040 | do { \ |
3e947943 | 1041 | if (SMC_32BIT(lp)) \ |
cfdfa865 MD |
1042 | SMC_outl((status) | (length)<<16, ioaddr, \ |
1043 | DATA_REG(lp)); \ | |
09779c6d | 1044 | else { \ |
cfdfa865 MD |
1045 | SMC_outw(status, ioaddr, DATA_REG(lp)); \ |
1046 | SMC_outw(length, ioaddr, DATA_REG(lp)); \ | |
09779c6d | 1047 | } \ |
1da177e4 | 1048 | } while (0) |
1da177e4 | 1049 | |
cfdfa865 | 1050 | #define SMC_GET_PKT_HDR(lp, status, length) \ |
1da177e4 | 1051 | do { \ |
3e947943 | 1052 | if (SMC_32BIT(lp)) { \ |
cfdfa865 | 1053 | unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ |
09779c6d NP |
1054 | (status) = __val & 0xffff; \ |
1055 | (length) = __val >> 16; \ | |
1056 | } else { \ | |
cfdfa865 MD |
1057 | (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ |
1058 | (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ | |
1da177e4 LT |
1059 | } \ |
1060 | } while (0) | |
1da177e4 | 1061 | |
cfdfa865 | 1062 | #define SMC_PUSH_DATA(lp, p, l) \ |
1da177e4 | 1063 | do { \ |
3e947943 | 1064 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1065 | void *__ptr = (p); \ |
1066 | int __len = (l); \ | |
fbd81976 | 1067 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1068 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
1069 | __len -= 2; \ | |
e9e4ea74 | 1070 | SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ |
09779c6d NP |
1071 | __ptr += 2; \ |
1072 | } \ | |
1073 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1074 | __ioaddr = lp->datacs; \ | |
cfdfa865 | 1075 | SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
09779c6d NP |
1076 | if (__len & 2) { \ |
1077 | __ptr += (__len & ~3); \ | |
e9e4ea74 | 1078 | SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ |
09779c6d | 1079 | } \ |
3e947943 | 1080 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1081 | SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1082 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1083 | SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ |
1da177e4 | 1084 | } while (0) |
1da177e4 | 1085 | |
cfdfa865 | 1086 | #define SMC_PULL_DATA(lp, p, l) \ |
09779c6d | 1087 | do { \ |
3e947943 | 1088 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1089 | void *__ptr = (p); \ |
1090 | int __len = (l); \ | |
fbd81976 | 1091 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1092 | if ((unsigned long)__ptr & 2) { \ |
1093 | /* \ | |
1094 | * We want 32bit alignment here. \ | |
1095 | * Since some buses perform a full \ | |
1096 | * 32bit fetch even for 16bit data \ | |
1097 | * we can't use SMC_inw() here. \ | |
1098 | * Back both source (on-chip) and \ | |
1099 | * destination pointers of 2 bytes. \ | |
1100 | * This is possible since the call to \ | |
1101 | * SMC_GET_PKT_HDR() already advanced \ | |
1102 | * the source pointer of 4 bytes, and \ | |
1103 | * the skb_reserve(skb, 2) advanced \ | |
1104 | * the destination pointer of 2 bytes. \ | |
1105 | */ \ | |
1106 | __ptr -= 2; \ | |
1107 | __len += 2; \ | |
cfdfa865 MD |
1108 | SMC_SET_PTR(lp, \ |
1109 | 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
09779c6d NP |
1110 | } \ |
1111 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1112 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1113 | __len += 2; \ |
cfdfa865 | 1114 | SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
3e947943 | 1115 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1116 | SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1117 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1118 | SMC_insb(ioaddr, DATA_REG(lp), p, l); \ |
09779c6d | 1119 | } while (0) |
1da177e4 LT |
1120 | |
1121 | #endif /* _SMC91X_H_ */ |