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fd9abb3d SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2004-2008 SMSC | |
4 | * Copyright (C) 2005-2008 ARM | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | * | |
20 | *************************************************************************** | |
21 | * Rewritten, heavily based on smsc911x simple driver by SMSC. | |
22 | * Partly uses io macros from smc91x.c by Nicolas Pitre | |
23 | * | |
24 | * Supported devices: | |
25 | * LAN9115, LAN9116, LAN9117, LAN9118 | |
26 | * LAN9215, LAN9216, LAN9217, LAN9218 | |
27 | * LAN9210, LAN9211 | |
28 | * LAN9220, LAN9221 | |
28c21379 | 29 | * LAN89218 |
fd9abb3d SG |
30 | * |
31 | */ | |
32 | ||
dffc6b24 JP |
33 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
34 | ||
fd9abb3d SG |
35 | #include <linux/crc32.h> |
36 | #include <linux/delay.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/init.h> | |
a6b7a407 | 41 | #include <linux/interrupt.h> |
fd9abb3d SG |
42 | #include <linux/ioport.h> |
43 | #include <linux/kernel.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/platform_device.h> | |
c7e963f6 | 47 | #include <linux/regulator/consumer.h> |
fd9abb3d | 48 | #include <linux/sched.h> |
fd9abb3d | 49 | #include <linux/timer.h> |
fd9abb3d SG |
50 | #include <linux/bug.h> |
51 | #include <linux/bitops.h> | |
52 | #include <linux/irq.h> | |
53 | #include <linux/io.h> | |
833cc67c | 54 | #include <linux/swab.h> |
fd9abb3d SG |
55 | #include <linux/phy.h> |
56 | #include <linux/smsc911x.h> | |
6cb87823 | 57 | #include <linux/device.h> |
79f88ee9 SG |
58 | #include <linux/of.h> |
59 | #include <linux/of_device.h> | |
60 | #include <linux/of_gpio.h> | |
61 | #include <linux/of_net.h> | |
fd9abb3d SG |
62 | #include "smsc911x.h" |
63 | ||
64 | #define SMSC_CHIPNAME "smsc911x" | |
65 | #define SMSC_MDIONAME "smsc911x-mdio" | |
66 | #define SMSC_DRV_VERSION "2008-10-21" | |
67 | ||
68 | MODULE_LICENSE("GPL"); | |
69 | MODULE_VERSION(SMSC_DRV_VERSION); | |
62038e4a | 70 | MODULE_ALIAS("platform:smsc911x"); |
fd9abb3d SG |
71 | |
72 | #if USE_DEBUG > 0 | |
73 | static int debug = 16; | |
74 | #else | |
75 | static int debug = 3; | |
76 | #endif | |
77 | ||
78 | module_param(debug, int, 0); | |
79 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
80 | ||
c326de88 MP |
81 | struct smsc911x_data; |
82 | ||
83 | struct smsc911x_ops { | |
84 | u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg); | |
85 | void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); | |
86 | void (*rx_readfifo)(struct smsc911x_data *pdata, | |
87 | unsigned int *buf, unsigned int wordcount); | |
88 | void (*tx_writefifo)(struct smsc911x_data *pdata, | |
89 | unsigned int *buf, unsigned int wordcount); | |
90 | }; | |
91 | ||
c7e963f6 RM |
92 | #define SMSC911X_NUM_SUPPLIES 2 |
93 | ||
fd9abb3d SG |
94 | struct smsc911x_data { |
95 | void __iomem *ioaddr; | |
96 | ||
97 | unsigned int idrev; | |
98 | ||
99 | /* used to decide which workarounds apply */ | |
100 | unsigned int generation; | |
101 | ||
102 | /* device configuration (copied from platform_data during probe) */ | |
2107fb8b | 103 | struct smsc911x_platform_config config; |
fd9abb3d SG |
104 | |
105 | /* This needs to be acquired before calling any of below: | |
106 | * smsc911x_mac_read(), smsc911x_mac_write() | |
107 | */ | |
108 | spinlock_t mac_lock; | |
109 | ||
492c5d94 | 110 | /* spinlock to ensure register accesses are serialised */ |
fd9abb3d | 111 | spinlock_t dev_lock; |
fd9abb3d SG |
112 | |
113 | struct phy_device *phy_dev; | |
114 | struct mii_bus *mii_bus; | |
115 | int phy_irq[PHY_MAX_ADDR]; | |
116 | unsigned int using_extphy; | |
117 | int last_duplex; | |
118 | int last_carrier; | |
119 | ||
120 | u32 msg_enable; | |
121 | unsigned int gpio_setting; | |
122 | unsigned int gpio_orig_setting; | |
123 | struct net_device *dev; | |
124 | struct napi_struct napi; | |
125 | ||
126 | unsigned int software_irq_signal; | |
127 | ||
128 | #ifdef USE_PHY_WORK_AROUND | |
129 | #define MIN_PACKET_SIZE (64) | |
130 | char loopback_tx_pkt[MIN_PACKET_SIZE]; | |
131 | char loopback_rx_pkt[MIN_PACKET_SIZE]; | |
132 | unsigned int resetcount; | |
133 | #endif | |
134 | ||
135 | /* Members for Multicast filter workaround */ | |
136 | unsigned int multicast_update_pending; | |
137 | unsigned int set_bits_mask; | |
138 | unsigned int clear_bits_mask; | |
139 | unsigned int hashhi; | |
140 | unsigned int hashlo; | |
c326de88 MP |
141 | |
142 | /* register access functions */ | |
143 | const struct smsc911x_ops *ops; | |
c7e963f6 RM |
144 | |
145 | /* regulators */ | |
146 | struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES]; | |
fd9abb3d SG |
147 | }; |
148 | ||
c326de88 MP |
149 | /* Easy access to information */ |
150 | #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift)) | |
151 | ||
492c5d94 | 152 | static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
fd9abb3d | 153 | { |
2107fb8b SG |
154 | if (pdata->config.flags & SMSC911X_USE_32BIT) |
155 | return readl(pdata->ioaddr + reg); | |
156 | ||
492c5d94 CM |
157 | if (pdata->config.flags & SMSC911X_USE_16BIT) |
158 | return ((readw(pdata->ioaddr + reg) & 0xFFFF) | | |
2107fb8b | 159 | ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); |
fd9abb3d | 160 | |
2107fb8b | 161 | BUG(); |
702403af | 162 | return 0; |
fd9abb3d SG |
163 | } |
164 | ||
c326de88 MP |
165 | static inline u32 |
166 | __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg) | |
167 | { | |
168 | if (pdata->config.flags & SMSC911X_USE_32BIT) | |
169 | return readl(pdata->ioaddr + __smsc_shift(pdata, reg)); | |
170 | ||
171 | if (pdata->config.flags & SMSC911X_USE_16BIT) | |
172 | return (readw(pdata->ioaddr + | |
173 | __smsc_shift(pdata, reg)) & 0xFFFF) | | |
174 | ((readw(pdata->ioaddr + | |
175 | __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16); | |
176 | ||
177 | BUG(); | |
178 | return 0; | |
179 | } | |
180 | ||
492c5d94 CM |
181 | static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
182 | { | |
183 | u32 data; | |
184 | unsigned long flags; | |
185 | ||
186 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 187 | data = pdata->ops->reg_read(pdata, reg); |
492c5d94 CM |
188 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
189 | ||
190 | return data; | |
191 | } | |
192 | ||
193 | static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, | |
194 | u32 val) | |
fd9abb3d | 195 | { |
2107fb8b SG |
196 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
197 | writel(val, pdata->ioaddr + reg); | |
198 | return; | |
199 | } | |
200 | ||
201 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
2107fb8b SG |
202 | writew(val & 0xFFFF, pdata->ioaddr + reg); |
203 | writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); | |
2107fb8b SG |
204 | return; |
205 | } | |
fd9abb3d | 206 | |
2107fb8b | 207 | BUG(); |
fd9abb3d SG |
208 | } |
209 | ||
c326de88 MP |
210 | static inline void |
211 | __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) | |
212 | { | |
213 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
214 | writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); | |
215 | return; | |
216 | } | |
217 | ||
218 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
219 | writew(val & 0xFFFF, | |
220 | pdata->ioaddr + __smsc_shift(pdata, reg)); | |
221 | writew((val >> 16) & 0xFFFF, | |
222 | pdata->ioaddr + __smsc_shift(pdata, reg + 2)); | |
223 | return; | |
224 | } | |
225 | ||
226 | BUG(); | |
227 | } | |
228 | ||
492c5d94 CM |
229 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
230 | u32 val) | |
231 | { | |
232 | unsigned long flags; | |
233 | ||
234 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 235 | pdata->ops->reg_write(pdata, reg, val); |
492c5d94 CM |
236 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
237 | } | |
238 | ||
fd9abb3d SG |
239 | /* Writes a packet to the TX_DATA_FIFO */ |
240 | static inline void | |
241 | smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, | |
242 | unsigned int wordcount) | |
243 | { | |
492c5d94 CM |
244 | unsigned long flags; |
245 | ||
246 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
247 | ||
833cc67c MD |
248 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
249 | while (wordcount--) | |
492c5d94 CM |
250 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, |
251 | swab32(*buf++)); | |
252 | goto out; | |
833cc67c MD |
253 | } |
254 | ||
2107fb8b SG |
255 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
256 | writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount); | |
492c5d94 | 257 | goto out; |
2107fb8b SG |
258 | } |
259 | ||
260 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
261 | while (wordcount--) | |
492c5d94 CM |
262 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++); |
263 | goto out; | |
2107fb8b SG |
264 | } |
265 | ||
266 | BUG(); | |
492c5d94 CM |
267 | out: |
268 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
fd9abb3d SG |
269 | } |
270 | ||
c326de88 MP |
271 | /* Writes a packet to the TX_DATA_FIFO - shifted version */ |
272 | static inline void | |
273 | smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
274 | unsigned int wordcount) | |
275 | { | |
276 | unsigned long flags; | |
277 | ||
278 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
279 | ||
280 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
281 | while (wordcount--) | |
282 | __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO, | |
283 | swab32(*buf++)); | |
284 | goto out; | |
285 | } | |
286 | ||
287 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
288 | writesl(pdata->ioaddr + __smsc_shift(pdata, | |
289 | TX_DATA_FIFO), buf, wordcount); | |
290 | goto out; | |
291 | } | |
292 | ||
293 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
294 | while (wordcount--) | |
295 | __smsc911x_reg_write_shift(pdata, | |
296 | TX_DATA_FIFO, *buf++); | |
297 | goto out; | |
298 | } | |
299 | ||
300 | BUG(); | |
301 | out: | |
302 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
303 | } | |
304 | ||
fd9abb3d SG |
305 | /* Reads a packet out of the RX_DATA_FIFO */ |
306 | static inline void | |
307 | smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, | |
308 | unsigned int wordcount) | |
309 | { | |
492c5d94 CM |
310 | unsigned long flags; |
311 | ||
312 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
313 | ||
833cc67c MD |
314 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
315 | while (wordcount--) | |
492c5d94 CM |
316 | *buf++ = swab32(__smsc911x_reg_read(pdata, |
317 | RX_DATA_FIFO)); | |
318 | goto out; | |
833cc67c MD |
319 | } |
320 | ||
2107fb8b SG |
321 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
322 | readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount); | |
492c5d94 | 323 | goto out; |
2107fb8b | 324 | } |
fd9abb3d | 325 | |
2107fb8b SG |
326 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
327 | while (wordcount--) | |
492c5d94 CM |
328 | *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO); |
329 | goto out; | |
2107fb8b SG |
330 | } |
331 | ||
332 | BUG(); | |
492c5d94 CM |
333 | out: |
334 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
2107fb8b | 335 | } |
fd9abb3d | 336 | |
c326de88 MP |
337 | /* Reads a packet out of the RX_DATA_FIFO - shifted version */ |
338 | static inline void | |
339 | smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
340 | unsigned int wordcount) | |
341 | { | |
342 | unsigned long flags; | |
343 | ||
344 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
345 | ||
346 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
347 | while (wordcount--) | |
348 | *buf++ = swab32(__smsc911x_reg_read_shift(pdata, | |
349 | RX_DATA_FIFO)); | |
350 | goto out; | |
351 | } | |
352 | ||
353 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
354 | readsl(pdata->ioaddr + __smsc_shift(pdata, | |
355 | RX_DATA_FIFO), buf, wordcount); | |
356 | goto out; | |
357 | } | |
358 | ||
359 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
360 | while (wordcount--) | |
361 | *buf++ = __smsc911x_reg_read_shift(pdata, | |
362 | RX_DATA_FIFO); | |
363 | goto out; | |
364 | } | |
365 | ||
366 | BUG(); | |
367 | out: | |
368 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
369 | } | |
370 | ||
c7e963f6 RM |
371 | /* |
372 | * enable resources, currently just regulators. | |
373 | */ | |
374 | static int smsc911x_enable_resources(struct platform_device *pdev) | |
375 | { | |
376 | struct net_device *ndev = platform_get_drvdata(pdev); | |
377 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
378 | int ret = 0; | |
379 | ||
380 | ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies), | |
381 | pdata->supplies); | |
382 | if (ret) | |
383 | netdev_err(ndev, "failed to enable regulators %d\n", | |
384 | ret); | |
385 | return ret; | |
386 | } | |
387 | ||
388 | /* | |
389 | * disable resources, currently just regulators. | |
390 | */ | |
391 | static int smsc911x_disable_resources(struct platform_device *pdev) | |
392 | { | |
393 | struct net_device *ndev = platform_get_drvdata(pdev); | |
394 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
395 | int ret = 0; | |
396 | ||
397 | ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies), | |
398 | pdata->supplies); | |
399 | return ret; | |
400 | } | |
401 | ||
402 | /* | |
403 | * Request resources, currently just regulators. | |
404 | * | |
405 | * The SMSC911x has two power pins: vddvario and vdd33a, in designs where | |
406 | * these are not always-on we need to request regulators to be turned on | |
407 | * before we can try to access the device registers. | |
408 | */ | |
409 | static int smsc911x_request_resources(struct platform_device *pdev) | |
410 | { | |
411 | struct net_device *ndev = platform_get_drvdata(pdev); | |
412 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
413 | int ret = 0; | |
414 | ||
415 | /* Request regulators */ | |
416 | pdata->supplies[0].supply = "vdd33a"; | |
417 | pdata->supplies[1].supply = "vddvario"; | |
418 | ret = regulator_bulk_get(&pdev->dev, | |
419 | ARRAY_SIZE(pdata->supplies), | |
420 | pdata->supplies); | |
421 | if (ret) | |
422 | netdev_err(ndev, "couldn't get regulators %d\n", | |
423 | ret); | |
424 | return ret; | |
425 | } | |
426 | ||
427 | /* | |
428 | * Free resources, currently just regulators. | |
429 | * | |
430 | */ | |
431 | static void smsc911x_free_resources(struct platform_device *pdev) | |
432 | { | |
433 | struct net_device *ndev = platform_get_drvdata(pdev); | |
434 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
435 | ||
436 | /* Free regulators */ | |
437 | regulator_bulk_free(ARRAY_SIZE(pdata->supplies), | |
438 | pdata->supplies); | |
439 | } | |
440 | ||
fd9abb3d SG |
441 | /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read |
442 | * and smsc911x_mac_write, so assumes mac_lock is held */ | |
443 | static int smsc911x_mac_complete(struct smsc911x_data *pdata) | |
444 | { | |
445 | int i; | |
446 | u32 val; | |
447 | ||
448 | SMSC_ASSERT_MAC_LOCK(pdata); | |
449 | ||
450 | for (i = 0; i < 40; i++) { | |
451 | val = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
452 | if (!(val & MAC_CSR_CMD_CSR_BUSY_)) | |
453 | return 0; | |
454 | } | |
dffc6b24 JP |
455 | SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. " |
456 | "MAC_CSR_CMD: 0x%08X", val); | |
fd9abb3d SG |
457 | return -EIO; |
458 | } | |
459 | ||
460 | /* Fetches a MAC register value. Assumes mac_lock is acquired */ | |
461 | static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) | |
462 | { | |
463 | unsigned int temp; | |
464 | ||
465 | SMSC_ASSERT_MAC_LOCK(pdata); | |
466 | ||
467 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
468 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 | 469 | SMSC_WARN(pdata, hw, "MAC busy at entry"); |
fd9abb3d SG |
470 | return 0xFFFFFFFF; |
471 | } | |
472 | ||
473 | /* Send the MAC cmd */ | |
474 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
475 | MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); | |
476 | ||
477 | /* Workaround for hardware read-after-write restriction */ | |
478 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
479 | ||
480 | /* Wait for the read to complete */ | |
481 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
482 | return smsc911x_reg_read(pdata, MAC_CSR_DATA); | |
483 | ||
dffc6b24 | 484 | SMSC_WARN(pdata, hw, "MAC busy after read"); |
fd9abb3d SG |
485 | return 0xFFFFFFFF; |
486 | } | |
487 | ||
488 | /* Set a mac register, mac_lock must be acquired before calling */ | |
489 | static void smsc911x_mac_write(struct smsc911x_data *pdata, | |
490 | unsigned int offset, u32 val) | |
491 | { | |
492 | unsigned int temp; | |
493 | ||
494 | SMSC_ASSERT_MAC_LOCK(pdata); | |
495 | ||
496 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
497 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 JP |
498 | SMSC_WARN(pdata, hw, |
499 | "smsc911x_mac_write failed, MAC busy at entry"); | |
fd9abb3d SG |
500 | return; |
501 | } | |
502 | ||
503 | /* Send data to write */ | |
504 | smsc911x_reg_write(pdata, MAC_CSR_DATA, val); | |
505 | ||
506 | /* Write the actual data */ | |
507 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
508 | MAC_CSR_CMD_CSR_BUSY_)); | |
509 | ||
510 | /* Workaround for hardware read-after-write restriction */ | |
511 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
512 | ||
513 | /* Wait for the write to complete */ | |
514 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
515 | return; | |
516 | ||
dffc6b24 | 517 | SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write"); |
fd9abb3d SG |
518 | } |
519 | ||
520 | /* Get a phy register */ | |
521 | static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | |
522 | { | |
523 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
524 | unsigned long flags; | |
525 | unsigned int addr; | |
526 | int i, reg; | |
527 | ||
528 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
529 | ||
530 | /* Confirm MII not busy */ | |
531 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 532 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???"); |
fd9abb3d SG |
533 | reg = -EIO; |
534 | goto out; | |
535 | } | |
536 | ||
537 | /* Set the address, index & direction (read from PHY) */ | |
538 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6); | |
539 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
540 | ||
541 | /* Wait for read to complete w/ timeout */ | |
542 | for (i = 0; i < 100; i++) | |
543 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
544 | reg = smsc911x_mac_read(pdata, MII_DATA); | |
545 | goto out; | |
546 | } | |
547 | ||
dffc6b24 | 548 | SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish"); |
fd9abb3d SG |
549 | reg = -EIO; |
550 | ||
551 | out: | |
552 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
553 | return reg; | |
554 | } | |
555 | ||
556 | /* Set a phy register */ | |
557 | static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
558 | u16 val) | |
559 | { | |
560 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
561 | unsigned long flags; | |
562 | unsigned int addr; | |
563 | int i, reg; | |
564 | ||
565 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
566 | ||
567 | /* Confirm MII not busy */ | |
568 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 569 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???"); |
fd9abb3d SG |
570 | reg = -EIO; |
571 | goto out; | |
572 | } | |
573 | ||
574 | /* Put the data to write in the MAC */ | |
575 | smsc911x_mac_write(pdata, MII_DATA, val); | |
576 | ||
577 | /* Set the address, index & direction (write to PHY) */ | |
578 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
579 | MII_ACC_MII_WRITE_; | |
580 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
581 | ||
582 | /* Wait for write to complete w/ timeout */ | |
583 | for (i = 0; i < 100; i++) | |
584 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
585 | reg = 0; | |
586 | goto out; | |
587 | } | |
588 | ||
dffc6b24 | 589 | SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish"); |
fd9abb3d SG |
590 | reg = -EIO; |
591 | ||
592 | out: | |
593 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
594 | return reg; | |
595 | } | |
596 | ||
d23f028a SG |
597 | /* Switch to external phy. Assumes tx and rx are stopped. */ |
598 | static void smsc911x_phy_enable_external(struct smsc911x_data *pdata) | |
fd9abb3d SG |
599 | { |
600 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
601 | ||
d23f028a SG |
602 | /* Disable phy clocks to the MAC */ |
603 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
604 | hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; | |
605 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
606 | udelay(10); /* Enough time for clocks to stop */ | |
fd9abb3d | 607 | |
d23f028a SG |
608 | /* Switch to external phy */ |
609 | hwcfg |= HW_CFG_EXT_PHY_EN_; | |
610 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
fd9abb3d | 611 | |
d23f028a SG |
612 | /* Enable phy clocks to the MAC */ |
613 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
614 | hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; | |
615 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
616 | udelay(10); /* Enough time for clocks to restart */ | |
fd9abb3d | 617 | |
d23f028a SG |
618 | hwcfg |= HW_CFG_SMI_SEL_; |
619 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
620 | } | |
fd9abb3d | 621 | |
d23f028a SG |
622 | /* Autodetects and enables external phy if present on supported chips. |
623 | * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY | |
624 | * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */ | |
625 | static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata) | |
626 | { | |
627 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
fd9abb3d | 628 | |
d23f028a | 629 | if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) { |
dffc6b24 | 630 | SMSC_TRACE(pdata, hw, "Forcing internal PHY"); |
d23f028a SG |
631 | pdata->using_extphy = 0; |
632 | } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) { | |
dffc6b24 | 633 | SMSC_TRACE(pdata, hw, "Forcing external PHY"); |
d23f028a SG |
634 | smsc911x_phy_enable_external(pdata); |
635 | pdata->using_extphy = 1; | |
636 | } else if (hwcfg & HW_CFG_EXT_PHY_DET_) { | |
dffc6b24 JP |
637 | SMSC_TRACE(pdata, hw, |
638 | "HW_CFG EXT_PHY_DET set, using external PHY"); | |
d23f028a | 639 | smsc911x_phy_enable_external(pdata); |
fd9abb3d SG |
640 | pdata->using_extphy = 1; |
641 | } else { | |
dffc6b24 JP |
642 | SMSC_TRACE(pdata, hw, |
643 | "HW_CFG EXT_PHY_DET clear, using internal PHY"); | |
d23f028a | 644 | pdata->using_extphy = 0; |
fd9abb3d | 645 | } |
fd9abb3d SG |
646 | } |
647 | ||
648 | /* Fetches a tx status out of the status fifo */ | |
649 | static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) | |
650 | { | |
651 | unsigned int result = | |
652 | smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; | |
653 | ||
654 | if (result != 0) | |
655 | result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); | |
656 | ||
657 | return result; | |
658 | } | |
659 | ||
660 | /* Fetches the next rx status */ | |
661 | static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) | |
662 | { | |
663 | unsigned int result = | |
664 | smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; | |
665 | ||
666 | if (result != 0) | |
667 | result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); | |
668 | ||
669 | return result; | |
670 | } | |
671 | ||
672 | #ifdef USE_PHY_WORK_AROUND | |
673 | static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) | |
674 | { | |
675 | unsigned int tries; | |
676 | u32 wrsz; | |
677 | u32 rdsz; | |
678 | ulong bufp; | |
679 | ||
680 | for (tries = 0; tries < 10; tries++) { | |
681 | unsigned int txcmd_a; | |
682 | unsigned int txcmd_b; | |
683 | unsigned int status; | |
684 | unsigned int pktlength; | |
685 | unsigned int i; | |
686 | ||
687 | /* Zero-out rx packet memory */ | |
688 | memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); | |
689 | ||
690 | /* Write tx packet to 118 */ | |
691 | txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16; | |
692 | txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
693 | txcmd_a |= MIN_PACKET_SIZE; | |
694 | ||
695 | txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; | |
696 | ||
697 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a); | |
698 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b); | |
699 | ||
700 | bufp = (ulong)pdata->loopback_tx_pkt & (~0x3); | |
701 | wrsz = MIN_PACKET_SIZE + 3; | |
702 | wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3); | |
703 | wrsz >>= 2; | |
704 | ||
c326de88 | 705 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d SG |
706 | |
707 | /* Wait till transmit is done */ | |
708 | i = 60; | |
709 | do { | |
710 | udelay(5); | |
711 | status = smsc911x_tx_get_txstatus(pdata); | |
712 | } while ((i--) && (!status)); | |
713 | ||
714 | if (!status) { | |
dffc6b24 JP |
715 | SMSC_WARN(pdata, hw, |
716 | "Failed to transmit during loopback test"); | |
fd9abb3d SG |
717 | continue; |
718 | } | |
719 | if (status & TX_STS_ES_) { | |
dffc6b24 JP |
720 | SMSC_WARN(pdata, hw, |
721 | "Transmit encountered errors during loopback test"); | |
fd9abb3d SG |
722 | continue; |
723 | } | |
724 | ||
725 | /* Wait till receive is done */ | |
726 | i = 60; | |
727 | do { | |
728 | udelay(5); | |
729 | status = smsc911x_rx_get_rxstatus(pdata); | |
730 | } while ((i--) && (!status)); | |
731 | ||
732 | if (!status) { | |
dffc6b24 JP |
733 | SMSC_WARN(pdata, hw, |
734 | "Failed to receive during loopback test"); | |
fd9abb3d SG |
735 | continue; |
736 | } | |
737 | if (status & RX_STS_ES_) { | |
dffc6b24 JP |
738 | SMSC_WARN(pdata, hw, |
739 | "Receive encountered errors during loopback test"); | |
fd9abb3d SG |
740 | continue; |
741 | } | |
742 | ||
743 | pktlength = ((status & 0x3FFF0000UL) >> 16); | |
744 | bufp = (ulong)pdata->loopback_rx_pkt; | |
745 | rdsz = pktlength + 3; | |
746 | rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3); | |
747 | rdsz >>= 2; | |
748 | ||
c326de88 | 749 | pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz); |
fd9abb3d SG |
750 | |
751 | if (pktlength != (MIN_PACKET_SIZE + 4)) { | |
dffc6b24 JP |
752 | SMSC_WARN(pdata, hw, "Unexpected packet size " |
753 | "during loop back test, size=%d, will retry", | |
754 | pktlength); | |
fd9abb3d SG |
755 | } else { |
756 | unsigned int j; | |
757 | int mismatch = 0; | |
758 | for (j = 0; j < MIN_PACKET_SIZE; j++) { | |
759 | if (pdata->loopback_tx_pkt[j] | |
760 | != pdata->loopback_rx_pkt[j]) { | |
761 | mismatch = 1; | |
762 | break; | |
763 | } | |
764 | } | |
765 | if (!mismatch) { | |
dffc6b24 | 766 | SMSC_TRACE(pdata, hw, "Successfully verified " |
fd9abb3d SG |
767 | "loopback packet"); |
768 | return 0; | |
769 | } else { | |
dffc6b24 JP |
770 | SMSC_WARN(pdata, hw, "Data mismatch " |
771 | "during loop back test, will retry"); | |
fd9abb3d SG |
772 | } |
773 | } | |
774 | } | |
775 | ||
776 | return -EIO; | |
777 | } | |
778 | ||
779 | static int smsc911x_phy_reset(struct smsc911x_data *pdata) | |
780 | { | |
781 | struct phy_device *phy_dev = pdata->phy_dev; | |
782 | unsigned int temp; | |
783 | unsigned int i = 100000; | |
784 | ||
785 | BUG_ON(!phy_dev); | |
786 | BUG_ON(!phy_dev->bus); | |
787 | ||
dffc6b24 | 788 | SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset"); |
fd9abb3d SG |
789 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET); |
790 | do { | |
791 | msleep(1); | |
792 | temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, | |
793 | MII_BMCR); | |
794 | } while ((i--) && (temp & BMCR_RESET)); | |
795 | ||
796 | if (temp & BMCR_RESET) { | |
dffc6b24 | 797 | SMSC_WARN(pdata, hw, "PHY reset failed to complete"); |
fd9abb3d SG |
798 | return -EIO; |
799 | } | |
800 | /* Extra delay required because the phy may not be completed with | |
801 | * its reset when BMCR_RESET is cleared. Specs say 256 uS is | |
802 | * enough delay but using 1ms here to be safe */ | |
803 | msleep(1); | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | static int smsc911x_phy_loopbacktest(struct net_device *dev) | |
809 | { | |
810 | struct smsc911x_data *pdata = netdev_priv(dev); | |
811 | struct phy_device *phy_dev = pdata->phy_dev; | |
812 | int result = -EIO; | |
813 | unsigned int i, val; | |
814 | unsigned long flags; | |
815 | ||
816 | /* Initialise tx packet using broadcast destination address */ | |
817 | memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN); | |
818 | ||
819 | /* Use incrementing source address */ | |
820 | for (i = 6; i < 12; i++) | |
821 | pdata->loopback_tx_pkt[i] = (char)i; | |
822 | ||
823 | /* Set length type field */ | |
824 | pdata->loopback_tx_pkt[12] = 0x00; | |
825 | pdata->loopback_tx_pkt[13] = 0x00; | |
826 | ||
827 | for (i = 14; i < MIN_PACKET_SIZE; i++) | |
828 | pdata->loopback_tx_pkt[i] = (char)i; | |
829 | ||
830 | val = smsc911x_reg_read(pdata, HW_CFG); | |
831 | val &= HW_CFG_TX_FIF_SZ_; | |
832 | val |= HW_CFG_SF_; | |
833 | smsc911x_reg_write(pdata, HW_CFG, val); | |
834 | ||
835 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
836 | smsc911x_reg_write(pdata, RX_CFG, | |
837 | (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8); | |
838 | ||
839 | for (i = 0; i < 10; i++) { | |
840 | /* Set PHY to 10/FD, no ANEG, and loopback mode */ | |
841 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, | |
842 | BMCR_LOOPBACK | BMCR_FULLDPLX); | |
843 | ||
844 | /* Enable MAC tx/rx, FD */ | |
845 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
846 | smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ | |
847 | | MAC_CR_TXEN_ | MAC_CR_RXEN_); | |
848 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
849 | ||
850 | if (smsc911x_phy_check_loopbackpkt(pdata) == 0) { | |
851 | result = 0; | |
852 | break; | |
853 | } | |
854 | pdata->resetcount++; | |
855 | ||
856 | /* Disable MAC rx */ | |
857 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
858 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
859 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
860 | ||
861 | smsc911x_phy_reset(pdata); | |
862 | } | |
863 | ||
864 | /* Disable MAC */ | |
865 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
866 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
867 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
868 | ||
869 | /* Cancel PHY loopback mode */ | |
870 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0); | |
871 | ||
872 | smsc911x_reg_write(pdata, TX_CFG, 0); | |
873 | smsc911x_reg_write(pdata, RX_CFG, 0); | |
874 | ||
875 | return result; | |
876 | } | |
877 | #endif /* USE_PHY_WORK_AROUND */ | |
878 | ||
fd9abb3d SG |
879 | static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) |
880 | { | |
881 | struct phy_device *phy_dev = pdata->phy_dev; | |
882 | u32 afc = smsc911x_reg_read(pdata, AFC_CFG); | |
883 | u32 flow; | |
884 | unsigned long flags; | |
885 | ||
886 | if (phy_dev->duplex == DUPLEX_FULL) { | |
887 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | |
888 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | |
bc02ff95 | 889 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
fd9abb3d SG |
890 | |
891 | if (cap & FLOW_CTRL_RX) | |
892 | flow = 0xFFFF0002; | |
893 | else | |
894 | flow = 0; | |
895 | ||
896 | if (cap & FLOW_CTRL_TX) | |
897 | afc |= 0xF; | |
898 | else | |
899 | afc &= ~0xF; | |
900 | ||
dffc6b24 JP |
901 | SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s", |
902 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | |
903 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | |
fd9abb3d | 904 | } else { |
dffc6b24 | 905 | SMSC_TRACE(pdata, hw, "half duplex"); |
fd9abb3d SG |
906 | flow = 0; |
907 | afc |= 0xF; | |
908 | } | |
909 | ||
910 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
911 | smsc911x_mac_write(pdata, FLOW, flow); | |
912 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
913 | ||
914 | smsc911x_reg_write(pdata, AFC_CFG, afc); | |
915 | } | |
916 | ||
917 | /* Update link mode if anything has changed. Called periodically when the | |
918 | * PHY is in polling mode, even if nothing has changed. */ | |
919 | static void smsc911x_phy_adjust_link(struct net_device *dev) | |
920 | { | |
921 | struct smsc911x_data *pdata = netdev_priv(dev); | |
922 | struct phy_device *phy_dev = pdata->phy_dev; | |
923 | unsigned long flags; | |
924 | int carrier; | |
925 | ||
926 | if (phy_dev->duplex != pdata->last_duplex) { | |
927 | unsigned int mac_cr; | |
dffc6b24 | 928 | SMSC_TRACE(pdata, hw, "duplex state has changed"); |
fd9abb3d SG |
929 | |
930 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
931 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
932 | if (phy_dev->duplex) { | |
dffc6b24 JP |
933 | SMSC_TRACE(pdata, hw, |
934 | "configuring for full duplex mode"); | |
fd9abb3d SG |
935 | mac_cr |= MAC_CR_FDPX_; |
936 | } else { | |
dffc6b24 JP |
937 | SMSC_TRACE(pdata, hw, |
938 | "configuring for half duplex mode"); | |
fd9abb3d SG |
939 | mac_cr &= ~MAC_CR_FDPX_; |
940 | } | |
941 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
942 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
943 | ||
944 | smsc911x_phy_update_flowcontrol(pdata); | |
945 | pdata->last_duplex = phy_dev->duplex; | |
946 | } | |
947 | ||
948 | carrier = netif_carrier_ok(dev); | |
949 | if (carrier != pdata->last_carrier) { | |
dffc6b24 | 950 | SMSC_TRACE(pdata, hw, "carrier state has changed"); |
fd9abb3d | 951 | if (carrier) { |
dffc6b24 | 952 | SMSC_TRACE(pdata, hw, "configuring for carrier OK"); |
fd9abb3d SG |
953 | if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && |
954 | (!pdata->using_extphy)) { | |
88393161 | 955 | /* Restore original GPIO configuration */ |
fd9abb3d SG |
956 | pdata->gpio_setting = pdata->gpio_orig_setting; |
957 | smsc911x_reg_write(pdata, GPIO_CFG, | |
958 | pdata->gpio_setting); | |
959 | } | |
960 | } else { | |
dffc6b24 | 961 | SMSC_TRACE(pdata, hw, "configuring for no carrier"); |
fd9abb3d SG |
962 | /* Check global setting that LED1 |
963 | * usage is 10/100 indicator */ | |
964 | pdata->gpio_setting = smsc911x_reg_read(pdata, | |
965 | GPIO_CFG); | |
8e95a202 JP |
966 | if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) && |
967 | (!pdata->using_extphy)) { | |
fd9abb3d | 968 | /* Force 10/100 LED off, after saving |
88393161 | 969 | * original GPIO configuration */ |
fd9abb3d SG |
970 | pdata->gpio_orig_setting = pdata->gpio_setting; |
971 | ||
972 | pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; | |
973 | pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ | |
974 | | GPIO_CFG_GPIODIR0_ | |
975 | | GPIO_CFG_GPIOD0_); | |
976 | smsc911x_reg_write(pdata, GPIO_CFG, | |
977 | pdata->gpio_setting); | |
978 | } | |
979 | } | |
980 | pdata->last_carrier = carrier; | |
981 | } | |
982 | } | |
983 | ||
984 | static int smsc911x_mii_probe(struct net_device *dev) | |
985 | { | |
986 | struct smsc911x_data *pdata = netdev_priv(dev); | |
987 | struct phy_device *phydev = NULL; | |
e4a474f8 | 988 | int ret; |
fd9abb3d SG |
989 | |
990 | /* find the first phy */ | |
e4a474f8 | 991 | phydev = phy_find_first(pdata->mii_bus); |
fd9abb3d | 992 | if (!phydev) { |
dffc6b24 | 993 | netdev_err(dev, "no PHY found\n"); |
fd9abb3d SG |
994 | return -ENODEV; |
995 | } | |
996 | ||
dffc6b24 JP |
997 | SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X", |
998 | phydev->addr, phydev->phy_id); | |
e4a474f8 | 999 | |
1000 | ret = phy_connect_direct(dev, phydev, | |
1001 | &smsc911x_phy_adjust_link, 0, | |
1002 | pdata->config.phy_interface); | |
fd9abb3d | 1003 | |
e4a474f8 | 1004 | if (ret) { |
dffc6b24 | 1005 | netdev_err(dev, "Could not attach to PHY\n"); |
e4a474f8 | 1006 | return ret; |
fd9abb3d SG |
1007 | } |
1008 | ||
dffc6b24 JP |
1009 | netdev_info(dev, |
1010 | "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
1011 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
fd9abb3d SG |
1012 | |
1013 | /* mask with MAC supported features */ | |
1014 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
1015 | SUPPORTED_Asym_Pause); | |
1016 | phydev->advertising = phydev->supported; | |
1017 | ||
1018 | pdata->phy_dev = phydev; | |
1019 | pdata->last_duplex = -1; | |
1020 | pdata->last_carrier = -1; | |
1021 | ||
1022 | #ifdef USE_PHY_WORK_AROUND | |
1023 | if (smsc911x_phy_loopbacktest(dev) < 0) { | |
dffc6b24 | 1024 | SMSC_WARN(pdata, hw, "Failed Loop Back Test"); |
fd9abb3d SG |
1025 | return -ENODEV; |
1026 | } | |
dffc6b24 | 1027 | SMSC_TRACE(pdata, hw, "Passed Loop Back Test"); |
fd9abb3d SG |
1028 | #endif /* USE_PHY_WORK_AROUND */ |
1029 | ||
dffc6b24 | 1030 | SMSC_TRACE(pdata, hw, "phy initialised successfully"); |
fd9abb3d SG |
1031 | return 0; |
1032 | } | |
1033 | ||
1034 | static int __devinit smsc911x_mii_init(struct platform_device *pdev, | |
1035 | struct net_device *dev) | |
1036 | { | |
1037 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1038 | int err = -ENXIO, i; | |
1039 | ||
1040 | pdata->mii_bus = mdiobus_alloc(); | |
1041 | if (!pdata->mii_bus) { | |
1042 | err = -ENOMEM; | |
1043 | goto err_out_1; | |
1044 | } | |
1045 | ||
1046 | pdata->mii_bus->name = SMSC_MDIONAME; | |
09ef0789 FF |
1047 | snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1048 | pdev->name, pdev->id); | |
fd9abb3d SG |
1049 | pdata->mii_bus->priv = pdata; |
1050 | pdata->mii_bus->read = smsc911x_mii_read; | |
1051 | pdata->mii_bus->write = smsc911x_mii_write; | |
1052 | pdata->mii_bus->irq = pdata->phy_irq; | |
1053 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1054 | pdata->mii_bus->irq[i] = PHY_POLL; | |
1055 | ||
1056 | pdata->mii_bus->parent = &pdev->dev; | |
fd9abb3d | 1057 | |
fd9abb3d SG |
1058 | switch (pdata->idrev & 0xFFFF0000) { |
1059 | case 0x01170000: | |
1060 | case 0x01150000: | |
1061 | case 0x117A0000: | |
1062 | case 0x115A0000: | |
1063 | /* External PHY supported, try to autodetect */ | |
d23f028a | 1064 | smsc911x_phy_initialise_external(pdata); |
fd9abb3d SG |
1065 | break; |
1066 | default: | |
dffc6b24 JP |
1067 | SMSC_TRACE(pdata, hw, "External PHY is not supported, " |
1068 | "using internal PHY"); | |
d23f028a | 1069 | pdata->using_extphy = 0; |
fd9abb3d SG |
1070 | break; |
1071 | } | |
1072 | ||
1073 | if (!pdata->using_extphy) { | |
1074 | /* Mask all PHYs except ID 1 (internal) */ | |
1075 | pdata->mii_bus->phy_mask = ~(1 << 1); | |
1076 | } | |
1077 | ||
1078 | if (mdiobus_register(pdata->mii_bus)) { | |
dffc6b24 | 1079 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1080 | goto err_out_free_bus_2; |
1081 | } | |
1082 | ||
1083 | if (smsc911x_mii_probe(dev) < 0) { | |
dffc6b24 | 1084 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1085 | goto err_out_unregister_bus_3; |
1086 | } | |
1087 | ||
1088 | return 0; | |
1089 | ||
1090 | err_out_unregister_bus_3: | |
1091 | mdiobus_unregister(pdata->mii_bus); | |
1092 | err_out_free_bus_2: | |
1093 | mdiobus_free(pdata->mii_bus); | |
1094 | err_out_1: | |
1095 | return err; | |
1096 | } | |
1097 | ||
1098 | /* Gets the number of tx statuses in the fifo */ | |
1099 | static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) | |
1100 | { | |
1101 | return (smsc911x_reg_read(pdata, TX_FIFO_INF) | |
1102 | & TX_FIFO_INF_TSUSED_) >> 16; | |
1103 | } | |
1104 | ||
1105 | /* Reads tx statuses and increments counters where necessary */ | |
1106 | static void smsc911x_tx_update_txcounters(struct net_device *dev) | |
1107 | { | |
1108 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1109 | unsigned int tx_stat; | |
1110 | ||
1111 | while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { | |
1112 | if (unlikely(tx_stat & 0x80000000)) { | |
1113 | /* In this driver the packet tag is used as the packet | |
1114 | * length. Since a packet length can never reach the | |
1115 | * size of 0x8000, this bit is reserved. It is worth | |
1116 | * noting that the "reserved bit" in the warning above | |
1117 | * does not reference a hardware defined reserved bit | |
1118 | * but rather a driver defined one. | |
1119 | */ | |
dffc6b24 | 1120 | SMSC_WARN(pdata, hw, "Packet tag reserved bit is high"); |
fd9abb3d | 1121 | } else { |
785b6f97 | 1122 | if (unlikely(tx_stat & TX_STS_ES_)) { |
fd9abb3d SG |
1123 | dev->stats.tx_errors++; |
1124 | } else { | |
1125 | dev->stats.tx_packets++; | |
1126 | dev->stats.tx_bytes += (tx_stat >> 16); | |
1127 | } | |
785b6f97 | 1128 | if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) { |
fd9abb3d SG |
1129 | dev->stats.collisions += 16; |
1130 | dev->stats.tx_aborted_errors += 1; | |
1131 | } else { | |
1132 | dev->stats.collisions += | |
1133 | ((tx_stat >> 3) & 0xF); | |
1134 | } | |
785b6f97 | 1135 | if (unlikely(tx_stat & TX_STS_LOST_CARRIER_)) |
fd9abb3d | 1136 | dev->stats.tx_carrier_errors += 1; |
785b6f97 | 1137 | if (unlikely(tx_stat & TX_STS_LATE_COL_)) { |
fd9abb3d SG |
1138 | dev->stats.collisions++; |
1139 | dev->stats.tx_aborted_errors++; | |
1140 | } | |
1141 | } | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /* Increments the Rx error counters */ | |
1146 | static void | |
1147 | smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat) | |
1148 | { | |
1149 | int crc_err = 0; | |
1150 | ||
785b6f97 | 1151 | if (unlikely(rxstat & RX_STS_ES_)) { |
fd9abb3d | 1152 | dev->stats.rx_errors++; |
785b6f97 | 1153 | if (unlikely(rxstat & RX_STS_CRC_ERR_)) { |
fd9abb3d SG |
1154 | dev->stats.rx_crc_errors++; |
1155 | crc_err = 1; | |
1156 | } | |
1157 | } | |
1158 | if (likely(!crc_err)) { | |
785b6f97 SG |
1159 | if (unlikely((rxstat & RX_STS_FRAME_TYPE_) && |
1160 | (rxstat & RX_STS_LENGTH_ERR_))) | |
fd9abb3d | 1161 | dev->stats.rx_length_errors++; |
fd9abb3d SG |
1162 | if (rxstat & RX_STS_MCAST_) |
1163 | dev->stats.multicast++; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | /* Quickly dumps bad packets */ | |
1168 | static void | |
1169 | smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes) | |
1170 | { | |
1171 | unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2; | |
1172 | ||
1173 | if (likely(pktwords >= 4)) { | |
1174 | unsigned int timeout = 500; | |
1175 | unsigned int val; | |
1176 | smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_); | |
1177 | do { | |
1178 | udelay(1); | |
1179 | val = smsc911x_reg_read(pdata, RX_DP_CTRL); | |
8dacd548 | 1180 | } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); |
fd9abb3d SG |
1181 | |
1182 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1183 | SMSC_WARN(pdata, hw, "Timed out waiting for " |
1184 | "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); | |
fd9abb3d SG |
1185 | } else { |
1186 | unsigned int temp; | |
1187 | while (pktwords--) | |
1188 | temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | /* NAPI poll function */ | |
1193 | static int smsc911x_poll(struct napi_struct *napi, int budget) | |
1194 | { | |
1195 | struct smsc911x_data *pdata = | |
1196 | container_of(napi, struct smsc911x_data, napi); | |
1197 | struct net_device *dev = pdata->dev; | |
1198 | int npackets = 0; | |
1199 | ||
f88c5b98 | 1200 | while (npackets < budget) { |
fd9abb3d SG |
1201 | unsigned int pktlength; |
1202 | unsigned int pktwords; | |
1203 | struct sk_buff *skb; | |
1204 | unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); | |
1205 | ||
1206 | if (!rxstat) { | |
1207 | unsigned int temp; | |
1208 | /* We processed all packets available. Tell NAPI it can | |
1209 | * stop polling then re-enable rx interrupts */ | |
1210 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_); | |
288379f0 | 1211 | napi_complete(napi); |
fd9abb3d SG |
1212 | temp = smsc911x_reg_read(pdata, INT_EN); |
1213 | temp |= INT_EN_RSFL_EN_; | |
1214 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1215 | break; | |
1216 | } | |
1217 | ||
1218 | /* Count packet for NAPI scheduling, even if it has an error. | |
1219 | * Error packets still require cycles to discard */ | |
1220 | npackets++; | |
1221 | ||
1222 | pktlength = ((rxstat & 0x3FFF0000) >> 16); | |
1223 | pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; | |
1224 | smsc911x_rx_counterrors(dev, rxstat); | |
1225 | ||
1226 | if (unlikely(rxstat & RX_STS_ES_)) { | |
dffc6b24 JP |
1227 | SMSC_WARN(pdata, rx_err, |
1228 | "Discarding packet with error bit set"); | |
fd9abb3d SG |
1229 | /* Packet has an error, discard it and continue with |
1230 | * the next */ | |
1231 | smsc911x_rx_fastforward(pdata, pktwords); | |
1232 | dev->stats.rx_dropped++; | |
1233 | continue; | |
1234 | } | |
1235 | ||
1236 | skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN); | |
1237 | if (unlikely(!skb)) { | |
dffc6b24 JP |
1238 | SMSC_WARN(pdata, rx_err, |
1239 | "Unable to allocate skb for rx packet"); | |
fd9abb3d SG |
1240 | /* Drop the packet and stop this polling iteration */ |
1241 | smsc911x_rx_fastforward(pdata, pktwords); | |
1242 | dev->stats.rx_dropped++; | |
1243 | break; | |
1244 | } | |
1245 | ||
1246 | skb->data = skb->head; | |
1247 | skb_reset_tail_pointer(skb); | |
1248 | ||
1249 | /* Align IP on 16B boundary */ | |
1250 | skb_reserve(skb, NET_IP_ALIGN); | |
1251 | skb_put(skb, pktlength - 4); | |
c326de88 MP |
1252 | pdata->ops->rx_readfifo(pdata, |
1253 | (unsigned int *)skb->head, pktwords); | |
fd9abb3d | 1254 | skb->protocol = eth_type_trans(skb, dev); |
bc8acf2c | 1255 | skb_checksum_none_assert(skb); |
fd9abb3d SG |
1256 | netif_receive_skb(skb); |
1257 | ||
1258 | /* Update counters */ | |
1259 | dev->stats.rx_packets++; | |
1260 | dev->stats.rx_bytes += (pktlength - 4); | |
fd9abb3d SG |
1261 | } |
1262 | ||
1263 | /* Return total received packets */ | |
1264 | return npackets; | |
1265 | } | |
1266 | ||
1267 | /* Returns hash bit number for given MAC address | |
1268 | * Example: | |
1269 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
1270 | static unsigned int smsc911x_hash(char addr[ETH_ALEN]) | |
1271 | { | |
1272 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
1273 | } | |
1274 | ||
1275 | static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) | |
1276 | { | |
1277 | /* Performs the multicast & mac_cr update. This is called when | |
1278 | * safe on the current hardware, and with the mac_lock held */ | |
1279 | unsigned int mac_cr; | |
1280 | ||
1281 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1282 | ||
1283 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1284 | mac_cr |= pdata->set_bits_mask; | |
1285 | mac_cr &= ~(pdata->clear_bits_mask); | |
1286 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1287 | smsc911x_mac_write(pdata, HASHH, pdata->hashhi); | |
1288 | smsc911x_mac_write(pdata, HASHL, pdata->hashlo); | |
dffc6b24 JP |
1289 | SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", |
1290 | mac_cr, pdata->hashhi, pdata->hashlo); | |
fd9abb3d SG |
1291 | } |
1292 | ||
1293 | static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) | |
1294 | { | |
1295 | unsigned int mac_cr; | |
1296 | ||
1297 | /* This function is only called for older LAN911x devices | |
1298 | * (revA or revB), where MAC_CR, HASHH and HASHL should not | |
1299 | * be modified during Rx - newer devices immediately update the | |
1300 | * registers. | |
1301 | * | |
1302 | * This is called from interrupt context */ | |
1303 | ||
1304 | spin_lock(&pdata->mac_lock); | |
1305 | ||
1306 | /* Check Rx has stopped */ | |
1307 | if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) | |
dffc6b24 | 1308 | SMSC_WARN(pdata, drv, "Rx not stopped"); |
fd9abb3d SG |
1309 | |
1310 | /* Perform the update - safe to do now Rx has stopped */ | |
1311 | smsc911x_rx_multicast_update(pdata); | |
1312 | ||
1313 | /* Re-enable Rx */ | |
1314 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1315 | mac_cr |= MAC_CR_RXEN_; | |
1316 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1317 | ||
1318 | pdata->multicast_update_pending = 0; | |
1319 | ||
1320 | spin_unlock(&pdata->mac_lock); | |
1321 | } | |
1322 | ||
6386994e JMC |
1323 | static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata) |
1324 | { | |
1325 | int rc = 0; | |
1326 | ||
1327 | if (!pdata->phy_dev) | |
1328 | return rc; | |
1329 | ||
1330 | rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS); | |
1331 | ||
1332 | if (rc < 0) { | |
1333 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1334 | return rc; | |
1335 | } | |
1336 | ||
1337 | /* | |
1338 | * If energy is detected the PHY is already awake so is not necessary | |
1339 | * to disable the energy detect power-down mode. | |
1340 | */ | |
1341 | if ((rc & MII_LAN83C185_EDPWRDOWN) && | |
1342 | !(rc & MII_LAN83C185_ENERGYON)) { | |
1343 | /* Disable energy detect mode for this SMSC Transceivers */ | |
1344 | rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, | |
1345 | rc & (~MII_LAN83C185_EDPWRDOWN)); | |
1346 | ||
1347 | if (rc < 0) { | |
1348 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1349 | return rc; | |
1350 | } | |
1351 | ||
1352 | mdelay(1); | |
1353 | } | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata) | |
1359 | { | |
1360 | int rc = 0; | |
1361 | ||
1362 | if (!pdata->phy_dev) | |
1363 | return rc; | |
1364 | ||
1365 | rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS); | |
1366 | ||
1367 | if (rc < 0) { | |
1368 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1369 | return rc; | |
1370 | } | |
1371 | ||
1372 | /* Only enable if energy detect mode is already disabled */ | |
1373 | if (!(rc & MII_LAN83C185_EDPWRDOWN)) { | |
1374 | mdelay(100); | |
1375 | /* Enable energy detect mode for this SMSC Transceivers */ | |
1376 | rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, | |
1377 | rc | MII_LAN83C185_EDPWRDOWN); | |
1378 | ||
1379 | if (rc < 0) { | |
1380 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1381 | return rc; | |
1382 | } | |
1383 | ||
1384 | mdelay(1); | |
1385 | } | |
1386 | return 0; | |
1387 | } | |
1388 | ||
fd9abb3d SG |
1389 | static int smsc911x_soft_reset(struct smsc911x_data *pdata) |
1390 | { | |
1391 | unsigned int timeout; | |
1392 | unsigned int temp; | |
6386994e JMC |
1393 | int ret; |
1394 | ||
1395 | /* | |
1396 | * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that | |
1397 | * are initialized in a Energy Detect Power-Down mode that prevents | |
1398 | * the MAC chip to be software reseted. So we have to wakeup the PHY | |
1399 | * before. | |
1400 | */ | |
1401 | if (pdata->generation == 4) { | |
1402 | ret = smsc911x_phy_disable_energy_detect(pdata); | |
1403 | ||
1404 | if (ret) { | |
1405 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1406 | return ret; | |
1407 | } | |
1408 | } | |
fd9abb3d SG |
1409 | |
1410 | /* Reset the LAN911x */ | |
1411 | smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); | |
1412 | timeout = 10; | |
1413 | do { | |
1414 | udelay(10); | |
1415 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1416 | } while ((--timeout) && (temp & HW_CFG_SRST_)); | |
1417 | ||
1418 | if (unlikely(temp & HW_CFG_SRST_)) { | |
dffc6b24 | 1419 | SMSC_WARN(pdata, drv, "Failed to complete reset"); |
fd9abb3d SG |
1420 | return -EIO; |
1421 | } | |
6386994e JMC |
1422 | |
1423 | if (pdata->generation == 4) { | |
1424 | ret = smsc911x_phy_enable_energy_detect(pdata); | |
1425 | ||
1426 | if (ret) { | |
1427 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1428 | return ret; | |
1429 | } | |
1430 | } | |
1431 | ||
fd9abb3d SG |
1432 | return 0; |
1433 | } | |
1434 | ||
1435 | /* Sets the device MAC address to dev_addr, called with mac_lock held */ | |
1436 | static void | |
225ddf49 | 1437 | smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) |
fd9abb3d SG |
1438 | { |
1439 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | |
1440 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
1441 | (dev_addr[1] << 8) | dev_addr[0]; | |
1442 | ||
1443 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1444 | ||
1445 | smsc911x_mac_write(pdata, ADDRH, mac_high16); | |
1446 | smsc911x_mac_write(pdata, ADDRL, mac_low32); | |
1447 | } | |
1448 | ||
1449 | static int smsc911x_open(struct net_device *dev) | |
1450 | { | |
1451 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1452 | unsigned int timeout; | |
1453 | unsigned int temp; | |
1454 | unsigned int intcfg; | |
1455 | ||
1456 | /* if the phy is not yet registered, retry later*/ | |
1457 | if (!pdata->phy_dev) { | |
dffc6b24 | 1458 | SMSC_WARN(pdata, hw, "phy_dev is NULL"); |
fd9abb3d SG |
1459 | return -EAGAIN; |
1460 | } | |
1461 | ||
1462 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
dffc6b24 | 1463 | SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address"); |
fd9abb3d SG |
1464 | return -EADDRNOTAVAIL; |
1465 | } | |
1466 | ||
1467 | /* Reset the LAN911x */ | |
1468 | if (smsc911x_soft_reset(pdata)) { | |
dffc6b24 | 1469 | SMSC_WARN(pdata, hw, "soft reset failed"); |
fd9abb3d SG |
1470 | return -EIO; |
1471 | } | |
1472 | ||
1473 | smsc911x_reg_write(pdata, HW_CFG, 0x00050000); | |
1474 | smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740); | |
1475 | ||
f277e65e GW |
1476 | /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */ |
1477 | spin_lock_irq(&pdata->mac_lock); | |
1478 | smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q); | |
1479 | spin_unlock_irq(&pdata->mac_lock); | |
1480 | ||
fd9abb3d SG |
1481 | /* Make sure EEPROM has finished loading before setting GPIO_CFG */ |
1482 | timeout = 50; | |
f7efb6cc SG |
1483 | while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) && |
1484 | --timeout) { | |
fd9abb3d SG |
1485 | udelay(10); |
1486 | } | |
1487 | ||
1488 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1489 | SMSC_WARN(pdata, ifup, |
1490 | "Timed out waiting for EEPROM busy bit to clear"); | |
fd9abb3d SG |
1491 | |
1492 | smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000); | |
1493 | ||
1494 | /* The soft reset above cleared the device's MAC address, | |
1495 | * restore it from local copy (set in probe) */ | |
1496 | spin_lock_irq(&pdata->mac_lock); | |
225ddf49 | 1497 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
fd9abb3d SG |
1498 | spin_unlock_irq(&pdata->mac_lock); |
1499 | ||
1500 | /* Initialise irqs, but leave all sources disabled */ | |
1501 | smsc911x_reg_write(pdata, INT_EN, 0); | |
1502 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
1503 | ||
1504 | /* Set interrupt deassertion to 100uS */ | |
1505 | intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); | |
1506 | ||
2107fb8b | 1507 | if (pdata->config.irq_polarity) { |
dffc6b24 | 1508 | SMSC_TRACE(pdata, ifup, "irq polarity: active high"); |
fd9abb3d SG |
1509 | intcfg |= INT_CFG_IRQ_POL_; |
1510 | } else { | |
dffc6b24 | 1511 | SMSC_TRACE(pdata, ifup, "irq polarity: active low"); |
fd9abb3d SG |
1512 | } |
1513 | ||
2107fb8b | 1514 | if (pdata->config.irq_type) { |
dffc6b24 | 1515 | SMSC_TRACE(pdata, ifup, "irq type: push-pull"); |
fd9abb3d SG |
1516 | intcfg |= INT_CFG_IRQ_TYPE_; |
1517 | } else { | |
dffc6b24 | 1518 | SMSC_TRACE(pdata, ifup, "irq type: open drain"); |
fd9abb3d SG |
1519 | } |
1520 | ||
1521 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
1522 | ||
dffc6b24 | 1523 | SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq); |
fd9abb3d SG |
1524 | pdata->software_irq_signal = 0; |
1525 | smp_wmb(); | |
1526 | ||
1527 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1528 | temp |= INT_EN_SW_INT_EN_; | |
1529 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1530 | ||
1531 | timeout = 1000; | |
1532 | while (timeout--) { | |
1533 | if (pdata->software_irq_signal) | |
1534 | break; | |
1535 | msleep(1); | |
1536 | } | |
1537 | ||
1538 | if (!pdata->software_irq_signal) { | |
dffc6b24 JP |
1539 | netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n", |
1540 | dev->irq); | |
fd9abb3d SG |
1541 | return -ENODEV; |
1542 | } | |
dffc6b24 JP |
1543 | SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d", |
1544 | dev->irq); | |
fd9abb3d | 1545 | |
dffc6b24 JP |
1546 | netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
1547 | (unsigned long)pdata->ioaddr, dev->irq); | |
fd9abb3d | 1548 | |
44c1d6f9 SG |
1549 | /* Reset the last known duplex and carrier */ |
1550 | pdata->last_duplex = -1; | |
1551 | pdata->last_carrier = -1; | |
1552 | ||
fd9abb3d SG |
1553 | /* Bring the PHY up */ |
1554 | phy_start(pdata->phy_dev); | |
1555 | ||
1556 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1557 | /* Preserve TX FIFO size and external PHY configuration */ | |
1558 | temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF); | |
1559 | temp |= HW_CFG_SF_; | |
1560 | smsc911x_reg_write(pdata, HW_CFG, temp); | |
1561 | ||
1562 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1563 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1564 | temp &= ~(FIFO_INT_RX_STS_LEVEL_); | |
1565 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1566 | ||
1567 | /* set RX Data offset to 2 bytes for alignment */ | |
1568 | smsc911x_reg_write(pdata, RX_CFG, (2 << 8)); | |
1569 | ||
1570 | /* enable NAPI polling before enabling RX interrupts */ | |
1571 | napi_enable(&pdata->napi); | |
1572 | ||
1573 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1373c0fd | 1574 | temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_); |
fd9abb3d SG |
1575 | smsc911x_reg_write(pdata, INT_EN, temp); |
1576 | ||
1577 | spin_lock_irq(&pdata->mac_lock); | |
1578 | temp = smsc911x_mac_read(pdata, MAC_CR); | |
1579 | temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); | |
1580 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1581 | spin_unlock_irq(&pdata->mac_lock); | |
1582 | ||
1583 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
1584 | ||
1585 | netif_start_queue(dev); | |
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | /* Entry point for stopping the interface */ | |
1590 | static int smsc911x_stop(struct net_device *dev) | |
1591 | { | |
1592 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1593 | unsigned int temp; | |
1594 | ||
fd9abb3d SG |
1595 | /* Disable all device interrupts */ |
1596 | temp = smsc911x_reg_read(pdata, INT_CFG); | |
1597 | temp &= ~INT_CFG_IRQ_EN_; | |
1598 | smsc911x_reg_write(pdata, INT_CFG, temp); | |
1599 | ||
1600 | /* Stop Tx and Rx polling */ | |
1601 | netif_stop_queue(dev); | |
1602 | napi_disable(&pdata->napi); | |
1603 | ||
1604 | /* At this point all Rx and Tx activity is stopped */ | |
1605 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1606 | smsc911x_tx_update_txcounters(dev); | |
1607 | ||
1608 | /* Bring the PHY down */ | |
dd045193 SG |
1609 | if (pdata->phy_dev) |
1610 | phy_stop(pdata->phy_dev); | |
fd9abb3d | 1611 | |
dffc6b24 | 1612 | SMSC_TRACE(pdata, ifdown, "Interface stopped"); |
fd9abb3d SG |
1613 | return 0; |
1614 | } | |
1615 | ||
1616 | /* Entry point for transmitting a packet */ | |
1617 | static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1618 | { | |
1619 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1620 | unsigned int freespace; | |
1621 | unsigned int tx_cmd_a; | |
1622 | unsigned int tx_cmd_b; | |
1623 | unsigned int temp; | |
1624 | u32 wrsz; | |
1625 | ulong bufp; | |
1626 | ||
1627 | freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; | |
1628 | ||
1629 | if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) | |
dffc6b24 JP |
1630 | SMSC_WARN(pdata, tx_err, |
1631 | "Tx data fifo low, space available: %d", freespace); | |
fd9abb3d SG |
1632 | |
1633 | /* Word alignment adjustment */ | |
1634 | tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16; | |
1635 | tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
1636 | tx_cmd_a |= (unsigned int)skb->len; | |
1637 | ||
1638 | tx_cmd_b = ((unsigned int)skb->len) << 16; | |
1639 | tx_cmd_b |= (unsigned int)skb->len; | |
1640 | ||
1641 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a); | |
1642 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b); | |
1643 | ||
1644 | bufp = (ulong)skb->data & (~0x3); | |
1645 | wrsz = (u32)skb->len + 3; | |
1646 | wrsz += (u32)((ulong)skb->data & 0x3); | |
1647 | wrsz >>= 2; | |
1648 | ||
c326de88 | 1649 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d | 1650 | freespace -= (skb->len + 32); |
8c0069ae | 1651 | skb_tx_timestamp(skb); |
fd9abb3d | 1652 | dev_kfree_skb(skb); |
fd9abb3d SG |
1653 | |
1654 | if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) | |
1655 | smsc911x_tx_update_txcounters(dev); | |
1656 | ||
1657 | if (freespace < TX_FIFO_LOW_THRESHOLD) { | |
1658 | netif_stop_queue(dev); | |
1659 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1660 | temp &= 0x00FFFFFF; | |
1661 | temp |= 0x32000000; | |
1662 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1663 | } | |
1664 | ||
1665 | return NETDEV_TX_OK; | |
1666 | } | |
1667 | ||
1668 | /* Entry point for getting status counters */ | |
1669 | static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) | |
1670 | { | |
1671 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1672 | smsc911x_tx_update_txcounters(dev); | |
1673 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1674 | return &dev->stats; | |
1675 | } | |
1676 | ||
1677 | /* Entry point for setting addressing modes */ | |
1678 | static void smsc911x_set_multicast_list(struct net_device *dev) | |
1679 | { | |
1680 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1681 | unsigned long flags; | |
1682 | ||
1683 | if (dev->flags & IFF_PROMISC) { | |
1684 | /* Enabling promiscuous mode */ | |
1685 | pdata->set_bits_mask = MAC_CR_PRMS_; | |
1686 | pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1687 | pdata->hashhi = 0; | |
1688 | pdata->hashlo = 0; | |
1689 | } else if (dev->flags & IFF_ALLMULTI) { | |
1690 | /* Enabling all multicast mode */ | |
1691 | pdata->set_bits_mask = MAC_CR_MCPAS_; | |
1692 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
1693 | pdata->hashhi = 0; | |
1694 | pdata->hashlo = 0; | |
4cd24eaf | 1695 | } else if (!netdev_mc_empty(dev)) { |
fd9abb3d SG |
1696 | /* Enabling specific multicast addresses */ |
1697 | unsigned int hash_high = 0; | |
1698 | unsigned int hash_low = 0; | |
22bedad3 | 1699 | struct netdev_hw_addr *ha; |
fd9abb3d SG |
1700 | |
1701 | pdata->set_bits_mask = MAC_CR_HPFILT_; | |
1702 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
1703 | ||
22bedad3 JP |
1704 | netdev_for_each_mc_addr(ha, dev) { |
1705 | unsigned int bitnum = smsc911x_hash(ha->addr); | |
2a0d18f9 JP |
1706 | unsigned int mask = 0x01 << (bitnum & 0x1F); |
1707 | ||
1708 | if (bitnum & 0x20) | |
1709 | hash_high |= mask; | |
1710 | else | |
1711 | hash_low |= mask; | |
fd9abb3d | 1712 | } |
fd9abb3d SG |
1713 | |
1714 | pdata->hashhi = hash_high; | |
1715 | pdata->hashlo = hash_low; | |
1716 | } else { | |
1717 | /* Enabling local MAC address only */ | |
1718 | pdata->set_bits_mask = 0; | |
1719 | pdata->clear_bits_mask = | |
1720 | (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1721 | pdata->hashhi = 0; | |
1722 | pdata->hashlo = 0; | |
1723 | } | |
1724 | ||
1725 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1726 | ||
1727 | if (pdata->generation <= 1) { | |
1728 | /* Older hardware revision - cannot change these flags while | |
1729 | * receiving data */ | |
1730 | if (!pdata->multicast_update_pending) { | |
1731 | unsigned int temp; | |
dffc6b24 | 1732 | SMSC_TRACE(pdata, hw, "scheduling mcast update"); |
fd9abb3d SG |
1733 | pdata->multicast_update_pending = 1; |
1734 | ||
1735 | /* Request the hardware to stop, then perform the | |
1736 | * update when we get an RX_STOP interrupt */ | |
fd9abb3d SG |
1737 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1738 | temp &= ~(MAC_CR_RXEN_); | |
1739 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1740 | } else { | |
1741 | /* There is another update pending, this should now | |
1742 | * use the newer values */ | |
1743 | } | |
1744 | } else { | |
1745 | /* Newer hardware revision - can write immediately */ | |
1746 | smsc911x_rx_multicast_update(pdata); | |
1747 | } | |
1748 | ||
1749 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1750 | } | |
1751 | ||
1752 | static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) | |
1753 | { | |
1754 | struct net_device *dev = dev_id; | |
1755 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1756 | u32 intsts = smsc911x_reg_read(pdata, INT_STS); | |
1757 | u32 inten = smsc911x_reg_read(pdata, INT_EN); | |
1758 | int serviced = IRQ_NONE; | |
1759 | u32 temp; | |
1760 | ||
1761 | if (unlikely(intsts & inten & INT_STS_SW_INT_)) { | |
1762 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1763 | temp &= (~INT_EN_SW_INT_EN_); | |
1764 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1765 | smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_); | |
1766 | pdata->software_irq_signal = 1; | |
1767 | smp_wmb(); | |
1768 | serviced = IRQ_HANDLED; | |
1769 | } | |
1770 | ||
1771 | if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { | |
1772 | /* Called when there is a multicast update scheduled and | |
1773 | * it is now safe to complete the update */ | |
dffc6b24 | 1774 | SMSC_TRACE(pdata, intr, "RX Stop interrupt"); |
fd9abb3d | 1775 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_); |
1373c0fd SG |
1776 | if (pdata->multicast_update_pending) |
1777 | smsc911x_rx_multicast_update_workaround(pdata); | |
fd9abb3d SG |
1778 | serviced = IRQ_HANDLED; |
1779 | } | |
1780 | ||
1781 | if (intsts & inten & INT_STS_TDFA_) { | |
1782 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1783 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1784 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1785 | smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_); | |
1786 | netif_wake_queue(dev); | |
1787 | serviced = IRQ_HANDLED; | |
1788 | } | |
1789 | ||
1790 | if (unlikely(intsts & inten & INT_STS_RXE_)) { | |
dffc6b24 | 1791 | SMSC_TRACE(pdata, intr, "RX Error interrupt"); |
fd9abb3d SG |
1792 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_); |
1793 | serviced = IRQ_HANDLED; | |
1794 | } | |
1795 | ||
1796 | if (likely(intsts & inten & INT_STS_RSFL_)) { | |
288379f0 | 1797 | if (likely(napi_schedule_prep(&pdata->napi))) { |
fd9abb3d SG |
1798 | /* Disable Rx interrupts */ |
1799 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1800 | temp &= (~INT_EN_RSFL_EN_); | |
1801 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1802 | /* Schedule a NAPI poll */ | |
288379f0 | 1803 | __napi_schedule(&pdata->napi); |
fd9abb3d | 1804 | } else { |
dffc6b24 | 1805 | SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed"); |
fd9abb3d SG |
1806 | } |
1807 | serviced = IRQ_HANDLED; | |
1808 | } | |
1809 | ||
1810 | return serviced; | |
1811 | } | |
1812 | ||
1813 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1757ab2f | 1814 | static void smsc911x_poll_controller(struct net_device *dev) |
fd9abb3d SG |
1815 | { |
1816 | disable_irq(dev->irq); | |
1817 | smsc911x_irqhandler(0, dev); | |
1818 | enable_irq(dev->irq); | |
1819 | } | |
1820 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1821 | ||
225ddf49 SG |
1822 | static int smsc911x_set_mac_address(struct net_device *dev, void *p) |
1823 | { | |
1824 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1825 | struct sockaddr *addr = p; | |
1826 | ||
1827 | /* On older hardware revisions we cannot change the mac address | |
1828 | * registers while receiving data. Newer devices can safely change | |
1829 | * this at any time. */ | |
1830 | if (pdata->generation <= 1 && netif_running(dev)) | |
1831 | return -EBUSY; | |
1832 | ||
1833 | if (!is_valid_ether_addr(addr->sa_data)) | |
1834 | return -EADDRNOTAVAIL; | |
1835 | ||
1836 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
1837 | ||
1838 | spin_lock_irq(&pdata->mac_lock); | |
1839 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); | |
1840 | spin_unlock_irq(&pdata->mac_lock); | |
1841 | ||
dffc6b24 | 1842 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
225ddf49 SG |
1843 | |
1844 | return 0; | |
1845 | } | |
1846 | ||
fd9abb3d SG |
1847 | /* Standard ioctls for mii-tool */ |
1848 | static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1849 | { | |
1850 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1851 | ||
1852 | if (!netif_running(dev) || !pdata->phy_dev) | |
1853 | return -EINVAL; | |
1854 | ||
28b04113 | 1855 | return phy_mii_ioctl(pdata->phy_dev, ifr, cmd); |
fd9abb3d SG |
1856 | } |
1857 | ||
1858 | static int | |
1859 | smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1860 | { | |
1861 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1862 | ||
1863 | cmd->maxtxpkt = 1; | |
1864 | cmd->maxrxpkt = 1; | |
1865 | return phy_ethtool_gset(pdata->phy_dev, cmd); | |
1866 | } | |
1867 | ||
1868 | static int | |
1869 | smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1870 | { | |
1871 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1872 | ||
1873 | return phy_ethtool_sset(pdata->phy_dev, cmd); | |
1874 | } | |
1875 | ||
1876 | static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, | |
1877 | struct ethtool_drvinfo *info) | |
1878 | { | |
1879 | strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); | |
1880 | strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); | |
db1d7bf7 | 1881 | strlcpy(info->bus_info, dev_name(dev->dev.parent), |
fd9abb3d SG |
1882 | sizeof(info->bus_info)); |
1883 | } | |
1884 | ||
1885 | static int smsc911x_ethtool_nwayreset(struct net_device *dev) | |
1886 | { | |
1887 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1888 | ||
1889 | return phy_start_aneg(pdata->phy_dev); | |
1890 | } | |
1891 | ||
1892 | static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) | |
1893 | { | |
1894 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1895 | return pdata->msg_enable; | |
1896 | } | |
1897 | ||
1898 | static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1899 | { | |
1900 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1901 | pdata->msg_enable = level; | |
1902 | } | |
1903 | ||
1904 | static int smsc911x_ethtool_getregslen(struct net_device *dev) | |
1905 | { | |
1906 | return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * | |
1907 | sizeof(u32); | |
1908 | } | |
1909 | ||
1910 | static void | |
1911 | smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | |
1912 | void *buf) | |
1913 | { | |
1914 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1915 | struct phy_device *phy_dev = pdata->phy_dev; | |
1916 | unsigned long flags; | |
1917 | unsigned int i; | |
1918 | unsigned int j = 0; | |
1919 | u32 *data = buf; | |
1920 | ||
1921 | regs->version = pdata->idrev; | |
1922 | for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32))) | |
1923 | data[j++] = smsc911x_reg_read(pdata, i); | |
1924 | ||
1925 | for (i = MAC_CR; i <= WUCSR; i++) { | |
1926 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1927 | data[j++] = smsc911x_mac_read(pdata, i); | |
1928 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1929 | } | |
1930 | ||
1931 | for (i = 0; i <= 31; i++) | |
1932 | data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i); | |
1933 | } | |
1934 | ||
1935 | static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) | |
1936 | { | |
1937 | unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); | |
1938 | temp &= ~GPIO_CFG_EEPR_EN_; | |
1939 | smsc911x_reg_write(pdata, GPIO_CFG, temp); | |
1940 | msleep(1); | |
1941 | } | |
1942 | ||
1943 | static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) | |
1944 | { | |
1945 | int timeout = 100; | |
1946 | u32 e2cmd; | |
1947 | ||
dffc6b24 | 1948 | SMSC_TRACE(pdata, drv, "op 0x%08x", op); |
fd9abb3d | 1949 | if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { |
dffc6b24 | 1950 | SMSC_WARN(pdata, drv, "Busy at start"); |
fd9abb3d SG |
1951 | return -EBUSY; |
1952 | } | |
1953 | ||
1954 | e2cmd = op | E2P_CMD_EPC_BUSY_; | |
1955 | smsc911x_reg_write(pdata, E2P_CMD, e2cmd); | |
1956 | ||
1957 | do { | |
1958 | msleep(1); | |
1959 | e2cmd = smsc911x_reg_read(pdata, E2P_CMD); | |
2cf0dbed | 1960 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
fd9abb3d SG |
1961 | |
1962 | if (!timeout) { | |
dffc6b24 | 1963 | SMSC_TRACE(pdata, drv, "TIMED OUT"); |
fd9abb3d SG |
1964 | return -EAGAIN; |
1965 | } | |
1966 | ||
1967 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | |
1c01a80c | 1968 | SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation"); |
fd9abb3d SG |
1969 | return -EINVAL; |
1970 | } | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, | |
1976 | u8 address, u8 *data) | |
1977 | { | |
1978 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | |
1979 | int ret; | |
1980 | ||
dffc6b24 | 1981 | SMSC_TRACE(pdata, drv, "address 0x%x", address); |
fd9abb3d SG |
1982 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1983 | ||
1984 | if (!ret) | |
1985 | data[address] = smsc911x_reg_read(pdata, E2P_DATA); | |
1986 | ||
1987 | return ret; | |
1988 | } | |
1989 | ||
1990 | static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, | |
1991 | u8 address, u8 data) | |
1992 | { | |
1993 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | |
58add9fc | 1994 | u32 temp; |
fd9abb3d SG |
1995 | int ret; |
1996 | ||
dffc6b24 | 1997 | SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data); |
fd9abb3d SG |
1998 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1999 | ||
2000 | if (!ret) { | |
2001 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | |
2002 | smsc911x_reg_write(pdata, E2P_DATA, (u32)data); | |
58add9fc SG |
2003 | |
2004 | /* Workaround for hardware read-after-write restriction */ | |
2005 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
2006 | ||
fd9abb3d SG |
2007 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2008 | } | |
2009 | ||
2010 | return ret; | |
2011 | } | |
2012 | ||
2013 | static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) | |
2014 | { | |
2015 | return SMSC911X_EEPROM_SIZE; | |
2016 | } | |
2017 | ||
2018 | static int smsc911x_ethtool_get_eeprom(struct net_device *dev, | |
2019 | struct ethtool_eeprom *eeprom, u8 *data) | |
2020 | { | |
2021 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2022 | u8 eeprom_data[SMSC911X_EEPROM_SIZE]; | |
2023 | int len; | |
2024 | int i; | |
2025 | ||
2026 | smsc911x_eeprom_enable_access(pdata); | |
2027 | ||
2028 | len = min(eeprom->len, SMSC911X_EEPROM_SIZE); | |
2029 | for (i = 0; i < len; i++) { | |
2030 | int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); | |
2031 | if (ret < 0) { | |
2032 | eeprom->len = 0; | |
2033 | return ret; | |
2034 | } | |
2035 | } | |
2036 | ||
2037 | memcpy(data, &eeprom_data[eeprom->offset], len); | |
2038 | eeprom->len = len; | |
2039 | return 0; | |
2040 | } | |
2041 | ||
2042 | static int smsc911x_ethtool_set_eeprom(struct net_device *dev, | |
2043 | struct ethtool_eeprom *eeprom, u8 *data) | |
2044 | { | |
2045 | int ret; | |
2046 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2047 | ||
2048 | smsc911x_eeprom_enable_access(pdata); | |
2049 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); | |
2050 | ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); | |
2051 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); | |
2052 | ||
2053 | /* Single byte write, according to man page */ | |
2054 | eeprom->len = 1; | |
2055 | ||
2056 | return ret; | |
2057 | } | |
2058 | ||
cb5b04fe | 2059 | static const struct ethtool_ops smsc911x_ethtool_ops = { |
fd9abb3d SG |
2060 | .get_settings = smsc911x_ethtool_getsettings, |
2061 | .set_settings = smsc911x_ethtool_setsettings, | |
2062 | .get_link = ethtool_op_get_link, | |
2063 | .get_drvinfo = smsc911x_ethtool_getdrvinfo, | |
2064 | .nway_reset = smsc911x_ethtool_nwayreset, | |
2065 | .get_msglevel = smsc911x_ethtool_getmsglevel, | |
2066 | .set_msglevel = smsc911x_ethtool_setmsglevel, | |
2067 | .get_regs_len = smsc911x_ethtool_getregslen, | |
2068 | .get_regs = smsc911x_ethtool_getregs, | |
2069 | .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, | |
2070 | .get_eeprom = smsc911x_ethtool_get_eeprom, | |
2071 | .set_eeprom = smsc911x_ethtool_set_eeprom, | |
2072 | }; | |
2073 | ||
631b7568 SG |
2074 | static const struct net_device_ops smsc911x_netdev_ops = { |
2075 | .ndo_open = smsc911x_open, | |
2076 | .ndo_stop = smsc911x_stop, | |
2077 | .ndo_start_xmit = smsc911x_hard_start_xmit, | |
2078 | .ndo_get_stats = smsc911x_get_stats, | |
afc4b13d | 2079 | .ndo_set_rx_mode = smsc911x_set_multicast_list, |
631b7568 | 2080 | .ndo_do_ioctl = smsc911x_do_ioctl, |
635ecaa7 | 2081 | .ndo_change_mtu = eth_change_mtu, |
631b7568 | 2082 | .ndo_validate_addr = eth_validate_addr, |
225ddf49 | 2083 | .ndo_set_mac_address = smsc911x_set_mac_address, |
631b7568 SG |
2084 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2085 | .ndo_poll_controller = smsc911x_poll_controller, | |
2086 | #endif | |
2087 | }; | |
2088 | ||
31f45747 SG |
2089 | /* copies the current mac address from hardware to dev->dev_addr */ |
2090 | static void __devinit smsc911x_read_mac_address(struct net_device *dev) | |
2091 | { | |
2092 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2093 | u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); | |
2094 | u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); | |
2095 | ||
2096 | dev->dev_addr[0] = (u8)(mac_low32); | |
2097 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | |
2098 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | |
2099 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | |
2100 | dev->dev_addr[4] = (u8)(mac_high16); | |
2101 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | |
2102 | } | |
2103 | ||
fd9abb3d SG |
2104 | /* Initializing private device structures, only called from probe */ |
2105 | static int __devinit smsc911x_init(struct net_device *dev) | |
2106 | { | |
2107 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2108 | unsigned int byte_test; | |
3ac3546e | 2109 | unsigned int to = 100; |
fd9abb3d | 2110 | |
dffc6b24 JP |
2111 | SMSC_TRACE(pdata, probe, "Driver Parameters:"); |
2112 | SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX", | |
2113 | (unsigned long)pdata->ioaddr); | |
2114 | SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq); | |
2115 | SMSC_TRACE(pdata, probe, "PHY will be autodetected."); | |
fd9abb3d | 2116 | |
fd9abb3d | 2117 | spin_lock_init(&pdata->dev_lock); |
35a67edf | 2118 | spin_lock_init(&pdata->mac_lock); |
fd9abb3d SG |
2119 | |
2120 | if (pdata->ioaddr == 0) { | |
dffc6b24 | 2121 | SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000"); |
fd9abb3d SG |
2122 | return -ENODEV; |
2123 | } | |
2124 | ||
3ac3546e RM |
2125 | /* |
2126 | * poll the READY bit in PMT_CTRL. Any other access to the device is | |
2127 | * forbidden while this bit isn't set. Try for 100ms | |
2128 | */ | |
2129 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) | |
2130 | udelay(1000); | |
2131 | if (to == 0) { | |
2132 | pr_err("Device not READY in 100ms aborting\n"); | |
2133 | return -ENODEV; | |
2134 | } | |
2135 | ||
fd9abb3d SG |
2136 | /* Check byte ordering */ |
2137 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
dffc6b24 | 2138 | SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2139 | if (byte_test == 0x43218765) { |
dffc6b24 JP |
2140 | SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, " |
2141 | "applying WORD_SWAP"); | |
fd9abb3d SG |
2142 | smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff); |
2143 | ||
2144 | /* 1 dummy read of BYTE_TEST is needed after a write to | |
2145 | * WORD_SWAP before its contents are valid */ | |
2146 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2147 | ||
2148 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2149 | } | |
2150 | ||
2151 | if (byte_test != 0x87654321) { | |
dffc6b24 | 2152 | SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2153 | if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) { |
dffc6b24 JP |
2154 | SMSC_WARN(pdata, probe, |
2155 | "top 16 bits equal to bottom 16 bits"); | |
2156 | SMSC_TRACE(pdata, probe, | |
2157 | "This may mean the chip is set " | |
2158 | "for 32 bit while the bus is reading 16 bit"); | |
fd9abb3d SG |
2159 | } |
2160 | return -ENODEV; | |
2161 | } | |
2162 | ||
2163 | /* Default generation to zero (all workarounds apply) */ | |
2164 | pdata->generation = 0; | |
2165 | ||
2166 | pdata->idrev = smsc911x_reg_read(pdata, ID_REV); | |
2167 | switch (pdata->idrev & 0xFFFF0000) { | |
2168 | case 0x01180000: | |
2169 | case 0x01170000: | |
2170 | case 0x01160000: | |
2171 | case 0x01150000: | |
28c21379 | 2172 | case 0x218A0000: |
fd9abb3d SG |
2173 | /* LAN911[5678] family */ |
2174 | pdata->generation = pdata->idrev & 0x0000FFFF; | |
2175 | break; | |
2176 | ||
2177 | case 0x118A0000: | |
2178 | case 0x117A0000: | |
2179 | case 0x116A0000: | |
2180 | case 0x115A0000: | |
2181 | /* LAN921[5678] family */ | |
2182 | pdata->generation = 3; | |
2183 | break; | |
2184 | ||
2185 | case 0x92100000: | |
2186 | case 0x92110000: | |
2187 | case 0x92200000: | |
2188 | case 0x92210000: | |
2189 | /* LAN9210/LAN9211/LAN9220/LAN9221 */ | |
2190 | pdata->generation = 4; | |
2191 | break; | |
2192 | ||
2193 | default: | |
dffc6b24 JP |
2194 | SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X", |
2195 | pdata->idrev); | |
fd9abb3d SG |
2196 | return -ENODEV; |
2197 | } | |
2198 | ||
dffc6b24 JP |
2199 | SMSC_TRACE(pdata, probe, |
2200 | "LAN911x identified, idrev: 0x%08X, generation: %d", | |
2201 | pdata->idrev, pdata->generation); | |
fd9abb3d SG |
2202 | |
2203 | if (pdata->generation == 0) | |
dffc6b24 JP |
2204 | SMSC_WARN(pdata, probe, |
2205 | "This driver is not intended for this chip revision"); | |
fd9abb3d | 2206 | |
31f45747 SG |
2207 | /* workaround for platforms without an eeprom, where the mac address |
2208 | * is stored elsewhere and set by the bootloader. This saves the | |
2209 | * mac address before resetting the device */ | |
35a67edf EBS |
2210 | if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) { |
2211 | spin_lock_irq(&pdata->mac_lock); | |
31f45747 | 2212 | smsc911x_read_mac_address(dev); |
35a67edf EBS |
2213 | spin_unlock_irq(&pdata->mac_lock); |
2214 | } | |
31f45747 | 2215 | |
fd9abb3d SG |
2216 | /* Reset the LAN911x */ |
2217 | if (smsc911x_soft_reset(pdata)) | |
2218 | return -ENODEV; | |
2219 | ||
2220 | /* Disable all interrupt sources until we bring the device up */ | |
2221 | smsc911x_reg_write(pdata, INT_EN, 0); | |
2222 | ||
2223 | ether_setup(dev); | |
fd9abb3d | 2224 | dev->flags |= IFF_MULTICAST; |
fd9abb3d | 2225 | netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT); |
631b7568 | 2226 | dev->netdev_ops = &smsc911x_netdev_ops; |
fd9abb3d SG |
2227 | dev->ethtool_ops = &smsc911x_ethtool_ops; |
2228 | ||
fd9abb3d SG |
2229 | return 0; |
2230 | } | |
2231 | ||
2232 | static int __devexit smsc911x_drv_remove(struct platform_device *pdev) | |
2233 | { | |
2234 | struct net_device *dev; | |
2235 | struct smsc911x_data *pdata; | |
2236 | struct resource *res; | |
2237 | ||
2238 | dev = platform_get_drvdata(pdev); | |
2239 | BUG_ON(!dev); | |
2240 | pdata = netdev_priv(dev); | |
2241 | BUG_ON(!pdata); | |
2242 | BUG_ON(!pdata->ioaddr); | |
2243 | BUG_ON(!pdata->phy_dev); | |
2244 | ||
dffc6b24 | 2245 | SMSC_TRACE(pdata, ifdown, "Stopping driver"); |
fd9abb3d SG |
2246 | |
2247 | phy_disconnect(pdata->phy_dev); | |
2248 | pdata->phy_dev = NULL; | |
2249 | mdiobus_unregister(pdata->mii_bus); | |
2250 | mdiobus_free(pdata->mii_bus); | |
2251 | ||
2252 | platform_set_drvdata(pdev, NULL); | |
2253 | unregister_netdev(dev); | |
2254 | free_irq(dev->irq, dev); | |
2255 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
2256 | "smsc911x-memory"); | |
2257 | if (!res) | |
d4522739 | 2258 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
fd9abb3d | 2259 | |
39424539 | 2260 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2261 | |
2262 | iounmap(pdata->ioaddr); | |
2263 | ||
c7e963f6 RM |
2264 | (void)smsc911x_disable_resources(pdev); |
2265 | smsc911x_free_resources(pdev); | |
2266 | ||
fd9abb3d SG |
2267 | free_netdev(dev); |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
c326de88 MP |
2272 | /* standard register acces */ |
2273 | static const struct smsc911x_ops standard_smsc911x_ops = { | |
2274 | .reg_read = __smsc911x_reg_read, | |
2275 | .reg_write = __smsc911x_reg_write, | |
2276 | .rx_readfifo = smsc911x_rx_readfifo, | |
2277 | .tx_writefifo = smsc911x_tx_writefifo, | |
2278 | }; | |
2279 | ||
2280 | /* shifted register access */ | |
2281 | static const struct smsc911x_ops shifted_smsc911x_ops = { | |
2282 | .reg_read = __smsc911x_reg_read_shift, | |
2283 | .reg_write = __smsc911x_reg_write_shift, | |
2284 | .rx_readfifo = smsc911x_rx_readfifo_shift, | |
2285 | .tx_writefifo = smsc911x_tx_writefifo_shift, | |
2286 | }; | |
2287 | ||
79f88ee9 SG |
2288 | #ifdef CONFIG_OF |
2289 | static int __devinit smsc911x_probe_config_dt( | |
2290 | struct smsc911x_platform_config *config, | |
2291 | struct device_node *np) | |
2292 | { | |
2293 | const char *mac; | |
2294 | u32 width = 0; | |
2295 | ||
2296 | if (!np) | |
2297 | return -ENODEV; | |
2298 | ||
2299 | config->phy_interface = of_get_phy_mode(np); | |
2300 | ||
2301 | mac = of_get_mac_address(np); | |
2302 | if (mac) | |
2303 | memcpy(config->mac, mac, ETH_ALEN); | |
2304 | ||
2305 | of_property_read_u32(np, "reg-shift", &config->shift); | |
2306 | ||
2307 | of_property_read_u32(np, "reg-io-width", &width); | |
2308 | if (width == 4) | |
2309 | config->flags |= SMSC911X_USE_32BIT; | |
f26cd41a DM |
2310 | else |
2311 | config->flags |= SMSC911X_USE_16BIT; | |
79f88ee9 SG |
2312 | |
2313 | if (of_get_property(np, "smsc,irq-active-high", NULL)) | |
2314 | config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH; | |
2315 | ||
2316 | if (of_get_property(np, "smsc,irq-push-pull", NULL)) | |
2317 | config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL; | |
2318 | ||
2319 | if (of_get_property(np, "smsc,force-internal-phy", NULL)) | |
2320 | config->flags |= SMSC911X_FORCE_INTERNAL_PHY; | |
2321 | ||
2322 | if (of_get_property(np, "smsc,force-external-phy", NULL)) | |
2323 | config->flags |= SMSC911X_FORCE_EXTERNAL_PHY; | |
2324 | ||
2325 | if (of_get_property(np, "smsc,save-mac-address", NULL)) | |
2326 | config->flags |= SMSC911X_SAVE_MAC_ADDRESS; | |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | #else | |
2331 | static inline int smsc911x_probe_config_dt( | |
2332 | struct smsc911x_platform_config *config, | |
2333 | struct device_node *np) | |
2334 | { | |
2335 | return -ENODEV; | |
2336 | } | |
2337 | #endif /* CONFIG_OF */ | |
2338 | ||
fd9abb3d SG |
2339 | static int __devinit smsc911x_drv_probe(struct platform_device *pdev) |
2340 | { | |
79f88ee9 | 2341 | struct device_node *np = pdev->dev.of_node; |
fd9abb3d SG |
2342 | struct net_device *dev; |
2343 | struct smsc911x_data *pdata; | |
2107fb8b | 2344 | struct smsc911x_platform_config *config = pdev->dev.platform_data; |
61307ed8 | 2345 | struct resource *res, *irq_res; |
fd9abb3d | 2346 | unsigned int intcfg = 0; |
61307ed8 | 2347 | int res_size, irq_flags; |
fd9abb3d | 2348 | int retval; |
fd9abb3d | 2349 | |
dffc6b24 | 2350 | pr_info("Driver version %s\n", SMSC_DRV_VERSION); |
fd9abb3d SG |
2351 | |
2352 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
2353 | "smsc911x-memory"); | |
2354 | if (!res) | |
2355 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2356 | if (!res) { | |
dffc6b24 | 2357 | pr_warn("Could not allocate resource\n"); |
fd9abb3d SG |
2358 | retval = -ENODEV; |
2359 | goto out_0; | |
2360 | } | |
39424539 | 2361 | res_size = resource_size(res); |
fd9abb3d | 2362 | |
61307ed8 SG |
2363 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2364 | if (!irq_res) { | |
dffc6b24 | 2365 | pr_warn("Could not allocate irq resource\n"); |
61307ed8 SG |
2366 | retval = -ENODEV; |
2367 | goto out_0; | |
2368 | } | |
2369 | ||
fd9abb3d SG |
2370 | if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { |
2371 | retval = -EBUSY; | |
2372 | goto out_0; | |
2373 | } | |
2374 | ||
2375 | dev = alloc_etherdev(sizeof(struct smsc911x_data)); | |
2376 | if (!dev) { | |
fd9abb3d SG |
2377 | retval = -ENOMEM; |
2378 | goto out_release_io_1; | |
2379 | } | |
2380 | ||
2381 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2382 | ||
2383 | pdata = netdev_priv(dev); | |
2384 | ||
61307ed8 SG |
2385 | dev->irq = irq_res->start; |
2386 | irq_flags = irq_res->flags & IRQF_TRIGGER_MASK; | |
fd9abb3d SG |
2387 | pdata->ioaddr = ioremap_nocache(res->start, res_size); |
2388 | ||
fd9abb3d SG |
2389 | pdata->dev = dev; |
2390 | pdata->msg_enable = ((1 << debug) - 1); | |
2391 | ||
c7e963f6 RM |
2392 | platform_set_drvdata(pdev, dev); |
2393 | ||
2394 | retval = smsc911x_request_resources(pdev); | |
2395 | if (retval) | |
2396 | goto out_return_resources; | |
2397 | ||
2398 | retval = smsc911x_enable_resources(pdev); | |
2399 | if (retval) | |
2400 | goto out_disable_resources; | |
2401 | ||
fd9abb3d | 2402 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2403 | SMSC_WARN(pdata, probe, "Error smsc911x base address invalid"); |
fd9abb3d | 2404 | retval = -ENOMEM; |
c7e963f6 | 2405 | goto out_disable_resources; |
fd9abb3d SG |
2406 | } |
2407 | ||
79f88ee9 SG |
2408 | retval = smsc911x_probe_config_dt(&pdata->config, np); |
2409 | if (retval && config) { | |
2410 | /* copy config parameters across to pdata */ | |
2411 | memcpy(&pdata->config, config, sizeof(pdata->config)); | |
2412 | retval = 0; | |
2413 | } | |
2414 | ||
2415 | if (retval) { | |
2416 | SMSC_WARN(pdata, probe, "Error smsc911x config not found"); | |
c7e963f6 | 2417 | goto out_disable_resources; |
79f88ee9 SG |
2418 | } |
2419 | ||
c326de88 MP |
2420 | /* assume standard, non-shifted, access to HW registers */ |
2421 | pdata->ops = &standard_smsc911x_ops; | |
2422 | /* apply the right access if shifting is needed */ | |
79f88ee9 | 2423 | if (pdata->config.shift) |
c326de88 MP |
2424 | pdata->ops = &shifted_smsc911x_ops; |
2425 | ||
fd9abb3d SG |
2426 | retval = smsc911x_init(dev); |
2427 | if (retval < 0) | |
c7e963f6 | 2428 | goto out_disable_resources; |
fd9abb3d SG |
2429 | |
2430 | /* configure irq polarity and type before connecting isr */ | |
2107fb8b | 2431 | if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH) |
fd9abb3d SG |
2432 | intcfg |= INT_CFG_IRQ_POL_; |
2433 | ||
2107fb8b | 2434 | if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL) |
fd9abb3d SG |
2435 | intcfg |= INT_CFG_IRQ_TYPE_; |
2436 | ||
2437 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
2438 | ||
2439 | /* Ensure interrupts are globally disabled before connecting ISR */ | |
2440 | smsc911x_reg_write(pdata, INT_EN, 0); | |
2441 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
2442 | ||
61307ed8 | 2443 | retval = request_irq(dev->irq, smsc911x_irqhandler, |
e81259b4 | 2444 | irq_flags | IRQF_SHARED, dev->name, dev); |
fd9abb3d | 2445 | if (retval) { |
dffc6b24 JP |
2446 | SMSC_WARN(pdata, probe, |
2447 | "Unable to claim requested irq: %d", dev->irq); | |
c7e963f6 | 2448 | goto out_free_irq; |
fd9abb3d SG |
2449 | } |
2450 | ||
fd9abb3d SG |
2451 | retval = register_netdev(dev); |
2452 | if (retval) { | |
dffc6b24 | 2453 | SMSC_WARN(pdata, probe, "Error %i registering device", retval); |
c7e963f6 | 2454 | goto out_free_irq; |
fd9abb3d | 2455 | } else { |
dffc6b24 JP |
2456 | SMSC_TRACE(pdata, probe, |
2457 | "Network interface: \"%s\"", dev->name); | |
fd9abb3d SG |
2458 | } |
2459 | ||
fd9abb3d SG |
2460 | retval = smsc911x_mii_init(pdev, dev); |
2461 | if (retval) { | |
dffc6b24 | 2462 | SMSC_WARN(pdata, probe, "Error %i initialising mii", retval); |
fd9abb3d SG |
2463 | goto out_unregister_netdev_5; |
2464 | } | |
2465 | ||
2466 | spin_lock_irq(&pdata->mac_lock); | |
2467 | ||
2468 | /* Check if mac address has been specified when bringing interface up */ | |
2469 | if (is_valid_ether_addr(dev->dev_addr)) { | |
225ddf49 | 2470 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2471 | SMSC_TRACE(pdata, probe, |
2472 | "MAC Address is specified by configuration"); | |
aace4959 ML |
2473 | } else if (is_valid_ether_addr(pdata->config.mac)) { |
2474 | memcpy(dev->dev_addr, pdata->config.mac, 6); | |
dffc6b24 JP |
2475 | SMSC_TRACE(pdata, probe, |
2476 | "MAC Address specified by platform data"); | |
fd9abb3d SG |
2477 | } else { |
2478 | /* Try reading mac address from device. if EEPROM is present | |
2479 | * it will already have been set */ | |
62747cd2 | 2480 | smsc_get_mac(dev); |
fd9abb3d SG |
2481 | |
2482 | if (is_valid_ether_addr(dev->dev_addr)) { | |
2483 | /* eeprom values are valid so use them */ | |
dffc6b24 JP |
2484 | SMSC_TRACE(pdata, probe, |
2485 | "Mac Address is read from LAN911x EEPROM"); | |
fd9abb3d SG |
2486 | } else { |
2487 | /* eeprom values are invalid, generate random MAC */ | |
2488 | random_ether_addr(dev->dev_addr); | |
225ddf49 | 2489 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2490 | SMSC_TRACE(pdata, probe, |
2491 | "MAC Address is set to random_ether_addr"); | |
fd9abb3d SG |
2492 | } |
2493 | } | |
2494 | ||
2495 | spin_unlock_irq(&pdata->mac_lock); | |
2496 | ||
dffc6b24 | 2497 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
fd9abb3d SG |
2498 | |
2499 | return 0; | |
2500 | ||
2501 | out_unregister_netdev_5: | |
2502 | unregister_netdev(dev); | |
c7e963f6 | 2503 | out_free_irq: |
fd9abb3d | 2504 | free_irq(dev->irq, dev); |
c7e963f6 RM |
2505 | out_disable_resources: |
2506 | (void)smsc911x_disable_resources(pdev); | |
2507 | out_return_resources: | |
2508 | smsc911x_free_resources(pdev); | |
2509 | platform_set_drvdata(pdev, NULL); | |
fd9abb3d | 2510 | iounmap(pdata->ioaddr); |
fd9abb3d SG |
2511 | free_netdev(dev); |
2512 | out_release_io_1: | |
39424539 | 2513 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2514 | out_0: |
2515 | return retval; | |
2516 | } | |
2517 | ||
b6907b0c DM |
2518 | #ifdef CONFIG_PM |
2519 | /* This implementation assumes the devices remains powered on its VDDVARIO | |
2520 | * pins during suspend. */ | |
2521 | ||
6cb87823 DM |
2522 | /* TODO: implement freeze/thaw callbacks for hibernation.*/ |
2523 | ||
2524 | static int smsc911x_suspend(struct device *dev) | |
b6907b0c | 2525 | { |
6cb87823 DM |
2526 | struct net_device *ndev = dev_get_drvdata(dev); |
2527 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2528 | |
2529 | /* enable wake on LAN, energy detection and the external PME | |
2530 | * signal. */ | |
2531 | smsc911x_reg_write(pdata, PMT_CTRL, | |
2532 | PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ | | |
2533 | PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_); | |
2534 | ||
2535 | return 0; | |
2536 | } | |
2537 | ||
6cb87823 | 2538 | static int smsc911x_resume(struct device *dev) |
b6907b0c | 2539 | { |
6cb87823 DM |
2540 | struct net_device *ndev = dev_get_drvdata(dev); |
2541 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2542 | unsigned int to = 100; |
2543 | ||
2544 | /* Note 3.11 from the datasheet: | |
2545 | * "When the LAN9220 is in a power saving state, a write of any | |
2546 | * data to the BYTE_TEST register will wake-up the device." | |
2547 | */ | |
2548 | smsc911x_reg_write(pdata, BYTE_TEST, 0); | |
2549 | ||
2550 | /* poll the READY bit in PMT_CTRL. Any other access to the device is | |
2551 | * forbidden while this bit isn't set. Try for 100ms and return -EIO | |
2552 | * if it failed. */ | |
2553 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) | |
2554 | udelay(1000); | |
2555 | ||
2556 | return (to == 0) ? -EIO : 0; | |
2557 | } | |
2558 | ||
47145210 | 2559 | static const struct dev_pm_ops smsc911x_pm_ops = { |
6cb87823 DM |
2560 | .suspend = smsc911x_suspend, |
2561 | .resume = smsc911x_resume, | |
2562 | }; | |
2563 | ||
2564 | #define SMSC911X_PM_OPS (&smsc911x_pm_ops) | |
2565 | ||
b6907b0c | 2566 | #else |
6cb87823 | 2567 | #define SMSC911X_PM_OPS NULL |
b6907b0c DM |
2568 | #endif |
2569 | ||
79f88ee9 SG |
2570 | static const struct of_device_id smsc911x_dt_ids[] = { |
2571 | { .compatible = "smsc,lan9115", }, | |
2572 | { /* sentinel */ } | |
2573 | }; | |
2574 | MODULE_DEVICE_TABLE(of, smsc911x_dt_ids); | |
2575 | ||
fd9abb3d SG |
2576 | static struct platform_driver smsc911x_driver = { |
2577 | .probe = smsc911x_drv_probe, | |
df911e2d | 2578 | .remove = __devexit_p(smsc911x_drv_remove), |
fd9abb3d | 2579 | .driver = { |
6cb87823 DM |
2580 | .name = SMSC_CHIPNAME, |
2581 | .owner = THIS_MODULE, | |
2582 | .pm = SMSC911X_PM_OPS, | |
79f88ee9 | 2583 | .of_match_table = smsc911x_dt_ids, |
fd9abb3d SG |
2584 | }, |
2585 | }; | |
2586 | ||
2587 | /* Entry point for loading the module */ | |
2588 | static int __init smsc911x_init_module(void) | |
2589 | { | |
62747cd2 | 2590 | SMSC_INITIALIZE(); |
fd9abb3d SG |
2591 | return platform_driver_register(&smsc911x_driver); |
2592 | } | |
2593 | ||
2594 | /* entry point for unloading the module */ | |
2595 | static void __exit smsc911x_cleanup_module(void) | |
2596 | { | |
2597 | platform_driver_unregister(&smsc911x_driver); | |
2598 | } | |
2599 | ||
2600 | module_init(smsc911x_init_module); | |
2601 | module_exit(smsc911x_cleanup_module); |