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net: phy: smsc: Move SMSC PHY constants to <linux/smscphy.h>
[deliverable/linux.git] / drivers / net / ethernet / smsc / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
28c21379 29 * LAN89218
fd9abb3d
SG		 30 *
31 */
32
dffc6b24
JP		 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
fd9abb3d
SG		 35#include <linux/crc32.h>
36#include <linux/delay.h>
37#include <linux/errno.h>
38#include <linux/etherdevice.h>
39#include <linux/ethtool.h>
40#include <linux/init.h>
a6b7a407 41#include <linux/interrupt.h>
fd9abb3d
SG		 42#include <linux/ioport.h>
43#include <linux/kernel.h>
44#include <linux/module.h>
45#include <linux/netdevice.h>
46#include <linux/platform_device.h>
c7e963f6 47#include <linux/regulator/consumer.h>
fd9abb3d 48#include <linux/sched.h>
fd9abb3d 49#include <linux/timer.h>
fd9abb3d
SG		 50#include <linux/bug.h>
51#include <linux/bitops.h>
52#include <linux/irq.h>
53#include <linux/io.h>
833cc67c 54#include <linux/swab.h>
fd9abb3d
SG		 55#include <linux/phy.h>
56#include <linux/smsc911x.h>
6cb87823 57#include <linux/device.h>
79f88ee9
SG		 58#include <linux/of.h>
59#include <linux/of_device.h>
60#include <linux/of_gpio.h>
61#include <linux/of_net.h>
fd9abb3d
SG		 62#include "smsc911x.h"
63
64#define SMSC_CHIPNAME "smsc911x"
65#define SMSC_MDIONAME "smsc911x-mdio"
66#define SMSC_DRV_VERSION "2008-10-21"
67
68MODULE_LICENSE("GPL");
69MODULE_VERSION(SMSC_DRV_VERSION);
62038e4a 70MODULE_ALIAS("platform:smsc911x");
fd9abb3d
SG		 71
72#if USE_DEBUG > 0
73static int debug = 16;
74#else
75static int debug = 3;
76#endif
77
78module_param(debug, int, 0);
79MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
80
c326de88
MP		 81struct smsc911x_data;
82
83struct smsc911x_ops {
84 u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
85 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
86 void (*rx_readfifo)(struct smsc911x_data *pdata,
87 unsigned int *buf, unsigned int wordcount);
88 void (*tx_writefifo)(struct smsc911x_data *pdata,
89 unsigned int *buf, unsigned int wordcount);
90};
91
c7e963f6
RM		 92#define SMSC911X_NUM_SUPPLIES 2
93
fd9abb3d
SG		 94struct smsc911x_data {
95 void __iomem *ioaddr;
96
97 unsigned int idrev;
98
99 /* used to decide which workarounds apply */
100 unsigned int generation;
101
102 /* device configuration (copied from platform_data during probe) */
2107fb8b 103 struct smsc911x_platform_config config;
fd9abb3d
SG		 104
105 /* This needs to be acquired before calling any of below:
106 * smsc911x_mac_read(), smsc911x_mac_write()
107 */
108 spinlock_t mac_lock;
109
492c5d94 110 /* spinlock to ensure register accesses are serialised */
fd9abb3d 111 spinlock_t dev_lock;
fd9abb3d
SG		 112
113 struct phy_device *phy_dev;
114 struct mii_bus *mii_bus;
115 int phy_irq[PHY_MAX_ADDR];
116 unsigned int using_extphy;
117 int last_duplex;
118 int last_carrier;
119
120 u32 msg_enable;
121 unsigned int gpio_setting;
122 unsigned int gpio_orig_setting;
123 struct net_device *dev;
124 struct napi_struct napi;
125
126 unsigned int software_irq_signal;
127
128#ifdef USE_PHY_WORK_AROUND
129#define MIN_PACKET_SIZE (64)
130 char loopback_tx_pkt[MIN_PACKET_SIZE];
131 char loopback_rx_pkt[MIN_PACKET_SIZE];
132 unsigned int resetcount;
133#endif
134
135 /* Members for Multicast filter workaround */
136 unsigned int multicast_update_pending;
137 unsigned int set_bits_mask;
138 unsigned int clear_bits_mask;
139 unsigned int hashhi;
140 unsigned int hashlo;
c326de88
MP		 141
142 /* register access functions */
143 const struct smsc911x_ops *ops;
c7e963f6
RM		 144
145 /* regulators */
146 struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
fd9abb3d
SG		 147};
148
c326de88
MP		 149/* Easy access to information */
150#define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
151
492c5d94 152static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 153{
2107fb8b
SG		 154 if (pdata->config.flags & SMSC911X_USE_32BIT)
155 return readl(pdata->ioaddr + reg);
156
492c5d94
CM		 157 if (pdata->config.flags & SMSC911X_USE_16BIT)
158 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 159 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 160
2107fb8b 161 BUG();
702403af 162 return 0;
fd9abb3d
SG		 163}
164
c326de88
MP		 165static inline u32
166__smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
167{
168 if (pdata->config.flags & SMSC911X_USE_32BIT)
169 return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
170
171 if (pdata->config.flags & SMSC911X_USE_16BIT)
172 return (readw(pdata->ioaddr +
173 __smsc_shift(pdata, reg)) & 0xFFFF) |
174 ((readw(pdata->ioaddr +
175 __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
176
177 BUG();
178 return 0;
179}
180
492c5d94
CM		 181static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
182{
183 u32 data;
184 unsigned long flags;
185
186 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 187 data = pdata->ops->reg_read(pdata, reg);
492c5d94
CM		 188 spin_unlock_irqrestore(&pdata->dev_lock, flags);
189
190 return data;
191}
192
193static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
194 u32 val)
fd9abb3d 195{
2107fb8b
SG		 196 if (pdata->config.flags & SMSC911X_USE_32BIT) {
197 writel(val, pdata->ioaddr + reg);
198 return;
199 }
200
201 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 202 writew(val & 0xFFFF, pdata->ioaddr + reg);
203 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 204 return;
205 }
fd9abb3d 206
2107fb8b 207 BUG();
fd9abb3d
SG		 208}
209
c326de88
MP		 210static inline void
211__smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
212{
213 if (pdata->config.flags & SMSC911X_USE_32BIT) {
214 writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
215 return;
216 }
217
218 if (pdata->config.flags & SMSC911X_USE_16BIT) {
219 writew(val & 0xFFFF,
220 pdata->ioaddr + __smsc_shift(pdata, reg));
221 writew((val >> 16) & 0xFFFF,
222 pdata->ioaddr + __smsc_shift(pdata, reg + 2));
223 return;
224 }
225
226 BUG();
227}
228
492c5d94
CM		 229static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
230 u32 val)
231{
232 unsigned long flags;
233
234 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 235 pdata->ops->reg_write(pdata, reg, val);
492c5d94
CM		 236 spin_unlock_irqrestore(&pdata->dev_lock, flags);
237}
238
fd9abb3d
SG		 239/* Writes a packet to the TX_DATA_FIFO */
240static inline void
241smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
242 unsigned int wordcount)
243{
492c5d94
CM		 244 unsigned long flags;
245
246 spin_lock_irqsave(&pdata->dev_lock, flags);
247
833cc67c
MD		 248 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
249 while (wordcount--)
492c5d94
CM		 250 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
251 swab32(*buf++));
252 goto out;
833cc67c
MD		 253 }
254
2107fb8b
SG		 255 if (pdata->config.flags & SMSC911X_USE_32BIT) {
256 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 257 goto out;
2107fb8b
SG		 258 }
259
260 if (pdata->config.flags & SMSC911X_USE_16BIT) {
261 while (wordcount--)
492c5d94
CM		 262 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
263 goto out;
2107fb8b
SG		 264 }
265
266 BUG();
492c5d94
CM		 267out:
268 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 269}
270
c326de88
MP		 271/* Writes a packet to the TX_DATA_FIFO - shifted version */
272static inline void
273smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
274 unsigned int wordcount)
275{
276 unsigned long flags;
277
278 spin_lock_irqsave(&pdata->dev_lock, flags);
279
280 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
281 while (wordcount--)
282 __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
283 swab32(*buf++));
284 goto out;
285 }
286
287 if (pdata->config.flags & SMSC911X_USE_32BIT) {
288 writesl(pdata->ioaddr + __smsc_shift(pdata,
289 TX_DATA_FIFO), buf, wordcount);
290 goto out;
291 }
292
293 if (pdata->config.flags & SMSC911X_USE_16BIT) {
294 while (wordcount--)
295 __smsc911x_reg_write_shift(pdata,
296 TX_DATA_FIFO, *buf++);
297 goto out;
298 }
299
300 BUG();
301out:
302 spin_unlock_irqrestore(&pdata->dev_lock, flags);
303}
304
fd9abb3d
SG		 305/* Reads a packet out of the RX_DATA_FIFO */
306static inline void
307smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
308 unsigned int wordcount)
309{
492c5d94
CM		 310 unsigned long flags;
311
312 spin_lock_irqsave(&pdata->dev_lock, flags);
313
833cc67c
MD		 314 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
315 while (wordcount--)
492c5d94
CM		 316 *buf++ = swab32(__smsc911x_reg_read(pdata,
317 RX_DATA_FIFO));
318 goto out;
833cc67c
MD		 319 }
320
2107fb8b
SG		 321 if (pdata->config.flags & SMSC911X_USE_32BIT) {
322 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 323 goto out;
2107fb8b 324 }
fd9abb3d 325
2107fb8b
SG		 326 if (pdata->config.flags & SMSC911X_USE_16BIT) {
327 while (wordcount--)
492c5d94
CM		 328 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
329 goto out;
2107fb8b
SG		 330 }
331
332 BUG();
492c5d94
CM		 333out:
334 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 335}
fd9abb3d 336
c326de88
MP		 337/* Reads a packet out of the RX_DATA_FIFO - shifted version */
338static inline void
339smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
340 unsigned int wordcount)
341{
342 unsigned long flags;
343
344 spin_lock_irqsave(&pdata->dev_lock, flags);
345
346 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
347 while (wordcount--)
348 *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
349 RX_DATA_FIFO));
350 goto out;
351 }
352
353 if (pdata->config.flags & SMSC911X_USE_32BIT) {
354 readsl(pdata->ioaddr + __smsc_shift(pdata,
355 RX_DATA_FIFO), buf, wordcount);
356 goto out;
357 }
358
359 if (pdata->config.flags & SMSC911X_USE_16BIT) {
360 while (wordcount--)
361 *buf++ = __smsc911x_reg_read_shift(pdata,
362 RX_DATA_FIFO);
363 goto out;
364 }
365
366 BUG();
367out:
368 spin_unlock_irqrestore(&pdata->dev_lock, flags);
369}
370
c7e963f6
RM		 371/*
372 * enable resources, currently just regulators.
373 */
374static int smsc911x_enable_resources(struct platform_device *pdev)
375{
376 struct net_device *ndev = platform_get_drvdata(pdev);
377 struct smsc911x_data *pdata = netdev_priv(ndev);
378 int ret = 0;
379
380 ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
381 pdata->supplies);
382 if (ret)
383 netdev_err(ndev, "failed to enable regulators %d\n",
384 ret);
385 return ret;
386}
387
388/*
389 * disable resources, currently just regulators.
390 */
391static int smsc911x_disable_resources(struct platform_device *pdev)
392{
393 struct net_device *ndev = platform_get_drvdata(pdev);
394 struct smsc911x_data *pdata = netdev_priv(ndev);
395 int ret = 0;
396
397 ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
398 pdata->supplies);
399 return ret;
400}
401
402/*
403 * Request resources, currently just regulators.
404 *
405 * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
406 * these are not always-on we need to request regulators to be turned on
407 * before we can try to access the device registers.
408 */
409static int smsc911x_request_resources(struct platform_device *pdev)
410{
411 struct net_device *ndev = platform_get_drvdata(pdev);
412 struct smsc911x_data *pdata = netdev_priv(ndev);
413 int ret = 0;
414
415 /* Request regulators */
416 pdata->supplies[0].supply = "vdd33a";
417 pdata->supplies[1].supply = "vddvario";
418 ret = regulator_bulk_get(&pdev->dev,
419 ARRAY_SIZE(pdata->supplies),
420 pdata->supplies);
421 if (ret)
422 netdev_err(ndev, "couldn't get regulators %d\n",
423 ret);
424 return ret;
425}
426
427/*
428 * Free resources, currently just regulators.
429 *
430 */
431static void smsc911x_free_resources(struct platform_device *pdev)
432{
433 struct net_device *ndev = platform_get_drvdata(pdev);
434 struct smsc911x_data *pdata = netdev_priv(ndev);
435
436 /* Free regulators */
437 regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
438 pdata->supplies);
439}
440
fd9abb3d
SG		 441/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
442 * and smsc911x_mac_write, so assumes mac_lock is held */
443static int smsc911x_mac_complete(struct smsc911x_data *pdata)
444{
445 int i;
446 u32 val;
447
448 SMSC_ASSERT_MAC_LOCK(pdata);
449
450 for (i = 0; i < 40; i++) {
451 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
452 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
453 return 0;
454 }
dffc6b24
JP		 455 SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
456 "MAC_CSR_CMD: 0x%08X", val);
fd9abb3d
SG		 457 return -EIO;
458}
459
460/* Fetches a MAC register value. Assumes mac_lock is acquired */
461static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
462{
463 unsigned int temp;
464
465 SMSC_ASSERT_MAC_LOCK(pdata);
466
467 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
468 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24 469 SMSC_WARN(pdata, hw, "MAC busy at entry");
fd9abb3d
SG		 470 return 0xFFFFFFFF;
471 }
472
473 /* Send the MAC cmd */
474 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
475 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
476
477 /* Workaround for hardware read-after-write restriction */
478 temp = smsc911x_reg_read(pdata, BYTE_TEST);
479
480 /* Wait for the read to complete */
481 if (likely(smsc911x_mac_complete(pdata) == 0))
482 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
483
dffc6b24 484 SMSC_WARN(pdata, hw, "MAC busy after read");
fd9abb3d
SG		 485 return 0xFFFFFFFF;
486}
487
488/* Set a mac register, mac_lock must be acquired before calling */
489static void smsc911x_mac_write(struct smsc911x_data *pdata,
490 unsigned int offset, u32 val)
491{
492 unsigned int temp;
493
494 SMSC_ASSERT_MAC_LOCK(pdata);
495
496 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
497 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24
JP		 498 SMSC_WARN(pdata, hw,
499 "smsc911x_mac_write failed, MAC busy at entry");
fd9abb3d
SG		 500 return;
501 }
502
503 /* Send data to write */
504 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
505
506 /* Write the actual data */
507 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
508 MAC_CSR_CMD_CSR_BUSY_));
509
510 /* Workaround for hardware read-after-write restriction */
511 temp = smsc911x_reg_read(pdata, BYTE_TEST);
512
513 /* Wait for the write to complete */
514 if (likely(smsc911x_mac_complete(pdata) == 0))
515 return;
516
dffc6b24 517 SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
fd9abb3d
SG		 518}
519
520/* Get a phy register */
521static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
522{
523 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
524 unsigned long flags;
525 unsigned int addr;
526 int i, reg;
527
528 spin_lock_irqsave(&pdata->mac_lock, flags);
529
530 /* Confirm MII not busy */
531 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 532 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
fd9abb3d
SG		 533 reg = -EIO;
534 goto out;
535 }
536
537 /* Set the address, index & direction (read from PHY) */
538 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
539 smsc911x_mac_write(pdata, MII_ACC, addr);
540
541 /* Wait for read to complete w/ timeout */
542 for (i = 0; i < 100; i++)
543 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
544 reg = smsc911x_mac_read(pdata, MII_DATA);
545 goto out;
546 }
547
dffc6b24 548 SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 549 reg = -EIO;
550
551out:
552 spin_unlock_irqrestore(&pdata->mac_lock, flags);
553 return reg;
554}
555
556/* Set a phy register */
557static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
558 u16 val)
559{
560 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
561 unsigned long flags;
562 unsigned int addr;
563 int i, reg;
564
565 spin_lock_irqsave(&pdata->mac_lock, flags);
566
567 /* Confirm MII not busy */
568 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 569 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
fd9abb3d
SG		 570 reg = -EIO;
571 goto out;
572 }
573
574 /* Put the data to write in the MAC */
575 smsc911x_mac_write(pdata, MII_DATA, val);
576
577 /* Set the address, index & direction (write to PHY) */
578 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
579 MII_ACC_MII_WRITE_;
580 smsc911x_mac_write(pdata, MII_ACC, addr);
581
582 /* Wait for write to complete w/ timeout */
583 for (i = 0; i < 100; i++)
584 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
585 reg = 0;
586 goto out;
587 }
588
dffc6b24 589 SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
fd9abb3d
SG		 590 reg = -EIO;
591
592out:
593 spin_unlock_irqrestore(&pdata->mac_lock, flags);
594 return reg;
595}
596
d23f028a
SG		 597/* Switch to external phy. Assumes tx and rx are stopped. */
598static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 599{
600 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
601
d23f028a
SG		 602 /* Disable phy clocks to the MAC */
603 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
604 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
605 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
606 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 607
d23f028a
SG		 608 /* Switch to external phy */
609 hwcfg |= HW_CFG_EXT_PHY_EN_;
610 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 611
d23f028a
SG		 612 /* Enable phy clocks to the MAC */
613 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
614 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
615 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
616 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 617
d23f028a
SG		 618 hwcfg |= HW_CFG_SMI_SEL_;
619 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
620}
fd9abb3d 621
d23f028a
SG		 622/* Autodetects and enables external phy if present on supported chips.
623 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
624 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
625static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
626{
627 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 628
d23f028a 629 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
dffc6b24 630 SMSC_TRACE(pdata, hw, "Forcing internal PHY");
d23f028a
SG		 631 pdata->using_extphy = 0;
632 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
dffc6b24 633 SMSC_TRACE(pdata, hw, "Forcing external PHY");
d23f028a
SG		 634 smsc911x_phy_enable_external(pdata);
635 pdata->using_extphy = 1;
636 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
dffc6b24
JP		 637 SMSC_TRACE(pdata, hw,
638 "HW_CFG EXT_PHY_DET set, using external PHY");
d23f028a 639 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 640 pdata->using_extphy = 1;
641 } else {
dffc6b24
JP		 642 SMSC_TRACE(pdata, hw,
643 "HW_CFG EXT_PHY_DET clear, using internal PHY");
d23f028a 644 pdata->using_extphy = 0;
fd9abb3d 645 }
fd9abb3d
SG		 646}
647
648/* Fetches a tx status out of the status fifo */
649static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
650{
651 unsigned int result =
652 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
653
654 if (result != 0)
655 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
656
657 return result;
658}
659
660/* Fetches the next rx status */
661static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
662{
663 unsigned int result =
664 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
665
666 if (result != 0)
667 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
668
669 return result;
670}
671
672#ifdef USE_PHY_WORK_AROUND
673static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
674{
675 unsigned int tries;
676 u32 wrsz;
677 u32 rdsz;
678 ulong bufp;
679
680 for (tries = 0; tries < 10; tries++) {
681 unsigned int txcmd_a;
682 unsigned int txcmd_b;
683 unsigned int status;
684 unsigned int pktlength;
685 unsigned int i;
686
687 /* Zero-out rx packet memory */
688 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
689
690 /* Write tx packet to 118 */
691 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
692 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
693 txcmd_a |= MIN_PACKET_SIZE;
694
695 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
696
697 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
698 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
699
700 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
701 wrsz = MIN_PACKET_SIZE + 3;
702 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
703 wrsz >>= 2;
704
c326de88 705 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d
SG		 706
707 /* Wait till transmit is done */
708 i = 60;
709 do {
710 udelay(5);
711 status = smsc911x_tx_get_txstatus(pdata);
712 } while ((i--) && (!status));
713
714 if (!status) {
dffc6b24
JP		 715 SMSC_WARN(pdata, hw,
716 "Failed to transmit during loopback test");
fd9abb3d
SG		 717 continue;
718 }
719 if (status & TX_STS_ES_) {
dffc6b24
JP		 720 SMSC_WARN(pdata, hw,
721 "Transmit encountered errors during loopback test");
fd9abb3d
SG		 722 continue;
723 }
724
725 /* Wait till receive is done */
726 i = 60;
727 do {
728 udelay(5);
729 status = smsc911x_rx_get_rxstatus(pdata);
730 } while ((i--) && (!status));
731
732 if (!status) {
dffc6b24
JP		 733 SMSC_WARN(pdata, hw,
734 "Failed to receive during loopback test");
fd9abb3d
SG		 735 continue;
736 }
737 if (status & RX_STS_ES_) {
dffc6b24
JP		 738 SMSC_WARN(pdata, hw,
739 "Receive encountered errors during loopback test");
fd9abb3d
SG		 740 continue;
741 }
742
743 pktlength = ((status & 0x3FFF0000UL) >> 16);
744 bufp = (ulong)pdata->loopback_rx_pkt;
745 rdsz = pktlength + 3;
746 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
747 rdsz >>= 2;
748
c326de88 749 pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
fd9abb3d
SG		 750
751 if (pktlength != (MIN_PACKET_SIZE + 4)) {
dffc6b24
JP		 752 SMSC_WARN(pdata, hw, "Unexpected packet size "
753 "during loop back test, size=%d, will retry",
754 pktlength);
fd9abb3d
SG		 755 } else {
756 unsigned int j;
757 int mismatch = 0;
758 for (j = 0; j < MIN_PACKET_SIZE; j++) {
759 if (pdata->loopback_tx_pkt[j]
760 != pdata->loopback_rx_pkt[j]) {
761 mismatch = 1;
762 break;
763 }
764 }
765 if (!mismatch) {
dffc6b24 766 SMSC_TRACE(pdata, hw, "Successfully verified "
fd9abb3d
SG		 767 "loopback packet");
768 return 0;
769 } else {
dffc6b24
JP		 770 SMSC_WARN(pdata, hw, "Data mismatch "
771 "during loop back test, will retry");
fd9abb3d
SG		 772 }
773 }
774 }
775
776 return -EIO;
777}
778
779static int smsc911x_phy_reset(struct smsc911x_data *pdata)
780{
781 struct phy_device *phy_dev = pdata->phy_dev;
782 unsigned int temp;
783 unsigned int i = 100000;
784
785 BUG_ON(!phy_dev);
786 BUG_ON(!phy_dev->bus);
787
dffc6b24 788 SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
fd9abb3d
SG		 789 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
790 do {
791 msleep(1);
792 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
793 MII_BMCR);
794 } while ((i--) && (temp & BMCR_RESET));
795
796 if (temp & BMCR_RESET) {
dffc6b24 797 SMSC_WARN(pdata, hw, "PHY reset failed to complete");
fd9abb3d
SG		 798 return -EIO;
799 }
800 /* Extra delay required because the phy may not be completed with
801 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
802 * enough delay but using 1ms here to be safe */
803 msleep(1);
804
805 return 0;
806}
807
808static int smsc911x_phy_loopbacktest(struct net_device *dev)
809{
810 struct smsc911x_data *pdata = netdev_priv(dev);
811 struct phy_device *phy_dev = pdata->phy_dev;
812 int result = -EIO;
813 unsigned int i, val;
814 unsigned long flags;
815
816 /* Initialise tx packet using broadcast destination address */
817 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
818
819 /* Use incrementing source address */
820 for (i = 6; i < 12; i++)
821 pdata->loopback_tx_pkt[i] = (char)i;
822
823 /* Set length type field */
824 pdata->loopback_tx_pkt[12] = 0x00;
825 pdata->loopback_tx_pkt[13] = 0x00;
826
827 for (i = 14; i < MIN_PACKET_SIZE; i++)
828 pdata->loopback_tx_pkt[i] = (char)i;
829
830 val = smsc911x_reg_read(pdata, HW_CFG);
831 val &= HW_CFG_TX_FIF_SZ_;
832 val |= HW_CFG_SF_;
833 smsc911x_reg_write(pdata, HW_CFG, val);
834
835 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
836 smsc911x_reg_write(pdata, RX_CFG,
837 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
838
839 for (i = 0; i < 10; i++) {
840 /* Set PHY to 10/FD, no ANEG, and loopback mode */
841 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
842 BMCR_LOOPBACK | BMCR_FULLDPLX);
843
844 /* Enable MAC tx/rx, FD */
845 spin_lock_irqsave(&pdata->mac_lock, flags);
846 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
847 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
848 spin_unlock_irqrestore(&pdata->mac_lock, flags);
849
850 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
851 result = 0;
852 break;
853 }
854 pdata->resetcount++;
855
856 /* Disable MAC rx */
857 spin_lock_irqsave(&pdata->mac_lock, flags);
858 smsc911x_mac_write(pdata, MAC_CR, 0);
859 spin_unlock_irqrestore(&pdata->mac_lock, flags);
860
861 smsc911x_phy_reset(pdata);
862 }
863
864 /* Disable MAC */
865 spin_lock_irqsave(&pdata->mac_lock, flags);
866 smsc911x_mac_write(pdata, MAC_CR, 0);
867 spin_unlock_irqrestore(&pdata->mac_lock, flags);
868
869 /* Cancel PHY loopback mode */
870 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
871
872 smsc911x_reg_write(pdata, TX_CFG, 0);
873 smsc911x_reg_write(pdata, RX_CFG, 0);
874
875 return result;
876}
877#endif /* USE_PHY_WORK_AROUND */
878
fd9abb3d
SG		 879static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
880{
881 struct phy_device *phy_dev = pdata->phy_dev;
882 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
883 u32 flow;
884 unsigned long flags;
885
886 if (phy_dev->duplex == DUPLEX_FULL) {
887 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
888 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 889 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 890
891 if (cap & FLOW_CTRL_RX)
892 flow = 0xFFFF0002;
893 else
894 flow = 0;
895
896 if (cap & FLOW_CTRL_TX)
897 afc |= 0xF;
898 else
899 afc &= ~0xF;
900
dffc6b24
JP		 901 SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
902 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
903 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
fd9abb3d 904 } else {
dffc6b24 905 SMSC_TRACE(pdata, hw, "half duplex");
fd9abb3d
SG		 906 flow = 0;
907 afc |= 0xF;
908 }
909
910 spin_lock_irqsave(&pdata->mac_lock, flags);
911 smsc911x_mac_write(pdata, FLOW, flow);
912 spin_unlock_irqrestore(&pdata->mac_lock, flags);
913
914 smsc911x_reg_write(pdata, AFC_CFG, afc);
915}
916
917/* Update link mode if anything has changed. Called periodically when the
918 * PHY is in polling mode, even if nothing has changed. */
919static void smsc911x_phy_adjust_link(struct net_device *dev)
920{
921 struct smsc911x_data *pdata = netdev_priv(dev);
922 struct phy_device *phy_dev = pdata->phy_dev;
923 unsigned long flags;
924 int carrier;
925
926 if (phy_dev->duplex != pdata->last_duplex) {
927 unsigned int mac_cr;
dffc6b24 928 SMSC_TRACE(pdata, hw, "duplex state has changed");
fd9abb3d
SG		 929
930 spin_lock_irqsave(&pdata->mac_lock, flags);
931 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
932 if (phy_dev->duplex) {
dffc6b24
JP		 933 SMSC_TRACE(pdata, hw,
934 "configuring for full duplex mode");
fd9abb3d
SG		 935 mac_cr |= MAC_CR_FDPX_;
936 } else {
dffc6b24
JP		 937 SMSC_TRACE(pdata, hw,
938 "configuring for half duplex mode");
fd9abb3d
SG		 939 mac_cr &= ~MAC_CR_FDPX_;
940 }
941 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
942 spin_unlock_irqrestore(&pdata->mac_lock, flags);
943
944 smsc911x_phy_update_flowcontrol(pdata);
945 pdata->last_duplex = phy_dev->duplex;
946 }
947
948 carrier = netif_carrier_ok(dev);
949 if (carrier != pdata->last_carrier) {
dffc6b24 950 SMSC_TRACE(pdata, hw, "carrier state has changed");
fd9abb3d 951 if (carrier) {
dffc6b24 952 SMSC_TRACE(pdata, hw, "configuring for carrier OK");
fd9abb3d
SG		 953 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
954 (!pdata->using_extphy)) {
88393161 955 /* Restore original GPIO configuration */
fd9abb3d
SG		 956 pdata->gpio_setting = pdata->gpio_orig_setting;
957 smsc911x_reg_write(pdata, GPIO_CFG,
958 pdata->gpio_setting);
959 }
960 } else {
dffc6b24 961 SMSC_TRACE(pdata, hw, "configuring for no carrier");
fd9abb3d
SG		 962 /* Check global setting that LED1
963 * usage is 10/100 indicator */
964 pdata->gpio_setting = smsc911x_reg_read(pdata,
965 GPIO_CFG);
8e95a202
JP		 966 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
967 (!pdata->using_extphy)) {
fd9abb3d 968 /* Force 10/100 LED off, after saving
88393161 969 * original GPIO configuration */
fd9abb3d
SG		 970 pdata->gpio_orig_setting = pdata->gpio_setting;
971
972 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
973 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
974 | GPIO_CFG_GPIODIR0_
975 | GPIO_CFG_GPIOD0_);
976 smsc911x_reg_write(pdata, GPIO_CFG,
977 pdata->gpio_setting);
978 }
979 }
980 pdata->last_carrier = carrier;
981 }
982}
983
984static int smsc911x_mii_probe(struct net_device *dev)
985{
986 struct smsc911x_data *pdata = netdev_priv(dev);
987 struct phy_device *phydev = NULL;
e4a474f8 988 int ret;
fd9abb3d
SG		 989
990 /* find the first phy */
e4a474f8 991 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d 992 if (!phydev) {
dffc6b24 993 netdev_err(dev, "no PHY found\n");
fd9abb3d
SG		 994 return -ENODEV;
995 }
996
dffc6b24
JP		 997 SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
998 phydev->addr, phydev->phy_id);
e4a474f8 999
1000 ret = phy_connect_direct(dev, phydev,
1001 &smsc911x_phy_adjust_link, 0,
1002 pdata->config.phy_interface);
fd9abb3d 1003
e4a474f8 1004 if (ret) {
dffc6b24 1005 netdev_err(dev, "Could not attach to PHY\n");
e4a474f8 1006 return ret;
fd9abb3d
SG		 1007 }
1008
dffc6b24
JP		 1009 netdev_info(dev,
1010 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1011 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 1012
1013 /* mask with MAC supported features */
1014 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1015 SUPPORTED_Asym_Pause);
1016 phydev->advertising = phydev->supported;
1017
1018 pdata->phy_dev = phydev;
1019 pdata->last_duplex = -1;
1020 pdata->last_carrier = -1;
1021
1022#ifdef USE_PHY_WORK_AROUND
1023 if (smsc911x_phy_loopbacktest(dev) < 0) {
dffc6b24 1024 SMSC_WARN(pdata, hw, "Failed Loop Back Test");
fd9abb3d
SG		 1025 return -ENODEV;
1026 }
dffc6b24 1027 SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
fd9abb3d
SG		 1028#endif /* USE_PHY_WORK_AROUND */
1029
dffc6b24 1030 SMSC_TRACE(pdata, hw, "phy initialised successfully");
fd9abb3d
SG		 1031 return 0;
1032}
1033
1034static int __devinit smsc911x_mii_init(struct platform_device *pdev,
1035 struct net_device *dev)
1036{
1037 struct smsc911x_data *pdata = netdev_priv(dev);
1038 int err = -ENXIO, i;
1039
1040 pdata->mii_bus = mdiobus_alloc();
1041 if (!pdata->mii_bus) {
1042 err = -ENOMEM;
1043 goto err_out_1;
1044 }
1045
1046 pdata->mii_bus->name = SMSC_MDIONAME;
1047 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
1048 pdata->mii_bus->priv = pdata;
1049 pdata->mii_bus->read = smsc911x_mii_read;
1050 pdata->mii_bus->write = smsc911x_mii_write;
1051 pdata->mii_bus->irq = pdata->phy_irq;
1052 for (i = 0; i < PHY_MAX_ADDR; ++i)
1053 pdata->mii_bus->irq[i] = PHY_POLL;
1054
1055 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 1056
fd9abb3d
SG		 1057 switch (pdata->idrev & 0xFFFF0000) {
1058 case 0x01170000:
1059 case 0x01150000:
1060 case 0x117A0000:
1061 case 0x115A0000:
1062 /* External PHY supported, try to autodetect */
d23f028a 1063 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 1064 break;
1065 default:
dffc6b24
JP		 1066 SMSC_TRACE(pdata, hw, "External PHY is not supported, "
1067 "using internal PHY");
d23f028a 1068 pdata->using_extphy = 0;
fd9abb3d
SG		 1069 break;
1070 }
1071
1072 if (!pdata->using_extphy) {
1073 /* Mask all PHYs except ID 1 (internal) */
1074 pdata->mii_bus->phy_mask = ~(1 << 1);
1075 }
1076
1077 if (mdiobus_register(pdata->mii_bus)) {
dffc6b24 1078 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1079 goto err_out_free_bus_2;
1080 }
1081
1082 if (smsc911x_mii_probe(dev) < 0) {
dffc6b24 1083 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1084 goto err_out_unregister_bus_3;
1085 }
1086
1087 return 0;
1088
1089err_out_unregister_bus_3:
1090 mdiobus_unregister(pdata->mii_bus);
1091err_out_free_bus_2:
1092 mdiobus_free(pdata->mii_bus);
1093err_out_1:
1094 return err;
1095}
1096
1097/* Gets the number of tx statuses in the fifo */
1098static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
1099{
1100 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
1101 & TX_FIFO_INF_TSUSED_) >> 16;
1102}
1103
1104/* Reads tx statuses and increments counters where necessary */
1105static void smsc911x_tx_update_txcounters(struct net_device *dev)
1106{
1107 struct smsc911x_data *pdata = netdev_priv(dev);
1108 unsigned int tx_stat;
1109
1110 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
1111 if (unlikely(tx_stat & 0x80000000)) {
1112 /* In this driver the packet tag is used as the packet
1113 * length. Since a packet length can never reach the
1114 * size of 0x8000, this bit is reserved. It is worth
1115 * noting that the "reserved bit" in the warning above
1116 * does not reference a hardware defined reserved bit
1117 * but rather a driver defined one.
1118 */
dffc6b24 1119 SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
fd9abb3d 1120 } else {
785b6f97 1121 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 1122 dev->stats.tx_errors++;
1123 } else {
1124 dev->stats.tx_packets++;
1125 dev->stats.tx_bytes += (tx_stat >> 16);
1126 }
785b6f97 1127 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 1128 dev->stats.collisions += 16;
1129 dev->stats.tx_aborted_errors += 1;
1130 } else {
1131 dev->stats.collisions +=
1132 ((tx_stat >> 3) & 0xF);
1133 }
785b6f97 1134 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 1135 dev->stats.tx_carrier_errors += 1;
785b6f97 1136 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 1137 dev->stats.collisions++;
1138 dev->stats.tx_aborted_errors++;
1139 }
1140 }
1141 }
1142}
1143
1144/* Increments the Rx error counters */
1145static void
1146smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
1147{
1148 int crc_err = 0;
1149
785b6f97 1150 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 1151 dev->stats.rx_errors++;
785b6f97 1152 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 1153 dev->stats.rx_crc_errors++;
1154 crc_err = 1;
1155 }
1156 }
1157 if (likely(!crc_err)) {
785b6f97
SG		 1158 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
1159 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 1160 dev->stats.rx_length_errors++;
fd9abb3d
SG		 1161 if (rxstat & RX_STS_MCAST_)
1162 dev->stats.multicast++;
1163 }
1164}
1165
1166/* Quickly dumps bad packets */
1167static void
1168smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
1169{
1170 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
1171
1172 if (likely(pktwords >= 4)) {
1173 unsigned int timeout = 500;
1174 unsigned int val;
1175 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
1176 do {
1177 udelay(1);
1178 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 1179 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 1180
1181 if (unlikely(timeout == 0))
dffc6b24
JP		 1182 SMSC_WARN(pdata, hw, "Timed out waiting for "
1183 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
fd9abb3d
SG		 1184 } else {
1185 unsigned int temp;
1186 while (pktwords--)
1187 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
1188 }
1189}
1190
1191/* NAPI poll function */
1192static int smsc911x_poll(struct napi_struct *napi, int budget)
1193{
1194 struct smsc911x_data *pdata =
1195 container_of(napi, struct smsc911x_data, napi);
1196 struct net_device *dev = pdata->dev;
1197 int npackets = 0;
1198
f88c5b98 1199 while (npackets < budget) {
fd9abb3d
SG		 1200 unsigned int pktlength;
1201 unsigned int pktwords;
1202 struct sk_buff *skb;
1203 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1204
1205 if (!rxstat) {
1206 unsigned int temp;
1207 /* We processed all packets available. Tell NAPI it can
1208 * stop polling then re-enable rx interrupts */
1209 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1210 napi_complete(napi);
fd9abb3d
SG		 1211 temp = smsc911x_reg_read(pdata, INT_EN);
1212 temp |= INT_EN_RSFL_EN_;
1213 smsc911x_reg_write(pdata, INT_EN, temp);
1214 break;
1215 }
1216
1217 /* Count packet for NAPI scheduling, even if it has an error.
1218 * Error packets still require cycles to discard */
1219 npackets++;
1220
1221 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1222 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1223 smsc911x_rx_counterrors(dev, rxstat);
1224
1225 if (unlikely(rxstat & RX_STS_ES_)) {
dffc6b24
JP		 1226 SMSC_WARN(pdata, rx_err,
1227 "Discarding packet with error bit set");
fd9abb3d
SG		 1228 /* Packet has an error, discard it and continue with
1229 * the next */
1230 smsc911x_rx_fastforward(pdata, pktwords);
1231 dev->stats.rx_dropped++;
1232 continue;
1233 }
1234
1235 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1236 if (unlikely(!skb)) {
dffc6b24
JP		 1237 SMSC_WARN(pdata, rx_err,
1238 "Unable to allocate skb for rx packet");
fd9abb3d
SG		 1239 /* Drop the packet and stop this polling iteration */
1240 smsc911x_rx_fastforward(pdata, pktwords);
1241 dev->stats.rx_dropped++;
1242 break;
1243 }
1244
1245 skb->data = skb->head;
1246 skb_reset_tail_pointer(skb);
1247
1248 /* Align IP on 16B boundary */
1249 skb_reserve(skb, NET_IP_ALIGN);
1250 skb_put(skb, pktlength - 4);
c326de88
MP		 1251 pdata->ops->rx_readfifo(pdata,
1252 (unsigned int *)skb->head, pktwords);
fd9abb3d 1253 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1254 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1255 netif_receive_skb(skb);
1256
1257 /* Update counters */
1258 dev->stats.rx_packets++;
1259 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1260 }
1261
1262 /* Return total received packets */
1263 return npackets;
1264}
1265
1266/* Returns hash bit number for given MAC address
1267 * Example:
1268 * 01 00 5E 00 00 01 -> returns bit number 31 */
1269static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1270{
1271 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1272}
1273
1274static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1275{
1276 /* Performs the multicast & mac_cr update. This is called when
1277 * safe on the current hardware, and with the mac_lock held */
1278 unsigned int mac_cr;
1279
1280 SMSC_ASSERT_MAC_LOCK(pdata);
1281
1282 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1283 mac_cr |= pdata->set_bits_mask;
1284 mac_cr &= ~(pdata->clear_bits_mask);
1285 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1286 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1287 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
dffc6b24
JP		 1288 SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1289 mac_cr, pdata->hashhi, pdata->hashlo);
fd9abb3d
SG		 1290}
1291
1292static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1293{
1294 unsigned int mac_cr;
1295
1296 /* This function is only called for older LAN911x devices
1297 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1298 * be modified during Rx - newer devices immediately update the
1299 * registers.
1300 *
1301 * This is called from interrupt context */
1302
1303 spin_lock(&pdata->mac_lock);
1304
1305 /* Check Rx has stopped */
1306 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
dffc6b24 1307 SMSC_WARN(pdata, drv, "Rx not stopped");
fd9abb3d
SG		 1308
1309 /* Perform the update - safe to do now Rx has stopped */
1310 smsc911x_rx_multicast_update(pdata);
1311
1312 /* Re-enable Rx */
1313 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1314 mac_cr |= MAC_CR_RXEN_;
1315 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1316
1317 pdata->multicast_update_pending = 0;
1318
1319 spin_unlock(&pdata->mac_lock);
1320}
1321
1322static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1323{
1324 unsigned int timeout;
1325 unsigned int temp;
1326
1327 /* Reset the LAN911x */
1328 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1329 timeout = 10;
1330 do {
1331 udelay(10);
1332 temp = smsc911x_reg_read(pdata, HW_CFG);
1333 } while ((--timeout) && (temp & HW_CFG_SRST_));
1334
1335 if (unlikely(temp & HW_CFG_SRST_)) {
dffc6b24 1336 SMSC_WARN(pdata, drv, "Failed to complete reset");
fd9abb3d
SG		 1337 return -EIO;
1338 }
1339 return 0;
1340}
1341
1342/* Sets the device MAC address to dev_addr, called with mac_lock held */
1343static void
225ddf49 1344smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1345{
1346 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1347 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1348 (dev_addr[1] << 8) | dev_addr[0];
1349
1350 SMSC_ASSERT_MAC_LOCK(pdata);
1351
1352 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1353 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1354}
1355
1356static int smsc911x_open(struct net_device *dev)
1357{
1358 struct smsc911x_data *pdata = netdev_priv(dev);
1359 unsigned int timeout;
1360 unsigned int temp;
1361 unsigned int intcfg;
1362
1363 /* if the phy is not yet registered, retry later*/
1364 if (!pdata->phy_dev) {
dffc6b24 1365 SMSC_WARN(pdata, hw, "phy_dev is NULL");
fd9abb3d
SG		 1366 return -EAGAIN;
1367 }
1368
1369 if (!is_valid_ether_addr(dev->dev_addr)) {
dffc6b24 1370 SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address");
fd9abb3d
SG		 1371 return -EADDRNOTAVAIL;
1372 }
1373
1374 /* Reset the LAN911x */
1375 if (smsc911x_soft_reset(pdata)) {
dffc6b24 1376 SMSC_WARN(pdata, hw, "soft reset failed");
fd9abb3d
SG		 1377 return -EIO;
1378 }
1379
1380 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1381 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1382
f277e65e
GW		 1383 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1384 spin_lock_irq(&pdata->mac_lock);
1385 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1386 spin_unlock_irq(&pdata->mac_lock);
1387
fd9abb3d
SG		 1388 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1389 timeout = 50;
f7efb6cc
SG		 1390 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1391 --timeout) {
fd9abb3d
SG		 1392 udelay(10);
1393 }
1394
1395 if (unlikely(timeout == 0))
dffc6b24
JP		 1396 SMSC_WARN(pdata, ifup,
1397 "Timed out waiting for EEPROM busy bit to clear");
fd9abb3d
SG		 1398
1399 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1400
1401 /* The soft reset above cleared the device's MAC address,
1402 * restore it from local copy (set in probe) */
1403 spin_lock_irq(&pdata->mac_lock);
225ddf49 1404 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1405 spin_unlock_irq(&pdata->mac_lock);
1406
1407 /* Initialise irqs, but leave all sources disabled */
1408 smsc911x_reg_write(pdata, INT_EN, 0);
1409 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1410
1411 /* Set interrupt deassertion to 100uS */
1412 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1413
2107fb8b 1414 if (pdata->config.irq_polarity) {
dffc6b24 1415 SMSC_TRACE(pdata, ifup, "irq polarity: active high");
fd9abb3d
SG		 1416 intcfg |= INT_CFG_IRQ_POL_;
1417 } else {
dffc6b24 1418 SMSC_TRACE(pdata, ifup, "irq polarity: active low");
fd9abb3d
SG		 1419 }
1420
2107fb8b 1421 if (pdata->config.irq_type) {
dffc6b24 1422 SMSC_TRACE(pdata, ifup, "irq type: push-pull");
fd9abb3d
SG		 1423 intcfg |= INT_CFG_IRQ_TYPE_;
1424 } else {
dffc6b24 1425 SMSC_TRACE(pdata, ifup, "irq type: open drain");
fd9abb3d
SG		 1426 }
1427
1428 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1429
dffc6b24 1430 SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
fd9abb3d
SG		 1431 pdata->software_irq_signal = 0;
1432 smp_wmb();
1433
1434 temp = smsc911x_reg_read(pdata, INT_EN);
1435 temp |= INT_EN_SW_INT_EN_;
1436 smsc911x_reg_write(pdata, INT_EN, temp);
1437
1438 timeout = 1000;
1439 while (timeout--) {
1440 if (pdata->software_irq_signal)
1441 break;
1442 msleep(1);
1443 }
1444
1445 if (!pdata->software_irq_signal) {
dffc6b24
JP		 1446 netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
1447 dev->irq);
fd9abb3d
SG		 1448 return -ENODEV;
1449 }
dffc6b24
JP		 1450 SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
1451 dev->irq);
fd9abb3d 1452
dffc6b24
JP		 1453 netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1454 (unsigned long)pdata->ioaddr, dev->irq);
fd9abb3d 1455
44c1d6f9
SG		 1456 /* Reset the last known duplex and carrier */
1457 pdata->last_duplex = -1;
1458 pdata->last_carrier = -1;
1459
fd9abb3d
SG		 1460 /* Bring the PHY up */
1461 phy_start(pdata->phy_dev);
1462
1463 temp = smsc911x_reg_read(pdata, HW_CFG);
1464 /* Preserve TX FIFO size and external PHY configuration */
1465 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1466 temp |= HW_CFG_SF_;
1467 smsc911x_reg_write(pdata, HW_CFG, temp);
1468
1469 temp = smsc911x_reg_read(pdata, FIFO_INT);
1470 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1471 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1472 smsc911x_reg_write(pdata, FIFO_INT, temp);
1473
1474 /* set RX Data offset to 2 bytes for alignment */
1475 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1476
1477 /* enable NAPI polling before enabling RX interrupts */
1478 napi_enable(&pdata->napi);
1479
1480 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1481 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1482 smsc911x_reg_write(pdata, INT_EN, temp);
1483
1484 spin_lock_irq(&pdata->mac_lock);
1485 temp = smsc911x_mac_read(pdata, MAC_CR);
1486 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1487 smsc911x_mac_write(pdata, MAC_CR, temp);
1488 spin_unlock_irq(&pdata->mac_lock);
1489
1490 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1491
1492 netif_start_queue(dev);
1493 return 0;
1494}
1495
1496/* Entry point for stopping the interface */
1497static int smsc911x_stop(struct net_device *dev)
1498{
1499 struct smsc911x_data *pdata = netdev_priv(dev);
1500 unsigned int temp;
1501
fd9abb3d
SG		 1502 /* Disable all device interrupts */
1503 temp = smsc911x_reg_read(pdata, INT_CFG);
1504 temp &= ~INT_CFG_IRQ_EN_;
1505 smsc911x_reg_write(pdata, INT_CFG, temp);
1506
1507 /* Stop Tx and Rx polling */
1508 netif_stop_queue(dev);
1509 napi_disable(&pdata->napi);
1510
1511 /* At this point all Rx and Tx activity is stopped */
1512 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1513 smsc911x_tx_update_txcounters(dev);
1514
1515 /* Bring the PHY down */
dd045193
SG		 1516 if (pdata->phy_dev)
1517 phy_stop(pdata->phy_dev);
fd9abb3d 1518
dffc6b24 1519 SMSC_TRACE(pdata, ifdown, "Interface stopped");
fd9abb3d
SG		 1520 return 0;
1521}
1522
1523/* Entry point for transmitting a packet */
1524static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1525{
1526 struct smsc911x_data *pdata = netdev_priv(dev);
1527 unsigned int freespace;
1528 unsigned int tx_cmd_a;
1529 unsigned int tx_cmd_b;
1530 unsigned int temp;
1531 u32 wrsz;
1532 ulong bufp;
1533
1534 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1535
1536 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
dffc6b24
JP		 1537 SMSC_WARN(pdata, tx_err,
1538 "Tx data fifo low, space available: %d", freespace);
fd9abb3d
SG		 1539
1540 /* Word alignment adjustment */
1541 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1542 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1543 tx_cmd_a |= (unsigned int)skb->len;
1544
1545 tx_cmd_b = ((unsigned int)skb->len) << 16;
1546 tx_cmd_b |= (unsigned int)skb->len;
1547
1548 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1549 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1550
1551 bufp = (ulong)skb->data & (~0x3);
1552 wrsz = (u32)skb->len + 3;
1553 wrsz += (u32)((ulong)skb->data & 0x3);
1554 wrsz >>= 2;
1555
c326de88 1556 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d 1557 freespace -= (skb->len + 32);
8c0069ae 1558 skb_tx_timestamp(skb);
fd9abb3d 1559 dev_kfree_skb(skb);
fd9abb3d
SG		 1560
1561 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1562 smsc911x_tx_update_txcounters(dev);
1563
1564 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1565 netif_stop_queue(dev);
1566 temp = smsc911x_reg_read(pdata, FIFO_INT);
1567 temp &= 0x00FFFFFF;
1568 temp |= 0x32000000;
1569 smsc911x_reg_write(pdata, FIFO_INT, temp);
1570 }
1571
1572 return NETDEV_TX_OK;
1573}
1574
1575/* Entry point for getting status counters */
1576static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1577{
1578 struct smsc911x_data *pdata = netdev_priv(dev);
1579 smsc911x_tx_update_txcounters(dev);
1580 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1581 return &dev->stats;
1582}
1583
1584/* Entry point for setting addressing modes */
1585static void smsc911x_set_multicast_list(struct net_device *dev)
1586{
1587 struct smsc911x_data *pdata = netdev_priv(dev);
1588 unsigned long flags;
1589
1590 if (dev->flags & IFF_PROMISC) {
1591 /* Enabling promiscuous mode */
1592 pdata->set_bits_mask = MAC_CR_PRMS_;
1593 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1594 pdata->hashhi = 0;
1595 pdata->hashlo = 0;
1596 } else if (dev->flags & IFF_ALLMULTI) {
1597 /* Enabling all multicast mode */
1598 pdata->set_bits_mask = MAC_CR_MCPAS_;
1599 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1600 pdata->hashhi = 0;
1601 pdata->hashlo = 0;
4cd24eaf 1602 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1603 /* Enabling specific multicast addresses */
1604 unsigned int hash_high = 0;
1605 unsigned int hash_low = 0;
22bedad3 1606 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1607
1608 pdata->set_bits_mask = MAC_CR_HPFILT_;
1609 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1610
22bedad3
JP		 1611 netdev_for_each_mc_addr(ha, dev) {
1612 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1613 unsigned int mask = 0x01 << (bitnum & 0x1F);
1614
1615 if (bitnum & 0x20)
1616 hash_high |= mask;
1617 else
1618 hash_low |= mask;
fd9abb3d 1619 }
fd9abb3d
SG		 1620
1621 pdata->hashhi = hash_high;
1622 pdata->hashlo = hash_low;
1623 } else {
1624 /* Enabling local MAC address only */
1625 pdata->set_bits_mask = 0;
1626 pdata->clear_bits_mask =
1627 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1628 pdata->hashhi = 0;
1629 pdata->hashlo = 0;
1630 }
1631
1632 spin_lock_irqsave(&pdata->mac_lock, flags);
1633
1634 if (pdata->generation <= 1) {
1635 /* Older hardware revision - cannot change these flags while
1636 * receiving data */
1637 if (!pdata->multicast_update_pending) {
1638 unsigned int temp;
dffc6b24 1639 SMSC_TRACE(pdata, hw, "scheduling mcast update");
fd9abb3d
SG		 1640 pdata->multicast_update_pending = 1;
1641
1642 /* Request the hardware to stop, then perform the
1643 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1644 temp = smsc911x_mac_read(pdata, MAC_CR);
1645 temp &= ~(MAC_CR_RXEN_);
1646 smsc911x_mac_write(pdata, MAC_CR, temp);
1647 } else {
1648 /* There is another update pending, this should now
1649 * use the newer values */
1650 }
1651 } else {
1652 /* Newer hardware revision - can write immediately */
1653 smsc911x_rx_multicast_update(pdata);
1654 }
1655
1656 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1657}
1658
1659static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1660{
1661 struct net_device *dev = dev_id;
1662 struct smsc911x_data *pdata = netdev_priv(dev);
1663 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1664 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1665 int serviced = IRQ_NONE;
1666 u32 temp;
1667
1668 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1669 temp = smsc911x_reg_read(pdata, INT_EN);
1670 temp &= (~INT_EN_SW_INT_EN_);
1671 smsc911x_reg_write(pdata, INT_EN, temp);
1672 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1673 pdata->software_irq_signal = 1;
1674 smp_wmb();
1675 serviced = IRQ_HANDLED;
1676 }
1677
1678 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1679 /* Called when there is a multicast update scheduled and
1680 * it is now safe to complete the update */
dffc6b24 1681 SMSC_TRACE(pdata, intr, "RX Stop interrupt");
fd9abb3d 1682 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1683 if (pdata->multicast_update_pending)
1684 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1685 serviced = IRQ_HANDLED;
1686 }
1687
1688 if (intsts & inten & INT_STS_TDFA_) {
1689 temp = smsc911x_reg_read(pdata, FIFO_INT);
1690 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1691 smsc911x_reg_write(pdata, FIFO_INT, temp);
1692 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1693 netif_wake_queue(dev);
1694 serviced = IRQ_HANDLED;
1695 }
1696
1697 if (unlikely(intsts & inten & INT_STS_RXE_)) {
dffc6b24 1698 SMSC_TRACE(pdata, intr, "RX Error interrupt");
fd9abb3d
SG		 1699 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1700 serviced = IRQ_HANDLED;
1701 }
1702
1703 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1704 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1705 /* Disable Rx interrupts */
1706 temp = smsc911x_reg_read(pdata, INT_EN);
1707 temp &= (~INT_EN_RSFL_EN_);
1708 smsc911x_reg_write(pdata, INT_EN, temp);
1709 /* Schedule a NAPI poll */
288379f0 1710 __napi_schedule(&pdata->napi);
fd9abb3d 1711 } else {
dffc6b24 1712 SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
fd9abb3d
SG		 1713 }
1714 serviced = IRQ_HANDLED;
1715 }
1716
1717 return serviced;
1718}
1719
1720#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1721static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1722{
1723 disable_irq(dev->irq);
1724 smsc911x_irqhandler(0, dev);
1725 enable_irq(dev->irq);
1726}
1727#endif /* CONFIG_NET_POLL_CONTROLLER */
1728
225ddf49
SG		 1729static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1730{
1731 struct smsc911x_data *pdata = netdev_priv(dev);
1732 struct sockaddr *addr = p;
1733
1734 /* On older hardware revisions we cannot change the mac address
1735 * registers while receiving data. Newer devices can safely change
1736 * this at any time. */
1737 if (pdata->generation <= 1 && netif_running(dev))
1738 return -EBUSY;
1739
1740 if (!is_valid_ether_addr(addr->sa_data))
1741 return -EADDRNOTAVAIL;
1742
1743 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1744
1745 spin_lock_irq(&pdata->mac_lock);
1746 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1747 spin_unlock_irq(&pdata->mac_lock);
1748
dffc6b24 1749 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
225ddf49
SG		 1750
1751 return 0;
1752}
1753
fd9abb3d
SG		 1754/* Standard ioctls for mii-tool */
1755static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1756{
1757 struct smsc911x_data *pdata = netdev_priv(dev);
1758
1759 if (!netif_running(dev) || !pdata->phy_dev)
1760 return -EINVAL;
1761
28b04113 1762 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1763}
1764
1765static int
1766smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1767{
1768 struct smsc911x_data *pdata = netdev_priv(dev);
1769
1770 cmd->maxtxpkt = 1;
1771 cmd->maxrxpkt = 1;
1772 return phy_ethtool_gset(pdata->phy_dev, cmd);
1773}
1774
1775static int
1776smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1777{
1778 struct smsc911x_data *pdata = netdev_priv(dev);
1779
1780 return phy_ethtool_sset(pdata->phy_dev, cmd);
1781}
1782
1783static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1784 struct ethtool_drvinfo *info)
1785{
1786 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1787 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1788 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1789 sizeof(info->bus_info));
1790}
1791
1792static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1793{
1794 struct smsc911x_data *pdata = netdev_priv(dev);
1795
1796 return phy_start_aneg(pdata->phy_dev);
1797}
1798
1799static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1800{
1801 struct smsc911x_data *pdata = netdev_priv(dev);
1802 return pdata->msg_enable;
1803}
1804
1805static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1806{
1807 struct smsc911x_data *pdata = netdev_priv(dev);
1808 pdata->msg_enable = level;
1809}
1810
1811static int smsc911x_ethtool_getregslen(struct net_device *dev)
1812{
1813 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1814 sizeof(u32);
1815}
1816
1817static void
1818smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1819 void *buf)
1820{
1821 struct smsc911x_data *pdata = netdev_priv(dev);
1822 struct phy_device *phy_dev = pdata->phy_dev;
1823 unsigned long flags;
1824 unsigned int i;
1825 unsigned int j = 0;
1826 u32 *data = buf;
1827
1828 regs->version = pdata->idrev;
1829 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1830 data[j++] = smsc911x_reg_read(pdata, i);
1831
1832 for (i = MAC_CR; i <= WUCSR; i++) {
1833 spin_lock_irqsave(&pdata->mac_lock, flags);
1834 data[j++] = smsc911x_mac_read(pdata, i);
1835 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1836 }
1837
1838 for (i = 0; i <= 31; i++)
1839 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1840}
1841
1842static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1843{
1844 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1845 temp &= ~GPIO_CFG_EEPR_EN_;
1846 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1847 msleep(1);
1848}
1849
1850static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1851{
1852 int timeout = 100;
1853 u32 e2cmd;
1854
dffc6b24 1855 SMSC_TRACE(pdata, drv, "op 0x%08x", op);
fd9abb3d 1856 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
dffc6b24 1857 SMSC_WARN(pdata, drv, "Busy at start");
fd9abb3d
SG		 1858 return -EBUSY;
1859 }
1860
1861 e2cmd = op | E2P_CMD_EPC_BUSY_;
1862 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1863
1864 do {
1865 msleep(1);
1866 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1867 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1868
1869 if (!timeout) {
dffc6b24 1870 SMSC_TRACE(pdata, drv, "TIMED OUT");
fd9abb3d
SG		 1871 return -EAGAIN;
1872 }
1873
1874 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1c01a80c 1875 SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
fd9abb3d
SG		 1876 return -EINVAL;
1877 }
1878
1879 return 0;
1880}
1881
1882static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1883 u8 address, u8 *data)
1884{
1885 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1886 int ret;
1887
dffc6b24 1888 SMSC_TRACE(pdata, drv, "address 0x%x", address);
fd9abb3d
SG		 1889 ret = smsc911x_eeprom_send_cmd(pdata, op);
1890
1891 if (!ret)
1892 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1893
1894 return ret;
1895}
1896
1897static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1898 u8 address, u8 data)
1899{
1900 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1901 u32 temp;
fd9abb3d
SG		 1902 int ret;
1903
dffc6b24 1904 SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
fd9abb3d
SG		 1905 ret = smsc911x_eeprom_send_cmd(pdata, op);
1906
1907 if (!ret) {
1908 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1909 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1910
1911 /* Workaround for hardware read-after-write restriction */
1912 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1913
fd9abb3d
SG		 1914 ret = smsc911x_eeprom_send_cmd(pdata, op);
1915 }
1916
1917 return ret;
1918}
1919
1920static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1921{
1922 return SMSC911X_EEPROM_SIZE;
1923}
1924
1925static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1926 struct ethtool_eeprom *eeprom, u8 *data)
1927{
1928 struct smsc911x_data *pdata = netdev_priv(dev);
1929 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1930 int len;
1931 int i;
1932
1933 smsc911x_eeprom_enable_access(pdata);
1934
1935 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1936 for (i = 0; i < len; i++) {
1937 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1938 if (ret < 0) {
1939 eeprom->len = 0;
1940 return ret;
1941 }
1942 }
1943
1944 memcpy(data, &eeprom_data[eeprom->offset], len);
1945 eeprom->len = len;
1946 return 0;
1947}
1948
1949static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1950 struct ethtool_eeprom *eeprom, u8 *data)
1951{
1952 int ret;
1953 struct smsc911x_data *pdata = netdev_priv(dev);
1954
1955 smsc911x_eeprom_enable_access(pdata);
1956 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1957 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1958 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1959
1960 /* Single byte write, according to man page */
1961 eeprom->len = 1;
1962
1963 return ret;
1964}
1965
cb5b04fe 1966static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1967 .get_settings = smsc911x_ethtool_getsettings,
1968 .set_settings = smsc911x_ethtool_setsettings,
1969 .get_link = ethtool_op_get_link,
1970 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1971 .nway_reset = smsc911x_ethtool_nwayreset,
1972 .get_msglevel = smsc911x_ethtool_getmsglevel,
1973 .set_msglevel = smsc911x_ethtool_setmsglevel,
1974 .get_regs_len = smsc911x_ethtool_getregslen,
1975 .get_regs = smsc911x_ethtool_getregs,
1976 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1977 .get_eeprom = smsc911x_ethtool_get_eeprom,
1978 .set_eeprom = smsc911x_ethtool_set_eeprom,
1979};
1980
631b7568
SG		 1981static const struct net_device_ops smsc911x_netdev_ops = {
1982 .ndo_open = smsc911x_open,
1983 .ndo_stop = smsc911x_stop,
1984 .ndo_start_xmit = smsc911x_hard_start_xmit,
1985 .ndo_get_stats = smsc911x_get_stats,
afc4b13d 1986 .ndo_set_rx_mode = smsc911x_set_multicast_list,
631b7568 1987 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1988 .ndo_change_mtu = eth_change_mtu,
631b7568 1989 .ndo_validate_addr = eth_validate_addr,
225ddf49 1990 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1991#ifdef CONFIG_NET_POLL_CONTROLLER
1992 .ndo_poll_controller = smsc911x_poll_controller,
1993#endif
1994};
1995
31f45747
SG		 1996/* copies the current mac address from hardware to dev->dev_addr */
1997static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1998{
1999 struct smsc911x_data *pdata = netdev_priv(dev);
2000 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
2001 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
2002
2003 dev->dev_addr[0] = (u8)(mac_low32);
2004 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
2005 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
2006 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
2007 dev->dev_addr[4] = (u8)(mac_high16);
2008 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
2009}
2010
fd9abb3d
SG		 2011/* Initializing private device structures, only called from probe */
2012static int __devinit smsc911x_init(struct net_device *dev)
2013{
2014 struct smsc911x_data *pdata = netdev_priv(dev);
2015 unsigned int byte_test;
3ac3546e 2016 unsigned int to = 100;
fd9abb3d 2017
dffc6b24
JP		 2018 SMSC_TRACE(pdata, probe, "Driver Parameters:");
2019 SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
2020 (unsigned long)pdata->ioaddr);
2021 SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
2022 SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
fd9abb3d 2023
fd9abb3d 2024 spin_lock_init(&pdata->dev_lock);
35a67edf 2025 spin_lock_init(&pdata->mac_lock);
fd9abb3d
SG		 2026
2027 if (pdata->ioaddr == 0) {
dffc6b24 2028 SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
fd9abb3d
SG		 2029 return -ENODEV;
2030 }
2031
3ac3546e
RM		 2032 /*
2033 * poll the READY bit in PMT_CTRL. Any other access to the device is
2034 * forbidden while this bit isn't set. Try for 100ms
2035 */
2036 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2037 udelay(1000);
2038 if (to == 0) {
2039 pr_err("Device not READY in 100ms aborting\n");
2040 return -ENODEV;
2041 }
2042
fd9abb3d
SG		 2043 /* Check byte ordering */
2044 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
dffc6b24 2045 SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 2046 if (byte_test == 0x43218765) {
dffc6b24
JP		 2047 SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
2048 "applying WORD_SWAP");
fd9abb3d
SG		 2049 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
2050
2051 /* 1 dummy read of BYTE_TEST is needed after a write to
2052 * WORD_SWAP before its contents are valid */
2053 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
2054
2055 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
2056 }
2057
2058 if (byte_test != 0x87654321) {
dffc6b24 2059 SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 2060 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
dffc6b24
JP		 2061 SMSC_WARN(pdata, probe,
2062 "top 16 bits equal to bottom 16 bits");
2063 SMSC_TRACE(pdata, probe,
2064 "This may mean the chip is set "
2065 "for 32 bit while the bus is reading 16 bit");
fd9abb3d
SG		 2066 }
2067 return -ENODEV;
2068 }
2069
2070 /* Default generation to zero (all workarounds apply) */
2071 pdata->generation = 0;
2072
2073 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
2074 switch (pdata->idrev & 0xFFFF0000) {
2075 case 0x01180000:
2076 case 0x01170000:
2077 case 0x01160000:
2078 case 0x01150000:
28c21379 2079 case 0x218A0000:
fd9abb3d
SG		 2080 /* LAN911[5678] family */
2081 pdata->generation = pdata->idrev & 0x0000FFFF;
2082 break;
2083
2084 case 0x118A0000:
2085 case 0x117A0000:
2086 case 0x116A0000:
2087 case 0x115A0000:
2088 /* LAN921[5678] family */
2089 pdata->generation = 3;
2090 break;
2091
2092 case 0x92100000:
2093 case 0x92110000:
2094 case 0x92200000:
2095 case 0x92210000:
2096 /* LAN9210/LAN9211/LAN9220/LAN9221 */
2097 pdata->generation = 4;
2098 break;
2099
2100 default:
dffc6b24
JP		 2101 SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
2102 pdata->idrev);
fd9abb3d
SG		 2103 return -ENODEV;
2104 }
2105
dffc6b24
JP		 2106 SMSC_TRACE(pdata, probe,
2107 "LAN911x identified, idrev: 0x%08X, generation: %d",
2108 pdata->idrev, pdata->generation);
fd9abb3d
SG		 2109
2110 if (pdata->generation == 0)
dffc6b24
JP		 2111 SMSC_WARN(pdata, probe,
2112 "This driver is not intended for this chip revision");
fd9abb3d 2113
31f45747
SG		 2114 /* workaround for platforms without an eeprom, where the mac address
2115 * is stored elsewhere and set by the bootloader. This saves the
2116 * mac address before resetting the device */
35a67edf
EBS		 2117 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
2118 spin_lock_irq(&pdata->mac_lock);
31f45747 2119 smsc911x_read_mac_address(dev);
35a67edf
EBS		 2120 spin_unlock_irq(&pdata->mac_lock);
2121 }
31f45747 2122
fd9abb3d
SG		 2123 /* Reset the LAN911x */
2124 if (smsc911x_soft_reset(pdata))
2125 return -ENODEV;
2126
2127 /* Disable all interrupt sources until we bring the device up */
2128 smsc911x_reg_write(pdata, INT_EN, 0);
2129
2130 ether_setup(dev);
fd9abb3d 2131 dev->flags |= IFF_MULTICAST;
fd9abb3d 2132 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 2133 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 2134 dev->ethtool_ops = &smsc911x_ethtool_ops;
2135
fd9abb3d
SG		 2136 return 0;
2137}
2138
2139static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
2140{
2141 struct net_device *dev;
2142 struct smsc911x_data *pdata;
2143 struct resource *res;
2144
2145 dev = platform_get_drvdata(pdev);
2146 BUG_ON(!dev);
2147 pdata = netdev_priv(dev);
2148 BUG_ON(!pdata);
2149 BUG_ON(!pdata->ioaddr);
2150 BUG_ON(!pdata->phy_dev);
2151
dffc6b24 2152 SMSC_TRACE(pdata, ifdown, "Stopping driver");
fd9abb3d
SG		 2153
2154 phy_disconnect(pdata->phy_dev);
2155 pdata->phy_dev = NULL;
2156 mdiobus_unregister(pdata->mii_bus);
2157 mdiobus_free(pdata->mii_bus);
2158
2159 platform_set_drvdata(pdev, NULL);
2160 unregister_netdev(dev);
2161 free_irq(dev->irq, dev);
2162 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2163 "smsc911x-memory");
2164 if (!res)
d4522739 2165 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 2166
39424539 2167 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2168
2169 iounmap(pdata->ioaddr);
2170
c7e963f6
RM		 2171 (void)smsc911x_disable_resources(pdev);
2172 smsc911x_free_resources(pdev);
2173
fd9abb3d
SG		 2174 free_netdev(dev);
2175
2176 return 0;
2177}
2178
c326de88
MP		 2179/* standard register acces */
2180static const struct smsc911x_ops standard_smsc911x_ops = {
2181 .reg_read = __smsc911x_reg_read,
2182 .reg_write = __smsc911x_reg_write,
2183 .rx_readfifo = smsc911x_rx_readfifo,
2184 .tx_writefifo = smsc911x_tx_writefifo,
2185};
2186
2187/* shifted register access */
2188static const struct smsc911x_ops shifted_smsc911x_ops = {
2189 .reg_read = __smsc911x_reg_read_shift,
2190 .reg_write = __smsc911x_reg_write_shift,
2191 .rx_readfifo = smsc911x_rx_readfifo_shift,
2192 .tx_writefifo = smsc911x_tx_writefifo_shift,
2193};
2194
79f88ee9
SG		 2195#ifdef CONFIG_OF
2196static int __devinit smsc911x_probe_config_dt(
2197 struct smsc911x_platform_config *config,
2198 struct device_node *np)
2199{
2200 const char *mac;
2201 u32 width = 0;
2202
2203 if (!np)
2204 return -ENODEV;
2205
2206 config->phy_interface = of_get_phy_mode(np);
2207
2208 mac = of_get_mac_address(np);
2209 if (mac)
2210 memcpy(config->mac, mac, ETH_ALEN);
2211
2212 of_property_read_u32(np, "reg-shift", &config->shift);
2213
2214 of_property_read_u32(np, "reg-io-width", &width);
2215 if (width == 4)
2216 config->flags |= SMSC911X_USE_32BIT;
f26cd41a
DM		 2217 else
2218 config->flags |= SMSC911X_USE_16BIT;
79f88ee9
SG		 2219
2220 if (of_get_property(np, "smsc,irq-active-high", NULL))
2221 config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
2222
2223 if (of_get_property(np, "smsc,irq-push-pull", NULL))
2224 config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
2225
2226 if (of_get_property(np, "smsc,force-internal-phy", NULL))
2227 config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
2228
2229 if (of_get_property(np, "smsc,force-external-phy", NULL))
2230 config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
2231
2232 if (of_get_property(np, "smsc,save-mac-address", NULL))
2233 config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
2234
2235 return 0;
2236}
2237#else
2238static inline int smsc911x_probe_config_dt(
2239 struct smsc911x_platform_config *config,
2240 struct device_node *np)
2241{
2242 return -ENODEV;
2243}
2244#endif /* CONFIG_OF */
2245
fd9abb3d
SG		 2246static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
2247{
79f88ee9 2248 struct device_node *np = pdev->dev.of_node;
fd9abb3d
SG		 2249 struct net_device *dev;
2250 struct smsc911x_data *pdata;
2107fb8b 2251 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 2252 struct resource *res, *irq_res;
fd9abb3d 2253 unsigned int intcfg = 0;
61307ed8 2254 int res_size, irq_flags;
fd9abb3d 2255 int retval;
fd9abb3d 2256
dffc6b24 2257 pr_info("Driver version %s\n", SMSC_DRV_VERSION);
fd9abb3d
SG		 2258
2259 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2260 "smsc911x-memory");
2261 if (!res)
2262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2263 if (!res) {
dffc6b24 2264 pr_warn("Could not allocate resource\n");
fd9abb3d
SG		 2265 retval = -ENODEV;
2266 goto out_0;
2267 }
39424539 2268 res_size = resource_size(res);
fd9abb3d 2269
61307ed8
SG		 2270 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2271 if (!irq_res) {
dffc6b24 2272 pr_warn("Could not allocate irq resource\n");
61307ed8
SG		 2273 retval = -ENODEV;
2274 goto out_0;
2275 }
2276
fd9abb3d
SG		 2277 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2278 retval = -EBUSY;
2279 goto out_0;
2280 }
2281
2282 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2283 if (!dev) {
dffc6b24 2284 pr_warn("Could not allocate device\n");
fd9abb3d
SG		 2285 retval = -ENOMEM;
2286 goto out_release_io_1;
2287 }
2288
2289 SET_NETDEV_DEV(dev, &pdev->dev);
2290
2291 pdata = netdev_priv(dev);
2292
61307ed8
SG		 2293 dev->irq = irq_res->start;
2294 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2295 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2296
fd9abb3d
SG		 2297 pdata->dev = dev;
2298 pdata->msg_enable = ((1 << debug) - 1);
2299
c7e963f6
RM		 2300 platform_set_drvdata(pdev, dev);
2301
2302 retval = smsc911x_request_resources(pdev);
2303 if (retval)
2304 goto out_return_resources;
2305
2306 retval = smsc911x_enable_resources(pdev);
2307 if (retval)
2308 goto out_disable_resources;
2309
fd9abb3d 2310 if (pdata->ioaddr == NULL) {
dffc6b24 2311 SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
fd9abb3d 2312 retval = -ENOMEM;
c7e963f6 2313 goto out_disable_resources;
fd9abb3d
SG		 2314 }
2315
79f88ee9
SG		 2316 retval = smsc911x_probe_config_dt(&pdata->config, np);
2317 if (retval && config) {
2318 /* copy config parameters across to pdata */
2319 memcpy(&pdata->config, config, sizeof(pdata->config));
2320 retval = 0;
2321 }
2322
2323 if (retval) {
2324 SMSC_WARN(pdata, probe, "Error smsc911x config not found");
c7e963f6 2325 goto out_disable_resources;
79f88ee9
SG		 2326 }
2327
c326de88
MP		 2328 /* assume standard, non-shifted, access to HW registers */
2329 pdata->ops = &standard_smsc911x_ops;
2330 /* apply the right access if shifting is needed */
79f88ee9 2331 if (pdata->config.shift)
c326de88
MP		 2332 pdata->ops = &shifted_smsc911x_ops;
2333
fd9abb3d
SG		 2334 retval = smsc911x_init(dev);
2335 if (retval < 0)
c7e963f6 2336 goto out_disable_resources;
fd9abb3d
SG		 2337
2338 /* configure irq polarity and type before connecting isr */
2107fb8b 2339 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2340 intcfg |= INT_CFG_IRQ_POL_;
2341
2107fb8b 2342 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2343 intcfg |= INT_CFG_IRQ_TYPE_;
2344
2345 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2346
2347 /* Ensure interrupts are globally disabled before connecting ISR */
2348 smsc911x_reg_write(pdata, INT_EN, 0);
2349 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2350
61307ed8 2351 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2352 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d 2353 if (retval) {
dffc6b24
JP		 2354 SMSC_WARN(pdata, probe,
2355 "Unable to claim requested irq: %d", dev->irq);
c7e963f6 2356 goto out_free_irq;
fd9abb3d
SG		 2357 }
2358
fd9abb3d
SG		 2359 retval = register_netdev(dev);
2360 if (retval) {
dffc6b24 2361 SMSC_WARN(pdata, probe, "Error %i registering device", retval);
c7e963f6 2362 goto out_free_irq;
fd9abb3d 2363 } else {
dffc6b24
JP		 2364 SMSC_TRACE(pdata, probe,
2365 "Network interface: \"%s\"", dev->name);
fd9abb3d
SG		 2366 }
2367
fd9abb3d
SG		 2368 retval = smsc911x_mii_init(pdev, dev);
2369 if (retval) {
dffc6b24 2370 SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
fd9abb3d
SG		 2371 goto out_unregister_netdev_5;
2372 }
2373
2374 spin_lock_irq(&pdata->mac_lock);
2375
2376 /* Check if mac address has been specified when bringing interface up */
2377 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2378 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2379 SMSC_TRACE(pdata, probe,
2380 "MAC Address is specified by configuration");
aace4959
ML		 2381 } else if (is_valid_ether_addr(pdata->config.mac)) {
2382 memcpy(dev->dev_addr, pdata->config.mac, 6);
dffc6b24
JP		 2383 SMSC_TRACE(pdata, probe,
2384 "MAC Address specified by platform data");
fd9abb3d
SG		 2385 } else {
2386 /* Try reading mac address from device. if EEPROM is present
2387 * it will already have been set */
62747cd2 2388 smsc_get_mac(dev);
fd9abb3d
SG		 2389
2390 if (is_valid_ether_addr(dev->dev_addr)) {
2391 /* eeprom values are valid so use them */
dffc6b24
JP		 2392 SMSC_TRACE(pdata, probe,
2393 "Mac Address is read from LAN911x EEPROM");
fd9abb3d
SG		 2394 } else {
2395 /* eeprom values are invalid, generate random MAC */
2396 random_ether_addr(dev->dev_addr);
225ddf49 2397 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2398 SMSC_TRACE(pdata, probe,
2399 "MAC Address is set to random_ether_addr");
fd9abb3d
SG		 2400 }
2401 }
2402
2403 spin_unlock_irq(&pdata->mac_lock);
2404
dffc6b24 2405 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2406
2407 return 0;
2408
2409out_unregister_netdev_5:
2410 unregister_netdev(dev);
c7e963f6 2411out_free_irq:
fd9abb3d 2412 free_irq(dev->irq, dev);
c7e963f6
RM		 2413out_disable_resources:
2414 (void)smsc911x_disable_resources(pdev);
2415out_return_resources:
2416 smsc911x_free_resources(pdev);
2417 platform_set_drvdata(pdev, NULL);
fd9abb3d 2418 iounmap(pdata->ioaddr);
fd9abb3d
SG		 2419 free_netdev(dev);
2420out_release_io_1:
39424539 2421 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2422out_0:
2423 return retval;
2424}
2425
b6907b0c
DM		 2426#ifdef CONFIG_PM
2427/* This implementation assumes the devices remains powered on its VDDVARIO
2428 * pins during suspend. */
2429
6cb87823
DM		 2430/* TODO: implement freeze/thaw callbacks for hibernation.*/
2431
2432static int smsc911x_suspend(struct device *dev)
b6907b0c 2433{
6cb87823
DM		 2434 struct net_device *ndev = dev_get_drvdata(dev);
2435 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2436
2437 /* enable wake on LAN, energy detection and the external PME
2438 * signal. */
2439 smsc911x_reg_write(pdata, PMT_CTRL,
2440 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2441 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2442
2443 return 0;
2444}
2445
6cb87823 2446static int smsc911x_resume(struct device *dev)
b6907b0c 2447{
6cb87823
DM		 2448 struct net_device *ndev = dev_get_drvdata(dev);
2449 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2450 unsigned int to = 100;
2451
2452 /* Note 3.11 from the datasheet:
2453 * "When the LAN9220 is in a power saving state, a write of any
2454 * data to the BYTE_TEST register will wake-up the device."
2455 */
2456 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2457
2458 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2459 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2460 * if it failed. */
2461 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2462 udelay(1000);
2463
2464 return (to == 0) ? -EIO : 0;
2465}
2466
47145210 2467static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2468 .suspend = smsc911x_suspend,
2469 .resume = smsc911x_resume,
2470};
2471
2472#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2473
b6907b0c 2474#else
6cb87823 2475#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2476#endif
2477
79f88ee9
SG		 2478static const struct of_device_id smsc911x_dt_ids[] = {
2479 { .compatible = "smsc,lan9115", },
2480 { /* sentinel */ }
2481};
2482MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
2483
fd9abb3d
SG		 2484static struct platform_driver smsc911x_driver = {
2485 .probe = smsc911x_drv_probe,
df911e2d 2486 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d 2487 .driver = {
6cb87823
DM		 2488 .name = SMSC_CHIPNAME,
2489 .owner = THIS_MODULE,
2490 .pm = SMSC911X_PM_OPS,
79f88ee9 2491 .of_match_table = smsc911x_dt_ids,
fd9abb3d
SG		 2492 },
2493};
2494
2495/* Entry point for loading the module */
2496static int __init smsc911x_init_module(void)
2497{
62747cd2 2498 SMSC_INITIALIZE();
fd9abb3d
SG		 2499 return platform_driver_register(&smsc911x_driver);
2500}
2501
2502/* entry point for unloading the module */
2503static void __exit smsc911x_cleanup_module(void)
2504{
2505 platform_driver_unregister(&smsc911x_driver);
2506}
2507
2508module_init(smsc911x_init_module);
2509module_exit(smsc911x_cleanup_module);
Linux kernel - Deliverables
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