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fd9abb3d SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2004-2008 SMSC | |
4 | * Copyright (C) 2005-2008 ARM | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
fd9abb3d SG |
18 | * |
19 | *************************************************************************** | |
20 | * Rewritten, heavily based on smsc911x simple driver by SMSC. | |
21 | * Partly uses io macros from smc91x.c by Nicolas Pitre | |
22 | * | |
23 | * Supported devices: | |
24 | * LAN9115, LAN9116, LAN9117, LAN9118 | |
25 | * LAN9215, LAN9216, LAN9217, LAN9218 | |
26 | * LAN9210, LAN9211 | |
27 | * LAN9220, LAN9221 | |
28c21379 | 28 | * LAN89218 |
fd9abb3d SG |
29 | * |
30 | */ | |
31 | ||
dffc6b24 JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
fd9abb3d | 34 | #include <linux/crc32.h> |
b6c23019 | 35 | #include <linux/clk.h> |
fd9abb3d SG |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/init.h> | |
a6b7a407 | 41 | #include <linux/interrupt.h> |
fd9abb3d SG |
42 | #include <linux/ioport.h> |
43 | #include <linux/kernel.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/platform_device.h> | |
c7e963f6 | 47 | #include <linux/regulator/consumer.h> |
fd9abb3d | 48 | #include <linux/sched.h> |
fd9abb3d | 49 | #include <linux/timer.h> |
fd9abb3d SG |
50 | #include <linux/bug.h> |
51 | #include <linux/bitops.h> | |
52 | #include <linux/irq.h> | |
53 | #include <linux/io.h> | |
833cc67c | 54 | #include <linux/swab.h> |
fd9abb3d SG |
55 | #include <linux/phy.h> |
56 | #include <linux/smsc911x.h> | |
6cb87823 | 57 | #include <linux/device.h> |
79f88ee9 SG |
58 | #include <linux/of.h> |
59 | #include <linux/of_device.h> | |
60 | #include <linux/of_gpio.h> | |
61 | #include <linux/of_net.h> | |
0b50dc4f | 62 | #include <linux/acpi.h> |
3a611e26 | 63 | #include <linux/pm_runtime.h> |
0b50dc4f | 64 | #include <linux/property.h> |
3a611e26 | 65 | |
fd9abb3d SG |
66 | #include "smsc911x.h" |
67 | ||
68 | #define SMSC_CHIPNAME "smsc911x" | |
69 | #define SMSC_MDIONAME "smsc911x-mdio" | |
70 | #define SMSC_DRV_VERSION "2008-10-21" | |
71 | ||
72 | MODULE_LICENSE("GPL"); | |
73 | MODULE_VERSION(SMSC_DRV_VERSION); | |
62038e4a | 74 | MODULE_ALIAS("platform:smsc911x"); |
fd9abb3d SG |
75 | |
76 | #if USE_DEBUG > 0 | |
77 | static int debug = 16; | |
78 | #else | |
79 | static int debug = 3; | |
80 | #endif | |
81 | ||
82 | module_param(debug, int, 0); | |
83 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
84 | ||
c326de88 MP |
85 | struct smsc911x_data; |
86 | ||
87 | struct smsc911x_ops { | |
88 | u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg); | |
89 | void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); | |
90 | void (*rx_readfifo)(struct smsc911x_data *pdata, | |
91 | unsigned int *buf, unsigned int wordcount); | |
92 | void (*tx_writefifo)(struct smsc911x_data *pdata, | |
93 | unsigned int *buf, unsigned int wordcount); | |
94 | }; | |
95 | ||
c7e963f6 RM |
96 | #define SMSC911X_NUM_SUPPLIES 2 |
97 | ||
fd9abb3d SG |
98 | struct smsc911x_data { |
99 | void __iomem *ioaddr; | |
100 | ||
101 | unsigned int idrev; | |
102 | ||
103 | /* used to decide which workarounds apply */ | |
104 | unsigned int generation; | |
105 | ||
106 | /* device configuration (copied from platform_data during probe) */ | |
2107fb8b | 107 | struct smsc911x_platform_config config; |
fd9abb3d SG |
108 | |
109 | /* This needs to be acquired before calling any of below: | |
110 | * smsc911x_mac_read(), smsc911x_mac_write() | |
111 | */ | |
112 | spinlock_t mac_lock; | |
113 | ||
492c5d94 | 114 | /* spinlock to ensure register accesses are serialised */ |
fd9abb3d | 115 | spinlock_t dev_lock; |
fd9abb3d SG |
116 | |
117 | struct phy_device *phy_dev; | |
118 | struct mii_bus *mii_bus; | |
119 | int phy_irq[PHY_MAX_ADDR]; | |
120 | unsigned int using_extphy; | |
121 | int last_duplex; | |
122 | int last_carrier; | |
123 | ||
124 | u32 msg_enable; | |
125 | unsigned int gpio_setting; | |
126 | unsigned int gpio_orig_setting; | |
127 | struct net_device *dev; | |
128 | struct napi_struct napi; | |
129 | ||
130 | unsigned int software_irq_signal; | |
131 | ||
132 | #ifdef USE_PHY_WORK_AROUND | |
133 | #define MIN_PACKET_SIZE (64) | |
134 | char loopback_tx_pkt[MIN_PACKET_SIZE]; | |
135 | char loopback_rx_pkt[MIN_PACKET_SIZE]; | |
136 | unsigned int resetcount; | |
137 | #endif | |
138 | ||
139 | /* Members for Multicast filter workaround */ | |
140 | unsigned int multicast_update_pending; | |
141 | unsigned int set_bits_mask; | |
142 | unsigned int clear_bits_mask; | |
143 | unsigned int hashhi; | |
144 | unsigned int hashlo; | |
c326de88 MP |
145 | |
146 | /* register access functions */ | |
147 | const struct smsc911x_ops *ops; | |
c7e963f6 RM |
148 | |
149 | /* regulators */ | |
150 | struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES]; | |
b6c23019 LJ |
151 | |
152 | /* clock */ | |
153 | struct clk *clk; | |
fd9abb3d SG |
154 | }; |
155 | ||
c326de88 MP |
156 | /* Easy access to information */ |
157 | #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift)) | |
158 | ||
492c5d94 | 159 | static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
fd9abb3d | 160 | { |
2107fb8b SG |
161 | if (pdata->config.flags & SMSC911X_USE_32BIT) |
162 | return readl(pdata->ioaddr + reg); | |
163 | ||
492c5d94 CM |
164 | if (pdata->config.flags & SMSC911X_USE_16BIT) |
165 | return ((readw(pdata->ioaddr + reg) & 0xFFFF) | | |
2107fb8b | 166 | ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); |
fd9abb3d | 167 | |
2107fb8b | 168 | BUG(); |
702403af | 169 | return 0; |
fd9abb3d SG |
170 | } |
171 | ||
c326de88 MP |
172 | static inline u32 |
173 | __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg) | |
174 | { | |
175 | if (pdata->config.flags & SMSC911X_USE_32BIT) | |
176 | return readl(pdata->ioaddr + __smsc_shift(pdata, reg)); | |
177 | ||
178 | if (pdata->config.flags & SMSC911X_USE_16BIT) | |
179 | return (readw(pdata->ioaddr + | |
180 | __smsc_shift(pdata, reg)) & 0xFFFF) | | |
181 | ((readw(pdata->ioaddr + | |
182 | __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16); | |
183 | ||
184 | BUG(); | |
185 | return 0; | |
186 | } | |
187 | ||
492c5d94 CM |
188 | static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
189 | { | |
190 | u32 data; | |
191 | unsigned long flags; | |
192 | ||
193 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 194 | data = pdata->ops->reg_read(pdata, reg); |
492c5d94 CM |
195 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
196 | ||
197 | return data; | |
198 | } | |
199 | ||
200 | static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, | |
201 | u32 val) | |
fd9abb3d | 202 | { |
2107fb8b SG |
203 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
204 | writel(val, pdata->ioaddr + reg); | |
205 | return; | |
206 | } | |
207 | ||
208 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
2107fb8b SG |
209 | writew(val & 0xFFFF, pdata->ioaddr + reg); |
210 | writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); | |
2107fb8b SG |
211 | return; |
212 | } | |
fd9abb3d | 213 | |
2107fb8b | 214 | BUG(); |
fd9abb3d SG |
215 | } |
216 | ||
c326de88 MP |
217 | static inline void |
218 | __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) | |
219 | { | |
220 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
221 | writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); | |
222 | return; | |
223 | } | |
224 | ||
225 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
226 | writew(val & 0xFFFF, | |
227 | pdata->ioaddr + __smsc_shift(pdata, reg)); | |
228 | writew((val >> 16) & 0xFFFF, | |
229 | pdata->ioaddr + __smsc_shift(pdata, reg + 2)); | |
230 | return; | |
231 | } | |
232 | ||
233 | BUG(); | |
234 | } | |
235 | ||
492c5d94 CM |
236 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
237 | u32 val) | |
238 | { | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 242 | pdata->ops->reg_write(pdata, reg, val); |
492c5d94 CM |
243 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
244 | } | |
245 | ||
fd9abb3d SG |
246 | /* Writes a packet to the TX_DATA_FIFO */ |
247 | static inline void | |
248 | smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, | |
249 | unsigned int wordcount) | |
250 | { | |
492c5d94 CM |
251 | unsigned long flags; |
252 | ||
253 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
254 | ||
833cc67c MD |
255 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
256 | while (wordcount--) | |
492c5d94 CM |
257 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, |
258 | swab32(*buf++)); | |
259 | goto out; | |
833cc67c MD |
260 | } |
261 | ||
2107fb8b | 262 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
2925f6c0 | 263 | iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount); |
492c5d94 | 264 | goto out; |
2107fb8b SG |
265 | } |
266 | ||
267 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
268 | while (wordcount--) | |
492c5d94 CM |
269 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++); |
270 | goto out; | |
2107fb8b SG |
271 | } |
272 | ||
273 | BUG(); | |
492c5d94 CM |
274 | out: |
275 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
fd9abb3d SG |
276 | } |
277 | ||
c326de88 MP |
278 | /* Writes a packet to the TX_DATA_FIFO - shifted version */ |
279 | static inline void | |
280 | smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
281 | unsigned int wordcount) | |
282 | { | |
283 | unsigned long flags; | |
284 | ||
285 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
286 | ||
287 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
288 | while (wordcount--) | |
289 | __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO, | |
290 | swab32(*buf++)); | |
291 | goto out; | |
292 | } | |
293 | ||
294 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
2925f6c0 | 295 | iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata, |
c326de88 MP |
296 | TX_DATA_FIFO), buf, wordcount); |
297 | goto out; | |
298 | } | |
299 | ||
300 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
301 | while (wordcount--) | |
302 | __smsc911x_reg_write_shift(pdata, | |
303 | TX_DATA_FIFO, *buf++); | |
304 | goto out; | |
305 | } | |
306 | ||
307 | BUG(); | |
308 | out: | |
309 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
310 | } | |
311 | ||
fd9abb3d SG |
312 | /* Reads a packet out of the RX_DATA_FIFO */ |
313 | static inline void | |
314 | smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, | |
315 | unsigned int wordcount) | |
316 | { | |
492c5d94 CM |
317 | unsigned long flags; |
318 | ||
319 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
320 | ||
833cc67c MD |
321 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
322 | while (wordcount--) | |
492c5d94 CM |
323 | *buf++ = swab32(__smsc911x_reg_read(pdata, |
324 | RX_DATA_FIFO)); | |
325 | goto out; | |
833cc67c MD |
326 | } |
327 | ||
2107fb8b | 328 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
2925f6c0 | 329 | ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount); |
492c5d94 | 330 | goto out; |
2107fb8b | 331 | } |
fd9abb3d | 332 | |
2107fb8b SG |
333 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
334 | while (wordcount--) | |
492c5d94 CM |
335 | *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO); |
336 | goto out; | |
2107fb8b SG |
337 | } |
338 | ||
339 | BUG(); | |
492c5d94 CM |
340 | out: |
341 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
2107fb8b | 342 | } |
fd9abb3d | 343 | |
c326de88 MP |
344 | /* Reads a packet out of the RX_DATA_FIFO - shifted version */ |
345 | static inline void | |
346 | smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
347 | unsigned int wordcount) | |
348 | { | |
349 | unsigned long flags; | |
350 | ||
351 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
352 | ||
353 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
354 | while (wordcount--) | |
355 | *buf++ = swab32(__smsc911x_reg_read_shift(pdata, | |
356 | RX_DATA_FIFO)); | |
357 | goto out; | |
358 | } | |
359 | ||
360 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
2925f6c0 | 361 | ioread32_rep(pdata->ioaddr + __smsc_shift(pdata, |
c326de88 MP |
362 | RX_DATA_FIFO), buf, wordcount); |
363 | goto out; | |
364 | } | |
365 | ||
366 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
367 | while (wordcount--) | |
368 | *buf++ = __smsc911x_reg_read_shift(pdata, | |
369 | RX_DATA_FIFO); | |
370 | goto out; | |
371 | } | |
372 | ||
373 | BUG(); | |
374 | out: | |
375 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
376 | } | |
377 | ||
c7e963f6 | 378 | /* |
b6c23019 | 379 | * enable regulator and clock resources. |
c7e963f6 RM |
380 | */ |
381 | static int smsc911x_enable_resources(struct platform_device *pdev) | |
382 | { | |
383 | struct net_device *ndev = platform_get_drvdata(pdev); | |
384 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
385 | int ret = 0; | |
386 | ||
387 | ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies), | |
388 | pdata->supplies); | |
389 | if (ret) | |
390 | netdev_err(ndev, "failed to enable regulators %d\n", | |
391 | ret); | |
b6c23019 LJ |
392 | |
393 | if (!IS_ERR(pdata->clk)) { | |
394 | ret = clk_prepare_enable(pdata->clk); | |
395 | if (ret < 0) | |
396 | netdev_err(ndev, "failed to enable clock %d\n", ret); | |
397 | } | |
398 | ||
c7e963f6 RM |
399 | return ret; |
400 | } | |
401 | ||
402 | /* | |
403 | * disable resources, currently just regulators. | |
404 | */ | |
405 | static int smsc911x_disable_resources(struct platform_device *pdev) | |
406 | { | |
407 | struct net_device *ndev = platform_get_drvdata(pdev); | |
408 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
409 | int ret = 0; | |
410 | ||
411 | ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies), | |
412 | pdata->supplies); | |
b6c23019 LJ |
413 | |
414 | if (!IS_ERR(pdata->clk)) | |
415 | clk_disable_unprepare(pdata->clk); | |
416 | ||
c7e963f6 RM |
417 | return ret; |
418 | } | |
419 | ||
420 | /* | |
421 | * Request resources, currently just regulators. | |
422 | * | |
423 | * The SMSC911x has two power pins: vddvario and vdd33a, in designs where | |
424 | * these are not always-on we need to request regulators to be turned on | |
425 | * before we can try to access the device registers. | |
426 | */ | |
427 | static int smsc911x_request_resources(struct platform_device *pdev) | |
428 | { | |
429 | struct net_device *ndev = platform_get_drvdata(pdev); | |
430 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
431 | int ret = 0; | |
432 | ||
433 | /* Request regulators */ | |
434 | pdata->supplies[0].supply = "vdd33a"; | |
435 | pdata->supplies[1].supply = "vddvario"; | |
436 | ret = regulator_bulk_get(&pdev->dev, | |
437 | ARRAY_SIZE(pdata->supplies), | |
438 | pdata->supplies); | |
439 | if (ret) | |
440 | netdev_err(ndev, "couldn't get regulators %d\n", | |
441 | ret); | |
b6c23019 LJ |
442 | |
443 | /* Request clock */ | |
444 | pdata->clk = clk_get(&pdev->dev, NULL); | |
445 | if (IS_ERR(pdata->clk)) | |
1e87af97 FE |
446 | dev_dbg(&pdev->dev, "couldn't get clock %li\n", |
447 | PTR_ERR(pdata->clk)); | |
b6c23019 | 448 | |
c7e963f6 RM |
449 | return ret; |
450 | } | |
451 | ||
452 | /* | |
453 | * Free resources, currently just regulators. | |
454 | * | |
455 | */ | |
456 | static void smsc911x_free_resources(struct platform_device *pdev) | |
457 | { | |
458 | struct net_device *ndev = platform_get_drvdata(pdev); | |
459 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
460 | ||
461 | /* Free regulators */ | |
462 | regulator_bulk_free(ARRAY_SIZE(pdata->supplies), | |
463 | pdata->supplies); | |
b6c23019 LJ |
464 | |
465 | /* Free clock */ | |
466 | if (!IS_ERR(pdata->clk)) { | |
467 | clk_put(pdata->clk); | |
468 | pdata->clk = NULL; | |
469 | } | |
c7e963f6 RM |
470 | } |
471 | ||
fd9abb3d SG |
472 | /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read |
473 | * and smsc911x_mac_write, so assumes mac_lock is held */ | |
474 | static int smsc911x_mac_complete(struct smsc911x_data *pdata) | |
475 | { | |
476 | int i; | |
477 | u32 val; | |
478 | ||
479 | SMSC_ASSERT_MAC_LOCK(pdata); | |
480 | ||
481 | for (i = 0; i < 40; i++) { | |
482 | val = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
483 | if (!(val & MAC_CSR_CMD_CSR_BUSY_)) | |
484 | return 0; | |
485 | } | |
dffc6b24 JP |
486 | SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. " |
487 | "MAC_CSR_CMD: 0x%08X", val); | |
fd9abb3d SG |
488 | return -EIO; |
489 | } | |
490 | ||
491 | /* Fetches a MAC register value. Assumes mac_lock is acquired */ | |
492 | static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) | |
493 | { | |
494 | unsigned int temp; | |
495 | ||
496 | SMSC_ASSERT_MAC_LOCK(pdata); | |
497 | ||
498 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
499 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 | 500 | SMSC_WARN(pdata, hw, "MAC busy at entry"); |
fd9abb3d SG |
501 | return 0xFFFFFFFF; |
502 | } | |
503 | ||
504 | /* Send the MAC cmd */ | |
505 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
506 | MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); | |
507 | ||
508 | /* Workaround for hardware read-after-write restriction */ | |
509 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
510 | ||
511 | /* Wait for the read to complete */ | |
512 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
513 | return smsc911x_reg_read(pdata, MAC_CSR_DATA); | |
514 | ||
dffc6b24 | 515 | SMSC_WARN(pdata, hw, "MAC busy after read"); |
fd9abb3d SG |
516 | return 0xFFFFFFFF; |
517 | } | |
518 | ||
519 | /* Set a mac register, mac_lock must be acquired before calling */ | |
520 | static void smsc911x_mac_write(struct smsc911x_data *pdata, | |
521 | unsigned int offset, u32 val) | |
522 | { | |
523 | unsigned int temp; | |
524 | ||
525 | SMSC_ASSERT_MAC_LOCK(pdata); | |
526 | ||
527 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
528 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 JP |
529 | SMSC_WARN(pdata, hw, |
530 | "smsc911x_mac_write failed, MAC busy at entry"); | |
fd9abb3d SG |
531 | return; |
532 | } | |
533 | ||
534 | /* Send data to write */ | |
535 | smsc911x_reg_write(pdata, MAC_CSR_DATA, val); | |
536 | ||
537 | /* Write the actual data */ | |
538 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
539 | MAC_CSR_CMD_CSR_BUSY_)); | |
540 | ||
541 | /* Workaround for hardware read-after-write restriction */ | |
542 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
543 | ||
544 | /* Wait for the write to complete */ | |
545 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
546 | return; | |
547 | ||
dffc6b24 | 548 | SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write"); |
fd9abb3d SG |
549 | } |
550 | ||
551 | /* Get a phy register */ | |
552 | static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | |
553 | { | |
554 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
555 | unsigned long flags; | |
556 | unsigned int addr; | |
557 | int i, reg; | |
558 | ||
559 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
560 | ||
561 | /* Confirm MII not busy */ | |
562 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 563 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???"); |
fd9abb3d SG |
564 | reg = -EIO; |
565 | goto out; | |
566 | } | |
567 | ||
568 | /* Set the address, index & direction (read from PHY) */ | |
569 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6); | |
570 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
571 | ||
572 | /* Wait for read to complete w/ timeout */ | |
573 | for (i = 0; i < 100; i++) | |
574 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
575 | reg = smsc911x_mac_read(pdata, MII_DATA); | |
576 | goto out; | |
577 | } | |
578 | ||
dffc6b24 | 579 | SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish"); |
fd9abb3d SG |
580 | reg = -EIO; |
581 | ||
582 | out: | |
583 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
584 | return reg; | |
585 | } | |
586 | ||
587 | /* Set a phy register */ | |
588 | static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
589 | u16 val) | |
590 | { | |
591 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
592 | unsigned long flags; | |
593 | unsigned int addr; | |
594 | int i, reg; | |
595 | ||
596 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
597 | ||
598 | /* Confirm MII not busy */ | |
599 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 600 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???"); |
fd9abb3d SG |
601 | reg = -EIO; |
602 | goto out; | |
603 | } | |
604 | ||
605 | /* Put the data to write in the MAC */ | |
606 | smsc911x_mac_write(pdata, MII_DATA, val); | |
607 | ||
608 | /* Set the address, index & direction (write to PHY) */ | |
609 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
610 | MII_ACC_MII_WRITE_; | |
611 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
612 | ||
613 | /* Wait for write to complete w/ timeout */ | |
614 | for (i = 0; i < 100; i++) | |
615 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
616 | reg = 0; | |
617 | goto out; | |
618 | } | |
619 | ||
dffc6b24 | 620 | SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish"); |
fd9abb3d SG |
621 | reg = -EIO; |
622 | ||
623 | out: | |
624 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
625 | return reg; | |
626 | } | |
627 | ||
d23f028a SG |
628 | /* Switch to external phy. Assumes tx and rx are stopped. */ |
629 | static void smsc911x_phy_enable_external(struct smsc911x_data *pdata) | |
fd9abb3d SG |
630 | { |
631 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
632 | ||
d23f028a SG |
633 | /* Disable phy clocks to the MAC */ |
634 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
635 | hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; | |
636 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
637 | udelay(10); /* Enough time for clocks to stop */ | |
fd9abb3d | 638 | |
d23f028a SG |
639 | /* Switch to external phy */ |
640 | hwcfg |= HW_CFG_EXT_PHY_EN_; | |
641 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
fd9abb3d | 642 | |
d23f028a SG |
643 | /* Enable phy clocks to the MAC */ |
644 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
645 | hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; | |
646 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
647 | udelay(10); /* Enough time for clocks to restart */ | |
fd9abb3d | 648 | |
d23f028a SG |
649 | hwcfg |= HW_CFG_SMI_SEL_; |
650 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
651 | } | |
fd9abb3d | 652 | |
d23f028a SG |
653 | /* Autodetects and enables external phy if present on supported chips. |
654 | * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY | |
655 | * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */ | |
656 | static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata) | |
657 | { | |
658 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
fd9abb3d | 659 | |
d23f028a | 660 | if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) { |
dffc6b24 | 661 | SMSC_TRACE(pdata, hw, "Forcing internal PHY"); |
d23f028a SG |
662 | pdata->using_extphy = 0; |
663 | } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) { | |
dffc6b24 | 664 | SMSC_TRACE(pdata, hw, "Forcing external PHY"); |
d23f028a SG |
665 | smsc911x_phy_enable_external(pdata); |
666 | pdata->using_extphy = 1; | |
667 | } else if (hwcfg & HW_CFG_EXT_PHY_DET_) { | |
dffc6b24 JP |
668 | SMSC_TRACE(pdata, hw, |
669 | "HW_CFG EXT_PHY_DET set, using external PHY"); | |
d23f028a | 670 | smsc911x_phy_enable_external(pdata); |
fd9abb3d SG |
671 | pdata->using_extphy = 1; |
672 | } else { | |
dffc6b24 JP |
673 | SMSC_TRACE(pdata, hw, |
674 | "HW_CFG EXT_PHY_DET clear, using internal PHY"); | |
d23f028a | 675 | pdata->using_extphy = 0; |
fd9abb3d | 676 | } |
fd9abb3d SG |
677 | } |
678 | ||
679 | /* Fetches a tx status out of the status fifo */ | |
680 | static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) | |
681 | { | |
682 | unsigned int result = | |
683 | smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; | |
684 | ||
685 | if (result != 0) | |
686 | result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); | |
687 | ||
688 | return result; | |
689 | } | |
690 | ||
691 | /* Fetches the next rx status */ | |
692 | static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) | |
693 | { | |
694 | unsigned int result = | |
695 | smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; | |
696 | ||
697 | if (result != 0) | |
698 | result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); | |
699 | ||
700 | return result; | |
701 | } | |
702 | ||
703 | #ifdef USE_PHY_WORK_AROUND | |
704 | static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) | |
705 | { | |
706 | unsigned int tries; | |
707 | u32 wrsz; | |
708 | u32 rdsz; | |
709 | ulong bufp; | |
710 | ||
711 | for (tries = 0; tries < 10; tries++) { | |
712 | unsigned int txcmd_a; | |
713 | unsigned int txcmd_b; | |
714 | unsigned int status; | |
715 | unsigned int pktlength; | |
716 | unsigned int i; | |
717 | ||
718 | /* Zero-out rx packet memory */ | |
719 | memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); | |
720 | ||
721 | /* Write tx packet to 118 */ | |
722 | txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16; | |
723 | txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
724 | txcmd_a |= MIN_PACKET_SIZE; | |
725 | ||
726 | txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; | |
727 | ||
728 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a); | |
729 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b); | |
730 | ||
731 | bufp = (ulong)pdata->loopback_tx_pkt & (~0x3); | |
732 | wrsz = MIN_PACKET_SIZE + 3; | |
733 | wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3); | |
734 | wrsz >>= 2; | |
735 | ||
c326de88 | 736 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d SG |
737 | |
738 | /* Wait till transmit is done */ | |
739 | i = 60; | |
740 | do { | |
741 | udelay(5); | |
742 | status = smsc911x_tx_get_txstatus(pdata); | |
743 | } while ((i--) && (!status)); | |
744 | ||
745 | if (!status) { | |
dffc6b24 JP |
746 | SMSC_WARN(pdata, hw, |
747 | "Failed to transmit during loopback test"); | |
fd9abb3d SG |
748 | continue; |
749 | } | |
750 | if (status & TX_STS_ES_) { | |
dffc6b24 JP |
751 | SMSC_WARN(pdata, hw, |
752 | "Transmit encountered errors during loopback test"); | |
fd9abb3d SG |
753 | continue; |
754 | } | |
755 | ||
756 | /* Wait till receive is done */ | |
757 | i = 60; | |
758 | do { | |
759 | udelay(5); | |
760 | status = smsc911x_rx_get_rxstatus(pdata); | |
761 | } while ((i--) && (!status)); | |
762 | ||
763 | if (!status) { | |
dffc6b24 JP |
764 | SMSC_WARN(pdata, hw, |
765 | "Failed to receive during loopback test"); | |
fd9abb3d SG |
766 | continue; |
767 | } | |
768 | if (status & RX_STS_ES_) { | |
dffc6b24 JP |
769 | SMSC_WARN(pdata, hw, |
770 | "Receive encountered errors during loopback test"); | |
fd9abb3d SG |
771 | continue; |
772 | } | |
773 | ||
774 | pktlength = ((status & 0x3FFF0000UL) >> 16); | |
775 | bufp = (ulong)pdata->loopback_rx_pkt; | |
776 | rdsz = pktlength + 3; | |
777 | rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3); | |
778 | rdsz >>= 2; | |
779 | ||
c326de88 | 780 | pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz); |
fd9abb3d SG |
781 | |
782 | if (pktlength != (MIN_PACKET_SIZE + 4)) { | |
dffc6b24 JP |
783 | SMSC_WARN(pdata, hw, "Unexpected packet size " |
784 | "during loop back test, size=%d, will retry", | |
785 | pktlength); | |
fd9abb3d SG |
786 | } else { |
787 | unsigned int j; | |
788 | int mismatch = 0; | |
789 | for (j = 0; j < MIN_PACKET_SIZE; j++) { | |
790 | if (pdata->loopback_tx_pkt[j] | |
791 | != pdata->loopback_rx_pkt[j]) { | |
792 | mismatch = 1; | |
793 | break; | |
794 | } | |
795 | } | |
796 | if (!mismatch) { | |
dffc6b24 | 797 | SMSC_TRACE(pdata, hw, "Successfully verified " |
fd9abb3d SG |
798 | "loopback packet"); |
799 | return 0; | |
800 | } else { | |
dffc6b24 JP |
801 | SMSC_WARN(pdata, hw, "Data mismatch " |
802 | "during loop back test, will retry"); | |
fd9abb3d SG |
803 | } |
804 | } | |
805 | } | |
806 | ||
807 | return -EIO; | |
808 | } | |
809 | ||
810 | static int smsc911x_phy_reset(struct smsc911x_data *pdata) | |
811 | { | |
fd9abb3d SG |
812 | unsigned int temp; |
813 | unsigned int i = 100000; | |
814 | ||
cd998ecd PF |
815 | temp = smsc911x_reg_read(pdata, PMT_CTRL); |
816 | smsc911x_reg_write(pdata, PMT_CTRL, temp | PMT_CTRL_PHY_RST_); | |
fd9abb3d SG |
817 | do { |
818 | msleep(1); | |
cd998ecd PF |
819 | temp = smsc911x_reg_read(pdata, PMT_CTRL); |
820 | } while ((i--) && (temp & PMT_CTRL_PHY_RST_)); | |
fd9abb3d | 821 | |
cd998ecd | 822 | if (unlikely(temp & PMT_CTRL_PHY_RST_)) { |
dffc6b24 | 823 | SMSC_WARN(pdata, hw, "PHY reset failed to complete"); |
fd9abb3d SG |
824 | return -EIO; |
825 | } | |
826 | /* Extra delay required because the phy may not be completed with | |
827 | * its reset when BMCR_RESET is cleared. Specs say 256 uS is | |
828 | * enough delay but using 1ms here to be safe */ | |
829 | msleep(1); | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | static int smsc911x_phy_loopbacktest(struct net_device *dev) | |
835 | { | |
836 | struct smsc911x_data *pdata = netdev_priv(dev); | |
837 | struct phy_device *phy_dev = pdata->phy_dev; | |
838 | int result = -EIO; | |
839 | unsigned int i, val; | |
840 | unsigned long flags; | |
841 | ||
842 | /* Initialise tx packet using broadcast destination address */ | |
c7bf7169 | 843 | eth_broadcast_addr(pdata->loopback_tx_pkt); |
fd9abb3d SG |
844 | |
845 | /* Use incrementing source address */ | |
846 | for (i = 6; i < 12; i++) | |
847 | pdata->loopback_tx_pkt[i] = (char)i; | |
848 | ||
849 | /* Set length type field */ | |
850 | pdata->loopback_tx_pkt[12] = 0x00; | |
851 | pdata->loopback_tx_pkt[13] = 0x00; | |
852 | ||
853 | for (i = 14; i < MIN_PACKET_SIZE; i++) | |
854 | pdata->loopback_tx_pkt[i] = (char)i; | |
855 | ||
856 | val = smsc911x_reg_read(pdata, HW_CFG); | |
857 | val &= HW_CFG_TX_FIF_SZ_; | |
858 | val |= HW_CFG_SF_; | |
859 | smsc911x_reg_write(pdata, HW_CFG, val); | |
860 | ||
861 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
862 | smsc911x_reg_write(pdata, RX_CFG, | |
863 | (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8); | |
864 | ||
865 | for (i = 0; i < 10; i++) { | |
866 | /* Set PHY to 10/FD, no ANEG, and loopback mode */ | |
867 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, | |
868 | BMCR_LOOPBACK | BMCR_FULLDPLX); | |
869 | ||
870 | /* Enable MAC tx/rx, FD */ | |
871 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
872 | smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ | |
873 | | MAC_CR_TXEN_ | MAC_CR_RXEN_); | |
874 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
875 | ||
876 | if (smsc911x_phy_check_loopbackpkt(pdata) == 0) { | |
877 | result = 0; | |
878 | break; | |
879 | } | |
880 | pdata->resetcount++; | |
881 | ||
882 | /* Disable MAC rx */ | |
883 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
884 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
885 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
886 | ||
887 | smsc911x_phy_reset(pdata); | |
888 | } | |
889 | ||
890 | /* Disable MAC */ | |
891 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
892 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
893 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
894 | ||
895 | /* Cancel PHY loopback mode */ | |
896 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0); | |
897 | ||
898 | smsc911x_reg_write(pdata, TX_CFG, 0); | |
899 | smsc911x_reg_write(pdata, RX_CFG, 0); | |
900 | ||
901 | return result; | |
902 | } | |
903 | #endif /* USE_PHY_WORK_AROUND */ | |
904 | ||
fd9abb3d SG |
905 | static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) |
906 | { | |
907 | struct phy_device *phy_dev = pdata->phy_dev; | |
908 | u32 afc = smsc911x_reg_read(pdata, AFC_CFG); | |
909 | u32 flow; | |
910 | unsigned long flags; | |
911 | ||
912 | if (phy_dev->duplex == DUPLEX_FULL) { | |
913 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | |
914 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | |
bc02ff95 | 915 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
fd9abb3d SG |
916 | |
917 | if (cap & FLOW_CTRL_RX) | |
918 | flow = 0xFFFF0002; | |
919 | else | |
920 | flow = 0; | |
921 | ||
922 | if (cap & FLOW_CTRL_TX) | |
923 | afc |= 0xF; | |
924 | else | |
925 | afc &= ~0xF; | |
926 | ||
dffc6b24 JP |
927 | SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s", |
928 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | |
929 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | |
fd9abb3d | 930 | } else { |
dffc6b24 | 931 | SMSC_TRACE(pdata, hw, "half duplex"); |
fd9abb3d SG |
932 | flow = 0; |
933 | afc |= 0xF; | |
934 | } | |
935 | ||
936 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
937 | smsc911x_mac_write(pdata, FLOW, flow); | |
938 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
939 | ||
940 | smsc911x_reg_write(pdata, AFC_CFG, afc); | |
941 | } | |
942 | ||
943 | /* Update link mode if anything has changed. Called periodically when the | |
944 | * PHY is in polling mode, even if nothing has changed. */ | |
945 | static void smsc911x_phy_adjust_link(struct net_device *dev) | |
946 | { | |
947 | struct smsc911x_data *pdata = netdev_priv(dev); | |
948 | struct phy_device *phy_dev = pdata->phy_dev; | |
949 | unsigned long flags; | |
950 | int carrier; | |
951 | ||
952 | if (phy_dev->duplex != pdata->last_duplex) { | |
953 | unsigned int mac_cr; | |
dffc6b24 | 954 | SMSC_TRACE(pdata, hw, "duplex state has changed"); |
fd9abb3d SG |
955 | |
956 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
957 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
958 | if (phy_dev->duplex) { | |
dffc6b24 JP |
959 | SMSC_TRACE(pdata, hw, |
960 | "configuring for full duplex mode"); | |
fd9abb3d SG |
961 | mac_cr |= MAC_CR_FDPX_; |
962 | } else { | |
dffc6b24 JP |
963 | SMSC_TRACE(pdata, hw, |
964 | "configuring for half duplex mode"); | |
fd9abb3d SG |
965 | mac_cr &= ~MAC_CR_FDPX_; |
966 | } | |
967 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
968 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
969 | ||
970 | smsc911x_phy_update_flowcontrol(pdata); | |
971 | pdata->last_duplex = phy_dev->duplex; | |
972 | } | |
973 | ||
974 | carrier = netif_carrier_ok(dev); | |
975 | if (carrier != pdata->last_carrier) { | |
dffc6b24 | 976 | SMSC_TRACE(pdata, hw, "carrier state has changed"); |
fd9abb3d | 977 | if (carrier) { |
dffc6b24 | 978 | SMSC_TRACE(pdata, hw, "configuring for carrier OK"); |
fd9abb3d SG |
979 | if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && |
980 | (!pdata->using_extphy)) { | |
88393161 | 981 | /* Restore original GPIO configuration */ |
fd9abb3d SG |
982 | pdata->gpio_setting = pdata->gpio_orig_setting; |
983 | smsc911x_reg_write(pdata, GPIO_CFG, | |
984 | pdata->gpio_setting); | |
985 | } | |
986 | } else { | |
dffc6b24 | 987 | SMSC_TRACE(pdata, hw, "configuring for no carrier"); |
fd9abb3d SG |
988 | /* Check global setting that LED1 |
989 | * usage is 10/100 indicator */ | |
990 | pdata->gpio_setting = smsc911x_reg_read(pdata, | |
991 | GPIO_CFG); | |
8e95a202 JP |
992 | if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) && |
993 | (!pdata->using_extphy)) { | |
fd9abb3d | 994 | /* Force 10/100 LED off, after saving |
88393161 | 995 | * original GPIO configuration */ |
fd9abb3d SG |
996 | pdata->gpio_orig_setting = pdata->gpio_setting; |
997 | ||
998 | pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; | |
999 | pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ | |
1000 | | GPIO_CFG_GPIODIR0_ | |
1001 | | GPIO_CFG_GPIOD0_); | |
1002 | smsc911x_reg_write(pdata, GPIO_CFG, | |
1003 | pdata->gpio_setting); | |
1004 | } | |
1005 | } | |
1006 | pdata->last_carrier = carrier; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | static int smsc911x_mii_probe(struct net_device *dev) | |
1011 | { | |
1012 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1013 | struct phy_device *phydev = NULL; | |
e4a474f8 | 1014 | int ret; |
fd9abb3d SG |
1015 | |
1016 | /* find the first phy */ | |
e4a474f8 | 1017 | phydev = phy_find_first(pdata->mii_bus); |
fd9abb3d | 1018 | if (!phydev) { |
dffc6b24 | 1019 | netdev_err(dev, "no PHY found\n"); |
fd9abb3d SG |
1020 | return -ENODEV; |
1021 | } | |
1022 | ||
dffc6b24 JP |
1023 | SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X", |
1024 | phydev->addr, phydev->phy_id); | |
e4a474f8 | 1025 | |
f9a8f83b FF |
1026 | ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link, |
1027 | pdata->config.phy_interface); | |
fd9abb3d | 1028 | |
e4a474f8 | 1029 | if (ret) { |
dffc6b24 | 1030 | netdev_err(dev, "Could not attach to PHY\n"); |
e4a474f8 | 1031 | return ret; |
fd9abb3d SG |
1032 | } |
1033 | ||
dffc6b24 JP |
1034 | netdev_info(dev, |
1035 | "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
84eff6d1 | 1036 | phydev->drv->name, phydev_name(phydev), phydev->irq); |
fd9abb3d SG |
1037 | |
1038 | /* mask with MAC supported features */ | |
1039 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
1040 | SUPPORTED_Asym_Pause); | |
1041 | phydev->advertising = phydev->supported; | |
1042 | ||
1043 | pdata->phy_dev = phydev; | |
1044 | pdata->last_duplex = -1; | |
1045 | pdata->last_carrier = -1; | |
1046 | ||
1047 | #ifdef USE_PHY_WORK_AROUND | |
1048 | if (smsc911x_phy_loopbacktest(dev) < 0) { | |
dffc6b24 | 1049 | SMSC_WARN(pdata, hw, "Failed Loop Back Test"); |
b43c142f | 1050 | phy_disconnect(phydev); |
fd9abb3d SG |
1051 | return -ENODEV; |
1052 | } | |
dffc6b24 | 1053 | SMSC_TRACE(pdata, hw, "Passed Loop Back Test"); |
fd9abb3d SG |
1054 | #endif /* USE_PHY_WORK_AROUND */ |
1055 | ||
dffc6b24 | 1056 | SMSC_TRACE(pdata, hw, "phy initialised successfully"); |
fd9abb3d SG |
1057 | return 0; |
1058 | } | |
1059 | ||
8489ec1f | 1060 | static int smsc911x_mii_init(struct platform_device *pdev, |
1dd06ae8 | 1061 | struct net_device *dev) |
fd9abb3d SG |
1062 | { |
1063 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1064 | int err = -ENXIO, i; | |
1065 | ||
1066 | pdata->mii_bus = mdiobus_alloc(); | |
1067 | if (!pdata->mii_bus) { | |
1068 | err = -ENOMEM; | |
1069 | goto err_out_1; | |
1070 | } | |
1071 | ||
1072 | pdata->mii_bus->name = SMSC_MDIONAME; | |
09ef0789 FF |
1073 | snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1074 | pdev->name, pdev->id); | |
fd9abb3d SG |
1075 | pdata->mii_bus->priv = pdata; |
1076 | pdata->mii_bus->read = smsc911x_mii_read; | |
1077 | pdata->mii_bus->write = smsc911x_mii_write; | |
1078 | pdata->mii_bus->irq = pdata->phy_irq; | |
1079 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1080 | pdata->mii_bus->irq[i] = PHY_POLL; | |
1081 | ||
1082 | pdata->mii_bus->parent = &pdev->dev; | |
fd9abb3d | 1083 | |
fd9abb3d SG |
1084 | switch (pdata->idrev & 0xFFFF0000) { |
1085 | case 0x01170000: | |
1086 | case 0x01150000: | |
1087 | case 0x117A0000: | |
1088 | case 0x115A0000: | |
1089 | /* External PHY supported, try to autodetect */ | |
d23f028a | 1090 | smsc911x_phy_initialise_external(pdata); |
fd9abb3d SG |
1091 | break; |
1092 | default: | |
dffc6b24 JP |
1093 | SMSC_TRACE(pdata, hw, "External PHY is not supported, " |
1094 | "using internal PHY"); | |
d23f028a | 1095 | pdata->using_extphy = 0; |
fd9abb3d SG |
1096 | break; |
1097 | } | |
1098 | ||
1099 | if (!pdata->using_extphy) { | |
1100 | /* Mask all PHYs except ID 1 (internal) */ | |
1101 | pdata->mii_bus->phy_mask = ~(1 << 1); | |
1102 | } | |
1103 | ||
1104 | if (mdiobus_register(pdata->mii_bus)) { | |
dffc6b24 | 1105 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1106 | goto err_out_free_bus_2; |
1107 | } | |
1108 | ||
1109 | if (smsc911x_mii_probe(dev) < 0) { | |
dffc6b24 | 1110 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1111 | goto err_out_unregister_bus_3; |
1112 | } | |
1113 | ||
1114 | return 0; | |
1115 | ||
1116 | err_out_unregister_bus_3: | |
1117 | mdiobus_unregister(pdata->mii_bus); | |
1118 | err_out_free_bus_2: | |
1119 | mdiobus_free(pdata->mii_bus); | |
1120 | err_out_1: | |
1121 | return err; | |
1122 | } | |
1123 | ||
1124 | /* Gets the number of tx statuses in the fifo */ | |
1125 | static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) | |
1126 | { | |
1127 | return (smsc911x_reg_read(pdata, TX_FIFO_INF) | |
1128 | & TX_FIFO_INF_TSUSED_) >> 16; | |
1129 | } | |
1130 | ||
1131 | /* Reads tx statuses and increments counters where necessary */ | |
1132 | static void smsc911x_tx_update_txcounters(struct net_device *dev) | |
1133 | { | |
1134 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1135 | unsigned int tx_stat; | |
1136 | ||
1137 | while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { | |
1138 | if (unlikely(tx_stat & 0x80000000)) { | |
1139 | /* In this driver the packet tag is used as the packet | |
1140 | * length. Since a packet length can never reach the | |
1141 | * size of 0x8000, this bit is reserved. It is worth | |
1142 | * noting that the "reserved bit" in the warning above | |
1143 | * does not reference a hardware defined reserved bit | |
1144 | * but rather a driver defined one. | |
1145 | */ | |
dffc6b24 | 1146 | SMSC_WARN(pdata, hw, "Packet tag reserved bit is high"); |
fd9abb3d | 1147 | } else { |
785b6f97 | 1148 | if (unlikely(tx_stat & TX_STS_ES_)) { |
fd9abb3d SG |
1149 | dev->stats.tx_errors++; |
1150 | } else { | |
1151 | dev->stats.tx_packets++; | |
1152 | dev->stats.tx_bytes += (tx_stat >> 16); | |
1153 | } | |
785b6f97 | 1154 | if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) { |
fd9abb3d SG |
1155 | dev->stats.collisions += 16; |
1156 | dev->stats.tx_aborted_errors += 1; | |
1157 | } else { | |
1158 | dev->stats.collisions += | |
1159 | ((tx_stat >> 3) & 0xF); | |
1160 | } | |
785b6f97 | 1161 | if (unlikely(tx_stat & TX_STS_LOST_CARRIER_)) |
fd9abb3d | 1162 | dev->stats.tx_carrier_errors += 1; |
785b6f97 | 1163 | if (unlikely(tx_stat & TX_STS_LATE_COL_)) { |
fd9abb3d SG |
1164 | dev->stats.collisions++; |
1165 | dev->stats.tx_aborted_errors++; | |
1166 | } | |
1167 | } | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | /* Increments the Rx error counters */ | |
1172 | static void | |
1173 | smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat) | |
1174 | { | |
1175 | int crc_err = 0; | |
1176 | ||
785b6f97 | 1177 | if (unlikely(rxstat & RX_STS_ES_)) { |
fd9abb3d | 1178 | dev->stats.rx_errors++; |
785b6f97 | 1179 | if (unlikely(rxstat & RX_STS_CRC_ERR_)) { |
fd9abb3d SG |
1180 | dev->stats.rx_crc_errors++; |
1181 | crc_err = 1; | |
1182 | } | |
1183 | } | |
1184 | if (likely(!crc_err)) { | |
785b6f97 SG |
1185 | if (unlikely((rxstat & RX_STS_FRAME_TYPE_) && |
1186 | (rxstat & RX_STS_LENGTH_ERR_))) | |
fd9abb3d | 1187 | dev->stats.rx_length_errors++; |
fd9abb3d SG |
1188 | if (rxstat & RX_STS_MCAST_) |
1189 | dev->stats.multicast++; | |
1190 | } | |
1191 | } | |
1192 | ||
1193 | /* Quickly dumps bad packets */ | |
1194 | static void | |
3c5e979b | 1195 | smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords) |
fd9abb3d | 1196 | { |
fd9abb3d SG |
1197 | if (likely(pktwords >= 4)) { |
1198 | unsigned int timeout = 500; | |
1199 | unsigned int val; | |
1200 | smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_); | |
1201 | do { | |
1202 | udelay(1); | |
1203 | val = smsc911x_reg_read(pdata, RX_DP_CTRL); | |
8dacd548 | 1204 | } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); |
fd9abb3d SG |
1205 | |
1206 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1207 | SMSC_WARN(pdata, hw, "Timed out waiting for " |
1208 | "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); | |
fd9abb3d SG |
1209 | } else { |
1210 | unsigned int temp; | |
1211 | while (pktwords--) | |
1212 | temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | /* NAPI poll function */ | |
1217 | static int smsc911x_poll(struct napi_struct *napi, int budget) | |
1218 | { | |
1219 | struct smsc911x_data *pdata = | |
1220 | container_of(napi, struct smsc911x_data, napi); | |
1221 | struct net_device *dev = pdata->dev; | |
1222 | int npackets = 0; | |
1223 | ||
f88c5b98 | 1224 | while (npackets < budget) { |
fd9abb3d SG |
1225 | unsigned int pktlength; |
1226 | unsigned int pktwords; | |
1227 | struct sk_buff *skb; | |
1228 | unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); | |
1229 | ||
1230 | if (!rxstat) { | |
1231 | unsigned int temp; | |
1232 | /* We processed all packets available. Tell NAPI it can | |
1233 | * stop polling then re-enable rx interrupts */ | |
1234 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_); | |
288379f0 | 1235 | napi_complete(napi); |
fd9abb3d SG |
1236 | temp = smsc911x_reg_read(pdata, INT_EN); |
1237 | temp |= INT_EN_RSFL_EN_; | |
1238 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1239 | break; | |
1240 | } | |
1241 | ||
1242 | /* Count packet for NAPI scheduling, even if it has an error. | |
1243 | * Error packets still require cycles to discard */ | |
1244 | npackets++; | |
1245 | ||
1246 | pktlength = ((rxstat & 0x3FFF0000) >> 16); | |
1247 | pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; | |
1248 | smsc911x_rx_counterrors(dev, rxstat); | |
1249 | ||
1250 | if (unlikely(rxstat & RX_STS_ES_)) { | |
dffc6b24 JP |
1251 | SMSC_WARN(pdata, rx_err, |
1252 | "Discarding packet with error bit set"); | |
fd9abb3d SG |
1253 | /* Packet has an error, discard it and continue with |
1254 | * the next */ | |
1255 | smsc911x_rx_fastforward(pdata, pktwords); | |
1256 | dev->stats.rx_dropped++; | |
1257 | continue; | |
1258 | } | |
1259 | ||
3c5e979b | 1260 | skb = netdev_alloc_skb(dev, pktwords << 2); |
fd9abb3d | 1261 | if (unlikely(!skb)) { |
dffc6b24 JP |
1262 | SMSC_WARN(pdata, rx_err, |
1263 | "Unable to allocate skb for rx packet"); | |
fd9abb3d SG |
1264 | /* Drop the packet and stop this polling iteration */ |
1265 | smsc911x_rx_fastforward(pdata, pktwords); | |
1266 | dev->stats.rx_dropped++; | |
1267 | break; | |
1268 | } | |
1269 | ||
3c5e979b WD |
1270 | pdata->ops->rx_readfifo(pdata, |
1271 | (unsigned int *)skb->data, pktwords); | |
fd9abb3d SG |
1272 | |
1273 | /* Align IP on 16B boundary */ | |
1274 | skb_reserve(skb, NET_IP_ALIGN); | |
1275 | skb_put(skb, pktlength - 4); | |
fd9abb3d | 1276 | skb->protocol = eth_type_trans(skb, dev); |
bc8acf2c | 1277 | skb_checksum_none_assert(skb); |
fd9abb3d SG |
1278 | netif_receive_skb(skb); |
1279 | ||
1280 | /* Update counters */ | |
1281 | dev->stats.rx_packets++; | |
1282 | dev->stats.rx_bytes += (pktlength - 4); | |
fd9abb3d SG |
1283 | } |
1284 | ||
1285 | /* Return total received packets */ | |
1286 | return npackets; | |
1287 | } | |
1288 | ||
1289 | /* Returns hash bit number for given MAC address | |
1290 | * Example: | |
1291 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
1292 | static unsigned int smsc911x_hash(char addr[ETH_ALEN]) | |
1293 | { | |
1294 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
1295 | } | |
1296 | ||
1297 | static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) | |
1298 | { | |
1299 | /* Performs the multicast & mac_cr update. This is called when | |
1300 | * safe on the current hardware, and with the mac_lock held */ | |
1301 | unsigned int mac_cr; | |
1302 | ||
1303 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1304 | ||
1305 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1306 | mac_cr |= pdata->set_bits_mask; | |
1307 | mac_cr &= ~(pdata->clear_bits_mask); | |
1308 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1309 | smsc911x_mac_write(pdata, HASHH, pdata->hashhi); | |
1310 | smsc911x_mac_write(pdata, HASHL, pdata->hashlo); | |
dffc6b24 JP |
1311 | SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", |
1312 | mac_cr, pdata->hashhi, pdata->hashlo); | |
fd9abb3d SG |
1313 | } |
1314 | ||
1315 | static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) | |
1316 | { | |
1317 | unsigned int mac_cr; | |
1318 | ||
1319 | /* This function is only called for older LAN911x devices | |
1320 | * (revA or revB), where MAC_CR, HASHH and HASHL should not | |
1321 | * be modified during Rx - newer devices immediately update the | |
1322 | * registers. | |
1323 | * | |
1324 | * This is called from interrupt context */ | |
1325 | ||
1326 | spin_lock(&pdata->mac_lock); | |
1327 | ||
1328 | /* Check Rx has stopped */ | |
1329 | if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) | |
dffc6b24 | 1330 | SMSC_WARN(pdata, drv, "Rx not stopped"); |
fd9abb3d SG |
1331 | |
1332 | /* Perform the update - safe to do now Rx has stopped */ | |
1333 | smsc911x_rx_multicast_update(pdata); | |
1334 | ||
1335 | /* Re-enable Rx */ | |
1336 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1337 | mac_cr |= MAC_CR_RXEN_; | |
1338 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1339 | ||
1340 | pdata->multicast_update_pending = 0; | |
1341 | ||
1342 | spin_unlock(&pdata->mac_lock); | |
1343 | } | |
1344 | ||
ccf899a2 EBS |
1345 | static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata) |
1346 | { | |
1347 | int rc = 0; | |
1348 | ||
1349 | if (!pdata->phy_dev) | |
1350 | return rc; | |
1351 | ||
1352 | /* If the internal PHY is in General Power-Down mode, all, except the | |
1353 | * management interface, is powered-down and stays in that condition as | |
1354 | * long as Phy register bit 0.11 is HIGH. | |
1355 | * | |
1356 | * In that case, clear the bit 0.11, so the PHY powers up and we can | |
1357 | * access to the phy registers. | |
1358 | */ | |
1359 | rc = phy_read(pdata->phy_dev, MII_BMCR); | |
1360 | if (rc < 0) { | |
1361 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1362 | return rc; | |
1363 | } | |
1364 | ||
1365 | /* If the PHY general power-down bit is not set is not necessary to | |
1366 | * disable the general power down-mode. | |
1367 | */ | |
1368 | if (rc & BMCR_PDOWN) { | |
1369 | rc = phy_write(pdata->phy_dev, MII_BMCR, rc & ~BMCR_PDOWN); | |
1370 | if (rc < 0) { | |
1371 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1372 | return rc; | |
1373 | } | |
1374 | ||
1375 | usleep_range(1000, 1500); | |
1376 | } | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
6386994e JMC |
1381 | static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata) |
1382 | { | |
1383 | int rc = 0; | |
1384 | ||
1385 | if (!pdata->phy_dev) | |
1386 | return rc; | |
1387 | ||
1388 | rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS); | |
1389 | ||
1390 | if (rc < 0) { | |
1391 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1392 | return rc; | |
1393 | } | |
1394 | ||
242bcd5b AK |
1395 | /* Only disable if energy detect mode is already enabled */ |
1396 | if (rc & MII_LAN83C185_EDPWRDOWN) { | |
6386994e JMC |
1397 | /* Disable energy detect mode for this SMSC Transceivers */ |
1398 | rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, | |
1399 | rc & (~MII_LAN83C185_EDPWRDOWN)); | |
1400 | ||
1401 | if (rc < 0) { | |
1402 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1403 | return rc; | |
1404 | } | |
6ff53fd3 AK |
1405 | /* Allow PHY to wakeup */ |
1406 | mdelay(2); | |
6386994e JMC |
1407 | } |
1408 | ||
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata) | |
1413 | { | |
1414 | int rc = 0; | |
1415 | ||
1416 | if (!pdata->phy_dev) | |
1417 | return rc; | |
1418 | ||
1419 | rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS); | |
1420 | ||
1421 | if (rc < 0) { | |
1422 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1423 | return rc; | |
1424 | } | |
1425 | ||
1426 | /* Only enable if energy detect mode is already disabled */ | |
1427 | if (!(rc & MII_LAN83C185_EDPWRDOWN)) { | |
6386994e JMC |
1428 | /* Enable energy detect mode for this SMSC Transceivers */ |
1429 | rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, | |
1430 | rc | MII_LAN83C185_EDPWRDOWN); | |
1431 | ||
1432 | if (rc < 0) { | |
1433 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1434 | return rc; | |
1435 | } | |
6386994e JMC |
1436 | } |
1437 | return 0; | |
1438 | } | |
1439 | ||
fd9abb3d SG |
1440 | static int smsc911x_soft_reset(struct smsc911x_data *pdata) |
1441 | { | |
1442 | unsigned int timeout; | |
1443 | unsigned int temp; | |
6386994e JMC |
1444 | int ret; |
1445 | ||
ccf899a2 EBS |
1446 | /* |
1447 | * Make sure to power-up the PHY chip before doing a reset, otherwise | |
1448 | * the reset fails. | |
1449 | */ | |
1450 | ret = smsc911x_phy_general_power_up(pdata); | |
1451 | if (ret) { | |
1452 | SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip"); | |
1453 | return ret; | |
1454 | } | |
1455 | ||
6386994e JMC |
1456 | /* |
1457 | * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that | |
1458 | * are initialized in a Energy Detect Power-Down mode that prevents | |
1459 | * the MAC chip to be software reseted. So we have to wakeup the PHY | |
1460 | * before. | |
1461 | */ | |
1462 | if (pdata->generation == 4) { | |
1463 | ret = smsc911x_phy_disable_energy_detect(pdata); | |
1464 | ||
1465 | if (ret) { | |
1466 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1467 | return ret; | |
1468 | } | |
1469 | } | |
fd9abb3d SG |
1470 | |
1471 | /* Reset the LAN911x */ | |
1472 | smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); | |
1473 | timeout = 10; | |
1474 | do { | |
1475 | udelay(10); | |
1476 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1477 | } while ((--timeout) && (temp & HW_CFG_SRST_)); | |
1478 | ||
1479 | if (unlikely(temp & HW_CFG_SRST_)) { | |
dffc6b24 | 1480 | SMSC_WARN(pdata, drv, "Failed to complete reset"); |
fd9abb3d SG |
1481 | return -EIO; |
1482 | } | |
6386994e JMC |
1483 | |
1484 | if (pdata->generation == 4) { | |
1485 | ret = smsc911x_phy_enable_energy_detect(pdata); | |
1486 | ||
1487 | if (ret) { | |
1488 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1489 | return ret; | |
1490 | } | |
1491 | } | |
1492 | ||
fd9abb3d SG |
1493 | return 0; |
1494 | } | |
1495 | ||
1496 | /* Sets the device MAC address to dev_addr, called with mac_lock held */ | |
1497 | static void | |
225ddf49 | 1498 | smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) |
fd9abb3d SG |
1499 | { |
1500 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | |
1501 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
1502 | (dev_addr[1] << 8) | dev_addr[0]; | |
1503 | ||
1504 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1505 | ||
1506 | smsc911x_mac_write(pdata, ADDRH, mac_high16); | |
1507 | smsc911x_mac_write(pdata, ADDRL, mac_low32); | |
1508 | } | |
1509 | ||
8e27628e MB |
1510 | static void smsc911x_disable_irq_chip(struct net_device *dev) |
1511 | { | |
1512 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1513 | ||
1514 | smsc911x_reg_write(pdata, INT_EN, 0); | |
1515 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
1516 | } | |
1517 | ||
fd9abb3d SG |
1518 | static int smsc911x_open(struct net_device *dev) |
1519 | { | |
1520 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1521 | unsigned int timeout; | |
1522 | unsigned int temp; | |
1523 | unsigned int intcfg; | |
1524 | ||
1525 | /* if the phy is not yet registered, retry later*/ | |
1526 | if (!pdata->phy_dev) { | |
dffc6b24 | 1527 | SMSC_WARN(pdata, hw, "phy_dev is NULL"); |
fd9abb3d SG |
1528 | return -EAGAIN; |
1529 | } | |
1530 | ||
fd9abb3d SG |
1531 | /* Reset the LAN911x */ |
1532 | if (smsc911x_soft_reset(pdata)) { | |
dffc6b24 | 1533 | SMSC_WARN(pdata, hw, "soft reset failed"); |
fd9abb3d SG |
1534 | return -EIO; |
1535 | } | |
1536 | ||
1537 | smsc911x_reg_write(pdata, HW_CFG, 0x00050000); | |
1538 | smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740); | |
1539 | ||
f277e65e GW |
1540 | /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */ |
1541 | spin_lock_irq(&pdata->mac_lock); | |
1542 | smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q); | |
1543 | spin_unlock_irq(&pdata->mac_lock); | |
1544 | ||
fd9abb3d SG |
1545 | /* Make sure EEPROM has finished loading before setting GPIO_CFG */ |
1546 | timeout = 50; | |
f7efb6cc SG |
1547 | while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) && |
1548 | --timeout) { | |
fd9abb3d SG |
1549 | udelay(10); |
1550 | } | |
1551 | ||
1552 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1553 | SMSC_WARN(pdata, ifup, |
1554 | "Timed out waiting for EEPROM busy bit to clear"); | |
fd9abb3d SG |
1555 | |
1556 | smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000); | |
1557 | ||
1558 | /* The soft reset above cleared the device's MAC address, | |
1559 | * restore it from local copy (set in probe) */ | |
1560 | spin_lock_irq(&pdata->mac_lock); | |
225ddf49 | 1561 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
fd9abb3d SG |
1562 | spin_unlock_irq(&pdata->mac_lock); |
1563 | ||
1564 | /* Initialise irqs, but leave all sources disabled */ | |
8e27628e | 1565 | smsc911x_disable_irq_chip(dev); |
fd9abb3d SG |
1566 | |
1567 | /* Set interrupt deassertion to 100uS */ | |
1568 | intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); | |
1569 | ||
2107fb8b | 1570 | if (pdata->config.irq_polarity) { |
dffc6b24 | 1571 | SMSC_TRACE(pdata, ifup, "irq polarity: active high"); |
fd9abb3d SG |
1572 | intcfg |= INT_CFG_IRQ_POL_; |
1573 | } else { | |
dffc6b24 | 1574 | SMSC_TRACE(pdata, ifup, "irq polarity: active low"); |
fd9abb3d SG |
1575 | } |
1576 | ||
2107fb8b | 1577 | if (pdata->config.irq_type) { |
dffc6b24 | 1578 | SMSC_TRACE(pdata, ifup, "irq type: push-pull"); |
fd9abb3d SG |
1579 | intcfg |= INT_CFG_IRQ_TYPE_; |
1580 | } else { | |
dffc6b24 | 1581 | SMSC_TRACE(pdata, ifup, "irq type: open drain"); |
fd9abb3d SG |
1582 | } |
1583 | ||
1584 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
1585 | ||
dffc6b24 | 1586 | SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq); |
fd9abb3d SG |
1587 | pdata->software_irq_signal = 0; |
1588 | smp_wmb(); | |
1589 | ||
1590 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1591 | temp |= INT_EN_SW_INT_EN_; | |
1592 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1593 | ||
1594 | timeout = 1000; | |
1595 | while (timeout--) { | |
1596 | if (pdata->software_irq_signal) | |
1597 | break; | |
1598 | msleep(1); | |
1599 | } | |
1600 | ||
1601 | if (!pdata->software_irq_signal) { | |
dffc6b24 JP |
1602 | netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n", |
1603 | dev->irq); | |
fd9abb3d SG |
1604 | return -ENODEV; |
1605 | } | |
dffc6b24 JP |
1606 | SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d", |
1607 | dev->irq); | |
fd9abb3d | 1608 | |
dffc6b24 JP |
1609 | netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
1610 | (unsigned long)pdata->ioaddr, dev->irq); | |
fd9abb3d | 1611 | |
44c1d6f9 SG |
1612 | /* Reset the last known duplex and carrier */ |
1613 | pdata->last_duplex = -1; | |
1614 | pdata->last_carrier = -1; | |
1615 | ||
fd9abb3d SG |
1616 | /* Bring the PHY up */ |
1617 | phy_start(pdata->phy_dev); | |
1618 | ||
1619 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1620 | /* Preserve TX FIFO size and external PHY configuration */ | |
1621 | temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF); | |
1622 | temp |= HW_CFG_SF_; | |
1623 | smsc911x_reg_write(pdata, HW_CFG, temp); | |
1624 | ||
1625 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1626 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1627 | temp &= ~(FIFO_INT_RX_STS_LEVEL_); | |
1628 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1629 | ||
1630 | /* set RX Data offset to 2 bytes for alignment */ | |
3c5e979b | 1631 | smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8)); |
fd9abb3d SG |
1632 | |
1633 | /* enable NAPI polling before enabling RX interrupts */ | |
1634 | napi_enable(&pdata->napi); | |
1635 | ||
1636 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1373c0fd | 1637 | temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_); |
fd9abb3d SG |
1638 | smsc911x_reg_write(pdata, INT_EN, temp); |
1639 | ||
1640 | spin_lock_irq(&pdata->mac_lock); | |
1641 | temp = smsc911x_mac_read(pdata, MAC_CR); | |
1642 | temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); | |
1643 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1644 | spin_unlock_irq(&pdata->mac_lock); | |
1645 | ||
1646 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
1647 | ||
1648 | netif_start_queue(dev); | |
1649 | return 0; | |
1650 | } | |
1651 | ||
1652 | /* Entry point for stopping the interface */ | |
1653 | static int smsc911x_stop(struct net_device *dev) | |
1654 | { | |
1655 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1656 | unsigned int temp; | |
1657 | ||
fd9abb3d SG |
1658 | /* Disable all device interrupts */ |
1659 | temp = smsc911x_reg_read(pdata, INT_CFG); | |
1660 | temp &= ~INT_CFG_IRQ_EN_; | |
1661 | smsc911x_reg_write(pdata, INT_CFG, temp); | |
1662 | ||
1663 | /* Stop Tx and Rx polling */ | |
1664 | netif_stop_queue(dev); | |
1665 | napi_disable(&pdata->napi); | |
1666 | ||
1667 | /* At this point all Rx and Tx activity is stopped */ | |
1668 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1669 | smsc911x_tx_update_txcounters(dev); | |
1670 | ||
1671 | /* Bring the PHY down */ | |
dd045193 SG |
1672 | if (pdata->phy_dev) |
1673 | phy_stop(pdata->phy_dev); | |
fd9abb3d | 1674 | |
dffc6b24 | 1675 | SMSC_TRACE(pdata, ifdown, "Interface stopped"); |
fd9abb3d SG |
1676 | return 0; |
1677 | } | |
1678 | ||
1679 | /* Entry point for transmitting a packet */ | |
1680 | static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1681 | { | |
1682 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1683 | unsigned int freespace; | |
1684 | unsigned int tx_cmd_a; | |
1685 | unsigned int tx_cmd_b; | |
1686 | unsigned int temp; | |
1687 | u32 wrsz; | |
1688 | ulong bufp; | |
1689 | ||
1690 | freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; | |
1691 | ||
1692 | if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) | |
dffc6b24 JP |
1693 | SMSC_WARN(pdata, tx_err, |
1694 | "Tx data fifo low, space available: %d", freespace); | |
fd9abb3d SG |
1695 | |
1696 | /* Word alignment adjustment */ | |
1697 | tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16; | |
1698 | tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
1699 | tx_cmd_a |= (unsigned int)skb->len; | |
1700 | ||
1701 | tx_cmd_b = ((unsigned int)skb->len) << 16; | |
1702 | tx_cmd_b |= (unsigned int)skb->len; | |
1703 | ||
1704 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a); | |
1705 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b); | |
1706 | ||
1707 | bufp = (ulong)skb->data & (~0x3); | |
1708 | wrsz = (u32)skb->len + 3; | |
1709 | wrsz += (u32)((ulong)skb->data & 0x3); | |
1710 | wrsz >>= 2; | |
1711 | ||
c326de88 | 1712 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d | 1713 | freespace -= (skb->len + 32); |
8c0069ae | 1714 | skb_tx_timestamp(skb); |
89a9eb63 | 1715 | dev_consume_skb_any(skb); |
fd9abb3d SG |
1716 | |
1717 | if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) | |
1718 | smsc911x_tx_update_txcounters(dev); | |
1719 | ||
1720 | if (freespace < TX_FIFO_LOW_THRESHOLD) { | |
1721 | netif_stop_queue(dev); | |
1722 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1723 | temp &= 0x00FFFFFF; | |
1724 | temp |= 0x32000000; | |
1725 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1726 | } | |
1727 | ||
1728 | return NETDEV_TX_OK; | |
1729 | } | |
1730 | ||
1731 | /* Entry point for getting status counters */ | |
1732 | static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) | |
1733 | { | |
1734 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1735 | smsc911x_tx_update_txcounters(dev); | |
1736 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1737 | return &dev->stats; | |
1738 | } | |
1739 | ||
1740 | /* Entry point for setting addressing modes */ | |
1741 | static void smsc911x_set_multicast_list(struct net_device *dev) | |
1742 | { | |
1743 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1744 | unsigned long flags; | |
1745 | ||
1746 | if (dev->flags & IFF_PROMISC) { | |
1747 | /* Enabling promiscuous mode */ | |
1748 | pdata->set_bits_mask = MAC_CR_PRMS_; | |
1749 | pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1750 | pdata->hashhi = 0; | |
1751 | pdata->hashlo = 0; | |
1752 | } else if (dev->flags & IFF_ALLMULTI) { | |
1753 | /* Enabling all multicast mode */ | |
1754 | pdata->set_bits_mask = MAC_CR_MCPAS_; | |
1755 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
1756 | pdata->hashhi = 0; | |
1757 | pdata->hashlo = 0; | |
4cd24eaf | 1758 | } else if (!netdev_mc_empty(dev)) { |
fd9abb3d SG |
1759 | /* Enabling specific multicast addresses */ |
1760 | unsigned int hash_high = 0; | |
1761 | unsigned int hash_low = 0; | |
22bedad3 | 1762 | struct netdev_hw_addr *ha; |
fd9abb3d SG |
1763 | |
1764 | pdata->set_bits_mask = MAC_CR_HPFILT_; | |
1765 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
1766 | ||
22bedad3 JP |
1767 | netdev_for_each_mc_addr(ha, dev) { |
1768 | unsigned int bitnum = smsc911x_hash(ha->addr); | |
2a0d18f9 JP |
1769 | unsigned int mask = 0x01 << (bitnum & 0x1F); |
1770 | ||
1771 | if (bitnum & 0x20) | |
1772 | hash_high |= mask; | |
1773 | else | |
1774 | hash_low |= mask; | |
fd9abb3d | 1775 | } |
fd9abb3d SG |
1776 | |
1777 | pdata->hashhi = hash_high; | |
1778 | pdata->hashlo = hash_low; | |
1779 | } else { | |
1780 | /* Enabling local MAC address only */ | |
1781 | pdata->set_bits_mask = 0; | |
1782 | pdata->clear_bits_mask = | |
1783 | (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1784 | pdata->hashhi = 0; | |
1785 | pdata->hashlo = 0; | |
1786 | } | |
1787 | ||
1788 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1789 | ||
1790 | if (pdata->generation <= 1) { | |
1791 | /* Older hardware revision - cannot change these flags while | |
1792 | * receiving data */ | |
1793 | if (!pdata->multicast_update_pending) { | |
1794 | unsigned int temp; | |
dffc6b24 | 1795 | SMSC_TRACE(pdata, hw, "scheduling mcast update"); |
fd9abb3d SG |
1796 | pdata->multicast_update_pending = 1; |
1797 | ||
1798 | /* Request the hardware to stop, then perform the | |
1799 | * update when we get an RX_STOP interrupt */ | |
fd9abb3d SG |
1800 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1801 | temp &= ~(MAC_CR_RXEN_); | |
1802 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1803 | } else { | |
1804 | /* There is another update pending, this should now | |
1805 | * use the newer values */ | |
1806 | } | |
1807 | } else { | |
1808 | /* Newer hardware revision - can write immediately */ | |
1809 | smsc911x_rx_multicast_update(pdata); | |
1810 | } | |
1811 | ||
1812 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1813 | } | |
1814 | ||
1815 | static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) | |
1816 | { | |
1817 | struct net_device *dev = dev_id; | |
1818 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1819 | u32 intsts = smsc911x_reg_read(pdata, INT_STS); | |
1820 | u32 inten = smsc911x_reg_read(pdata, INT_EN); | |
1821 | int serviced = IRQ_NONE; | |
1822 | u32 temp; | |
1823 | ||
1824 | if (unlikely(intsts & inten & INT_STS_SW_INT_)) { | |
1825 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1826 | temp &= (~INT_EN_SW_INT_EN_); | |
1827 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1828 | smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_); | |
1829 | pdata->software_irq_signal = 1; | |
1830 | smp_wmb(); | |
1831 | serviced = IRQ_HANDLED; | |
1832 | } | |
1833 | ||
1834 | if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { | |
1835 | /* Called when there is a multicast update scheduled and | |
1836 | * it is now safe to complete the update */ | |
dffc6b24 | 1837 | SMSC_TRACE(pdata, intr, "RX Stop interrupt"); |
fd9abb3d | 1838 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_); |
1373c0fd SG |
1839 | if (pdata->multicast_update_pending) |
1840 | smsc911x_rx_multicast_update_workaround(pdata); | |
fd9abb3d SG |
1841 | serviced = IRQ_HANDLED; |
1842 | } | |
1843 | ||
1844 | if (intsts & inten & INT_STS_TDFA_) { | |
1845 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1846 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1847 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1848 | smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_); | |
1849 | netif_wake_queue(dev); | |
1850 | serviced = IRQ_HANDLED; | |
1851 | } | |
1852 | ||
1853 | if (unlikely(intsts & inten & INT_STS_RXE_)) { | |
dffc6b24 | 1854 | SMSC_TRACE(pdata, intr, "RX Error interrupt"); |
fd9abb3d SG |
1855 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_); |
1856 | serviced = IRQ_HANDLED; | |
1857 | } | |
1858 | ||
1859 | if (likely(intsts & inten & INT_STS_RSFL_)) { | |
288379f0 | 1860 | if (likely(napi_schedule_prep(&pdata->napi))) { |
fd9abb3d SG |
1861 | /* Disable Rx interrupts */ |
1862 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1863 | temp &= (~INT_EN_RSFL_EN_); | |
1864 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1865 | /* Schedule a NAPI poll */ | |
288379f0 | 1866 | __napi_schedule(&pdata->napi); |
fd9abb3d | 1867 | } else { |
dffc6b24 | 1868 | SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed"); |
fd9abb3d SG |
1869 | } |
1870 | serviced = IRQ_HANDLED; | |
1871 | } | |
1872 | ||
1873 | return serviced; | |
1874 | } | |
1875 | ||
1876 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1757ab2f | 1877 | static void smsc911x_poll_controller(struct net_device *dev) |
fd9abb3d SG |
1878 | { |
1879 | disable_irq(dev->irq); | |
1880 | smsc911x_irqhandler(0, dev); | |
1881 | enable_irq(dev->irq); | |
1882 | } | |
1883 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1884 | ||
225ddf49 SG |
1885 | static int smsc911x_set_mac_address(struct net_device *dev, void *p) |
1886 | { | |
1887 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1888 | struct sockaddr *addr = p; | |
1889 | ||
1890 | /* On older hardware revisions we cannot change the mac address | |
1891 | * registers while receiving data. Newer devices can safely change | |
1892 | * this at any time. */ | |
1893 | if (pdata->generation <= 1 && netif_running(dev)) | |
1894 | return -EBUSY; | |
1895 | ||
1896 | if (!is_valid_ether_addr(addr->sa_data)) | |
1897 | return -EADDRNOTAVAIL; | |
1898 | ||
1899 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
1900 | ||
1901 | spin_lock_irq(&pdata->mac_lock); | |
1902 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); | |
1903 | spin_unlock_irq(&pdata->mac_lock); | |
1904 | ||
dffc6b24 | 1905 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
225ddf49 SG |
1906 | |
1907 | return 0; | |
1908 | } | |
1909 | ||
fd9abb3d SG |
1910 | /* Standard ioctls for mii-tool */ |
1911 | static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1912 | { | |
1913 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1914 | ||
1915 | if (!netif_running(dev) || !pdata->phy_dev) | |
1916 | return -EINVAL; | |
1917 | ||
28b04113 | 1918 | return phy_mii_ioctl(pdata->phy_dev, ifr, cmd); |
fd9abb3d SG |
1919 | } |
1920 | ||
1921 | static int | |
1922 | smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1923 | { | |
1924 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1925 | ||
1926 | cmd->maxtxpkt = 1; | |
1927 | cmd->maxrxpkt = 1; | |
1928 | return phy_ethtool_gset(pdata->phy_dev, cmd); | |
1929 | } | |
1930 | ||
1931 | static int | |
1932 | smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1933 | { | |
1934 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1935 | ||
1936 | return phy_ethtool_sset(pdata->phy_dev, cmd); | |
1937 | } | |
1938 | ||
1939 | static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, | |
1940 | struct ethtool_drvinfo *info) | |
1941 | { | |
1942 | strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); | |
1943 | strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); | |
db1d7bf7 | 1944 | strlcpy(info->bus_info, dev_name(dev->dev.parent), |
fd9abb3d SG |
1945 | sizeof(info->bus_info)); |
1946 | } | |
1947 | ||
1948 | static int smsc911x_ethtool_nwayreset(struct net_device *dev) | |
1949 | { | |
1950 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1951 | ||
1952 | return phy_start_aneg(pdata->phy_dev); | |
1953 | } | |
1954 | ||
1955 | static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) | |
1956 | { | |
1957 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1958 | return pdata->msg_enable; | |
1959 | } | |
1960 | ||
1961 | static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1962 | { | |
1963 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1964 | pdata->msg_enable = level; | |
1965 | } | |
1966 | ||
1967 | static int smsc911x_ethtool_getregslen(struct net_device *dev) | |
1968 | { | |
1969 | return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * | |
1970 | sizeof(u32); | |
1971 | } | |
1972 | ||
1973 | static void | |
1974 | smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | |
1975 | void *buf) | |
1976 | { | |
1977 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1978 | struct phy_device *phy_dev = pdata->phy_dev; | |
1979 | unsigned long flags; | |
1980 | unsigned int i; | |
1981 | unsigned int j = 0; | |
1982 | u32 *data = buf; | |
1983 | ||
1984 | regs->version = pdata->idrev; | |
1985 | for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32))) | |
1986 | data[j++] = smsc911x_reg_read(pdata, i); | |
1987 | ||
1988 | for (i = MAC_CR; i <= WUCSR; i++) { | |
1989 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1990 | data[j++] = smsc911x_mac_read(pdata, i); | |
1991 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1992 | } | |
1993 | ||
1994 | for (i = 0; i <= 31; i++) | |
1995 | data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i); | |
1996 | } | |
1997 | ||
1998 | static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) | |
1999 | { | |
2000 | unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); | |
2001 | temp &= ~GPIO_CFG_EEPR_EN_; | |
2002 | smsc911x_reg_write(pdata, GPIO_CFG, temp); | |
2003 | msleep(1); | |
2004 | } | |
2005 | ||
2006 | static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) | |
2007 | { | |
2008 | int timeout = 100; | |
2009 | u32 e2cmd; | |
2010 | ||
dffc6b24 | 2011 | SMSC_TRACE(pdata, drv, "op 0x%08x", op); |
fd9abb3d | 2012 | if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { |
dffc6b24 | 2013 | SMSC_WARN(pdata, drv, "Busy at start"); |
fd9abb3d SG |
2014 | return -EBUSY; |
2015 | } | |
2016 | ||
2017 | e2cmd = op | E2P_CMD_EPC_BUSY_; | |
2018 | smsc911x_reg_write(pdata, E2P_CMD, e2cmd); | |
2019 | ||
2020 | do { | |
2021 | msleep(1); | |
2022 | e2cmd = smsc911x_reg_read(pdata, E2P_CMD); | |
2cf0dbed | 2023 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
fd9abb3d SG |
2024 | |
2025 | if (!timeout) { | |
dffc6b24 | 2026 | SMSC_TRACE(pdata, drv, "TIMED OUT"); |
fd9abb3d SG |
2027 | return -EAGAIN; |
2028 | } | |
2029 | ||
2030 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | |
1c01a80c | 2031 | SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation"); |
fd9abb3d SG |
2032 | return -EINVAL; |
2033 | } | |
2034 | ||
2035 | return 0; | |
2036 | } | |
2037 | ||
2038 | static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, | |
2039 | u8 address, u8 *data) | |
2040 | { | |
2041 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | |
2042 | int ret; | |
2043 | ||
dffc6b24 | 2044 | SMSC_TRACE(pdata, drv, "address 0x%x", address); |
fd9abb3d SG |
2045 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2046 | ||
2047 | if (!ret) | |
2048 | data[address] = smsc911x_reg_read(pdata, E2P_DATA); | |
2049 | ||
2050 | return ret; | |
2051 | } | |
2052 | ||
2053 | static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, | |
2054 | u8 address, u8 data) | |
2055 | { | |
2056 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | |
58add9fc | 2057 | u32 temp; |
fd9abb3d SG |
2058 | int ret; |
2059 | ||
dffc6b24 | 2060 | SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data); |
fd9abb3d SG |
2061 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2062 | ||
2063 | if (!ret) { | |
2064 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | |
2065 | smsc911x_reg_write(pdata, E2P_DATA, (u32)data); | |
58add9fc SG |
2066 | |
2067 | /* Workaround for hardware read-after-write restriction */ | |
2068 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
2069 | ||
fd9abb3d SG |
2070 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2071 | } | |
2072 | ||
2073 | return ret; | |
2074 | } | |
2075 | ||
2076 | static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) | |
2077 | { | |
2078 | return SMSC911X_EEPROM_SIZE; | |
2079 | } | |
2080 | ||
2081 | static int smsc911x_ethtool_get_eeprom(struct net_device *dev, | |
2082 | struct ethtool_eeprom *eeprom, u8 *data) | |
2083 | { | |
2084 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2085 | u8 eeprom_data[SMSC911X_EEPROM_SIZE]; | |
2086 | int len; | |
2087 | int i; | |
2088 | ||
2089 | smsc911x_eeprom_enable_access(pdata); | |
2090 | ||
2091 | len = min(eeprom->len, SMSC911X_EEPROM_SIZE); | |
2092 | for (i = 0; i < len; i++) { | |
2093 | int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); | |
2094 | if (ret < 0) { | |
2095 | eeprom->len = 0; | |
2096 | return ret; | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | memcpy(data, &eeprom_data[eeprom->offset], len); | |
2101 | eeprom->len = len; | |
2102 | return 0; | |
2103 | } | |
2104 | ||
2105 | static int smsc911x_ethtool_set_eeprom(struct net_device *dev, | |
2106 | struct ethtool_eeprom *eeprom, u8 *data) | |
2107 | { | |
2108 | int ret; | |
2109 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2110 | ||
2111 | smsc911x_eeprom_enable_access(pdata); | |
2112 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); | |
2113 | ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); | |
2114 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); | |
2115 | ||
2116 | /* Single byte write, according to man page */ | |
2117 | eeprom->len = 1; | |
2118 | ||
2119 | return ret; | |
2120 | } | |
2121 | ||
cb5b04fe | 2122 | static const struct ethtool_ops smsc911x_ethtool_ops = { |
fd9abb3d SG |
2123 | .get_settings = smsc911x_ethtool_getsettings, |
2124 | .set_settings = smsc911x_ethtool_setsettings, | |
2125 | .get_link = ethtool_op_get_link, | |
2126 | .get_drvinfo = smsc911x_ethtool_getdrvinfo, | |
2127 | .nway_reset = smsc911x_ethtool_nwayreset, | |
2128 | .get_msglevel = smsc911x_ethtool_getmsglevel, | |
2129 | .set_msglevel = smsc911x_ethtool_setmsglevel, | |
2130 | .get_regs_len = smsc911x_ethtool_getregslen, | |
2131 | .get_regs = smsc911x_ethtool_getregs, | |
2132 | .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, | |
2133 | .get_eeprom = smsc911x_ethtool_get_eeprom, | |
2134 | .set_eeprom = smsc911x_ethtool_set_eeprom, | |
b5d1d256 | 2135 | .get_ts_info = ethtool_op_get_ts_info, |
fd9abb3d SG |
2136 | }; |
2137 | ||
631b7568 SG |
2138 | static const struct net_device_ops smsc911x_netdev_ops = { |
2139 | .ndo_open = smsc911x_open, | |
2140 | .ndo_stop = smsc911x_stop, | |
2141 | .ndo_start_xmit = smsc911x_hard_start_xmit, | |
2142 | .ndo_get_stats = smsc911x_get_stats, | |
afc4b13d | 2143 | .ndo_set_rx_mode = smsc911x_set_multicast_list, |
631b7568 | 2144 | .ndo_do_ioctl = smsc911x_do_ioctl, |
635ecaa7 | 2145 | .ndo_change_mtu = eth_change_mtu, |
631b7568 | 2146 | .ndo_validate_addr = eth_validate_addr, |
225ddf49 | 2147 | .ndo_set_mac_address = smsc911x_set_mac_address, |
631b7568 SG |
2148 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2149 | .ndo_poll_controller = smsc911x_poll_controller, | |
2150 | #endif | |
2151 | }; | |
2152 | ||
31f45747 | 2153 | /* copies the current mac address from hardware to dev->dev_addr */ |
8489ec1f | 2154 | static void smsc911x_read_mac_address(struct net_device *dev) |
31f45747 SG |
2155 | { |
2156 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2157 | u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); | |
2158 | u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); | |
2159 | ||
2160 | dev->dev_addr[0] = (u8)(mac_low32); | |
2161 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | |
2162 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | |
2163 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | |
2164 | dev->dev_addr[4] = (u8)(mac_high16); | |
2165 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | |
2166 | } | |
2167 | ||
fd9abb3d | 2168 | /* Initializing private device structures, only called from probe */ |
8489ec1f | 2169 | static int smsc911x_init(struct net_device *dev) |
fd9abb3d SG |
2170 | { |
2171 | struct smsc911x_data *pdata = netdev_priv(dev); | |
769ce4c9 | 2172 | unsigned int byte_test, mask; |
3ac3546e | 2173 | unsigned int to = 100; |
fd9abb3d | 2174 | |
dffc6b24 JP |
2175 | SMSC_TRACE(pdata, probe, "Driver Parameters:"); |
2176 | SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX", | |
2177 | (unsigned long)pdata->ioaddr); | |
2178 | SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq); | |
2179 | SMSC_TRACE(pdata, probe, "PHY will be autodetected."); | |
fd9abb3d | 2180 | |
fd9abb3d | 2181 | spin_lock_init(&pdata->dev_lock); |
35a67edf | 2182 | spin_lock_init(&pdata->mac_lock); |
fd9abb3d | 2183 | |
6fed9592 | 2184 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2185 | SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000"); |
fd9abb3d SG |
2186 | return -ENODEV; |
2187 | } | |
2188 | ||
3ac3546e RM |
2189 | /* |
2190 | * poll the READY bit in PMT_CTRL. Any other access to the device is | |
2191 | * forbidden while this bit isn't set. Try for 100ms | |
769ce4c9 KP |
2192 | * |
2193 | * Note that this test is done before the WORD_SWAP register is | |
2194 | * programmed. So in some configurations the READY bit is at 16 before | |
2195 | * WORD_SWAP is written to. This issue is worked around by waiting | |
2196 | * until either bit 0 or bit 16 gets set in PMT_CTRL. | |
2197 | * | |
2198 | * SMSC has confirmed that checking bit 16 (marked as reserved in | |
2199 | * the datasheet) is fine since these bits "will either never be set | |
2200 | * or can only go high after READY does (so also indicate the device | |
2201 | * is ready)". | |
3ac3546e | 2202 | */ |
769ce4c9 KP |
2203 | |
2204 | mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_); | |
2205 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to) | |
3ac3546e | 2206 | udelay(1000); |
769ce4c9 | 2207 | |
3ac3546e | 2208 | if (to == 0) { |
b1a04a62 | 2209 | netdev_err(dev, "Device not READY in 100ms aborting\n"); |
3ac3546e RM |
2210 | return -ENODEV; |
2211 | } | |
2212 | ||
fd9abb3d SG |
2213 | /* Check byte ordering */ |
2214 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
dffc6b24 | 2215 | SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2216 | if (byte_test == 0x43218765) { |
dffc6b24 JP |
2217 | SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, " |
2218 | "applying WORD_SWAP"); | |
fd9abb3d SG |
2219 | smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff); |
2220 | ||
2221 | /* 1 dummy read of BYTE_TEST is needed after a write to | |
2222 | * WORD_SWAP before its contents are valid */ | |
2223 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2224 | ||
2225 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2226 | } | |
2227 | ||
2228 | if (byte_test != 0x87654321) { | |
dffc6b24 | 2229 | SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2230 | if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) { |
dffc6b24 JP |
2231 | SMSC_WARN(pdata, probe, |
2232 | "top 16 bits equal to bottom 16 bits"); | |
2233 | SMSC_TRACE(pdata, probe, | |
2234 | "This may mean the chip is set " | |
2235 | "for 32 bit while the bus is reading 16 bit"); | |
fd9abb3d SG |
2236 | } |
2237 | return -ENODEV; | |
2238 | } | |
2239 | ||
2240 | /* Default generation to zero (all workarounds apply) */ | |
2241 | pdata->generation = 0; | |
2242 | ||
2243 | pdata->idrev = smsc911x_reg_read(pdata, ID_REV); | |
2244 | switch (pdata->idrev & 0xFFFF0000) { | |
2245 | case 0x01180000: | |
2246 | case 0x01170000: | |
2247 | case 0x01160000: | |
2248 | case 0x01150000: | |
28c21379 | 2249 | case 0x218A0000: |
fd9abb3d SG |
2250 | /* LAN911[5678] family */ |
2251 | pdata->generation = pdata->idrev & 0x0000FFFF; | |
2252 | break; | |
2253 | ||
2254 | case 0x118A0000: | |
2255 | case 0x117A0000: | |
2256 | case 0x116A0000: | |
2257 | case 0x115A0000: | |
2258 | /* LAN921[5678] family */ | |
2259 | pdata->generation = 3; | |
2260 | break; | |
2261 | ||
2262 | case 0x92100000: | |
2263 | case 0x92110000: | |
2264 | case 0x92200000: | |
2265 | case 0x92210000: | |
2266 | /* LAN9210/LAN9211/LAN9220/LAN9221 */ | |
2267 | pdata->generation = 4; | |
2268 | break; | |
2269 | ||
2270 | default: | |
dffc6b24 JP |
2271 | SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X", |
2272 | pdata->idrev); | |
fd9abb3d SG |
2273 | return -ENODEV; |
2274 | } | |
2275 | ||
dffc6b24 JP |
2276 | SMSC_TRACE(pdata, probe, |
2277 | "LAN911x identified, idrev: 0x%08X, generation: %d", | |
2278 | pdata->idrev, pdata->generation); | |
fd9abb3d SG |
2279 | |
2280 | if (pdata->generation == 0) | |
dffc6b24 JP |
2281 | SMSC_WARN(pdata, probe, |
2282 | "This driver is not intended for this chip revision"); | |
fd9abb3d | 2283 | |
31f45747 SG |
2284 | /* workaround for platforms without an eeprom, where the mac address |
2285 | * is stored elsewhere and set by the bootloader. This saves the | |
2286 | * mac address before resetting the device */ | |
35a67edf EBS |
2287 | if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) { |
2288 | spin_lock_irq(&pdata->mac_lock); | |
31f45747 | 2289 | smsc911x_read_mac_address(dev); |
35a67edf EBS |
2290 | spin_unlock_irq(&pdata->mac_lock); |
2291 | } | |
31f45747 | 2292 | |
fd9abb3d | 2293 | /* Reset the LAN911x */ |
cd998ecd | 2294 | if (smsc911x_phy_reset(pdata) || smsc911x_soft_reset(pdata)) |
fd9abb3d SG |
2295 | return -ENODEV; |
2296 | ||
fd9abb3d | 2297 | dev->flags |= IFF_MULTICAST; |
fd9abb3d | 2298 | netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT); |
631b7568 | 2299 | dev->netdev_ops = &smsc911x_netdev_ops; |
fd9abb3d SG |
2300 | dev->ethtool_ops = &smsc911x_ethtool_ops; |
2301 | ||
fd9abb3d SG |
2302 | return 0; |
2303 | } | |
2304 | ||
8489ec1f | 2305 | static int smsc911x_drv_remove(struct platform_device *pdev) |
fd9abb3d SG |
2306 | { |
2307 | struct net_device *dev; | |
2308 | struct smsc911x_data *pdata; | |
2309 | struct resource *res; | |
2310 | ||
2311 | dev = platform_get_drvdata(pdev); | |
2312 | BUG_ON(!dev); | |
2313 | pdata = netdev_priv(dev); | |
2314 | BUG_ON(!pdata); | |
2315 | BUG_ON(!pdata->ioaddr); | |
2316 | BUG_ON(!pdata->phy_dev); | |
2317 | ||
dffc6b24 | 2318 | SMSC_TRACE(pdata, ifdown, "Stopping driver"); |
fd9abb3d SG |
2319 | |
2320 | phy_disconnect(pdata->phy_dev); | |
2321 | pdata->phy_dev = NULL; | |
2322 | mdiobus_unregister(pdata->mii_bus); | |
2323 | mdiobus_free(pdata->mii_bus); | |
2324 | ||
fd9abb3d SG |
2325 | unregister_netdev(dev); |
2326 | free_irq(dev->irq, dev); | |
2327 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
2328 | "smsc911x-memory"); | |
2329 | if (!res) | |
d4522739 | 2330 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
fd9abb3d | 2331 | |
39424539 | 2332 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2333 | |
2334 | iounmap(pdata->ioaddr); | |
2335 | ||
c7e963f6 RM |
2336 | (void)smsc911x_disable_resources(pdev); |
2337 | smsc911x_free_resources(pdev); | |
2338 | ||
fd9abb3d SG |
2339 | free_netdev(dev); |
2340 | ||
3a611e26 GU |
2341 | pm_runtime_put(&pdev->dev); |
2342 | pm_runtime_disable(&pdev->dev); | |
2343 | ||
fd9abb3d SG |
2344 | return 0; |
2345 | } | |
2346 | ||
c326de88 MP |
2347 | /* standard register acces */ |
2348 | static const struct smsc911x_ops standard_smsc911x_ops = { | |
2349 | .reg_read = __smsc911x_reg_read, | |
2350 | .reg_write = __smsc911x_reg_write, | |
2351 | .rx_readfifo = smsc911x_rx_readfifo, | |
2352 | .tx_writefifo = smsc911x_tx_writefifo, | |
2353 | }; | |
2354 | ||
2355 | /* shifted register access */ | |
2356 | static const struct smsc911x_ops shifted_smsc911x_ops = { | |
2357 | .reg_read = __smsc911x_reg_read_shift, | |
2358 | .reg_write = __smsc911x_reg_write_shift, | |
2359 | .rx_readfifo = smsc911x_rx_readfifo_shift, | |
2360 | .tx_writefifo = smsc911x_tx_writefifo_shift, | |
2361 | }; | |
2362 | ||
0b50dc4f JL |
2363 | static int smsc911x_probe_config(struct smsc911x_platform_config *config, |
2364 | struct device *dev) | |
79f88ee9 | 2365 | { |
62ee783b | 2366 | int phy_interface; |
79f88ee9 | 2367 | u32 width = 0; |
31cb5c9e | 2368 | int err; |
79f88ee9 | 2369 | |
62ee783b GR |
2370 | phy_interface = device_get_phy_mode(dev); |
2371 | if (phy_interface < 0) | |
31cb5c9e | 2372 | phy_interface = PHY_INTERFACE_MODE_NA; |
62ee783b | 2373 | config->phy_interface = phy_interface; |
79f88ee9 | 2374 | |
0b50dc4f | 2375 | device_get_mac_address(dev, config->mac, ETH_ALEN); |
79f88ee9 | 2376 | |
31cb5c9e GR |
2377 | err = device_property_read_u32(dev, "reg-io-width", &width); |
2378 | if (err == -ENXIO) | |
2379 | return err; | |
2380 | if (!err && width == 4) | |
79f88ee9 | 2381 | config->flags |= SMSC911X_USE_32BIT; |
f26cd41a DM |
2382 | else |
2383 | config->flags |= SMSC911X_USE_16BIT; | |
79f88ee9 | 2384 | |
31cb5c9e GR |
2385 | device_property_read_u32(dev, "reg-shift", &config->shift); |
2386 | ||
0b50dc4f | 2387 | if (device_property_present(dev, "smsc,irq-active-high")) |
79f88ee9 SG |
2388 | config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH; |
2389 | ||
0b50dc4f | 2390 | if (device_property_present(dev, "smsc,irq-push-pull")) |
79f88ee9 SG |
2391 | config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL; |
2392 | ||
0b50dc4f | 2393 | if (device_property_present(dev, "smsc,force-internal-phy")) |
79f88ee9 SG |
2394 | config->flags |= SMSC911X_FORCE_INTERNAL_PHY; |
2395 | ||
0b50dc4f | 2396 | if (device_property_present(dev, "smsc,force-external-phy")) |
79f88ee9 SG |
2397 | config->flags |= SMSC911X_FORCE_EXTERNAL_PHY; |
2398 | ||
0b50dc4f | 2399 | if (device_property_present(dev, "smsc,save-mac-address")) |
79f88ee9 SG |
2400 | config->flags |= SMSC911X_SAVE_MAC_ADDRESS; |
2401 | ||
2402 | return 0; | |
2403 | } | |
79f88ee9 | 2404 | |
8489ec1f | 2405 | static int smsc911x_drv_probe(struct platform_device *pdev) |
fd9abb3d SG |
2406 | { |
2407 | struct net_device *dev; | |
2408 | struct smsc911x_data *pdata; | |
495c765d | 2409 | struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev); |
965b2aa7 | 2410 | struct resource *res; |
fd9abb3d | 2411 | unsigned int intcfg = 0; |
965b2aa7 | 2412 | int res_size, irq, irq_flags; |
fd9abb3d | 2413 | int retval; |
fd9abb3d | 2414 | |
fd9abb3d SG |
2415 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2416 | "smsc911x-memory"); | |
2417 | if (!res) | |
2418 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2419 | if (!res) { | |
dffc6b24 | 2420 | pr_warn("Could not allocate resource\n"); |
fd9abb3d SG |
2421 | retval = -ENODEV; |
2422 | goto out_0; | |
2423 | } | |
39424539 | 2424 | res_size = resource_size(res); |
fd9abb3d | 2425 | |
965b2aa7 | 2426 | irq = platform_get_irq(pdev, 0); |
f892a84c TL |
2427 | if (irq == -EPROBE_DEFER) { |
2428 | retval = -EPROBE_DEFER; | |
2429 | goto out_0; | |
2430 | } else if (irq <= 0) { | |
dffc6b24 | 2431 | pr_warn("Could not allocate irq resource\n"); |
61307ed8 SG |
2432 | retval = -ENODEV; |
2433 | goto out_0; | |
2434 | } | |
2435 | ||
fd9abb3d SG |
2436 | if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { |
2437 | retval = -EBUSY; | |
2438 | goto out_0; | |
2439 | } | |
2440 | ||
2441 | dev = alloc_etherdev(sizeof(struct smsc911x_data)); | |
2442 | if (!dev) { | |
fd9abb3d SG |
2443 | retval = -ENOMEM; |
2444 | goto out_release_io_1; | |
2445 | } | |
2446 | ||
2447 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2448 | ||
2449 | pdata = netdev_priv(dev); | |
965b2aa7 KP |
2450 | dev->irq = irq; |
2451 | irq_flags = irq_get_trigger_type(irq); | |
fd9abb3d SG |
2452 | pdata->ioaddr = ioremap_nocache(res->start, res_size); |
2453 | ||
fd9abb3d SG |
2454 | pdata->dev = dev; |
2455 | pdata->msg_enable = ((1 << debug) - 1); | |
2456 | ||
c7e963f6 RM |
2457 | platform_set_drvdata(pdev, dev); |
2458 | ||
2459 | retval = smsc911x_request_resources(pdev); | |
2460 | if (retval) | |
2e1d4a06 | 2461 | goto out_request_resources_fail; |
c7e963f6 RM |
2462 | |
2463 | retval = smsc911x_enable_resources(pdev); | |
2464 | if (retval) | |
2e1d4a06 | 2465 | goto out_enable_resources_fail; |
c7e963f6 | 2466 | |
fd9abb3d | 2467 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2468 | SMSC_WARN(pdata, probe, "Error smsc911x base address invalid"); |
fd9abb3d | 2469 | retval = -ENOMEM; |
c7e963f6 | 2470 | goto out_disable_resources; |
fd9abb3d SG |
2471 | } |
2472 | ||
0b50dc4f | 2473 | retval = smsc911x_probe_config(&pdata->config, &pdev->dev); |
79f88ee9 SG |
2474 | if (retval && config) { |
2475 | /* copy config parameters across to pdata */ | |
2476 | memcpy(&pdata->config, config, sizeof(pdata->config)); | |
2477 | retval = 0; | |
2478 | } | |
2479 | ||
2480 | if (retval) { | |
2481 | SMSC_WARN(pdata, probe, "Error smsc911x config not found"); | |
c7e963f6 | 2482 | goto out_disable_resources; |
79f88ee9 SG |
2483 | } |
2484 | ||
c326de88 MP |
2485 | /* assume standard, non-shifted, access to HW registers */ |
2486 | pdata->ops = &standard_smsc911x_ops; | |
2487 | /* apply the right access if shifting is needed */ | |
79f88ee9 | 2488 | if (pdata->config.shift) |
c326de88 MP |
2489 | pdata->ops = &shifted_smsc911x_ops; |
2490 | ||
3a611e26 GU |
2491 | pm_runtime_enable(&pdev->dev); |
2492 | pm_runtime_get_sync(&pdev->dev); | |
2493 | ||
fd9abb3d SG |
2494 | retval = smsc911x_init(dev); |
2495 | if (retval < 0) | |
c7e963f6 | 2496 | goto out_disable_resources; |
fd9abb3d SG |
2497 | |
2498 | /* configure irq polarity and type before connecting isr */ | |
2107fb8b | 2499 | if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH) |
fd9abb3d SG |
2500 | intcfg |= INT_CFG_IRQ_POL_; |
2501 | ||
2107fb8b | 2502 | if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL) |
fd9abb3d SG |
2503 | intcfg |= INT_CFG_IRQ_TYPE_; |
2504 | ||
2505 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
2506 | ||
2507 | /* Ensure interrupts are globally disabled before connecting ISR */ | |
8e27628e | 2508 | smsc911x_disable_irq_chip(dev); |
fd9abb3d | 2509 | |
61307ed8 | 2510 | retval = request_irq(dev->irq, smsc911x_irqhandler, |
e81259b4 | 2511 | irq_flags | IRQF_SHARED, dev->name, dev); |
fd9abb3d | 2512 | if (retval) { |
dffc6b24 JP |
2513 | SMSC_WARN(pdata, probe, |
2514 | "Unable to claim requested irq: %d", dev->irq); | |
163faf31 | 2515 | goto out_disable_resources; |
fd9abb3d SG |
2516 | } |
2517 | ||
31f6f291 BK |
2518 | netif_carrier_off(dev); |
2519 | ||
fd9abb3d SG |
2520 | retval = register_netdev(dev); |
2521 | if (retval) { | |
dffc6b24 | 2522 | SMSC_WARN(pdata, probe, "Error %i registering device", retval); |
c7e963f6 | 2523 | goto out_free_irq; |
fd9abb3d | 2524 | } else { |
dffc6b24 JP |
2525 | SMSC_TRACE(pdata, probe, |
2526 | "Network interface: \"%s\"", dev->name); | |
fd9abb3d SG |
2527 | } |
2528 | ||
fd9abb3d SG |
2529 | retval = smsc911x_mii_init(pdev, dev); |
2530 | if (retval) { | |
dffc6b24 | 2531 | SMSC_WARN(pdata, probe, "Error %i initialising mii", retval); |
fd9abb3d SG |
2532 | goto out_unregister_netdev_5; |
2533 | } | |
2534 | ||
2535 | spin_lock_irq(&pdata->mac_lock); | |
2536 | ||
2537 | /* Check if mac address has been specified when bringing interface up */ | |
2538 | if (is_valid_ether_addr(dev->dev_addr)) { | |
225ddf49 | 2539 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2540 | SMSC_TRACE(pdata, probe, |
2541 | "MAC Address is specified by configuration"); | |
aace4959 | 2542 | } else if (is_valid_ether_addr(pdata->config.mac)) { |
d458cdf7 | 2543 | memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN); |
dffc6b24 JP |
2544 | SMSC_TRACE(pdata, probe, |
2545 | "MAC Address specified by platform data"); | |
fd9abb3d SG |
2546 | } else { |
2547 | /* Try reading mac address from device. if EEPROM is present | |
2548 | * it will already have been set */ | |
62747cd2 | 2549 | smsc_get_mac(dev); |
fd9abb3d SG |
2550 | |
2551 | if (is_valid_ether_addr(dev->dev_addr)) { | |
2552 | /* eeprom values are valid so use them */ | |
dffc6b24 JP |
2553 | SMSC_TRACE(pdata, probe, |
2554 | "Mac Address is read from LAN911x EEPROM"); | |
fd9abb3d SG |
2555 | } else { |
2556 | /* eeprom values are invalid, generate random MAC */ | |
7ce5d222 | 2557 | eth_hw_addr_random(dev); |
225ddf49 | 2558 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 | 2559 | SMSC_TRACE(pdata, probe, |
7efd26d0 | 2560 | "MAC Address is set to eth_random_addr"); |
fd9abb3d SG |
2561 | } |
2562 | } | |
2563 | ||
2564 | spin_unlock_irq(&pdata->mac_lock); | |
2565 | ||
dffc6b24 | 2566 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
fd9abb3d SG |
2567 | |
2568 | return 0; | |
2569 | ||
2570 | out_unregister_netdev_5: | |
2571 | unregister_netdev(dev); | |
c7e963f6 | 2572 | out_free_irq: |
fd9abb3d | 2573 | free_irq(dev->irq, dev); |
c7e963f6 | 2574 | out_disable_resources: |
3a611e26 GU |
2575 | pm_runtime_put(&pdev->dev); |
2576 | pm_runtime_disable(&pdev->dev); | |
c7e963f6 | 2577 | (void)smsc911x_disable_resources(pdev); |
2e1d4a06 | 2578 | out_enable_resources_fail: |
c7e963f6 | 2579 | smsc911x_free_resources(pdev); |
2e1d4a06 | 2580 | out_request_resources_fail: |
fd9abb3d | 2581 | iounmap(pdata->ioaddr); |
fd9abb3d SG |
2582 | free_netdev(dev); |
2583 | out_release_io_1: | |
39424539 | 2584 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2585 | out_0: |
2586 | return retval; | |
2587 | } | |
2588 | ||
b6907b0c DM |
2589 | #ifdef CONFIG_PM |
2590 | /* This implementation assumes the devices remains powered on its VDDVARIO | |
2591 | * pins during suspend. */ | |
2592 | ||
6cb87823 DM |
2593 | /* TODO: implement freeze/thaw callbacks for hibernation.*/ |
2594 | ||
2595 | static int smsc911x_suspend(struct device *dev) | |
b6907b0c | 2596 | { |
6cb87823 DM |
2597 | struct net_device *ndev = dev_get_drvdata(dev); |
2598 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2599 | |
2600 | /* enable wake on LAN, energy detection and the external PME | |
2601 | * signal. */ | |
2602 | smsc911x_reg_write(pdata, PMT_CTRL, | |
2603 | PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ | | |
2604 | PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_); | |
2605 | ||
2606 | return 0; | |
2607 | } | |
2608 | ||
6cb87823 | 2609 | static int smsc911x_resume(struct device *dev) |
b6907b0c | 2610 | { |
6cb87823 DM |
2611 | struct net_device *ndev = dev_get_drvdata(dev); |
2612 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2613 | unsigned int to = 100; |
2614 | ||
2615 | /* Note 3.11 from the datasheet: | |
2616 | * "When the LAN9220 is in a power saving state, a write of any | |
2617 | * data to the BYTE_TEST register will wake-up the device." | |
2618 | */ | |
2619 | smsc911x_reg_write(pdata, BYTE_TEST, 0); | |
2620 | ||
2621 | /* poll the READY bit in PMT_CTRL. Any other access to the device is | |
2622 | * forbidden while this bit isn't set. Try for 100ms and return -EIO | |
2623 | * if it failed. */ | |
2624 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) | |
2625 | udelay(1000); | |
2626 | ||
2627 | return (to == 0) ? -EIO : 0; | |
2628 | } | |
2629 | ||
47145210 | 2630 | static const struct dev_pm_ops smsc911x_pm_ops = { |
6cb87823 DM |
2631 | .suspend = smsc911x_suspend, |
2632 | .resume = smsc911x_resume, | |
2633 | }; | |
2634 | ||
2635 | #define SMSC911X_PM_OPS (&smsc911x_pm_ops) | |
2636 | ||
b6907b0c | 2637 | #else |
6cb87823 | 2638 | #define SMSC911X_PM_OPS NULL |
b6907b0c DM |
2639 | #endif |
2640 | ||
d62fdf8b | 2641 | #ifdef CONFIG_OF |
79f88ee9 SG |
2642 | static const struct of_device_id smsc911x_dt_ids[] = { |
2643 | { .compatible = "smsc,lan9115", }, | |
2644 | { /* sentinel */ } | |
2645 | }; | |
2646 | MODULE_DEVICE_TABLE(of, smsc911x_dt_ids); | |
d62fdf8b | 2647 | #endif |
79f88ee9 | 2648 | |
0b50dc4f JL |
2649 | static const struct acpi_device_id smsc911x_acpi_match[] = { |
2650 | { "ARMH9118", 0 }, | |
2651 | { } | |
2652 | }; | |
2653 | MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match); | |
2654 | ||
fd9abb3d SG |
2655 | static struct platform_driver smsc911x_driver = { |
2656 | .probe = smsc911x_drv_probe, | |
8489ec1f | 2657 | .remove = smsc911x_drv_remove, |
fd9abb3d | 2658 | .driver = { |
6cb87823 | 2659 | .name = SMSC_CHIPNAME, |
6cb87823 | 2660 | .pm = SMSC911X_PM_OPS, |
d62fdf8b | 2661 | .of_match_table = of_match_ptr(smsc911x_dt_ids), |
0b50dc4f | 2662 | .acpi_match_table = ACPI_PTR(smsc911x_acpi_match), |
fd9abb3d SG |
2663 | }, |
2664 | }; | |
2665 | ||
2666 | /* Entry point for loading the module */ | |
2667 | static int __init smsc911x_init_module(void) | |
2668 | { | |
62747cd2 | 2669 | SMSC_INITIALIZE(); |
fd9abb3d SG |
2670 | return platform_driver_register(&smsc911x_driver); |
2671 | } | |
2672 | ||
2673 | /* entry point for unloading the module */ | |
2674 | static void __exit smsc911x_cleanup_module(void) | |
2675 | { | |
2676 | platform_driver_unregister(&smsc911x_driver); | |
2677 | } | |
2678 | ||
2679 | module_init(smsc911x_init_module); | |
2680 | module_exit(smsc911x_cleanup_module); |