projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ethernet: Remove casts to same type
[deliverable/linux.git] / drivers / net / ethernet / smsc / smsc9420.c
CommitLineData
2cb37728
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
a6b7a407 22#include <linux/interrupt.h>
2cb37728
SG		 23#include <linux/kernel.h>
24#include <linux/netdevice.h>
25#include <linux/phy.h>
26#include <linux/pci.h>
27#include <linux/if_vlan.h>
28#include <linux/dma-mapping.h>
29#include <linux/crc32.h>
5a0e3ad6 30#include <linux/slab.h>
9d9779e7 31#include <linux/module.h>
2cb37728
SG		 32#include <asm/unaligned.h>
33#include "smsc9420.h"
34
35#define DRV_NAME "smsc9420"
36#define PFX DRV_NAME ": "
37#define DRV_MDIONAME "smsc9420-mdio"
38#define DRV_DESCRIPTION "SMSC LAN9420 driver"
39#define DRV_VERSION "1.01"
40
41MODULE_LICENSE("GPL");
42MODULE_VERSION(DRV_VERSION);
43
44struct smsc9420_dma_desc {
45 u32 status;
46 u32 length;
47 u32 buffer1;
48 u32 buffer2;
49};
50
51struct smsc9420_ring_info {
52 struct sk_buff *skb;
53 dma_addr_t mapping;
54};
55
56struct smsc9420_pdata {
b5a80837 57 void __iomem *ioaddr;
2cb37728
SG		 58 struct pci_dev *pdev;
59 struct net_device *dev;
60
61 struct smsc9420_dma_desc *rx_ring;
62 struct smsc9420_dma_desc *tx_ring;
63 struct smsc9420_ring_info *tx_buffers;
64 struct smsc9420_ring_info *rx_buffers;
65 dma_addr_t rx_dma_addr;
66 dma_addr_t tx_dma_addr;
67 int tx_ring_head, tx_ring_tail;
68 int rx_ring_head, rx_ring_tail;
69
70 spinlock_t int_lock;
71 spinlock_t phy_lock;
72
73 struct napi_struct napi;
74
75 bool software_irq_signal;
76 bool rx_csum;
77 u32 msg_enable;
78
79 struct phy_device *phy_dev;
80 struct mii_bus *mii_bus;
81 int phy_irq[PHY_MAX_ADDR];
82 int last_duplex;
83 int last_carrier;
84};
85
a3aa1884 86static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
2cb37728
SG		 87 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
88 { 0, }
89};
90
91MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
92
93#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
94
95static uint smsc_debug;
96static uint debug = -1;
97module_param(debug, uint, 0);
98MODULE_PARM_DESC(debug, "debug level");
99
100#define smsc_dbg(TYPE, f, a...) \
101do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_DEBUG PFX f "\n", ## a); \
103} while (0)
104
105#define smsc_info(TYPE, f, a...) \
106do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_INFO PFX f "\n", ## a); \
108} while (0)
109
110#define smsc_warn(TYPE, f, a...) \
111do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
112 printk(KERN_WARNING PFX f "\n", ## a); \
113} while (0)
114
115static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
116{
b5a80837 117 return ioread32(pd->ioaddr + offset);
2cb37728
SG		 118}
119
120static inline void
121smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
122{
b5a80837 123 iowrite32(value, pd->ioaddr + offset);
2cb37728
SG		 124}
125
126static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
127{
128 /* to ensure PCI write completion, we must perform a PCI read */
129 smsc9420_reg_read(pd, ID_REV);
130}
131
132static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
133{
134 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
135 unsigned long flags;
136 u32 addr;
137 int i, reg = -EIO;
138
139 spin_lock_irqsave(&pd->phy_lock, flags);
140
141 /* confirm MII not busy */
142 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
143 smsc_warn(DRV, "MII is busy???");
144 goto out;
145 }
146
147 /* set the address, index & direction (read from PHY) */
148 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
149 MII_ACCESS_MII_READ_;
150 smsc9420_reg_write(pd, MII_ACCESS, addr);
151
152 /* wait for read to complete with 50us timeout */
153 for (i = 0; i < 5; i++) {
154 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
155 MII_ACCESS_MII_BUSY_)) {
156 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
157 goto out;
158 }
159 udelay(10);
160 }
161
162 smsc_warn(DRV, "MII busy timeout!");
163
164out:
165 spin_unlock_irqrestore(&pd->phy_lock, flags);
166 return reg;
167}
168
169static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
170 u16 val)
171{
172 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
173 unsigned long flags;
174 u32 addr;
175 int i, reg = -EIO;
176
177 spin_lock_irqsave(&pd->phy_lock, flags);
178
179 /* confirm MII not busy */
180 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
181 smsc_warn(DRV, "MII is busy???");
182 goto out;
183 }
184
185 /* put the data to write in the MAC */
186 smsc9420_reg_write(pd, MII_DATA, (u32)val);
187
188 /* set the address, index & direction (write to PHY) */
189 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
190 MII_ACCESS_MII_WRITE_;
191 smsc9420_reg_write(pd, MII_ACCESS, addr);
192
193 /* wait for write to complete with 50us timeout */
194 for (i = 0; i < 5; i++) {
195 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
196 MII_ACCESS_MII_BUSY_)) {
197 reg = 0;
198 goto out;
199 }
200 udelay(10);
201 }
202
203 smsc_warn(DRV, "MII busy timeout!");
204
205out:
206 spin_unlock_irqrestore(&pd->phy_lock, flags);
207 return reg;
208}
209
210/* Returns hash bit number for given MAC address
211 * Example:
212 * 01 00 5E 00 00 01 -> returns bit number 31 */
213static u32 smsc9420_hash(u8 addr[ETH_ALEN])
214{
215 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
216}
217
218static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
219{
220 int timeout = 100000;
221
222 BUG_ON(!pd);
223
224 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
225 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
226 return -EIO;
227 }
228
229 smsc9420_reg_write(pd, E2P_CMD,
230 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
231
232 do {
233 udelay(10);
234 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
235 return 0;
236 } while (timeout--);
237
238 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
239 return -EIO;
240}
241
242/* Standard ioctls for mii-tool */
243static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
244{
245 struct smsc9420_pdata *pd = netdev_priv(dev);
246
247 if (!netif_running(dev) || !pd->phy_dev)
248 return -EINVAL;
249
28b04113 250 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
2cb37728
SG		 251}
252
253static int smsc9420_ethtool_get_settings(struct net_device *dev,
254 struct ethtool_cmd *cmd)
255{
256 struct smsc9420_pdata *pd = netdev_priv(dev);
257
6c53b1b1
SG		 258 if (!pd->phy_dev)
259 return -ENODEV;
260
2cb37728
SG		 261 cmd->maxtxpkt = 1;
262 cmd->maxrxpkt = 1;
263 return phy_ethtool_gset(pd->phy_dev, cmd);
264}
265
266static int smsc9420_ethtool_set_settings(struct net_device *dev,
267 struct ethtool_cmd *cmd)
268{
269 struct smsc9420_pdata *pd = netdev_priv(dev);
270
6c53b1b1
SG		 271 if (!pd->phy_dev)
272 return -ENODEV;
273
2cb37728
SG		 274 return phy_ethtool_sset(pd->phy_dev, cmd);
275}
276
277static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
278 struct ethtool_drvinfo *drvinfo)
279{
280 struct smsc9420_pdata *pd = netdev_priv(netdev);
281
68aad78c
RJ		 282 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
283 strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
284 sizeof(drvinfo->bus_info));
285 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
2cb37728
SG		 286}
287
288static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
289{
290 struct smsc9420_pdata *pd = netdev_priv(netdev);
291 return pd->msg_enable;
292}
293
294static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
295{
296 struct smsc9420_pdata *pd = netdev_priv(netdev);
297 pd->msg_enable = data;
298}
299
300static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
301{
302 struct smsc9420_pdata *pd = netdev_priv(netdev);
6c53b1b1
SG		 303
304 if (!pd->phy_dev)
305 return -ENODEV;
306
2cb37728
SG		 307 return phy_start_aneg(pd->phy_dev);
308}
309
a7276db6
SG		 310static int smsc9420_ethtool_getregslen(struct net_device *dev)
311{
312 /* all smsc9420 registers plus all phy registers */
313 return 0x100 + (32 * sizeof(u32));
314}
315
316static void
317smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
318 void *buf)
319{
320 struct smsc9420_pdata *pd = netdev_priv(dev);
321 struct phy_device *phy_dev = pd->phy_dev;
322 unsigned int i, j = 0;
323 u32 *data = buf;
324
325 regs->version = smsc9420_reg_read(pd, ID_REV);
326 for (i = 0; i < 0x100; i += (sizeof(u32)))
327 data[j++] = smsc9420_reg_read(pd, i);
328
6c53b1b1
SG		 329 // cannot read phy registers if the net device is down
330 if (!phy_dev)
331 return;
332
a7276db6
SG		 333 for (i = 0; i <= 31; i++)
334 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
335}
336
012b215c
SG		 337static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
338{
339 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
340 temp &= ~GPIO_CFG_EEPR_EN_;
341 smsc9420_reg_write(pd, GPIO_CFG, temp);
342 msleep(1);
343}
344
345static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
346{
347 int timeout = 100;
348 u32 e2cmd;
349
350 smsc_dbg(HW, "op 0x%08x", op);
351 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
352 smsc_warn(HW, "Busy at start");
353 return -EBUSY;
354 }
355
356 e2cmd = op | E2P_CMD_EPC_BUSY_;
357 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
358
359 do {
360 msleep(1);
361 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
9df8f4e3 362 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
012b215c
SG		 363
364 if (!timeout) {
365 smsc_info(HW, "TIMED OUT");
366 return -EAGAIN;
367 }
368
369 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
25985edc 370 smsc_info(HW, "Error occurred during eeprom operation");
012b215c
SG		 371 return -EINVAL;
372 }
373
374 return 0;
375}
376
377static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
378 u8 address, u8 *data)
379{
380 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
381 int ret;
382
383 smsc_dbg(HW, "address 0x%x", address);
384 ret = smsc9420_eeprom_send_cmd(pd, op);
385
386 if (!ret)
387 data[address] = smsc9420_reg_read(pd, E2P_DATA);
388
389 return ret;
390}
391
392static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
393 u8 address, u8 data)
394{
395 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
396 int ret;
397
398 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
399 ret = smsc9420_eeprom_send_cmd(pd, op);
400
401 if (!ret) {
402 op = E2P_CMD_EPC_CMD_WRITE_ | address;
403 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
404 ret = smsc9420_eeprom_send_cmd(pd, op);
405 }
406
407 return ret;
408}
409
410static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
411{
412 return SMSC9420_EEPROM_SIZE;
413}
414
415static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
416 struct ethtool_eeprom *eeprom, u8 *data)
417{
418 struct smsc9420_pdata *pd = netdev_priv(dev);
419 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
420 int len, i;
421
422 smsc9420_eeprom_enable_access(pd);
423
424 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
425 for (i = 0; i < len; i++) {
426 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
427 if (ret < 0) {
428 eeprom->len = 0;
429 return ret;
430 }
431 }
432
433 memcpy(data, &eeprom_data[eeprom->offset], len);
196b7e1b 434 eeprom->magic = SMSC9420_EEPROM_MAGIC;
012b215c
SG		 435 eeprom->len = len;
436 return 0;
437}
438
439static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
440 struct ethtool_eeprom *eeprom, u8 *data)
441{
442 struct smsc9420_pdata *pd = netdev_priv(dev);
443 int ret;
444
196b7e1b
SG		 445 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
446 return -EINVAL;
447
012b215c
SG		 448 smsc9420_eeprom_enable_access(pd);
449 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
450 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
451 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
452
453 /* Single byte write, according to man page */
454 eeprom->len = 1;
455
456 return ret;
457}
458
2cb37728
SG		 459static const struct ethtool_ops smsc9420_ethtool_ops = {
460 .get_settings = smsc9420_ethtool_get_settings,
461 .set_settings = smsc9420_ethtool_set_settings,
462 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
463 .get_msglevel = smsc9420_ethtool_get_msglevel,
464 .set_msglevel = smsc9420_ethtool_set_msglevel,
465 .nway_reset = smsc9420_ethtool_nway_reset,
466 .get_link = ethtool_op_get_link,
012b215c
SG		 467 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
468 .get_eeprom = smsc9420_ethtool_get_eeprom,
469 .set_eeprom = smsc9420_ethtool_set_eeprom,
a7276db6
SG		 470 .get_regs_len = smsc9420_ethtool_getregslen,
471 .get_regs = smsc9420_ethtool_getregs,
50c0c110 472 .get_ts_info = ethtool_op_get_ts_info,
2cb37728
SG		 473};
474
475/* Sets the device MAC address to dev_addr */
476static void smsc9420_set_mac_address(struct net_device *dev)
477{
478 struct smsc9420_pdata *pd = netdev_priv(dev);
479 u8 *dev_addr = dev->dev_addr;
480 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
481 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
482 (dev_addr[1] << 8) | dev_addr[0];
483
484 smsc9420_reg_write(pd, ADDRH, mac_high16);
485 smsc9420_reg_write(pd, ADDRL, mac_low32);
486}
487
488static void smsc9420_check_mac_address(struct net_device *dev)
489{
490 struct smsc9420_pdata *pd = netdev_priv(dev);
491
492 /* Check if mac address has been specified when bringing interface up */
493 if (is_valid_ether_addr(dev->dev_addr)) {
494 smsc9420_set_mac_address(dev);
495 smsc_dbg(PROBE, "MAC Address is specified by configuration");
496 } else {
497 /* Try reading mac address from device. if EEPROM is present
498 * it will already have been set */
499 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
500 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
501 dev->dev_addr[0] = (u8)(mac_low32);
502 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
503 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
504 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
505 dev->dev_addr[4] = (u8)(mac_high16);
506 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
507
508 if (is_valid_ether_addr(dev->dev_addr)) {
509 /* eeprom values are valid so use them */
510 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
511 } else {
512 /* eeprom values are invalid, generate random MAC */
f2cedb63 513 eth_hw_addr_random(dev);
2cb37728 514 smsc9420_set_mac_address(dev);
f2cedb63 515 smsc_dbg(PROBE, "MAC Address is set to random");
2cb37728
SG		 516 }
517 }
518}
519
520static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
521{
522 u32 dmac_control, mac_cr, dma_intr_ena;
46578a69 523 int timeout = 1000;
2cb37728
SG		 524
525 /* disable TX DMAC */
526 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
527 dmac_control &= (~DMAC_CONTROL_ST_);
528 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
529
530 /* Wait max 10ms for transmit process to stop */
46578a69 531 while (--timeout) {
2cb37728
SG		 532 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
533 break;
534 udelay(10);
535 }
536
46578a69 537 if (!timeout)
2cb37728
SG		 538 smsc_warn(IFDOWN, "TX DMAC failed to stop");
539
540 /* ACK Tx DMAC stop bit */
541 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
542
543 /* mask TX DMAC interrupts */
544 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
545 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
546 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
547 smsc9420_pci_flush_write(pd);
548
549 /* stop MAC TX */
550 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
551 smsc9420_reg_write(pd, MAC_CR, mac_cr);
552 smsc9420_pci_flush_write(pd);
553}
554
555static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
556{
557 int i;
558
559 BUG_ON(!pd->tx_ring);
560
561 if (!pd->tx_buffers)
562 return;
563
564 for (i = 0; i < TX_RING_SIZE; i++) {
565 struct sk_buff *skb = pd->tx_buffers[i].skb;
566
567 if (skb) {
568 BUG_ON(!pd->tx_buffers[i].mapping);
569 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
570 skb->len, PCI_DMA_TODEVICE);
571 dev_kfree_skb_any(skb);
572 }
573
574 pd->tx_ring[i].status = 0;
575 pd->tx_ring[i].length = 0;
576 pd->tx_ring[i].buffer1 = 0;
577 pd->tx_ring[i].buffer2 = 0;
578 }
579 wmb();
580
581 kfree(pd->tx_buffers);
582 pd->tx_buffers = NULL;
583
584 pd->tx_ring_head = 0;
585 pd->tx_ring_tail = 0;
586}
587
588static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
589{
590 int i;
591
592 BUG_ON(!pd->rx_ring);
593
594 if (!pd->rx_buffers)
595 return;
596
597 for (i = 0; i < RX_RING_SIZE; i++) {
598 if (pd->rx_buffers[i].skb)
599 dev_kfree_skb_any(pd->rx_buffers[i].skb);
600
601 if (pd->rx_buffers[i].mapping)
602 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
603 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
604
605 pd->rx_ring[i].status = 0;
606 pd->rx_ring[i].length = 0;
607 pd->rx_ring[i].buffer1 = 0;
608 pd->rx_ring[i].buffer2 = 0;
609 }
610 wmb();
611
612 kfree(pd->rx_buffers);
613 pd->rx_buffers = NULL;
614
615 pd->rx_ring_head = 0;
616 pd->rx_ring_tail = 0;
617}
618
619static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
620{
46578a69 621 int timeout = 1000;
2cb37728
SG		 622 u32 mac_cr, dmac_control, dma_intr_ena;
623
624 /* mask RX DMAC interrupts */
625 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
626 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
627 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
628 smsc9420_pci_flush_write(pd);
629
630 /* stop RX MAC prior to stoping DMA */
631 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
632 smsc9420_reg_write(pd, MAC_CR, mac_cr);
633 smsc9420_pci_flush_write(pd);
634
635 /* stop RX DMAC */
636 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
637 dmac_control &= (~DMAC_CONTROL_SR_);
638 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
639 smsc9420_pci_flush_write(pd);
640
641 /* wait up to 10ms for receive to stop */
46578a69 642 while (--timeout) {
2cb37728
SG		 643 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
644 break;
645 udelay(10);
646 }
647
46578a69 648 if (!timeout)
2cb37728
SG		 649 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
650
651 /* ACK the Rx DMAC stop bit */
652 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
653}
654
655static irqreturn_t smsc9420_isr(int irq, void *dev_id)
656{
657 struct smsc9420_pdata *pd = dev_id;
658 u32 int_cfg, int_sts, int_ctl;
659 irqreturn_t ret = IRQ_NONE;
660 ulong flags;
661
662 BUG_ON(!pd);
b5a80837 663 BUG_ON(!pd->ioaddr);
2cb37728
SG		 664
665 int_cfg = smsc9420_reg_read(pd, INT_CFG);
666
667 /* check if it's our interrupt */
668 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
669 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
670 return IRQ_NONE;
671
672 int_sts = smsc9420_reg_read(pd, INT_STAT);
673
674 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
675 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
676 u32 ints_to_clear = 0;
677
678 if (status & DMAC_STS_TX_) {
679 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
680 netif_wake_queue(pd->dev);
681 }
682
683 if (status & DMAC_STS_RX_) {
684 /* mask RX DMAC interrupts */
685 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
686 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
687 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
688 smsc9420_pci_flush_write(pd);
689
690 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
288379f0 691 napi_schedule(&pd->napi);
2cb37728
SG		 692 }
693
694 if (ints_to_clear)
695 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
696
697 ret = IRQ_HANDLED;
698 }
699
700 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
701 /* mask software interrupt */
702 spin_lock_irqsave(&pd->int_lock, flags);
703 int_ctl = smsc9420_reg_read(pd, INT_CTL);
704 int_ctl &= (~INT_CTL_SW_INT_EN_);
705 smsc9420_reg_write(pd, INT_CTL, int_ctl);
706 spin_unlock_irqrestore(&pd->int_lock, flags);
707
708 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
709 pd->software_irq_signal = true;
710 smp_wmb();
711
712 ret = IRQ_HANDLED;
713 }
714
715 /* to ensure PCI write completion, we must perform a PCI read */
716 smsc9420_pci_flush_write(pd);
717
718 return ret;
719}
720
e312674f
SG		 721#ifdef CONFIG_NET_POLL_CONTROLLER
722static void smsc9420_poll_controller(struct net_device *dev)
723{
b5a80837
FR		 724 struct smsc9420_pdata *pd = netdev_priv(dev);
725 const int irq = pd->pdev->irq;
726
727 disable_irq(irq);
e312674f 728 smsc9420_isr(0, dev);
b5a80837 729 enable_irq(irq);
e312674f
SG		 730}
731#endif /* CONFIG_NET_POLL_CONTROLLER */
732
2cb37728
SG		 733static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
734{
735 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
736 smsc9420_reg_read(pd, BUS_MODE);
737 udelay(2);
738 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
739 smsc_warn(DRV, "Software reset not cleared");
740}
741
742static int smsc9420_stop(struct net_device *dev)
743{
744 struct smsc9420_pdata *pd = netdev_priv(dev);
745 u32 int_cfg;
746 ulong flags;
747
748 BUG_ON(!pd);
749 BUG_ON(!pd->phy_dev);
750
751 /* disable master interrupt */
752 spin_lock_irqsave(&pd->int_lock, flags);
753 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
754 smsc9420_reg_write(pd, INT_CFG, int_cfg);
755 spin_unlock_irqrestore(&pd->int_lock, flags);
756
757 netif_tx_disable(dev);
758 napi_disable(&pd->napi);
759
760 smsc9420_stop_tx(pd);
761 smsc9420_free_tx_ring(pd);
762
763 smsc9420_stop_rx(pd);
764 smsc9420_free_rx_ring(pd);
765
b5a80837 766 free_irq(pd->pdev->irq, pd);
2cb37728
SG		 767
768 smsc9420_dmac_soft_reset(pd);
769
770 phy_stop(pd->phy_dev);
771
772 phy_disconnect(pd->phy_dev);
773 pd->phy_dev = NULL;
774 mdiobus_unregister(pd->mii_bus);
775 mdiobus_free(pd->mii_bus);
776
777 return 0;
778}
779
780static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
781{
782 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
783 dev->stats.rx_errors++;
784 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
785 dev->stats.rx_over_errors++;
786 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
787 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
788 dev->stats.rx_frame_errors++;
789 else if (desc_status & RDES0_CRC_ERROR_)
790 dev->stats.rx_crc_errors++;
791 }
792
793 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
794 dev->stats.rx_length_errors++;
795
796 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
797 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
798 dev->stats.rx_length_errors++;
799
800 if (desc_status & RDES0_MULTICAST_FRAME_)
801 dev->stats.multicast++;
802}
803
804static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
805 const u32 status)
806{
807 struct net_device *dev = pd->dev;
808 struct sk_buff *skb;
809 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
810 >> RDES0_FRAME_LENGTH_SHFT_;
811
812 /* remove crc from packet lendth */
813 packet_length -= 4;
814
815 if (pd->rx_csum)
816 packet_length -= 2;
817
818 dev->stats.rx_packets++;
819 dev->stats.rx_bytes += packet_length;
820
821 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
822 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
823 pd->rx_buffers[index].mapping = 0;
824
825 skb = pd->rx_buffers[index].skb;
826 pd->rx_buffers[index].skb = NULL;
827
828 if (pd->rx_csum) {
829 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
830 NET_IP_ALIGN + packet_length + 4);
cd7a3b75 831 put_unaligned_le16(hw_csum, &skb->csum);
2cb37728
SG		 832 skb->ip_summed = CHECKSUM_COMPLETE;
833 }
834
835 skb_reserve(skb, NET_IP_ALIGN);
836 skb_put(skb, packet_length);
837
838 skb->protocol = eth_type_trans(skb, dev);
839
840 netif_receive_skb(skb);
2cb37728
SG		 841}
842
843static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
844{
845 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
846 dma_addr_t mapping;
847
848 BUG_ON(pd->rx_buffers[index].skb);
849 BUG_ON(pd->rx_buffers[index].mapping);
850
851 if (unlikely(!skb)) {
852 smsc_warn(RX_ERR, "Failed to allocate new skb!");
853 return -ENOMEM;
854 }
855
2cb37728
SG		 856 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
857 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
858 if (pci_dma_mapping_error(pd->pdev, mapping)) {
859 dev_kfree_skb_any(skb);
860 smsc_warn(RX_ERR, "pci_map_single failed!");
861 return -ENOMEM;
862 }
863
864 pd->rx_buffers[index].skb = skb;
865 pd->rx_buffers[index].mapping = mapping;
866 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
867 pd->rx_ring[index].status = RDES0_OWN_;
868 wmb();
869
870 return 0;
871}
872
873static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
874{
875 while (pd->rx_ring_tail != pd->rx_ring_head) {
876 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
877 break;
878
879 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
880 }
881}
882
883static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
884{
885 struct smsc9420_pdata *pd =
886 container_of(napi, struct smsc9420_pdata, napi);
887 struct net_device *dev = pd->dev;
888 u32 drop_frame_cnt, dma_intr_ena, status;
889 int work_done;
890
891 for (work_done = 0; work_done < budget; work_done++) {
892 rmb();
893 status = pd->rx_ring[pd->rx_ring_head].status;
894
895 /* stop if DMAC owns this dma descriptor */
896 if (status & RDES0_OWN_)
897 break;
898
899 smsc9420_rx_count_stats(dev, status);
900 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
901 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
902 smsc9420_alloc_new_rx_buffers(pd);
903 }
904
905 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
906 dev->stats.rx_dropped +=
907 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
908
909 /* Kick RXDMA */
910 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
911 smsc9420_pci_flush_write(pd);
912
913 if (work_done < budget) {
288379f0 914 napi_complete(&pd->napi);
2cb37728
SG		 915
916 /* re-enable RX DMA interrupts */
917 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
918 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
919 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
920 smsc9420_pci_flush_write(pd);
921 }
922 return work_done;
923}
924
925static void
926smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
927{
928 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
929 dev->stats.tx_errors++;
930 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
931 TDES0_EXCESSIVE_COLLISIONS_))
932 dev->stats.tx_aborted_errors++;
933
934 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
935 dev->stats.tx_carrier_errors++;
936 } else {
937 dev->stats.tx_packets++;
938 dev->stats.tx_bytes += (length & 0x7FF);
939 }
940
941 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
942 dev->stats.collisions += 16;
943 } else {
944 dev->stats.collisions +=
945 (status & TDES0_COLLISION_COUNT_MASK_) >>
946 TDES0_COLLISION_COUNT_SHFT_;
947 }
948
949 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
950 dev->stats.tx_heartbeat_errors++;
951}
952
953/* Check for completed dma transfers, update stats and free skbs */
954static void smsc9420_complete_tx(struct net_device *dev)
955{
956 struct smsc9420_pdata *pd = netdev_priv(dev);
957
958 while (pd->tx_ring_tail != pd->tx_ring_head) {
959 int index = pd->tx_ring_tail;
960 u32 status, length;
961
962 rmb();
963 status = pd->tx_ring[index].status;
964 length = pd->tx_ring[index].length;
965
966 /* Check if DMA still owns this descriptor */
967 if (unlikely(TDES0_OWN_ & status))
968 break;
969
970 smsc9420_tx_update_stats(dev, status, length);
971
972 BUG_ON(!pd->tx_buffers[index].skb);
973 BUG_ON(!pd->tx_buffers[index].mapping);
974
975 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
976 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
977 pd->tx_buffers[index].mapping = 0;
978
979 dev_kfree_skb_any(pd->tx_buffers[index].skb);
980 pd->tx_buffers[index].skb = NULL;
981
982 pd->tx_ring[index].buffer1 = 0;
983 wmb();
984
985 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
986 }
987}
988
61357325
SH		 989static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
990 struct net_device *dev)
2cb37728
SG		 991{
992 struct smsc9420_pdata *pd = netdev_priv(dev);
993 dma_addr_t mapping;
994 int index = pd->tx_ring_head;
995 u32 tmp_desc1;
996 bool about_to_take_last_desc =
997 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
998
999 smsc9420_complete_tx(dev);
1000
1001 rmb();
1002 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
1003 BUG_ON(pd->tx_buffers[index].skb);
1004 BUG_ON(pd->tx_buffers[index].mapping);
1005
1006 mapping = pci_map_single(pd->pdev, skb->data,
1007 skb->len, PCI_DMA_TODEVICE);
1008 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1009 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
1010 return NETDEV_TX_BUSY;
1011 }
1012
1013 pd->tx_buffers[index].skb = skb;
1014 pd->tx_buffers[index].mapping = mapping;
1015
1016 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1017 if (unlikely(about_to_take_last_desc)) {
1018 tmp_desc1 |= TDES1_IC_;
1019 netif_stop_queue(pd->dev);
1020 }
1021
1022 /* check if we are at the last descriptor and need to set EOR */
1023 if (unlikely(index == (TX_RING_SIZE - 1)))
1024 tmp_desc1 |= TDES1_TER_;
1025
1026 pd->tx_ring[index].buffer1 = mapping;
1027 pd->tx_ring[index].length = tmp_desc1;
1028 wmb();
1029
1030 /* increment head */
1031 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1032
1033 /* assign ownership to DMAC */
1034 pd->tx_ring[index].status = TDES0_OWN_;
1035 wmb();
1036
62412072
RC		 1037 skb_tx_timestamp(skb);
1038
2cb37728
SG		 1039 /* kick the DMA */
1040 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1041 smsc9420_pci_flush_write(pd);
1042
2cb37728
SG		 1043 return NETDEV_TX_OK;
1044}
1045
1046static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1047{
1048 struct smsc9420_pdata *pd = netdev_priv(dev);
1049 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1050 dev->stats.rx_dropped +=
1051 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1052 return &dev->stats;
1053}
1054
1055static void smsc9420_set_multicast_list(struct net_device *dev)
1056{
1057 struct smsc9420_pdata *pd = netdev_priv(dev);
1058 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1059
1060 if (dev->flags & IFF_PROMISC) {
1061 smsc_dbg(HW, "Promiscuous Mode Enabled");
1062 mac_cr |= MAC_CR_PRMS_;
1063 mac_cr &= (~MAC_CR_MCPAS_);
1064 mac_cr &= (~MAC_CR_HPFILT_);
1065 } else if (dev->flags & IFF_ALLMULTI) {
1066 smsc_dbg(HW, "Receive all Multicast Enabled");
1067 mac_cr &= (~MAC_CR_PRMS_);
1068 mac_cr |= MAC_CR_MCPAS_;
1069 mac_cr &= (~MAC_CR_HPFILT_);
4cd24eaf 1070 } else if (!netdev_mc_empty(dev)) {
22bedad3 1071 struct netdev_hw_addr *ha;
2cb37728
SG		 1072 u32 hash_lo = 0, hash_hi = 0;
1073
1074 smsc_dbg(HW, "Multicast filter enabled");
22bedad3
JP		 1075 netdev_for_each_mc_addr(ha, dev) {
1076 u32 bit_num = smsc9420_hash(ha->addr);
2cb37728
SG		 1077 u32 mask = 1 << (bit_num & 0x1F);
1078
1079 if (bit_num & 0x20)
1080 hash_hi |= mask;
1081 else
1082 hash_lo |= mask;
1083
2cb37728
SG		 1084 }
1085 smsc9420_reg_write(pd, HASHH, hash_hi);
1086 smsc9420_reg_write(pd, HASHL, hash_lo);
1087
1088 mac_cr &= (~MAC_CR_PRMS_);
1089 mac_cr &= (~MAC_CR_MCPAS_);
1090 mac_cr |= MAC_CR_HPFILT_;
1091 } else {
1092 smsc_dbg(HW, "Receive own packets only.");
1093 smsc9420_reg_write(pd, HASHH, 0);
1094 smsc9420_reg_write(pd, HASHL, 0);
1095
1096 mac_cr &= (~MAC_CR_PRMS_);
1097 mac_cr &= (~MAC_CR_MCPAS_);
1098 mac_cr &= (~MAC_CR_HPFILT_);
1099 }
1100
1101 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1102 smsc9420_pci_flush_write(pd);
1103}
1104
2cb37728
SG		 1105static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1106{
1107 struct phy_device *phy_dev = pd->phy_dev;
1108 u32 flow;
1109
1110 if (phy_dev->duplex == DUPLEX_FULL) {
1111 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1112 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 1113 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
2cb37728
SG		 1114
1115 if (cap & FLOW_CTRL_RX)
1116 flow = 0xFFFF0002;
1117 else
1118 flow = 0;
1119
1120 smsc_info(LINK, "rx pause %s, tx pause %s",
1121 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1122 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1123 } else {
1124 smsc_info(LINK, "half duplex");
1125 flow = 0;
1126 }
1127
1128 smsc9420_reg_write(pd, FLOW, flow);
1129}
1130
1131/* Update link mode if anything has changed. Called periodically when the
1132 * PHY is in polling mode, even if nothing has changed. */
1133static void smsc9420_phy_adjust_link(struct net_device *dev)
1134{
1135 struct smsc9420_pdata *pd = netdev_priv(dev);
1136 struct phy_device *phy_dev = pd->phy_dev;
1137 int carrier;
1138
1139 if (phy_dev->duplex != pd->last_duplex) {
1140 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1141 if (phy_dev->duplex) {
1142 smsc_dbg(LINK, "full duplex mode");
1143 mac_cr |= MAC_CR_FDPX_;
1144 } else {
1145 smsc_dbg(LINK, "half duplex mode");
1146 mac_cr &= ~MAC_CR_FDPX_;
1147 }
1148 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1149
1150 smsc9420_phy_update_flowcontrol(pd);
1151 pd->last_duplex = phy_dev->duplex;
1152 }
1153
1154 carrier = netif_carrier_ok(dev);
1155 if (carrier != pd->last_carrier) {
1156 if (carrier)
1157 smsc_dbg(LINK, "carrier OK");
1158 else
1159 smsc_dbg(LINK, "no carrier");
1160 pd->last_carrier = carrier;
1161 }
1162}
1163
1164static int smsc9420_mii_probe(struct net_device *dev)
1165{
1166 struct smsc9420_pdata *pd = netdev_priv(dev);
1167 struct phy_device *phydev = NULL;
1168
1169 BUG_ON(pd->phy_dev);
1170
1171 /* Device only supports internal PHY at address 1 */
1172 if (!pd->mii_bus->phy_map[1]) {
1173 pr_err("%s: no PHY found at address 1\n", dev->name);
1174 return -ENODEV;
1175 }
1176
1177 phydev = pd->mii_bus->phy_map[1];
1178 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1179 phydev->phy_id);
1180
db1d7bf7 1181 phydev = phy_connect(dev, dev_name(&phydev->dev),
a974a679 1182 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2cb37728
SG		 1183
1184 if (IS_ERR(phydev)) {
1185 pr_err("%s: Could not attach to PHY\n", dev->name);
1186 return PTR_ERR(phydev);
1187 }
1188
1189 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7 1190 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2cb37728
SG		 1191
1192 /* mask with MAC supported features */
1193 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1194 SUPPORTED_Asym_Pause);
1195 phydev->advertising = phydev->supported;
1196
1197 pd->phy_dev = phydev;
1198 pd->last_duplex = -1;
1199 pd->last_carrier = -1;
1200
1201 return 0;
1202}
1203
1204static int smsc9420_mii_init(struct net_device *dev)
1205{
1206 struct smsc9420_pdata *pd = netdev_priv(dev);
1207 int err = -ENXIO, i;
1208
1209 pd->mii_bus = mdiobus_alloc();
1210 if (!pd->mii_bus) {
1211 err = -ENOMEM;
1212 goto err_out_1;
1213 }
1214 pd->mii_bus->name = DRV_MDIONAME;
1215 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1216 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1217 pd->mii_bus->priv = pd;
1218 pd->mii_bus->read = smsc9420_mii_read;
1219 pd->mii_bus->write = smsc9420_mii_write;
1220 pd->mii_bus->irq = pd->phy_irq;
1221 for (i = 0; i < PHY_MAX_ADDR; ++i)
1222 pd->mii_bus->irq[i] = PHY_POLL;
1223
1224 /* Mask all PHYs except ID 1 (internal) */
1225 pd->mii_bus->phy_mask = ~(1 << 1);
1226
1227 if (mdiobus_register(pd->mii_bus)) {
1228 smsc_warn(PROBE, "Error registering mii bus");
1229 goto err_out_free_bus_2;
1230 }
1231
1232 if (smsc9420_mii_probe(dev) < 0) {
1233 smsc_warn(PROBE, "Error probing mii bus");
1234 goto err_out_unregister_bus_3;
1235 }
1236
1237 return 0;
1238
1239err_out_unregister_bus_3:
1240 mdiobus_unregister(pd->mii_bus);
1241err_out_free_bus_2:
1242 mdiobus_free(pd->mii_bus);
1243err_out_1:
1244 return err;
1245}
1246
1247static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1248{
1249 int i;
1250
1251 BUG_ON(!pd->tx_ring);
1252
1253 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1254 TX_RING_SIZE), GFP_KERNEL);
1255 if (!pd->tx_buffers) {
1256 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1257 return -ENOMEM;
1258 }
1259
1260 /* Initialize the TX Ring */
1261 for (i = 0; i < TX_RING_SIZE; i++) {
1262 pd->tx_buffers[i].skb = NULL;
1263 pd->tx_buffers[i].mapping = 0;
1264 pd->tx_ring[i].status = 0;
1265 pd->tx_ring[i].length = 0;
1266 pd->tx_ring[i].buffer1 = 0;
1267 pd->tx_ring[i].buffer2 = 0;
1268 }
1269 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1270 wmb();
1271
1272 pd->tx_ring_head = 0;
1273 pd->tx_ring_tail = 0;
1274
1275 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1276 smsc9420_pci_flush_write(pd);
1277
1278 return 0;
1279}
1280
1281static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1282{
1283 int i;
1284
1285 BUG_ON(!pd->rx_ring);
1286
1287 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1288 RX_RING_SIZE), GFP_KERNEL);
1289 if (pd->rx_buffers == NULL) {
1290 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1291 goto out;
1292 }
1293
1294 /* initialize the rx ring */
1295 for (i = 0; i < RX_RING_SIZE; i++) {
1296 pd->rx_ring[i].status = 0;
1297 pd->rx_ring[i].length = PKT_BUF_SZ;
1298 pd->rx_ring[i].buffer2 = 0;
1299 pd->rx_buffers[i].skb = NULL;
1300 pd->rx_buffers[i].mapping = 0;
1301 }
1302 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1303
1304 /* now allocate the entire ring of skbs */
1305 for (i = 0; i < RX_RING_SIZE; i++) {
1306 if (smsc9420_alloc_rx_buffer(pd, i)) {
1307 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1308 goto out_free_rx_skbs;
1309 }
1310 }
1311
1312 pd->rx_ring_head = 0;
1313 pd->rx_ring_tail = 0;
1314
1315 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1316 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1317
1318 if (pd->rx_csum) {
1319 /* Enable RX COE */
1320 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1321 smsc9420_reg_write(pd, COE_CR, coe);
1322 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1323 }
1324
1325 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1326 smsc9420_pci_flush_write(pd);
1327
1328 return 0;
1329
1330out_free_rx_skbs:
1331 smsc9420_free_rx_ring(pd);
1332out:
1333 return -ENOMEM;
1334}
1335
1336static int smsc9420_open(struct net_device *dev)
1337{
b5a80837 1338 struct smsc9420_pdata *pd = netdev_priv(dev);
2cb37728 1339 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
b5a80837 1340 const int irq = pd->pdev->irq;
2cb37728
SG		 1341 unsigned long flags;
1342 int result = 0, timeout;
1343
2cb37728
SG		 1344 if (!is_valid_ether_addr(dev->dev_addr)) {
1345 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1346 result = -EADDRNOTAVAIL;
1347 goto out_0;
1348 }
1349
1350 netif_carrier_off(dev);
1351
3ad2f3fb 1352 /* disable, mask and acknowledge all interrupts */
2cb37728
SG		 1353 spin_lock_irqsave(&pd->int_lock, flags);
1354 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1355 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1356 smsc9420_reg_write(pd, INT_CTL, 0);
1357 spin_unlock_irqrestore(&pd->int_lock, flags);
1358 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1359 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1360 smsc9420_pci_flush_write(pd);
1361
b5a80837
FR		 1362 result = request_irq(irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1363 DRV_NAME, pd);
1364 if (result) {
1365 smsc_warn(IFUP, "Unable to use IRQ = %d", irq);
2cb37728
SG		 1366 result = -ENODEV;
1367 goto out_0;
1368 }
1369
1370 smsc9420_dmac_soft_reset(pd);
1371
1372 /* make sure MAC_CR is sane */
1373 smsc9420_reg_write(pd, MAC_CR, 0);
1374
1375 smsc9420_set_mac_address(dev);
1376
1377 /* Configure GPIO pins to drive LEDs */
1378 smsc9420_reg_write(pd, GPIO_CFG,
1379 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1380
1381 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1382
1383#ifdef __BIG_ENDIAN
1384 bus_mode |= BUS_MODE_DBO_;
1385#endif
1386
1387 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1388
1389 smsc9420_pci_flush_write(pd);
1390
1391 /* set bus master bridge arbitration priority for Rx and TX DMA */
1392 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1393
1394 smsc9420_reg_write(pd, DMAC_CONTROL,
1395 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1396
1397 smsc9420_pci_flush_write(pd);
1398
1399 /* test the IRQ connection to the ISR */
b5a80837 1400 smsc_dbg(IFUP, "Testing ISR using IRQ %d", irq);
16095595 1401 pd->software_irq_signal = false;
2cb37728
SG		 1402
1403 spin_lock_irqsave(&pd->int_lock, flags);
1404 /* configure interrupt deassertion timer and enable interrupts */
1405 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1406 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1407 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1408 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1409
1410 /* unmask software interrupt */
1411 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1412 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1413 spin_unlock_irqrestore(&pd->int_lock, flags);
1414 smsc9420_pci_flush_write(pd);
1415
1416 timeout = 1000;
2cb37728
SG		 1417 while (timeout--) {
1418 if (pd->software_irq_signal)
1419 break;
1420 msleep(1);
1421 }
1422
1423 /* disable interrupts */
1424 spin_lock_irqsave(&pd->int_lock, flags);
1425 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1426 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1427 spin_unlock_irqrestore(&pd->int_lock, flags);
1428
1429 if (!pd->software_irq_signal) {
1430 smsc_warn(IFUP, "ISR failed signaling test");
1431 result = -ENODEV;
1432 goto out_free_irq_1;
1433 }
1434
b5a80837 1435 smsc_dbg(IFUP, "ISR passed test using IRQ %d", irq);
2cb37728
SG		 1436
1437 result = smsc9420_alloc_tx_ring(pd);
1438 if (result) {
1439 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1440 result = -ENOMEM;
1441 goto out_free_irq_1;
1442 }
1443
1444 result = smsc9420_alloc_rx_ring(pd);
1445 if (result) {
1446 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1447 result = -ENOMEM;
1448 goto out_free_tx_ring_2;
1449 }
1450
1451 result = smsc9420_mii_init(dev);
1452 if (result) {
1453 smsc_warn(IFUP, "Failed to initialize Phy");
1454 result = -ENODEV;
1455 goto out_free_rx_ring_3;
1456 }
1457
1458 /* Bring the PHY up */
1459 phy_start(pd->phy_dev);
1460
1461 napi_enable(&pd->napi);
1462
1463 /* start tx and rx */
1464 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1465 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1466
1467 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1468 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1469 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1470 smsc9420_pci_flush_write(pd);
1471
1472 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1473 dma_intr_ena |=
1474 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1475 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1476 smsc9420_pci_flush_write(pd);
1477
1478 netif_wake_queue(dev);
1479
1480 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1481
1482 /* enable interrupts */
1483 spin_lock_irqsave(&pd->int_lock, flags);
1484 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1485 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1486 spin_unlock_irqrestore(&pd->int_lock, flags);
1487
1488 return 0;
1489
1490out_free_rx_ring_3:
1491 smsc9420_free_rx_ring(pd);
1492out_free_tx_ring_2:
1493 smsc9420_free_tx_ring(pd);
1494out_free_irq_1:
b5a80837 1495 free_irq(irq, pd);
2cb37728
SG		 1496out_0:
1497 return result;
1498}
1499
1500#ifdef CONFIG_PM
1501
1502static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1503{
1504 struct net_device *dev = pci_get_drvdata(pdev);
1505 struct smsc9420_pdata *pd = netdev_priv(dev);
1506 u32 int_cfg;
1507 ulong flags;
1508
1509 /* disable interrupts */
1510 spin_lock_irqsave(&pd->int_lock, flags);
1511 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1512 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1513 spin_unlock_irqrestore(&pd->int_lock, flags);
1514
1515 if (netif_running(dev)) {
1516 netif_tx_disable(dev);
1517 smsc9420_stop_tx(pd);
1518 smsc9420_free_tx_ring(pd);
1519
1520 napi_disable(&pd->napi);
1521 smsc9420_stop_rx(pd);
1522 smsc9420_free_rx_ring(pd);
1523
b5a80837 1524 free_irq(pd->pdev->irq, pd);
2cb37728
SG		 1525
1526 netif_device_detach(dev);
1527 }
1528
1529 pci_save_state(pdev);
1530 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1531 pci_disable_device(pdev);
1532 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1533
1534 return 0;
1535}
1536
1537static int smsc9420_resume(struct pci_dev *pdev)
1538{
1539 struct net_device *dev = pci_get_drvdata(pdev);
1540 struct smsc9420_pdata *pd = netdev_priv(dev);
1541 int err;
1542
1543 pci_set_power_state(pdev, PCI_D0);
1544 pci_restore_state(pdev);
1545
1546 err = pci_enable_device(pdev);
1547 if (err)
1548 return err;
1549
1550 pci_set_master(pdev);
1551
1552 err = pci_enable_wake(pdev, 0, 0);
1553 if (err)
1554 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1555
1556 if (netif_running(dev)) {
b5a80837 1557 /* FIXME: gross. It looks like ancient PM relic.*/
2cb37728
SG		 1558 err = smsc9420_open(dev);
1559 netif_device_attach(dev);
1560 }
1561 return err;
1562}
1563
1564#endif /* CONFIG_PM */
1565
1566static const struct net_device_ops smsc9420_netdev_ops = {
1567 .ndo_open = smsc9420_open,
1568 .ndo_stop = smsc9420_stop,
1569 .ndo_start_xmit = smsc9420_hard_start_xmit,
1570 .ndo_get_stats = smsc9420_get_stats,
afc4b13d 1571 .ndo_set_rx_mode = smsc9420_set_multicast_list,
2cb37728
SG		 1572 .ndo_do_ioctl = smsc9420_do_ioctl,
1573 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 1574 .ndo_set_mac_address = eth_mac_addr,
e312674f
SG		 1575#ifdef CONFIG_NET_POLL_CONTROLLER
1576 .ndo_poll_controller = smsc9420_poll_controller,
1577#endif /* CONFIG_NET_POLL_CONTROLLER */
2cb37728
SG		 1578};
1579
1580static int __devinit
1581smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1582{
1583 struct net_device *dev;
1584 struct smsc9420_pdata *pd;
1585 void __iomem *virt_addr;
1586 int result = 0;
1587 u32 id_rev;
1588
1589 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1590
1591 /* First do the PCI initialisation */
1592 result = pci_enable_device(pdev);
1593 if (unlikely(result)) {
1594 printk(KERN_ERR "Cannot enable smsc9420\n");
1595 goto out_0;
1596 }
1597
1598 pci_set_master(pdev);
1599
1600 dev = alloc_etherdev(sizeof(*pd));
41de8d4c 1601 if (!dev)
2cb37728 1602 goto out_disable_pci_device_1;
2cb37728
SG		 1603
1604 SET_NETDEV_DEV(dev, &pdev->dev);
1605
1606 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1607 printk(KERN_ERR "Cannot find PCI device base address\n");
1608 goto out_free_netdev_2;
1609 }
1610
1611 if ((pci_request_regions(pdev, DRV_NAME))) {
1612 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1613 goto out_free_netdev_2;
1614 }
1615
284901a9 1616 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2cb37728
SG		 1617 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1618 goto out_free_regions_3;
1619 }
1620
1621 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1622 pci_resource_len(pdev, SMSC_BAR));
1623 if (!virt_addr) {
1624 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1625 goto out_free_regions_3;
1626 }
1627
1628 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1629 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1630
2cb37728
SG		 1631 pd = netdev_priv(dev);
1632
1633 /* pci descriptors are created in the PCI consistent area */
1634 pd->rx_ring = pci_alloc_consistent(pdev,
1635 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1636 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1637 &pd->rx_dma_addr);
1638
1639 if (!pd->rx_ring)
1640 goto out_free_io_4;
1641
1642 /* descriptors are aligned due to the nature of pci_alloc_consistent */
64699336 1643 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
2cb37728
SG		 1644 pd->tx_dma_addr = pd->rx_dma_addr +
1645 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1646
1647 pd->pdev = pdev;
1648 pd->dev = dev;
b5a80837 1649 pd->ioaddr = virt_addr;
2cb37728
SG		 1650 pd->msg_enable = smsc_debug;
1651 pd->rx_csum = true;
1652
1653 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1654
1655 id_rev = smsc9420_reg_read(pd, ID_REV);
1656 switch (id_rev & 0xFFFF0000) {
1657 case 0x94200000:
1658 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1659 break;
1660 default:
1661 smsc_warn(PROBE, "LAN9420 NOT identified");
1662 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1663 goto out_free_dmadesc_5;
1664 }
1665
1666 smsc9420_dmac_soft_reset(pd);
1667 smsc9420_eeprom_reload(pd);
1668 smsc9420_check_mac_address(dev);
1669
1670 dev->netdev_ops = &smsc9420_netdev_ops;
1671 dev->ethtool_ops = &smsc9420_ethtool_ops;
2cb37728
SG		 1672
1673 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1674
1675 result = register_netdev(dev);
1676 if (result) {
1677 smsc_warn(PROBE, "error %i registering device", result);
1678 goto out_free_dmadesc_5;
1679 }
1680
1681 pci_set_drvdata(pdev, dev);
1682
1683 spin_lock_init(&pd->int_lock);
1684 spin_lock_init(&pd->phy_lock);
1685
1686 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1687
1688 return 0;
1689
1690out_free_dmadesc_5:
1691 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1692 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1693out_free_io_4:
1694 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1695out_free_regions_3:
1696 pci_release_regions(pdev);
1697out_free_netdev_2:
1698 free_netdev(dev);
1699out_disable_pci_device_1:
1700 pci_disable_device(pdev);
1701out_0:
1702 return -ENODEV;
1703}
1704
1705static void __devexit smsc9420_remove(struct pci_dev *pdev)
1706{
1707 struct net_device *dev;
1708 struct smsc9420_pdata *pd;
1709
1710 dev = pci_get_drvdata(pdev);
1711 if (!dev)
1712 return;
1713
1714 pci_set_drvdata(pdev, NULL);
1715
1716 pd = netdev_priv(dev);
1717 unregister_netdev(dev);
1718
1719 /* tx_buffers and rx_buffers are freed in stop */
1720 BUG_ON(pd->tx_buffers);
1721 BUG_ON(pd->rx_buffers);
1722
1723 BUG_ON(!pd->tx_ring);
1724 BUG_ON(!pd->rx_ring);
1725
1726 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1727 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1728
b5a80837 1729 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
2cb37728
SG		 1730 pci_release_regions(pdev);
1731 free_netdev(dev);
1732 pci_disable_device(pdev);
1733}
1734
1735static struct pci_driver smsc9420_driver = {
1736 .name = DRV_NAME,
1737 .id_table = smsc9420_id_table,
1738 .probe = smsc9420_probe,
1739 .remove = __devexit_p(smsc9420_remove),
1740#ifdef CONFIG_PM
1741 .suspend = smsc9420_suspend,
1742 .resume = smsc9420_resume,
1743#endif /* CONFIG_PM */
1744};
1745
1746static int __init smsc9420_init_module(void)
1747{
1748 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1749
1750 return pci_register_driver(&smsc9420_driver);
1751}
1752
1753static void __exit smsc9420_exit_module(void)
1754{
1755 pci_unregister_driver(&smsc9420_driver);
1756}
1757
1758module_init(smsc9420_init_module);
1759module_exit(smsc9420_exit_module);
Linux kernel - Deliverables
This page took 0.499673 seconds and 5 git commands to generate.