[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / common.h

/*******************************************************************************
  STMMAC Common Header File

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __COMMON_H__
#define __COMMON_H__

#include <linux/etherdevice.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <linux/module.h>
#include <linux/init.h>
#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define STMMAC_VLAN_TAG_USED
#include <linux/if_vlan.h>
#endif

#include "descs.h"
#include "mmc.h"

#undef CHIP_DEBUG_PRINT
/* Turn-on extra printk debug for MAC core, dma and descriptors */
/* #define CHIP_DEBUG_PRINT */

#ifdef CHIP_DEBUG_PRINT
#define CHIP_DBG(fmt, args...)  printk(fmt, ## args)
#else
#define CHIP_DBG(fmt, args...)  do { } while (0)
#endif

/* Synopsys Core versions */
#define	DWMAC_CORE_3_40	0x34
#define	DWMAC_CORE_3_50	0x35

#undef FRAME_FILTER_DEBUG
/* #define FRAME_FILTER_DEBUG */

struct stmmac_extra_stats {
	/* Transmit errors */
	unsigned long tx_underflow ____cacheline_aligned;
	unsigned long tx_carrier;
	unsigned long tx_losscarrier;
	unsigned long vlan_tag;
	unsigned long tx_deferred;
	unsigned long tx_vlan;
	unsigned long tx_jabber;
	unsigned long tx_frame_flushed;
	unsigned long tx_payload_error;
	unsigned long tx_ip_header_error;
	/* Receive errors */
	unsigned long rx_desc;
	unsigned long sa_filter_fail;
	unsigned long overflow_error;
	unsigned long ipc_csum_error;
	unsigned long rx_collision;
	unsigned long rx_crc;
	unsigned long dribbling_bit;
	unsigned long rx_length;
	unsigned long rx_mii;
	unsigned long rx_multicast;
	unsigned long rx_gmac_overflow;
	unsigned long rx_watchdog;
	unsigned long da_rx_filter_fail;
	unsigned long sa_rx_filter_fail;
	unsigned long rx_missed_cntr;
	unsigned long rx_overflow_cntr;
	unsigned long rx_vlan;
	/* Tx/Rx IRQ error info */
	unsigned long tx_undeflow_irq;
	unsigned long tx_process_stopped_irq;
	unsigned long tx_jabber_irq;
	unsigned long rx_overflow_irq;
	unsigned long rx_buf_unav_irq;
	unsigned long rx_process_stopped_irq;
	unsigned long rx_watchdog_irq;
	unsigned long tx_early_irq;
	unsigned long fatal_bus_error_irq;
	/* Tx/Rx IRQ Events */
	unsigned long rx_early_irq;
	unsigned long threshold;
	unsigned long tx_pkt_n;
	unsigned long rx_pkt_n;
	unsigned long normal_irq_n;
	unsigned long rx_normal_irq_n;
	unsigned long napi_poll;
	unsigned long tx_normal_irq_n;
	unsigned long tx_clean;
	unsigned long tx_reset_ic_bit;
	unsigned long irq_receive_pmt_irq_n;
	/* MMC info */
	unsigned long mmc_tx_irq_n;
	unsigned long mmc_rx_irq_n;
	unsigned long mmc_rx_csum_offload_irq_n;
	/* EEE */
	unsigned long irq_tx_path_in_lpi_mode_n;
	unsigned long irq_tx_path_exit_lpi_mode_n;
	unsigned long irq_rx_path_in_lpi_mode_n;
	unsigned long irq_rx_path_exit_lpi_mode_n;
	unsigned long phy_eee_wakeup_error_n;
};

/* CSR Frequency Access Defines*/
#define CSR_F_35M	35000000
#define CSR_F_60M	60000000
#define CSR_F_100M	100000000
#define CSR_F_150M	150000000
#define CSR_F_250M	250000000
#define CSR_F_300M	300000000

#define	MAC_CSR_H_FRQ_MASK	0x20

#define HASH_TABLE_SIZE 64
#define PAUSE_TIME 0x200

/* Flow Control defines */
#define FLOW_OFF	0
#define FLOW_RX		1
#define FLOW_TX		2
#define FLOW_AUTO	(FLOW_TX | FLOW_RX)

#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */

/* DAM HW feature register fields */
#define DMA_HW_FEAT_MIISEL	0x00000001 /* 10/100 Mbps Support */
#define DMA_HW_FEAT_GMIISEL	0x00000002 /* 1000 Mbps Support */
#define DMA_HW_FEAT_HDSEL	0x00000004 /* Half-Duplex Support */
#define DMA_HW_FEAT_EXTHASHEN	0x00000008 /* Expanded DA Hash Filter */
#define DMA_HW_FEAT_HASHSEL	0x00000010 /* HASH Filter */
#define DMA_HW_FEAT_ADDMACADRSEL	0x00000020 /* Multiple MAC Addr Reg */
#define DMA_HW_FEAT_PCSSEL	0x00000040 /* PCS registers */
#define DMA_HW_FEAT_L3L4FLTREN	0x00000080 /* Layer 3 & Layer 4 Feature */
#define DMA_HW_FEAT_SMASEL	0x00000100 /* SMA(MDIO) Interface */
#define DMA_HW_FEAT_RWKSEL	0x00000200 /* PMT Remote Wakeup */
#define DMA_HW_FEAT_MGKSEL	0x00000400 /* PMT Magic Packet */
#define DMA_HW_FEAT_MMCSEL	0x00000800 /* RMON Module */
#define DMA_HW_FEAT_TSVER1SEL	0x00001000 /* Only IEEE 1588-2002 Timestamp */
#define DMA_HW_FEAT_TSVER2SEL	0x00002000 /* IEEE 1588-2008 Adv Timestamp */
#define DMA_HW_FEAT_EEESEL	0x00004000 /* Energy Efficient Ethernet */
#define DMA_HW_FEAT_AVSEL	0x00008000 /* AV Feature */
#define DMA_HW_FEAT_TXCOESEL	0x00010000 /* Checksum Offload in Tx */
#define DMA_HW_FEAT_RXTYP1COE	0x00020000 /* IP csum Offload(Type 1) in Rx */
#define DMA_HW_FEAT_RXTYP2COE	0x00040000 /* IP csum Offload(Type 2) in Rx */
#define DMA_HW_FEAT_RXFIFOSIZE	0x00080000 /* Rx FIFO > 2048 Bytes */
#define DMA_HW_FEAT_RXCHCNT	0x00300000 /* No. of additional Rx Channels */
#define DMA_HW_FEAT_TXCHCNT	0x00c00000 /* No. of additional Tx Channels */
#define DMA_HW_FEAT_ENHDESSEL	0x01000000 /* Alternate (Enhanced Descriptor) */
#define DMA_HW_FEAT_INTTSEN	0x02000000 /* Timestamping with Internal
					      System Time */
#define DMA_HW_FEAT_FLEXIPPSEN	0x04000000 /* Flexible PPS Output */
#define DMA_HW_FEAT_SAVLANINS	0x08000000 /* Source Addr or VLAN Insertion */
#define DMA_HW_FEAT_ACTPHYIF	0x70000000 /* Active/selected PHY interface */
#define DEFAULT_DMA_PBL		8

/* Max/Min RI Watchdog Timer count value */
#define MAX_DMA_RIWT		0xff
#define MIN_DMA_RIWT		0x20
/* Tx coalesce parameters */
#define STMMAC_COAL_TX_TIMER	40000
#define STMMAC_MAX_COAL_TX_TICK	100000
#define STMMAC_TX_MAX_FRAMES	256
#define STMMAC_TX_FRAMES	64

enum rx_frame_status { /* IPC status */
	good_frame = 0,
	discard_frame = 1,
	csum_none = 2,
	llc_snap = 4,
};

enum dma_irq_status {
	tx_hard_error = 0x1,
	tx_hard_error_bump_tc = 0x2,
	handle_rx = 0x4,
	handle_tx = 0x8,
};

enum core_specific_irq_mask {
	core_mmc_tx_irq = 1,
	core_mmc_rx_irq = 2,
	core_mmc_rx_csum_offload_irq = 4,
	core_irq_receive_pmt_irq = 8,
	core_irq_tx_path_in_lpi_mode = 16,
	core_irq_tx_path_exit_lpi_mode = 32,
	core_irq_rx_path_in_lpi_mode = 64,
	core_irq_rx_path_exit_lpi_mode = 128,
};

/* DMA HW capabilities */
struct dma_features {
	unsigned int mbps_10_100;
	unsigned int mbps_1000;
	unsigned int half_duplex;
	unsigned int hash_filter;
	unsigned int multi_addr;
	unsigned int pcs;
	unsigned int sma_mdio;
	unsigned int pmt_remote_wake_up;
	unsigned int pmt_magic_frame;
	unsigned int rmon;
	/* IEEE 1588-2002*/
	unsigned int time_stamp;
	/* IEEE 1588-2008*/
	unsigned int atime_stamp;
	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	unsigned int eee;
	unsigned int av;
	/* TX and RX csum */
	unsigned int tx_coe;
	unsigned int rx_coe_type1;
	unsigned int rx_coe_type2;
	unsigned int rxfifo_over_2048;
	/* TX and RX number of channels */
	unsigned int number_rx_channel;
	unsigned int number_tx_channel;
	/* Alternate (enhanced) DESC mode*/
	unsigned int enh_desc;
};

/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
#define BUF_SIZE_16KiB 16384
#define BUF_SIZE_8KiB 8192
#define BUF_SIZE_4KiB 4096
#define BUF_SIZE_2KiB 2048

/* Power Down and WOL */
#define PMT_NOT_SUPPORTED 0
#define PMT_SUPPORTED 1

/* Common MAC defines */
#define MAC_CTRL_REG		0x00000000	/* MAC Control */
#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
#define MAC_RNABLE_RX		0x00000004	/* Receiver Enable */

/* Default LPI timers */
#define STMMAC_DEFAULT_LIT_LS_TIMER	0x3E8
#define STMMAC_DEFAULT_TWT_LS_TIMER	0x0

struct stmmac_desc_ops {
	/* DMA RX descriptor ring initialization */
	void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
			      int disable_rx_ic);
	/* DMA TX descriptor ring initialization */
	void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);

	/* Invoked by the xmit function to prepare the tx descriptor */
	void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
				 int csum_flag);
	/* Set/get the owner of the descriptor */
	void (*set_tx_owner) (struct dma_desc *p);
	int (*get_tx_owner) (struct dma_desc *p);
	/* Invoked by the xmit function to close the tx descriptor */
	void (*close_tx_desc) (struct dma_desc *p);
	/* Clean the tx descriptor as soon as the tx irq is received */
	void (*release_tx_desc) (struct dma_desc *p);
	/* Clear interrupt on tx frame completion. When this bit is
	 * set an interrupt happens as soon as the frame is transmitted */
	void (*clear_tx_ic) (struct dma_desc *p);
	/* Last tx segment reports the transmit status */
	int (*get_tx_ls) (struct dma_desc *p);
	/* Return the transmit status looking at the TDES1 */
	int (*tx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p, void __iomem *ioaddr);
	/* Get the buffer size from the descriptor */
	int (*get_tx_len) (struct dma_desc *p);
	/* Handle extra events on specific interrupts hw dependent */
	int (*get_rx_owner) (struct dma_desc *p);
	void (*set_rx_owner) (struct dma_desc *p);
	/* Get the receive frame size */
	int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
	/* Return the reception status looking at the RDES1 */
	int (*rx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p);
};

struct stmmac_dma_ops {
	/* DMA core initialization */
	int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
		     int burst_len, u32 dma_tx, u32 dma_rx);
	/* Dump DMA registers */
	void (*dump_regs) (void __iomem *ioaddr);
	/* Set tx/rx threshold in the csr6 register
	 * An invalid value enables the store-and-forward mode */
	void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
	/* To track extra statistic (if supported) */
	void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
				   void __iomem *ioaddr);
	void (*enable_dma_transmission) (void __iomem *ioaddr);
	void (*enable_dma_irq) (void __iomem *ioaddr);
	void (*disable_dma_irq) (void __iomem *ioaddr);
	void (*start_tx) (void __iomem *ioaddr);
	void (*stop_tx) (void __iomem *ioaddr);
	void (*start_rx) (void __iomem *ioaddr);
	void (*stop_rx) (void __iomem *ioaddr);
	int (*dma_interrupt) (void __iomem *ioaddr,
			      struct stmmac_extra_stats *x);
	/* If supported then get the optional core features */
	unsigned int (*get_hw_feature) (void __iomem *ioaddr);
	/* Program the HW RX Watchdog */
	void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
};

struct stmmac_ops {
	/* MAC core initialization */
	void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
	/* Enable and verify that the IPC module is supported */
	int (*rx_ipc) (void __iomem *ioaddr);
	/* Dump MAC registers */
	void (*dump_regs) (void __iomem *ioaddr);
	/* Handle extra events on specific interrupts hw dependent */
	int (*host_irq_status) (void __iomem *ioaddr);
	/* Multicast filter setting */
	void (*set_filter) (struct net_device *dev, int id);
	/* Flow control setting */
	void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
			   unsigned int fc, unsigned int pause_time);
	/* Set power management mode (e.g. magic frame) */
	void (*pmt) (void __iomem *ioaddr, unsigned long mode);
	/* Set/Get Unicast MAC addresses */
	void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
			       unsigned int reg_n);
	void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
			       unsigned int reg_n);
	void (*set_eee_mode) (void __iomem *ioaddr);
	void (*reset_eee_mode) (void __iomem *ioaddr);
	void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
	void (*set_eee_pls) (void __iomem *ioaddr, int link);
};

struct mac_link {
	int port;
	int duplex;
	int speed;
};

struct mii_regs {
	unsigned int addr;	/* MII Address */
	unsigned int data;	/* MII Data */
};

struct stmmac_ring_mode_ops {
	unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
	unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
	void (*refill_desc3) (int bfsize, struct dma_desc *p);
	void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
	void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
				unsigned int size);
	void (*clean_desc3) (struct dma_desc *p);
	int (*set_16kib_bfsize) (int mtu);
};

struct mac_device_info {
	const struct stmmac_ops		*mac;
	const struct stmmac_desc_ops	*desc;
	const struct stmmac_dma_ops	*dma;
	const struct stmmac_ring_mode_ops	*ring;
	struct mii_regs mii;	/* MII register Addresses */
	struct mac_link link;
	unsigned int synopsys_uid;
};

struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);

extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
				unsigned int high, unsigned int low);
extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low);

extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);

extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
extern const struct stmmac_ring_mode_ops ring_mode_ops;

#endif /* __COMMON_H__ */
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Common Header File
	3
	4	Copyright (C) 2007-2009 STMicroelectronics Ltd
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	23	*******************************************************************************/
	24
bd4242df RK	25	#ifndef __COMMON_H__
	26	#define __COMMON_H__
	27
bfab27a1	28	#include <linux/etherdevice.h>
5e33c791	29	#include <linux/netdevice.h>
bfab27a1 GC	30	#include <linux/phy.h>
	31	#include <linux/module.h>
	32	#include <linux/init.h>
8f617541 GC	33	#if defined(CONFIG_VLAN_8021Q) \|\| defined(CONFIG_VLAN_8021Q_MODULE)
	34	#define STMMAC_VLAN_TAG_USED
	35	#include <linux/if_vlan.h>
	36	#endif
	37
56b106ae	38	#include "descs.h"
1c901a46	39	#include "mmc.h"
56b106ae GC	40
	41	#undef CHIP_DEBUG_PRINT
	42	/* Turn-on extra printk debug for MAC core, dma and descriptors */
	43	/* #define CHIP_DEBUG_PRINT */
	44
	45	#ifdef CHIP_DEBUG_PRINT
	46	#define CHIP_DBG(fmt, args...) printk(fmt, ## args)
	47	#else
	48	#define CHIP_DBG(fmt, args...) do { } while (0)
	49	#endif
	50
62a2ab93 GC	51	/* Synopsys Core versions */
	52	#define DWMAC_CORE_3_40 0x34
	53	#define DWMAC_CORE_3_50 0x35
	54
56b106ae GC	55	#undef FRAME_FILTER_DEBUG
56b106ae GC	56	/* #define FRAME_FILTER_DEBUG */
47dd7a54	57
47dd7a54 GC	58	struct stmmac_extra_stats {
	59	/* Transmit errors */
	60	unsigned long tx_underflow ____cacheline_aligned;
	61	unsigned long tx_carrier;
	62	unsigned long tx_losscarrier;
3c20f72f	63	unsigned long vlan_tag;
47dd7a54 GC	64	unsigned long tx_deferred;
	65	unsigned long tx_vlan;
	66	unsigned long tx_jabber;
	67	unsigned long tx_frame_flushed;
	68	unsigned long tx_payload_error;
	69	unsigned long tx_ip_header_error;
	70	/* Receive errors */
	71	unsigned long rx_desc;
3c20f72f GC	72	unsigned long sa_filter_fail;
	73	unsigned long overflow_error;
	74	unsigned long ipc_csum_error;
47dd7a54 GC	75	unsigned long rx_collision;
47dd7a54 GC	76	unsigned long rx_crc;
1cc5a735	77	unsigned long dribbling_bit;
1b924032	78	unsigned long rx_length;
47dd7a54 GC	79	unsigned long rx_mii;
	80	unsigned long rx_multicast;
	81	unsigned long rx_gmac_overflow;
	82	unsigned long rx_watchdog;
	83	unsigned long da_rx_filter_fail;
	84	unsigned long sa_rx_filter_fail;
	85	unsigned long rx_missed_cntr;
	86	unsigned long rx_overflow_cntr;
	87	unsigned long rx_vlan;
62a2ab93	88	/* Tx/Rx IRQ error info */
47dd7a54 GC	89	unsigned long tx_undeflow_irq;
	90	unsigned long tx_process_stopped_irq;
	91	unsigned long tx_jabber_irq;
	92	unsigned long rx_overflow_irq;
	93	unsigned long rx_buf_unav_irq;
	94	unsigned long rx_process_stopped_irq;
	95	unsigned long rx_watchdog_irq;
	96	unsigned long tx_early_irq;
	97	unsigned long fatal_bus_error_irq;
62a2ab93 GC	98	/* Tx/Rx IRQ Events */
62a2ab93 GC	99	unsigned long rx_early_irq;
47dd7a54 GC	100	unsigned long threshold;
	101	unsigned long tx_pkt_n;
	102	unsigned long rx_pkt_n;
47dd7a54	103	unsigned long normal_irq_n;
9125cdd1 GC	104	unsigned long rx_normal_irq_n;
	105	unsigned long napi_poll;
	106	unsigned long tx_normal_irq_n;
	107	unsigned long tx_clean;
	108	unsigned long tx_reset_ic_bit;
62a2ab93 GC	109	unsigned long irq_receive_pmt_irq_n;
62a2ab93 GC	110	/* MMC info */
d765955d GC	111	unsigned long mmc_tx_irq_n;
	112	unsigned long mmc_rx_irq_n;
	113	unsigned long mmc_rx_csum_offload_irq_n;
	114	/* EEE */
d765955d GC	115	unsigned long irq_tx_path_in_lpi_mode_n;
	116	unsigned long irq_tx_path_exit_lpi_mode_n;
	117	unsigned long irq_rx_path_in_lpi_mode_n;
	118	unsigned long irq_rx_path_exit_lpi_mode_n;
	119	unsigned long phy_eee_wakeup_error_n;
47dd7a54 GC	120	};
47dd7a54 GC	121
cd7201f4 GC	122	/* CSR Frequency Access Defines*/
	123	#define CSR_F_35M 35000000
	124	#define CSR_F_60M 60000000
	125	#define CSR_F_100M 100000000
	126	#define CSR_F_150M 150000000
	127	#define CSR_F_250M 250000000
	128	#define CSR_F_300M 300000000
	129
	130	#define MAC_CSR_H_FRQ_MASK 0x20
	131
aec7ff27 GC	132	#define HASH_TABLE_SIZE 64
	133	#define PAUSE_TIME 0x200
	134
	135	/* Flow Control defines */
	136	#define FLOW_OFF 0
	137	#define FLOW_RX 1
	138	#define FLOW_TX 2
	139	#define FLOW_AUTO (FLOW_TX \| FLOW_RX)
	140
	141	#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
	142
1db123fb RK	143	/* DAM HW feature register fields */
	144	#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
	145	#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
	146	#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
	147	#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
	148	#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
	149	#define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
	150	#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
	151	#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
	152	#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
	153	#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
	154	#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
	155	#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
	156	#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
	157	#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
	158	#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
	159	#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
	160	#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
	161	#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
	162	#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
	163	#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
	164	#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
	165	#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
	166	#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
	167	#define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
	168	System Time */
	169	#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
	170	#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
	171	#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
0f1f88a8	172	#define DEFAULT_DMA_PBL 8
1db123fb	173
62a2ab93 GC	174	/* Max/Min RI Watchdog Timer count value */
	175	#define MAX_DMA_RIWT 0xff
	176	#define MIN_DMA_RIWT 0x20
9125cdd1 GC	177	/* Tx coalesce parameters */
	178	#define STMMAC_COAL_TX_TIMER 40000
	179	#define STMMAC_MAX_COAL_TX_TICK 100000
	180	#define STMMAC_TX_MAX_FRAMES 256
	181	#define STMMAC_TX_FRAMES 64
	182
aec7ff27	183	enum rx_frame_status { /* IPC status */
47dd7a54 GC	184	good_frame = 0,
	185	discard_frame = 1,
	186	csum_none = 2,
3eeb2997	187	llc_snap = 4,
47dd7a54 GC	188	};
47dd7a54 GC	189
9125cdd1 GC	190	enum dma_irq_status {
	191	tx_hard_error = 0x1,
	192	tx_hard_error_bump_tc = 0x2,
	193	handle_rx = 0x4,
	194	handle_tx = 0x8,
aec7ff27	195	};
47dd7a54	196
d765955d GC	197	enum core_specific_irq_mask {
	198	core_mmc_tx_irq = 1,
	199	core_mmc_rx_irq = 2,
	200	core_mmc_rx_csum_offload_irq = 4,
	201	core_irq_receive_pmt_irq = 8,
	202	core_irq_tx_path_in_lpi_mode = 16,
	203	core_irq_tx_path_exit_lpi_mode = 32,
	204	core_irq_rx_path_in_lpi_mode = 64,
	205	core_irq_rx_path_exit_lpi_mode = 128,
	206	};
	207
e7434821 GC	208	/* DMA HW capabilities */
	209	struct dma_features {
	210	unsigned int mbps_10_100;
	211	unsigned int mbps_1000;
	212	unsigned int half_duplex;
	213	unsigned int hash_filter;
	214	unsigned int multi_addr;
	215	unsigned int pcs;
	216	unsigned int sma_mdio;
	217	unsigned int pmt_remote_wake_up;
	218	unsigned int pmt_magic_frame;
	219	unsigned int rmon;
	220	/* IEEE 1588-2002*/
	221	unsigned int time_stamp;
	222	/* IEEE 1588-2008*/
	223	unsigned int atime_stamp;
	224	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	225	unsigned int eee;
	226	unsigned int av;
	227	/* TX and RX csum */
	228	unsigned int tx_coe;
	229	unsigned int rx_coe_type1;
	230	unsigned int rx_coe_type2;
	231	unsigned int rxfifo_over_2048;
	232	/* TX and RX number of channels */
	233	unsigned int number_rx_channel;
	234	unsigned int number_tx_channel;
	235	/* Alternate (enhanced) DESC mode*/
	236	unsigned int enh_desc;
	237	};
	238
aec7ff27 GC	239	/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
	240	#define BUF_SIZE_16KiB 16384
	241	#define BUF_SIZE_8KiB 8192
	242	#define BUF_SIZE_4KiB 4096
	243	#define BUF_SIZE_2KiB 2048
47dd7a54	244
aec7ff27 GC	245	/* Power Down and WOL */
	246	#define PMT_NOT_SUPPORTED 0
	247	#define PMT_SUPPORTED 1
47dd7a54	248
aec7ff27 GC	249	/* Common MAC defines */
	250	#define MAC_CTRL_REG 0x00000000 /* MAC Control */
	251	#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
	252	#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54	253
d765955d GC	254	/* Default LPI timers */
	255	#define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
	256	#define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
	257
db98a0b0 GC	258	struct stmmac_desc_ops {
db98a0b0 GC	259	/* DMA RX descriptor ring initialization */
47dd7a54	260	void (init_rx_desc) (struct dma_desc p, unsigned int ring_size,
db98a0b0 GC	261	int disable_rx_ic);
db98a0b0 GC	262	/* DMA TX descriptor ring initialization */
47dd7a54 GC	263	void (init_tx_desc) (struct dma_desc p, unsigned int ring_size);
	264
	265	/* Invoked by the xmit function to prepare the tx descriptor */
	266	void (prepare_tx_desc) (struct dma_desc p, int is_fs, int len,
	267	int csum_flag);
	268	/* Set/get the owner of the descriptor */
	269	void (set_tx_owner) (struct dma_desc p);
	270	int (get_tx_owner) (struct dma_desc p);
	271	/* Invoked by the xmit function to close the tx descriptor */
	272	void (close_tx_desc) (struct dma_desc p);
	273	/* Clean the tx descriptor as soon as the tx irq is received */
	274	void (release_tx_desc) (struct dma_desc p);
	275	/* Clear interrupt on tx frame completion. When this bit is
	276	* set an interrupt happens as soon as the frame is transmitted */
	277	void (clear_tx_ic) (struct dma_desc p);
	278	/* Last tx segment reports the transmit status */
	279	int (get_tx_ls) (struct dma_desc p);
	280	/* Return the transmit status looking at the TDES1 */
	281	int (tx_status) (void data, struct stmmac_extra_stats *x,
ad01b7d4	282	struct dma_desc p, void __iomem ioaddr);
47dd7a54 GC	283	/* Get the buffer size from the descriptor */
	284	int (get_tx_len) (struct dma_desc p);
	285	/* Handle extra events on specific interrupts hw dependent */
47dd7a54 GC	286	int (get_rx_owner) (struct dma_desc p);
	287	void (set_rx_owner) (struct dma_desc p);
	288	/* Get the receive frame size */
38912bdb	289	int (get_rx_frame_len) (struct dma_desc p, int rx_coe_type);
47dd7a54 GC	290	/* Return the reception status looking at the RDES1 */
	291	int (rx_status) (void data, struct stmmac_extra_stats *x,
	292	struct dma_desc *p);
db98a0b0 GC	293	};
	294
	295	struct stmmac_dma_ops {
	296	/* DMA core initialization */
b9cde0a8 GC	297	int (init) (void __iomem ioaddr, int pbl, int fb, int mb,
b9cde0a8 GC	298	int burst_len, u32 dma_tx, u32 dma_rx);
db98a0b0	299	/* Dump DMA registers */
ad01b7d4	300	void (dump_regs) (void __iomem ioaddr);
db98a0b0 GC	301	/* Set tx/rx threshold in the csr6 register
db98a0b0 GC	302	* An invalid value enables the store-and-forward mode */
ad01b7d4	303	void (dma_mode) (void __iomem ioaddr, int txmode, int rxmode);
db98a0b0 GC	304	/* To track extra statistic (if supported) */
db98a0b0 GC	305	void (dma_diagnostic_fr) (void data, struct stmmac_extra_stats *x,
ad01b7d4 GC	306	void __iomem *ioaddr);
	307	void (enable_dma_transmission) (void __iomem ioaddr);
	308	void (enable_dma_irq) (void __iomem ioaddr);
	309	void (disable_dma_irq) (void __iomem ioaddr);
	310	void (start_tx) (void __iomem ioaddr);
	311	void (stop_tx) (void __iomem ioaddr);
	312	void (start_rx) (void __iomem ioaddr);
	313	void (stop_rx) (void __iomem ioaddr);
	314	int (dma_interrupt) (void __iomem ioaddr,
aec7ff27	315	struct stmmac_extra_stats *x);
e7434821 GC	316	/* If supported then get the optional core features */
e7434821 GC	317	unsigned int (get_hw_feature) (void __iomem ioaddr);
62a2ab93 GC	318	/* Program the HW RX Watchdog */
62a2ab93 GC	319	void (rx_watchdog) (void __iomem ioaddr, u32 riwt);
db98a0b0 GC	320	};
	321
	322	struct stmmac_ops {
	323	/* MAC core initialization */
ad01b7d4	324	void (core_init) (void __iomem ioaddr) ____cacheline_aligned;
38912bdb DS	325	/* Enable and verify that the IPC module is supported */
38912bdb DS	326	int (rx_ipc) (void __iomem ioaddr);
db98a0b0	327	/* Dump MAC registers */
ad01b7d4	328	void (dump_regs) (void __iomem ioaddr);
db98a0b0	329	/* Handle extra events on specific interrupts hw dependent */
d765955d	330	int (host_irq_status) (void __iomem ioaddr);
47dd7a54	331	/* Multicast filter setting */
cffb13f4	332	void (set_filter) (struct net_device dev, int id);
47dd7a54	333	/* Flow control setting */
ad01b7d4	334	void (flow_ctrl) (void __iomem ioaddr, unsigned int duplex,
47dd7a54 GC	335	unsigned int fc, unsigned int pause_time);
47dd7a54 GC	336	/* Set power management mode (e.g. magic frame) */
ad01b7d4	337	void (pmt) (void __iomem ioaddr, unsigned long mode);
47dd7a54	338	/* Set/Get Unicast MAC addresses */
ad01b7d4	339	void (set_umac_addr) (void __iomem ioaddr, unsigned char *addr,
db98a0b0	340	unsigned int reg_n);
ad01b7d4	341	void (get_umac_addr) (void __iomem ioaddr, unsigned char *addr,
db98a0b0	342	unsigned int reg_n);
d765955d GC	343	void (set_eee_mode) (void __iomem ioaddr);
	344	void (reset_eee_mode) (void __iomem ioaddr);
	345	void (set_eee_timer) (void __iomem ioaddr, int ls, int tw);
	346	void (set_eee_pls) (void __iomem ioaddr, int link);
47dd7a54 GC	347	};
	348
	349	struct mac_link {
	350	int port;
	351	int duplex;
	352	int speed;
	353	};
	354
	355	struct mii_regs {
	356	unsigned int addr; /* MII Address */
	357	unsigned int data; /* MII Data */
	358	};
	359
286a8372 GC	360	struct stmmac_ring_mode_ops {
	361	unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
	362	unsigned int (jumbo_frm) (void priv, struct sk_buff *skb, int csum);
	363	void (refill_desc3) (int bfsize, struct dma_desc p);
	364	void (init_desc3) (int des3_as_data_buf, struct dma_desc p);
	365	void (init_dma_chain) (struct dma_desc des, dma_addr_t phy_addr,
	366	unsigned int size);
	367	void (clean_desc3) (struct dma_desc p);
	368	int (*set_16kib_bfsize) (int mtu);
	369	};
	370
47dd7a54	371	struct mac_device_info {
cadb7924	372	const struct stmmac_ops *mac;
	373	const struct stmmac_desc_ops *desc;
	374	const struct stmmac_dma_ops *dma;
286a8372	375	const struct stmmac_ring_mode_ops *ring;
db98a0b0 GC	376	struct mii_regs mii; /* MII register Addresses */
db98a0b0 GC	377	struct mac_link link;
f0b9d786	378	unsigned int synopsys_uid;
47dd7a54 GC	379	};
47dd7a54 GC	380
ad01b7d4 GC	381	struct mac_device_info dwmac1000_setup(void __iomem ioaddr);
ad01b7d4 GC	382	struct mac_device_info dwmac100_setup(void __iomem ioaddr);
aec7ff27	383
ad01b7d4	384	extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
aec7ff27	385	unsigned int high, unsigned int low);
ad01b7d4	386	extern void stmmac_get_mac_addr(void __iomem ioaddr, unsigned char addr,
aec7ff27	387	unsigned int high, unsigned int low);
bfab27a1 GC	388
	389	extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
	390
ad01b7d4	391	extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
286a8372	392	extern const struct stmmac_ring_mode_ops ring_mode_ops;
bd4242df RK	393
bd4242df RK	394	#endif /* __COMMON_H__ */