[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / dwmac-socfpga.c

/* Copyright Altera Corporation (C) 2014. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2,
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Adopted from dwmac-sti.c
 */

#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/stmmac.h>

#include "stmmac.h"
#include "stmmac_platform.h"

#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010

#define SYSMGR_FPGAGRP_MODULE_REG  0x00000028
#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004

#define EMAC_SPLITTER_CTRL_REG			0x0
#define EMAC_SPLITTER_CTRL_SPEED_MASK		0x3
#define EMAC_SPLITTER_CTRL_SPEED_10		0x2
#define EMAC_SPLITTER_CTRL_SPEED_100		0x3
#define EMAC_SPLITTER_CTRL_SPEED_1000		0x0

struct socfpga_dwmac {
	int	interface;
	u32	reg_offset;
	u32	reg_shift;
	struct	device *dev;
	struct regmap *sys_mgr_base_addr;
	void __iomem *splitter_base;
	bool f2h_ptp_ref_clk;
};

static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
{
	struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
	void __iomem *splitter_base = dwmac->splitter_base;
	u32 val;

	if (!splitter_base)
		return;

	val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
	val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;

	switch (speed) {
	case 1000:
		val |= EMAC_SPLITTER_CTRL_SPEED_1000;
		break;
	case 100:
		val |= EMAC_SPLITTER_CTRL_SPEED_100;
		break;
	case 10:
		val |= EMAC_SPLITTER_CTRL_SPEED_10;
		break;
	default:
		return;
	}

	writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
}

static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct regmap *sys_mgr_base_addr;
	u32 reg_offset, reg_shift;
	int ret;
	struct device_node *np_splitter;
	struct resource res_splitter;

	dwmac->interface = of_get_phy_mode(np);

	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	if (IS_ERR(sys_mgr_base_addr)) {
		dev_info(dev, "No sysmgr-syscon node found\n");
		return PTR_ERR(sys_mgr_base_addr);
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	if (ret) {
		dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
		return -EINVAL;
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	if (ret) {
		dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
		return -EINVAL;
	}

	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");

	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
	if (np_splitter) {
		if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
			dev_info(dev, "Missing emac splitter address\n");
			return -EINVAL;
		}

		dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
		if (IS_ERR(dwmac->splitter_base)) {
			dev_info(dev, "Failed to mapping emac splitter\n");
			return PTR_ERR(dwmac->splitter_base);
		}
	}

	dwmac->reg_offset = reg_offset;
	dwmac->reg_shift = reg_shift;
	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	dwmac->dev = dev;

	return 0;
}

static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
{
	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	int phymode = dwmac->interface;
	u32 reg_offset = dwmac->reg_offset;
	u32 reg_shift = dwmac->reg_shift;
	u32 ctrl, val, module;

	switch (phymode) {
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
		break;
	case PHY_INTERFACE_MODE_MII:
	case PHY_INTERFACE_MODE_GMII:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
		break;
	default:
		dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
		return -EINVAL;
	}

	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	 * is the actual phy mode on phy hardware, but phy interface from
	 * EMAC core is GMII.
	 */
	if (dwmac->splitter_base)
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;

	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	ctrl |= val << reg_shift;

	if (dwmac->f2h_ptp_ref_clk) {
		ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
		regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
			    &module);
		module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
		regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
			     module);
	} else {
		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
	}

	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);

	return 0;
}

static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
{
	struct socfpga_dwmac *dwmac = priv;
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct stmmac_priv *stpriv = NULL;
	int ret = 0;

	if (!ndev)
		return -EINVAL;

	stpriv = netdev_priv(ndev);
	if (!stpriv)
		return -EINVAL;

	/* Assert reset to the enet controller before changing the phy mode */
	if (stpriv->stmmac_rst)
		reset_control_assert(stpriv->stmmac_rst);

	/* Setup the phy mode in the system manager registers according to
	 * devicetree configuration
	 */
	ret = socfpga_dwmac_setup(dwmac);

	/* Deassert reset for the phy configuration to be sampled by
	 * the enet controller, and operation to start in requested mode
	 */
	if (stpriv->stmmac_rst)
		reset_control_deassert(stpriv->stmmac_rst);

	/* Before the enet controller is suspended, the phy is suspended.
	 * This causes the phy clock to be gated. The enet controller is
	 * resumed before the phy, so the clock is still gated "off" when
	 * the enet controller is resumed. This code makes sure the phy
	 * is "resumed" before reinitializing the enet controller since
	 * the enet controller depends on an active phy clock to complete
	 * a DMA reset. A DMA reset will "time out" if executed
	 * with no phy clock input on the Synopsys enet controller.
	 * Verified through Synopsys Case #8000711656.
	 *
	 * Note that the phy clock is also gated when the phy is isolated.
	 * Phy "suspend" and "isolate" controls are located in phy basic
	 * control register 0, and can be modified by the phy driver
	 * framework.
	 */
	if (stpriv->phydev)
		phy_resume(stpriv->phydev);

	return ret;
}

static int socfpga_dwmac_probe(struct platform_device *pdev)
{
	struct plat_stmmacenet_data *plat_dat;
	struct stmmac_resources stmmac_res;
	struct device		*dev = &pdev->dev;
	int			ret;
	struct socfpga_dwmac	*dwmac;

	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
	if (ret)
		return ret;

	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
	if (IS_ERR(plat_dat))
		return PTR_ERR(plat_dat);

	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
	if (!dwmac)
		return -ENOMEM;

	ret = socfpga_dwmac_parse_data(dwmac, dev);
	if (ret) {
		dev_err(dev, "Unable to parse OF data\n");
		return ret;
	}

	ret = socfpga_dwmac_setup(dwmac);
	if (ret) {
		dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
		return ret;
	}

	plat_dat->bsp_priv = dwmac;
	plat_dat->init = socfpga_dwmac_init;
	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;

	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
	if (!ret)
		ret = socfpga_dwmac_init(pdev, dwmac);

	return ret;
}

static const struct of_device_id socfpga_dwmac_match[] = {
	{ .compatible = "altr,socfpga-stmmac" },
	{ }
};
MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);

static struct platform_driver socfpga_dwmac_driver = {
	.probe  = socfpga_dwmac_probe,
	.remove = stmmac_pltfr_remove,
	.driver = {
		.name           = "socfpga-dwmac",
		.pm		= &stmmac_pltfr_pm_ops,
		.of_match_table = socfpga_dwmac_match,
	},
};
module_platform_driver(socfpga_dwmac_driver);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
801d233b DN	1	/* Copyright Altera Corporation (C) 2014. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License, version 2,
	5	* as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	14	*
	15	* Adopted from dwmac-sti.c
	16	*/
	17
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/of.h>
b4834c86	20	#include <linux/of_address.h>
801d233b DN	21	#include <linux/of_net.h>
	22	#include <linux/phy.h>
	23	#include <linux/regmap.h>
2d871aa0	24	#include <linux/reset.h>
801d233b	25	#include <linux/stmmac.h>
f10f9fb2	26
2d871aa0	27	#include "stmmac.h"
f10f9fb2	28	#include "stmmac_platform.h"
801d233b DN	29
	30	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
	31	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
	32	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
	33	#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
	34	#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
43569814	35	#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
801d233b	36
734e00fa PR	37	#define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
	38	#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
	39
b4834c86 LFT	40	#define EMAC_SPLITTER_CTRL_REG 0x0
	41	#define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
	42	#define EMAC_SPLITTER_CTRL_SPEED_10 0x2
	43	#define EMAC_SPLITTER_CTRL_SPEED_100 0x3
	44	#define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
	45
801d233b DN	46	struct socfpga_dwmac {
	47	int interface;
	48	u32 reg_offset;
	49	u32 reg_shift;
	50	struct device *dev;
	51	struct regmap *sys_mgr_base_addr;
b4834c86	52	void __iomem *splitter_base;
43569814	53	bool f2h_ptp_ref_clk;
801d233b DN	54	};
801d233b DN	55
b4834c86 LFT	56	static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
	57	{
	58	struct socfpga_dwmac dwmac = (struct socfpga_dwmac )priv;
	59	void __iomem *splitter_base = dwmac->splitter_base;
	60	u32 val;
	61
	62	if (!splitter_base)
	63	return;
	64
	65	val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
	66	val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
	67
	68	switch (speed) {
	69	case 1000:
	70	val \|= EMAC_SPLITTER_CTRL_SPEED_1000;
	71	break;
	72	case 100:
	73	val \|= EMAC_SPLITTER_CTRL_SPEED_100;
	74	break;
	75	case 10:
	76	val \|= EMAC_SPLITTER_CTRL_SPEED_10;
	77	break;
	78	default:
	79	return;
	80	}
	81
	82	writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
	83	}
	84
801d233b DN	85	static int socfpga_dwmac_parse_data(struct socfpga_dwmac dwmac, struct device dev)
	86	{
	87	struct device_node *np = dev->of_node;
	88	struct regmap *sys_mgr_base_addr;
	89	u32 reg_offset, reg_shift;
	90	int ret;
b4834c86 LFT	91	struct device_node *np_splitter;
b4834c86 LFT	92	struct resource res_splitter;
801d233b DN	93
	94	dwmac->interface = of_get_phy_mode(np);
	95
	96	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	97	if (IS_ERR(sys_mgr_base_addr)) {
	98	dev_info(dev, "No sysmgr-syscon node found\n");
	99	return PTR_ERR(sys_mgr_base_addr);
	100	}
	101
	102	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	103	if (ret) {
	104	dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
	105	return -EINVAL;
	106	}
	107
	108	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	109	if (ret) {
	110	dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
	111	return -EINVAL;
	112	}
	113
43569814 PR	114	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
43569814 PR	115
b4834c86 LFT	116	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
	117	if (np_splitter) {
	118	if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
	119	dev_info(dev, "Missing emac splitter address\n");
	120	return -EINVAL;
	121	}
	122
dace1b54	123	dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
f19f916d	124	if (IS_ERR(dwmac->splitter_base)) {
b4834c86	125	dev_info(dev, "Failed to mapping emac splitter\n");
f19f916d	126	return PTR_ERR(dwmac->splitter_base);
b4834c86 LFT	127	}
	128	}
	129
801d233b DN	130	dwmac->reg_offset = reg_offset;
	131	dwmac->reg_shift = reg_shift;
	132	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	133	dwmac->dev = dev;
	134
	135	return 0;
	136	}
	137
	138	static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
	139	{
	140	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	141	int phymode = dwmac->interface;
	142	u32 reg_offset = dwmac->reg_offset;
	143	u32 reg_shift = dwmac->reg_shift;
734e00fa	144	u32 ctrl, val, module;
801d233b DN	145
	146	switch (phymode) {
	147	case PHY_INTERFACE_MODE_RGMII:
b4834c86	148	case PHY_INTERFACE_MODE_RGMII_ID:
801d233b DN	149	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
	150	break;
	151	case PHY_INTERFACE_MODE_MII:
	152	case PHY_INTERFACE_MODE_GMII:
	153	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	154	break;
	155	default:
	156	dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
	157	return -EINVAL;
	158	}
	159
b4834c86 LFT	160	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	161	* is the actual phy mode on phy hardware, but phy interface from
	162	* EMAC core is GMII.
	163	*/
	164	if (dwmac->splitter_base)
	165	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	166
801d233b DN	167	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	168	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	169	ctrl \|= val << reg_shift;
	170
734e00fa	171	if (dwmac->f2h_ptp_ref_clk) {
43569814	172	ctrl \|= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
734e00fa PR	173	regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
	174	&module);
	175	module \|= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
	176	regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
	177	module);
	178	} else {
43569814	179	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
734e00fa	180	}
43569814	181
801d233b	182	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
734e00fa	183
801d233b DN	184	return 0;
	185	}
	186
2d871aa0 VB	187	static int socfpga_dwmac_init(struct platform_device pdev, void priv)
2d871aa0 VB	188	{
3c201b5a	189	struct socfpga_dwmac *dwmac = priv;
2d871aa0 VB	190	struct net_device *ndev = platform_get_drvdata(pdev);
	191	struct stmmac_priv *stpriv = NULL;
	192	int ret = 0;
	193
3c201b5a MV	194	if (!ndev)
	195	return -EINVAL;
	196
	197	stpriv = netdev_priv(ndev);
	198	if (!stpriv)
	199	return -EINVAL;
2d871aa0 VB	200
2d871aa0 VB	201	/* Assert reset to the enet controller before changing the phy mode */
3c201b5a MV	202	if (stpriv->stmmac_rst)
3c201b5a MV	203	reset_control_assert(stpriv->stmmac_rst);
2d871aa0 VB	204
	205	/* Setup the phy mode in the system manager registers according to
	206	* devicetree configuration
	207	*/
	208	ret = socfpga_dwmac_setup(dwmac);
	209
	210	/* Deassert reset for the phy configuration to be sampled by
	211	* the enet controller, and operation to start in requested mode
	212	*/
3c201b5a MV	213	if (stpriv->stmmac_rst)
3c201b5a MV	214	reset_control_deassert(stpriv->stmmac_rst);
2d871aa0 VB	215
	216	/* Before the enet controller is suspended, the phy is suspended.
	217	* This causes the phy clock to be gated. The enet controller is
	218	* resumed before the phy, so the clock is still gated "off" when
	219	* the enet controller is resumed. This code makes sure the phy
	220	* is "resumed" before reinitializing the enet controller since
	221	* the enet controller depends on an active phy clock to complete
	222	* a DMA reset. A DMA reset will "time out" if executed
	223	* with no phy clock input on the Synopsys enet controller.
	224	* Verified through Synopsys Case #8000711656.
	225	*
	226	* Note that the phy clock is also gated when the phy is isolated.
	227	* Phy "suspend" and "isolate" controls are located in phy basic
	228	* control register 0, and can be modified by the phy driver
	229	* framework.
	230	*/
3c201b5a	231	if (stpriv->phydev)
2d871aa0 VB	232	phy_resume(stpriv->phydev);
	233
	234	return ret;
	235	}
	236
8880b6c8	237	static int socfpga_dwmac_probe(struct platform_device *pdev)
82732789	238	{
8880b6c8 JE	239	struct plat_stmmacenet_data *plat_dat;
8880b6c8 JE	240	struct stmmac_resources stmmac_res;
82732789 JE	241	struct device *dev = &pdev->dev;
	242	int ret;
	243	struct socfpga_dwmac *dwmac;
	244
8880b6c8 JE	245	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
	246	if (ret)
	247	return ret;
	248
	249	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
	250	if (IS_ERR(plat_dat))
	251	return PTR_ERR(plat_dat);
	252
82732789 JE	253	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
82732789 JE	254	if (!dwmac)
8880b6c8	255	return -ENOMEM;
82732789 JE	256
	257	ret = socfpga_dwmac_parse_data(dwmac, dev);
	258	if (ret) {
	259	dev_err(dev, "Unable to parse OF data\n");
8880b6c8	260	return ret;
82732789 JE	261	}
	262
	263	ret = socfpga_dwmac_setup(dwmac);
	264	if (ret) {
	265	dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
8880b6c8	266	return ret;
82732789 JE	267	}
82732789 JE	268
8880b6c8 JE	269	plat_dat->bsp_priv = dwmac;
8880b6c8 JE	270	plat_dat->init = socfpga_dwmac_init;
8880b6c8	271	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
82732789	272
3c201b5a MV	273	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
	274	if (!ret)
	275	ret = socfpga_dwmac_init(pdev, dwmac);
8880b6c8	276
3c201b5a	277	return ret;
8880b6c8	278	}
c7c52ae7 JE	279
c7c52ae7 JE	280	static const struct of_device_id socfpga_dwmac_match[] = {
8880b6c8	281	{ .compatible = "altr,socfpga-stmmac" },
c7c52ae7 JE	282	{ }
	283	};
	284	MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
	285
	286	static struct platform_driver socfpga_dwmac_driver = {
8880b6c8	287	.probe = socfpga_dwmac_probe,
c7c52ae7 JE	288	.remove = stmmac_pltfr_remove,
	289	.driver = {
	290	.name = "socfpga-dwmac",
	291	.pm = &stmmac_pltfr_pm_ops,
	292	.of_match_table = socfpga_dwmac_match,
	293	},
	294	};
	295	module_platform_driver(socfpga_dwmac_driver);
	296
	297	MODULE_LICENSE("GPL v2");