[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / dwmac-socfpga.c

/* Copyright Altera Corporation (C) 2014. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2,
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Adopted from dwmac-sti.c
 */

#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/stmmac.h>

#include "stmmac.h"
#include "stmmac_platform.h"

#include "altr_tse_pcs.h"

#define SGMII_ADAPTER_CTRL_REG                          0x00
#define SGMII_ADAPTER_DISABLE                           0x0001

#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010

#define SYSMGR_FPGAGRP_MODULE_REG  0x00000028
#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004

#define EMAC_SPLITTER_CTRL_REG			0x0
#define EMAC_SPLITTER_CTRL_SPEED_MASK		0x3
#define EMAC_SPLITTER_CTRL_SPEED_10		0x2
#define EMAC_SPLITTER_CTRL_SPEED_100		0x3
#define EMAC_SPLITTER_CTRL_SPEED_1000		0x0

struct socfpga_dwmac {
	int	interface;
	u32	reg_offset;
	u32	reg_shift;
	struct	device *dev;
	struct regmap *sys_mgr_base_addr;
	struct reset_control *stmmac_rst;
	void __iomem *splitter_base;
	bool f2h_ptp_ref_clk;
	struct tse_pcs pcs;
};

static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
{
	struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
	void __iomem *splitter_base = dwmac->splitter_base;
	void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
	void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
	struct device *dev = dwmac->dev;
	struct net_device *ndev = dev_get_drvdata(dev);
	struct phy_device *phy_dev = ndev->phydev;
	u32 val;

	if ((tse_pcs_base) && (sgmii_adapter_base))
		writew(SGMII_ADAPTER_DISABLE,
		       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);

	if (splitter_base) {
		val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
		val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;

		switch (speed) {
		case 1000:
			val |= EMAC_SPLITTER_CTRL_SPEED_1000;
			break;
		case 100:
			val |= EMAC_SPLITTER_CTRL_SPEED_100;
			break;
		case 10:
			val |= EMAC_SPLITTER_CTRL_SPEED_10;
			break;
		default:
			return;
		}
		writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
	}

	if (tse_pcs_base && sgmii_adapter_base)
		tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
}

static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct regmap *sys_mgr_base_addr;
	u32 reg_offset, reg_shift;
	int ret, index;
	struct device_node *np_splitter = NULL;
	struct device_node *np_sgmii_adapter = NULL;
	struct resource res_splitter;
	struct resource res_tse_pcs;
	struct resource res_sgmii_adapter;

	dwmac->interface = of_get_phy_mode(np);

	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	if (IS_ERR(sys_mgr_base_addr)) {
		dev_info(dev, "No sysmgr-syscon node found\n");
		return PTR_ERR(sys_mgr_base_addr);
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	if (ret) {
		dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
		return -EINVAL;
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	if (ret) {
		dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
		return -EINVAL;
	}

	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");

	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
	if (np_splitter) {
		if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
			dev_info(dev, "Missing emac splitter address\n");
			return -EINVAL;
		}

		dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
		if (IS_ERR(dwmac->splitter_base)) {
			dev_info(dev, "Failed to mapping emac splitter\n");
			return PTR_ERR(dwmac->splitter_base);
		}
	}

	np_sgmii_adapter = of_parse_phandle(np,
					    "altr,gmii-to-sgmii-converter", 0);
	if (np_sgmii_adapter) {
		index = of_property_match_string(np_sgmii_adapter, "reg-names",
						 "hps_emac_interface_splitter_avalon_slave");

		if (index >= 0) {
			if (of_address_to_resource(np_sgmii_adapter, index,
						   &res_splitter)) {
				dev_err(dev,
					"%s: ERROR: missing emac splitter address\n",
					__func__);
				return -EINVAL;
			}

			dwmac->splitter_base =
			    devm_ioremap_resource(dev, &res_splitter);

			if (IS_ERR(dwmac->splitter_base)) {
				dev_err(dev,
					"%s: ERROR: failed mapping emac splitter\n",
					__func__);
				return PTR_ERR(dwmac->splitter_base);
			}
		}

		index = of_property_match_string(np_sgmii_adapter, "reg-names",
						 "gmii_to_sgmii_adapter_avalon_slave");

		if (index >= 0) {
			if (of_address_to_resource(np_sgmii_adapter, index,
						   &res_sgmii_adapter)) {
				dev_err(dev,
					"%s: ERROR: failed mapping adapter\n",
					__func__);
				return -EINVAL;
			}

			dwmac->pcs.sgmii_adapter_base =
			    devm_ioremap_resource(dev, &res_sgmii_adapter);

			if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
				dev_err(dev, "%s: failed to mapping adapter\n",
					__func__);
				return PTR_ERR(dwmac->pcs.sgmii_adapter_base);
			}
		}

		index = of_property_match_string(np_sgmii_adapter, "reg-names",
						 "eth_tse_control_port");

		if (index >= 0) {
			if (of_address_to_resource(np_sgmii_adapter, index,
						   &res_tse_pcs)) {
				dev_err(dev,
					"%s: ERROR: failed mapping tse control port\n",
					__func__);
				return -EINVAL;
			}

			dwmac->pcs.tse_pcs_base =
			    devm_ioremap_resource(dev, &res_tse_pcs);

			if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
				dev_err(dev,
					"%s: ERROR: failed mapping tse control port\n",
					__func__);
				return PTR_ERR(dwmac->pcs.sgmii_adapter_base);
			}
		}
	}
	dwmac->reg_offset = reg_offset;
	dwmac->reg_shift = reg_shift;
	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	dwmac->dev = dev;

	return 0;
}

static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
{
	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	int phymode = dwmac->interface;
	u32 reg_offset = dwmac->reg_offset;
	u32 reg_shift = dwmac->reg_shift;
	u32 ctrl, val, module;

	switch (phymode) {
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
		break;
	case PHY_INTERFACE_MODE_MII:
	case PHY_INTERFACE_MODE_GMII:
	case PHY_INTERFACE_MODE_SGMII:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
		break;
	default:
		dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
		return -EINVAL;
	}

	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	 * is the actual phy mode on phy hardware, but phy interface from
	 * EMAC core is GMII.
	 */
	if (dwmac->splitter_base)
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;

	/* Assert reset to the enet controller before changing the phy mode */
	if (dwmac->stmmac_rst)
		reset_control_assert(dwmac->stmmac_rst);

	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	ctrl |= val << reg_shift;

	if (dwmac->f2h_ptp_ref_clk) {
		ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
		regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
			    &module);
		module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
		regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
			     module);
	} else {
		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
	}

	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);

	/* Deassert reset for the phy configuration to be sampled by
	 * the enet controller, and operation to start in requested mode
	 */
	if (dwmac->stmmac_rst)
		reset_control_deassert(dwmac->stmmac_rst);
	if (phymode == PHY_INTERFACE_MODE_SGMII) {
		if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
			dev_err(dwmac->dev, "Unable to initialize TSE PCS");
			return -EINVAL;
		}
	}

	return 0;
}

static int socfpga_dwmac_probe(struct platform_device *pdev)
{
	struct plat_stmmacenet_data *plat_dat;
	struct stmmac_resources stmmac_res;
	struct device		*dev = &pdev->dev;
	int			ret;
	struct socfpga_dwmac	*dwmac;

	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
	if (ret)
		return ret;

	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
	if (IS_ERR(plat_dat))
		return PTR_ERR(plat_dat);

	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
	if (!dwmac)
		return -ENOMEM;

	ret = socfpga_dwmac_parse_data(dwmac, dev);
	if (ret) {
		dev_err(dev, "Unable to parse OF data\n");
		return ret;
	}

	plat_dat->bsp_priv = dwmac;
	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;

	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);

	if (!ret) {
		struct net_device *ndev = platform_get_drvdata(pdev);
		struct stmmac_priv *stpriv = netdev_priv(ndev);

		/* The socfpga driver needs to control the stmmac reset to
		 * set the phy mode. Create a copy of the core reset handel
		 * so it can be used by the driver later.
		 */
		dwmac->stmmac_rst = stpriv->stmmac_rst;

		ret = socfpga_dwmac_set_phy_mode(dwmac);
	}

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int socfpga_dwmac_resume(struct device *dev)
{
	struct net_device *ndev = dev_get_drvdata(dev);
	struct stmmac_priv *priv = netdev_priv(ndev);

	socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);

	/* Before the enet controller is suspended, the phy is suspended.
	 * This causes the phy clock to be gated. The enet controller is
	 * resumed before the phy, so the clock is still gated "off" when
	 * the enet controller is resumed. This code makes sure the phy
	 * is "resumed" before reinitializing the enet controller since
	 * the enet controller depends on an active phy clock to complete
	 * a DMA reset. A DMA reset will "time out" if executed
	 * with no phy clock input on the Synopsys enet controller.
	 * Verified through Synopsys Case #8000711656.
	 *
	 * Note that the phy clock is also gated when the phy is isolated.
	 * Phy "suspend" and "isolate" controls are located in phy basic
	 * control register 0, and can be modified by the phy driver
	 * framework.
	 */
	if (priv->phydev)
		phy_resume(priv->phydev);

	return stmmac_resume(dev);
}
#endif /* CONFIG_PM_SLEEP */

static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
					       socfpga_dwmac_resume);

static const struct of_device_id socfpga_dwmac_match[] = {
	{ .compatible = "altr,socfpga-stmmac" },
	{ }
};
MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);

static struct platform_driver socfpga_dwmac_driver = {
	.probe  = socfpga_dwmac_probe,
	.remove = stmmac_pltfr_remove,
	.driver = {
		.name           = "socfpga-dwmac",
		.pm		= &socfpga_dwmac_pm_ops,
		.of_match_table = socfpga_dwmac_match,
	},
};
module_platform_driver(socfpga_dwmac_driver);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
801d233b DN	1	/* Copyright Altera Corporation (C) 2014. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License, version 2,
	5	* as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	14	*
	15	* Adopted from dwmac-sti.c
	16	*/
	17
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/of.h>
b4834c86	20	#include <linux/of_address.h>
801d233b DN	21	#include <linux/of_net.h>
	22	#include <linux/phy.h>
	23	#include <linux/regmap.h>
2d871aa0	24	#include <linux/reset.h>
801d233b	25	#include <linux/stmmac.h>
f10f9fb2	26
2d871aa0	27	#include "stmmac.h"
f10f9fb2	28	#include "stmmac_platform.h"
801d233b	29
fb3bbdb8 THL	30	#include "altr_tse_pcs.h"
	31
	32	#define SGMII_ADAPTER_CTRL_REG 0x00
	33	#define SGMII_ADAPTER_DISABLE 0x0001
	34
801d233b DN	35	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
	36	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
	37	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
	38	#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
	39	#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
43569814	40	#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
801d233b	41
734e00fa PR	42	#define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
	43	#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
	44
b4834c86 LFT	45	#define EMAC_SPLITTER_CTRL_REG 0x0
	46	#define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
	47	#define EMAC_SPLITTER_CTRL_SPEED_10 0x2
	48	#define EMAC_SPLITTER_CTRL_SPEED_100 0x3
	49	#define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
	50
801d233b DN	51	struct socfpga_dwmac {
	52	int interface;
	53	u32 reg_offset;
	54	u32 reg_shift;
	55	struct device *dev;
	56	struct regmap *sys_mgr_base_addr;
70cb136f	57	struct reset_control *stmmac_rst;
b4834c86	58	void __iomem *splitter_base;
43569814	59	bool f2h_ptp_ref_clk;
fb3bbdb8	60	struct tse_pcs pcs;
801d233b DN	61	};
801d233b DN	62
b4834c86 LFT	63	static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
	64	{
	65	struct socfpga_dwmac dwmac = (struct socfpga_dwmac )priv;
	66	void __iomem *splitter_base = dwmac->splitter_base;
fb3bbdb8 THL	67	void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
	68	void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
	69	struct device *dev = dwmac->dev;
	70	struct net_device *ndev = dev_get_drvdata(dev);
	71	struct phy_device *phy_dev = ndev->phydev;
b4834c86 LFT	72	u32 val;
b4834c86 LFT	73
fb3bbdb8 THL	74	if ((tse_pcs_base) && (sgmii_adapter_base))
	75	writew(SGMII_ADAPTER_DISABLE,
	76	sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
	77
	78	if (splitter_base) {
	79	val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
	80	val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
	81
	82	switch (speed) {
	83	case 1000:
	84	val \|= EMAC_SPLITTER_CTRL_SPEED_1000;
	85	break;
	86	case 100:
	87	val \|= EMAC_SPLITTER_CTRL_SPEED_100;
	88	break;
	89	case 10:
	90	val \|= EMAC_SPLITTER_CTRL_SPEED_10;
	91	break;
	92	default:
	93	return;
	94	}
	95	writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
b4834c86 LFT	96	}
b4834c86 LFT	97
fb3bbdb8 THL	98	if (tse_pcs_base && sgmii_adapter_base)
fb3bbdb8 THL	99	tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
b4834c86 LFT	100	}
b4834c86 LFT	101
801d233b DN	102	static int socfpga_dwmac_parse_data(struct socfpga_dwmac dwmac, struct device dev)
	103	{
	104	struct device_node *np = dev->of_node;
	105	struct regmap *sys_mgr_base_addr;
	106	u32 reg_offset, reg_shift;
fb3bbdb8 THL	107	int ret, index;
	108	struct device_node *np_splitter = NULL;
	109	struct device_node *np_sgmii_adapter = NULL;
b4834c86	110	struct resource res_splitter;
fb3bbdb8 THL	111	struct resource res_tse_pcs;
fb3bbdb8 THL	112	struct resource res_sgmii_adapter;
801d233b DN	113
	114	dwmac->interface = of_get_phy_mode(np);
	115
	116	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	117	if (IS_ERR(sys_mgr_base_addr)) {
	118	dev_info(dev, "No sysmgr-syscon node found\n");
	119	return PTR_ERR(sys_mgr_base_addr);
	120	}
	121
	122	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	123	if (ret) {
	124	dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
	125	return -EINVAL;
	126	}
	127
	128	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	129	if (ret) {
	130	dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
	131	return -EINVAL;
	132	}
	133
43569814 PR	134	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
43569814 PR	135
b4834c86 LFT	136	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
	137	if (np_splitter) {
	138	if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
	139	dev_info(dev, "Missing emac splitter address\n");
	140	return -EINVAL;
	141	}
	142
dace1b54	143	dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
f19f916d	144	if (IS_ERR(dwmac->splitter_base)) {
b4834c86	145	dev_info(dev, "Failed to mapping emac splitter\n");
f19f916d	146	return PTR_ERR(dwmac->splitter_base);
b4834c86 LFT	147	}
	148	}
	149
fb3bbdb8 THL	150	np_sgmii_adapter = of_parse_phandle(np,
	151	"altr,gmii-to-sgmii-converter", 0);
	152	if (np_sgmii_adapter) {
	153	index = of_property_match_string(np_sgmii_adapter, "reg-names",
	154	"hps_emac_interface_splitter_avalon_slave");
	155
	156	if (index >= 0) {
	157	if (of_address_to_resource(np_sgmii_adapter, index,
	158	&res_splitter)) {
	159	dev_err(dev,
	160	"%s: ERROR: missing emac splitter address\n",
	161	__func__);
	162	return -EINVAL;
	163	}
	164
	165	dwmac->splitter_base =
	166	devm_ioremap_resource(dev, &res_splitter);
	167
	168	if (IS_ERR(dwmac->splitter_base)) {
	169	dev_err(dev,
	170	"%s: ERROR: failed mapping emac splitter\n",
	171	__func__);
	172	return PTR_ERR(dwmac->splitter_base);
	173	}
	174	}
	175
	176	index = of_property_match_string(np_sgmii_adapter, "reg-names",
	177	"gmii_to_sgmii_adapter_avalon_slave");
	178
	179	if (index >= 0) {
	180	if (of_address_to_resource(np_sgmii_adapter, index,
	181	&res_sgmii_adapter)) {
	182	dev_err(dev,
	183	"%s: ERROR: failed mapping adapter\n",
	184	__func__);
	185	return -EINVAL;
	186	}
	187
	188	dwmac->pcs.sgmii_adapter_base =
	189	devm_ioremap_resource(dev, &res_sgmii_adapter);
	190
	191	if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
	192	dev_err(dev, "%s: failed to mapping adapter\n",
	193	__func__);
	194	return PTR_ERR(dwmac->pcs.sgmii_adapter_base);
	195	}
	196	}
	197
	198	index = of_property_match_string(np_sgmii_adapter, "reg-names",
	199	"eth_tse_control_port");
	200
	201	if (index >= 0) {
	202	if (of_address_to_resource(np_sgmii_adapter, index,
	203	&res_tse_pcs)) {
	204	dev_err(dev,
	205	"%s: ERROR: failed mapping tse control port\n",
	206	__func__);
	207	return -EINVAL;
	208	}
	209
	210	dwmac->pcs.tse_pcs_base =
	211	devm_ioremap_resource(dev, &res_tse_pcs);
	212
	213	if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
214	dev_err(dev,
215	"%s: ERROR: failed mapping tse control port\n",
216	__func__);
217	return PTR_ERR(dwmac->pcs.sgmii_adapter_base);
218	}
219	}
220	}
801d233b DN	221	dwmac->reg_offset = reg_offset;
	222	dwmac->reg_shift = reg_shift;
	223	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	224	dwmac->dev = dev;
	225
	226	return 0;
	227	}
	228
0f400a87	229	static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
801d233b DN	230	{
	231	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	232	int phymode = dwmac->interface;
	233	u32 reg_offset = dwmac->reg_offset;
	234	u32 reg_shift = dwmac->reg_shift;
734e00fa	235	u32 ctrl, val, module;
801d233b DN	236
	237	switch (phymode) {
	238	case PHY_INTERFACE_MODE_RGMII:
b4834c86	239	case PHY_INTERFACE_MODE_RGMII_ID:
801d233b DN	240	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
	241	break;
	242	case PHY_INTERFACE_MODE_MII:
	243	case PHY_INTERFACE_MODE_GMII:
fb3bbdb8	244	case PHY_INTERFACE_MODE_SGMII:
801d233b DN	245	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	246	break;
	247	default:
	248	dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
	249	return -EINVAL;
	250	}
	251
b4834c86 LFT	252	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	253	* is the actual phy mode on phy hardware, but phy interface from
	254	* EMAC core is GMII.
	255	*/
	256	if (dwmac->splitter_base)
	257	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	258
70cb136f JE	259	/* Assert reset to the enet controller before changing the phy mode */
	260	if (dwmac->stmmac_rst)
	261	reset_control_assert(dwmac->stmmac_rst);
	262
801d233b DN	263	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	264	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	265	ctrl \|= val << reg_shift;
	266
734e00fa	267	if (dwmac->f2h_ptp_ref_clk) {
43569814	268	ctrl \|= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
734e00fa PR	269	regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
	270	&module);
	271	module \|= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
	272	regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
	273	module);
	274	} else {
43569814	275	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
734e00fa	276	}
43569814	277
801d233b	278	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
734e00fa	279
70cb136f JE	280	/* Deassert reset for the phy configuration to be sampled by
	281	* the enet controller, and operation to start in requested mode
	282	*/
	283	if (dwmac->stmmac_rst)
	284	reset_control_deassert(dwmac->stmmac_rst);
fb3bbdb8 THL	285	if (phymode == PHY_INTERFACE_MODE_SGMII) {
	286	if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
	287	dev_err(dwmac->dev, "Unable to initialize TSE PCS");
	288	return -EINVAL;
	289	}
	290	}
70cb136f	291
801d233b DN	292	return 0;
	293	}
	294
8880b6c8	295	static int socfpga_dwmac_probe(struct platform_device *pdev)
82732789	296	{
8880b6c8 JE	297	struct plat_stmmacenet_data *plat_dat;
8880b6c8 JE	298	struct stmmac_resources stmmac_res;
82732789 JE	299	struct device *dev = &pdev->dev;
	300	int ret;
	301	struct socfpga_dwmac *dwmac;
	302
8880b6c8 JE	303	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
	304	if (ret)
	305	return ret;
	306
	307	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
	308	if (IS_ERR(plat_dat))
	309	return PTR_ERR(plat_dat);
	310
82732789 JE	311	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
82732789 JE	312	if (!dwmac)
8880b6c8	313	return -ENOMEM;
82732789 JE	314
	315	ret = socfpga_dwmac_parse_data(dwmac, dev);
	316	if (ret) {
	317	dev_err(dev, "Unable to parse OF data\n");
8880b6c8	318	return ret;
82732789 JE	319	}
82732789 JE	320
8880b6c8	321	plat_dat->bsp_priv = dwmac;
8880b6c8	322	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
82732789	323
3c201b5a	324	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
fb3bbdb8	325
70cb136f JE	326	if (!ret) {
	327	struct net_device *ndev = platform_get_drvdata(pdev);
	328	struct stmmac_priv *stpriv = netdev_priv(ndev);
	329
	330	/* The socfpga driver needs to control the stmmac reset to
	331	* set the phy mode. Create a copy of the core reset handel
	332	* so it can be used by the driver later.
	333	*/
	334	dwmac->stmmac_rst = stpriv->stmmac_rst;
	335
0f400a87	336	ret = socfpga_dwmac_set_phy_mode(dwmac);
70cb136f	337	}
8880b6c8	338
3c201b5a	339	return ret;
8880b6c8	340	}
c7c52ae7	341
56868dee JE	342	#ifdef CONFIG_PM_SLEEP
	343	static int socfpga_dwmac_resume(struct device *dev)
	344	{
56868dee JE	345	struct net_device *ndev = dev_get_drvdata(dev);
	346	struct stmmac_priv *priv = netdev_priv(ndev);
	347
0f400a87	348	socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);
56868dee	349
53737247 JE	350	/* Before the enet controller is suspended, the phy is suspended.
	351	* This causes the phy clock to be gated. The enet controller is
	352	* resumed before the phy, so the clock is still gated "off" when
	353	* the enet controller is resumed. This code makes sure the phy
	354	* is "resumed" before reinitializing the enet controller since
	355	* the enet controller depends on an active phy clock to complete
	356	* a DMA reset. A DMA reset will "time out" if executed
	357	* with no phy clock input on the Synopsys enet controller.
	358	* Verified through Synopsys Case #8000711656.
	359	*
	360	* Note that the phy clock is also gated when the phy is isolated.
	361	* Phy "suspend" and "isolate" controls are located in phy basic
	362	* control register 0, and can be modified by the phy driver
	363	* framework.
	364	*/
	365	if (priv->phydev)
	366	phy_resume(priv->phydev);
	367
56868dee JE	368	return stmmac_resume(dev);
	369	}
	370	#endif /* CONFIG_PM_SLEEP */
	371
bfca2eba JE	372	static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
bfca2eba JE	373	socfpga_dwmac_resume);
56868dee	374
c7c52ae7	375	static const struct of_device_id socfpga_dwmac_match[] = {
8880b6c8	376	{ .compatible = "altr,socfpga-stmmac" },
c7c52ae7 JE	377	{ }
	378	};
	379	MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
	380
	381	static struct platform_driver socfpga_dwmac_driver = {
8880b6c8	382	.probe = socfpga_dwmac_probe,
c7c52ae7 JE	383	.remove = stmmac_pltfr_remove,
	384	.driver = {
	385	.name = "socfpga-dwmac",
56868dee	386	.pm = &socfpga_dwmac_pm_ops,
c7c52ae7 JE	387	.of_match_table = socfpga_dwmac_match,
	388	},
	389	};
	390	module_platform_driver(socfpga_dwmac_driver);
	391
	392	MODULE_LICENSE("GPL v2");