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sch_sfq: rehash queues in perturb timer
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
01789349 44#include <linux/if.h>
47dd7a54
GC		 45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
5a0e3ad6 47#include <linux/slab.h>
70c71606 48#include <linux/prefetch.h>
7ac29055
GC		 49#ifdef CONFIG_STMMAC_DEBUG_FS
50#include <linux/debugfs.h>
51#include <linux/seq_file.h>
52#endif
286a8372 53#include "stmmac.h"
47dd7a54
GC		 54
55#define STMMAC_RESOURCE_NAME "stmmaceth"
47dd7a54
GC		 56
57#undef STMMAC_DEBUG
58/*#define STMMAC_DEBUG*/
59#ifdef STMMAC_DEBUG
60#define DBG(nlevel, klevel, fmt, args...) \
61 ((void)(netif_msg_##nlevel(priv) && \
62 printk(KERN_##klevel fmt, ## args)))
63#else
64#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
65#endif
66
67#undef STMMAC_RX_DEBUG
68/*#define STMMAC_RX_DEBUG*/
69#ifdef STMMAC_RX_DEBUG
70#define RX_DBG(fmt, args...) printk(fmt, ## args)
71#else
72#define RX_DBG(fmt, args...) do { } while (0)
73#endif
74
75#undef STMMAC_XMIT_DEBUG
76/*#define STMMAC_XMIT_DEBUG*/
77#ifdef STMMAC_TX_DEBUG
78#define TX_DBG(fmt, args...) printk(fmt, ## args)
79#else
80#define TX_DBG(fmt, args...) do { } while (0)
81#endif
82
83#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
84#define JUMBO_LEN 9000
85
86/* Module parameters */
87#define TX_TIMEO 5000 /* default 5 seconds */
88static int watchdog = TX_TIMEO;
89module_param(watchdog, int, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
91
92static int debug = -1; /* -1: default, 0: no output, 16: all */
93module_param(debug, int, S_IRUGO | S_IWUSR);
94MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
95
96static int phyaddr = -1;
97module_param(phyaddr, int, S_IRUGO);
98MODULE_PARM_DESC(phyaddr, "Physical device address");
99
100#define DMA_TX_SIZE 256
101static int dma_txsize = DMA_TX_SIZE;
102module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
103MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
104
105#define DMA_RX_SIZE 256
106static int dma_rxsize = DMA_RX_SIZE;
107module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
108MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
109
110static int flow_ctrl = FLOW_OFF;
111module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
112MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
113
114static int pause = PAUSE_TIME;
115module_param(pause, int, S_IRUGO | S_IWUSR);
116MODULE_PARM_DESC(pause, "Flow Control Pause Time");
117
118#define TC_DEFAULT 64
119static int tc = TC_DEFAULT;
120module_param(tc, int, S_IRUGO | S_IWUSR);
121MODULE_PARM_DESC(tc, "DMA threshold control value");
122
47dd7a54
GC		 123/* Pay attention to tune this parameter; take care of both
124 * hardware capability and network stabitily/performance impact.
125 * Many tests showed that ~4ms latency seems to be good enough. */
126#ifdef CONFIG_STMMAC_TIMER
127#define DEFAULT_PERIODIC_RATE 256
128static int tmrate = DEFAULT_PERIODIC_RATE;
129module_param(tmrate, int, S_IRUGO | S_IWUSR);
130MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
131#endif
132
133#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
134static int buf_sz = DMA_BUFFER_SIZE;
135module_param(buf_sz, int, S_IRUGO | S_IWUSR);
136MODULE_PARM_DESC(buf_sz, "DMA buffer size");
137
47dd7a54
GC		 138static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
139 NETIF_MSG_LINK | NETIF_MSG_IFUP |
140 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
141
142static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54
GC		 143
144/**
145 * stmmac_verify_args - verify the driver parameters.
146 * Description: it verifies if some wrong parameter is passed to the driver.
147 * Note that wrong parameters are replaced with the default values.
148 */
149static void stmmac_verify_args(void)
150{
151 if (unlikely(watchdog < 0))
152 watchdog = TX_TIMEO;
153 if (unlikely(dma_rxsize < 0))
154 dma_rxsize = DMA_RX_SIZE;
155 if (unlikely(dma_txsize < 0))
156 dma_txsize = DMA_TX_SIZE;
157 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
158 buf_sz = DMA_BUFFER_SIZE;
159 if (unlikely(flow_ctrl > 1))
160 flow_ctrl = FLOW_AUTO;
161 else if (likely(flow_ctrl < 0))
162 flow_ctrl = FLOW_OFF;
163 if (unlikely((pause < 0) || (pause > 0xffff)))
164 pause = PAUSE_TIME;
47dd7a54
GC		 165}
166
167#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
168static void print_pkt(unsigned char *buf, int len)
169{
170 int j;
171 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
172 for (j = 0; j < len; j++) {
173 if ((j % 16) == 0)
174 pr_info("\n %03x:", j);
175 pr_info(" %02x", buf[j]);
176 }
177 pr_info("\n");
47dd7a54
GC		 178}
179#endif
180
181/* minimum number of free TX descriptors required to wake up TX process */
182#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183
184static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
185{
186 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
187}
188
9dfeb4d9
GC		 189/* On some ST platforms, some HW system configuraton registers have to be
190 * set according to the link speed negotiated.
191 */
192static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
193{
194 struct phy_device *phydev = priv->phydev;
195
196 if (likely(priv->plat->fix_mac_speed))
197 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
198 phydev->speed);
199}
200
47dd7a54
GC		 201/**
202 * stmmac_adjust_link
203 * @dev: net device structure
204 * Description: it adjusts the link parameters.
205 */
206static void stmmac_adjust_link(struct net_device *dev)
207{
208 struct stmmac_priv *priv = netdev_priv(dev);
209 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 210 unsigned long flags;
211 int new_state = 0;
212 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
213
214 if (phydev == NULL)
215 return;
216
217 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
218 phydev->addr, phydev->link);
219
220 spin_lock_irqsave(&priv->lock, flags);
221 if (phydev->link) {
ad01b7d4 222 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 223
224 /* Now we make sure that we can be in full duplex mode.
225 * If not, we operate in half-duplex mode. */
226 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1;
228 if (!(phydev->duplex))
db98a0b0 229 ctrl &= ~priv->hw->link.duplex;
47dd7a54 230 else
db98a0b0 231 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 232 priv->oldduplex = phydev->duplex;
233 }
234 /* Flow Control operation */
235 if (phydev->pause)
ad01b7d4 236 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 237 fc, pause_time);
47dd7a54
GC		 238
239 if (phydev->speed != priv->speed) {
240 new_state = 1;
241 switch (phydev->speed) {
242 case 1000:
9dfeb4d9 243 if (likely(priv->plat->has_gmac))
db98a0b0 244 ctrl &= ~priv->hw->link.port;
9dfeb4d9 245 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 246 break;
247 case 100:
248 case 10:
9dfeb4d9 249 if (priv->plat->has_gmac) {
db98a0b0 250 ctrl |= priv->hw->link.port;
47dd7a54 251 if (phydev->speed == SPEED_100) {
db98a0b0 252 ctrl |= priv->hw->link.speed;
47dd7a54 253 } else {
db98a0b0 254 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 255 }
256 } else {
db98a0b0 257 ctrl &= ~priv->hw->link.port;
47dd7a54 258 }
9dfeb4d9 259 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 260 break;
261 default:
262 if (netif_msg_link(priv))
263 pr_warning("%s: Speed (%d) is not 10"
264 " or 100!\n", dev->name, phydev->speed);
265 break;
266 }
267
268 priv->speed = phydev->speed;
269 }
270
ad01b7d4 271 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 272
273 if (!priv->oldlink) {
274 new_state = 1;
275 priv->oldlink = 1;
276 }
277 } else if (priv->oldlink) {
278 new_state = 1;
279 priv->oldlink = 0;
280 priv->speed = 0;
281 priv->oldduplex = -1;
282 }
283
284 if (new_state && netif_msg_link(priv))
285 phy_print_status(phydev);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
290}
291
292/**
293 * stmmac_init_phy - PHY initialization
294 * @dev: net device structure
295 * Description: it initializes the driver's PHY state, and attaches the PHY
296 * to the mac driver.
297 * Return value:
298 * 0 on success
299 */
300static int stmmac_init_phy(struct net_device *dev)
301{
302 struct stmmac_priv *priv = netdev_priv(dev);
303 struct phy_device *phydev;
109cdd66
GC		 304 char phy_id[MII_BUS_ID_SIZE + 3];
305 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 306 int interface = priv->plat->interface;
47dd7a54
GC		 307 priv->oldlink = 0;
308 priv->speed = 0;
309 priv->oldduplex = -1;
310
9dfeb4d9 311 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
109cdd66 312 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 313 priv->plat->phy_addr);
47dd7a54
GC		 314 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
315
79ee1dc3 316 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
47dd7a54
GC		 317
318 if (IS_ERR(phydev)) {
319 pr_err("%s: Could not attach to PHY\n", dev->name);
320 return PTR_ERR(phydev);
321 }
322
79ee1dc3 323 /* Stop Advertising 1000BASE Capability if interface is not GMII */
c5b9b4e4
SK		 324 if ((interface == PHY_INTERFACE_MODE_MII) ||
325 (interface == PHY_INTERFACE_MODE_RMII))
326 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
327 SUPPORTED_1000baseT_Full);
79ee1dc3 328
47dd7a54
GC		 329 /*
330 * Broken HW is sometimes missing the pull-up resistor on the
331 * MDIO line, which results in reads to non-existent devices returning
332 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
333 * device as well.
334 * Note: phydev->phy_id is the result of reading the UID PHY registers.
335 */
336 if (phydev->phy_id == 0) {
337 phy_disconnect(phydev);
338 return -ENODEV;
339 }
340 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 341 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 342
343 priv->phydev = phydev;
344
345 return 0;
346}
347
19449bfc 348static inline void stmmac_enable_mac(void __iomem *ioaddr)
47dd7a54
GC		 349{
350 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 351
19449bfc 352 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
47dd7a54
GC		 353 writel(value, ioaddr + MAC_CTRL_REG);
354}
355
19449bfc 356static inline void stmmac_disable_mac(void __iomem *ioaddr)
47dd7a54
GC		 357{
358 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 359
19449bfc 360 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
47dd7a54
GC		 361 writel(value, ioaddr + MAC_CTRL_REG);
362}
363
364/**
365 * display_ring
366 * @p: pointer to the ring.
367 * @size: size of the ring.
368 * Description: display all the descriptors within the ring.
369 */
370static void display_ring(struct dma_desc *p, int size)
371{
372 struct tmp_s {
373 u64 a;
374 unsigned int b;
375 unsigned int c;
376 };
377 int i;
378 for (i = 0; i < size; i++) {
379 struct tmp_s *x = (struct tmp_s *)(p + i);
380 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
381 i, (unsigned int)virt_to_phys(&p[i]),
382 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
383 x->b, x->c);
384 pr_info("\n");
385 }
386}
387
286a8372
GC		 388static int stmmac_set_bfsize(int mtu, int bufsize)
389{
390 int ret = bufsize;
391
392 if (mtu >= BUF_SIZE_4KiB)
393 ret = BUF_SIZE_8KiB;
394 else if (mtu >= BUF_SIZE_2KiB)
395 ret = BUF_SIZE_4KiB;
396 else if (mtu >= DMA_BUFFER_SIZE)
397 ret = BUF_SIZE_2KiB;
398 else
399 ret = DMA_BUFFER_SIZE;
400
401 return ret;
402}
403
47dd7a54
GC		 404/**
405 * init_dma_desc_rings - init the RX/TX descriptor rings
406 * @dev: net device structure
407 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 408 * and allocates the socket buffers. It suppors the chained and ring
409 * modes.
47dd7a54
GC		 410 */
411static void init_dma_desc_rings(struct net_device *dev)
412{
413 int i;
414 struct stmmac_priv *priv = netdev_priv(dev);
415 struct sk_buff *skb;
416 unsigned int txsize = priv->dma_tx_size;
417 unsigned int rxsize = priv->dma_rx_size;
286a8372
GC		 418 unsigned int bfsize;
419 int dis_ic = 0;
420 int des3_as_data_buf = 0;
47dd7a54 421
286a8372
GC		 422 /* Set the max buffer size according to the DESC mode
423 * and the MTU. Note that RING mode allows 16KiB bsize. */
424 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
425
426 if (bfsize == BUF_SIZE_16KiB)
427 des3_as_data_buf = 1;
47dd7a54 428 else
286a8372 429 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 430
73cfe264
GC		 431#ifdef CONFIG_STMMAC_TIMER
432 /* Disable interrupts on completion for the reception if timer is on */
433 if (likely(priv->tm->enable))
434 dis_ic = 1;
435#endif
47dd7a54
GC		 436
437 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
438 txsize, rxsize, bfsize);
439
440 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
441 priv->rx_skbuff =
442 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
443 priv->dma_rx =
444 (struct dma_desc *)dma_alloc_coherent(priv->device,
445 rxsize *
446 sizeof(struct dma_desc),
447 &priv->dma_rx_phy,
448 GFP_KERNEL);
449 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
450 GFP_KERNEL);
451 priv->dma_tx =
452 (struct dma_desc *)dma_alloc_coherent(priv->device,
453 txsize *
454 sizeof(struct dma_desc),
455 &priv->dma_tx_phy,
456 GFP_KERNEL);
457
458 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
459 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
460 return;
461 }
462
286a8372 463 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
47dd7a54
GC		 464 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
465 dev->name, priv->dma_rx, priv->dma_tx,
466 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
467
468 /* RX INITIALIZATION */
469 DBG(probe, INFO, "stmmac: SKB addresses:\n"
470 "skb\t\tskb data\tdma data\n");
471
472 for (i = 0; i < rxsize; i++) {
473 struct dma_desc *p = priv->dma_rx + i;
474
45db81e1
GC		 475 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
476 GFP_KERNEL);
47dd7a54
GC		 477 if (unlikely(skb == NULL)) {
478 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
479 break;
480 }
45db81e1 481 skb_reserve(skb, NET_IP_ALIGN);
47dd7a54
GC		 482 priv->rx_skbuff[i] = skb;
483 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
484 bfsize, DMA_FROM_DEVICE);
485
486 p->des2 = priv->rx_skbuff_dma[i];
286a8372
GC		 487
488 priv->hw->ring->init_desc3(des3_as_data_buf, p);
489
47dd7a54
GC		 490 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
491 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
492 }
493 priv->cur_rx = 0;
494 priv->dirty_rx = (unsigned int)(i - rxsize);
495 priv->dma_buf_sz = bfsize;
496 buf_sz = bfsize;
497
498 /* TX INITIALIZATION */
499 for (i = 0; i < txsize; i++) {
500 priv->tx_skbuff[i] = NULL;
501 priv->dma_tx[i].des2 = 0;
502 }
286a8372
GC		 503
504 /* In case of Chained mode this sets the des3 to the next
505 * element in the chain */
506 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
507 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
508
47dd7a54
GC		 509 priv->dirty_tx = 0;
510 priv->cur_tx = 0;
511
512 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 513 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
514 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 515
516 if (netif_msg_hw(priv)) {
517 pr_info("RX descriptor ring:\n");
518 display_ring(priv->dma_rx, rxsize);
519 pr_info("TX descriptor ring:\n");
520 display_ring(priv->dma_tx, txsize);
521 }
47dd7a54
GC		 522}
523
524static void dma_free_rx_skbufs(struct stmmac_priv *priv)
525{
526 int i;
527
528 for (i = 0; i < priv->dma_rx_size; i++) {
529 if (priv->rx_skbuff[i]) {
530 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
531 priv->dma_buf_sz, DMA_FROM_DEVICE);
532 dev_kfree_skb_any(priv->rx_skbuff[i]);
533 }
534 priv->rx_skbuff[i] = NULL;
535 }
47dd7a54
GC		 536}
537
538static void dma_free_tx_skbufs(struct stmmac_priv *priv)
539{
540 int i;
541
542 for (i = 0; i < priv->dma_tx_size; i++) {
543 if (priv->tx_skbuff[i] != NULL) {
544 struct dma_desc *p = priv->dma_tx + i;
545 if (p->des2)
546 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 547 priv->hw->desc->get_tx_len(p),
548 DMA_TO_DEVICE);
47dd7a54
GC		 549 dev_kfree_skb_any(priv->tx_skbuff[i]);
550 priv->tx_skbuff[i] = NULL;
551 }
552 }
47dd7a54
GC		 553}
554
555static void free_dma_desc_resources(struct stmmac_priv *priv)
556{
557 /* Release the DMA TX/RX socket buffers */
558 dma_free_rx_skbufs(priv);
559 dma_free_tx_skbufs(priv);
560
561 /* Free the region of consistent memory previously allocated for
562 * the DMA */
563 dma_free_coherent(priv->device,
564 priv->dma_tx_size * sizeof(struct dma_desc),
565 priv->dma_tx, priv->dma_tx_phy);
566 dma_free_coherent(priv->device,
567 priv->dma_rx_size * sizeof(struct dma_desc),
568 priv->dma_rx, priv->dma_rx_phy);
569 kfree(priv->rx_skbuff_dma);
570 kfree(priv->rx_skbuff);
571 kfree(priv->tx_skbuff);
47dd7a54
GC		 572}
573
47dd7a54
GC		 574/**
575 * stmmac_dma_operation_mode - HW DMA operation mode
576 * @priv : pointer to the private device structure.
577 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 578 * or Store-And-Forward capability.
47dd7a54
GC		 579 */
580static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
581{
61b8013a
SK		 582 if (likely(priv->plat->force_sf_dma_mode ||
583 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
584 /*
585 * In case of GMAC, SF mode can be enabled
586 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 587 * 1) TX COE if actually supported
588 * 2) There is no bugged Jumbo frame support
589 * that needs to not insert csum in the TDES.
590 */
591 priv->hw->dma->dma_mode(priv->ioaddr,
592 SF_DMA_MODE, SF_DMA_MODE);
593 tc = SF_DMA_MODE;
594 } else
595 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 596}
597
47dd7a54
GC		 598/**
599 * stmmac_tx:
600 * @priv: private driver structure
601 * Description: it reclaims resources after transmission completes.
602 */
603static void stmmac_tx(struct stmmac_priv *priv)
604{
605 unsigned int txsize = priv->dma_tx_size;
47dd7a54 606
a9097a96
GC		 607 spin_lock(&priv->tx_lock);
608
47dd7a54
GC		 609 while (priv->dirty_tx != priv->cur_tx) {
610 int last;
611 unsigned int entry = priv->dirty_tx % txsize;
612 struct sk_buff *skb = priv->tx_skbuff[entry];
613 struct dma_desc *p = priv->dma_tx + entry;
614
615 /* Check if the descriptor is owned by the DMA. */
db98a0b0 616 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 617 break;
618
619 /* Verify tx error by looking at the last segment */
db98a0b0 620 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 621 if (likely(last)) {
622 int tx_error =
db98a0b0
GC		 623 priv->hw->desc->tx_status(&priv->dev->stats,
624 &priv->xstats, p,
ad01b7d4 625 priv->ioaddr);
47dd7a54
GC		 626 if (likely(tx_error == 0)) {
627 priv->dev->stats.tx_packets++;
628 priv->xstats.tx_pkt_n++;
629 } else
630 priv->dev->stats.tx_errors++;
631 }
632 TX_DBG("%s: curr %d, dirty %d\n", __func__,
633 priv->cur_tx, priv->dirty_tx);
634
635 if (likely(p->des2))
636 dma_unmap_single(priv->device, p->des2,
db98a0b0 637 priv->hw->desc->get_tx_len(p),
47dd7a54 638 DMA_TO_DEVICE);
286a8372 639 priv->hw->ring->clean_desc3(p);
47dd7a54
GC		 640
641 if (likely(skb != NULL)) {
642 /*
643 * If there's room in the queue (limit it to size)
644 * we add this skb back into the pool,
645 * if it's the right size.
646 */
647 if ((skb_queue_len(&priv->rx_recycle) <
648 priv->dma_rx_size) &&
649 skb_recycle_check(skb, priv->dma_buf_sz))
650 __skb_queue_head(&priv->rx_recycle, skb);
651 else
652 dev_kfree_skb(skb);
653
654 priv->tx_skbuff[entry] = NULL;
655 }
656
db98a0b0 657 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 658
659 entry = (++priv->dirty_tx) % txsize;
660 }
661 if (unlikely(netif_queue_stopped(priv->dev) &&
662 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
663 netif_tx_lock(priv->dev);
664 if (netif_queue_stopped(priv->dev) &&
665 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
666 TX_DBG("%s: restart transmit\n", __func__);
667 netif_wake_queue(priv->dev);
668 }
669 netif_tx_unlock(priv->dev);
670 }
a9097a96 671 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 672}
673
674static inline void stmmac_enable_irq(struct stmmac_priv *priv)
675{
73cfe264
GC		 676#ifdef CONFIG_STMMAC_TIMER
677 if (likely(priv->tm->enable))
678 priv->tm->timer_start(tmrate);
679 else
47dd7a54 680#endif
ad01b7d4 681 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 682}
683
684static inline void stmmac_disable_irq(struct stmmac_priv *priv)
685{
73cfe264
GC		 686#ifdef CONFIG_STMMAC_TIMER
687 if (likely(priv->tm->enable))
688 priv->tm->timer_stop();
689 else
47dd7a54 690#endif
ad01b7d4 691 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 692}
693
694static int stmmac_has_work(struct stmmac_priv *priv)
695{
696 unsigned int has_work = 0;
697 int rxret, tx_work = 0;
698
db98a0b0 699 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 700 (priv->cur_rx % priv->dma_rx_size));
701
702 if (priv->dirty_tx != priv->cur_tx)
703 tx_work = 1;
704
705 if (likely(!rxret || tx_work))
706 has_work = 1;
707
708 return has_work;
709}
710
711static inline void _stmmac_schedule(struct stmmac_priv *priv)
712{
713 if (likely(stmmac_has_work(priv))) {
714 stmmac_disable_irq(priv);
715 napi_schedule(&priv->napi);
716 }
717}
718
719#ifdef CONFIG_STMMAC_TIMER
720void stmmac_schedule(struct net_device *dev)
721{
722 struct stmmac_priv *priv = netdev_priv(dev);
723
724 priv->xstats.sched_timer_n++;
725
726 _stmmac_schedule(priv);
47dd7a54
GC		 727}
728
729static void stmmac_no_timer_started(unsigned int x)
730{;
731};
732
733static void stmmac_no_timer_stopped(void)
734{;
735};
736#endif
737
738/**
739 * stmmac_tx_err:
740 * @priv: pointer to the private device structure
741 * Description: it cleans the descriptors and restarts the transmission
742 * in case of errors.
743 */
744static void stmmac_tx_err(struct stmmac_priv *priv)
745{
746 netif_stop_queue(priv->dev);
747
ad01b7d4 748 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 749 dma_free_tx_skbufs(priv);
db98a0b0 750 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 751 priv->dirty_tx = 0;
752 priv->cur_tx = 0;
ad01b7d4 753 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 754
755 priv->dev->stats.tx_errors++;
756 netif_wake_queue(priv->dev);
47dd7a54
GC		 757}
758
47dd7a54 759
aec7ff27
GC		 760static void stmmac_dma_interrupt(struct stmmac_priv *priv)
761{
aec7ff27
GC		 762 int status;
763
ad01b7d4 764 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 765 if (likely(status == handle_tx_rx))
766 _stmmac_schedule(priv);
767
768 else if (unlikely(status == tx_hard_error_bump_tc)) {
769 /* Try to bump up the dma threshold on this failure */
770 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
771 tc += 64;
ad01b7d4 772 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 773 priv->xstats.threshold = tc;
47dd7a54 774 }
aec7ff27
GC		 775 } else if (unlikely(status == tx_hard_error))
776 stmmac_tx_err(priv);
47dd7a54
GC		 777}
778
1c901a46
GC		 779static void stmmac_mmc_setup(struct stmmac_priv *priv)
780{
781 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
782 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
783
4f795b25
GC		 784 /* Mask MMC irq, counters are managed in SW and registers
785 * are cleared on each READ eventually. */
1c901a46 786 dwmac_mmc_intr_all_mask(priv->ioaddr);
4f795b25
GC		 787
788 if (priv->dma_cap.rmon) {
789 dwmac_mmc_ctrl(priv->ioaddr, mode);
790 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
791 } else
792 pr_info(" No MAC Management Counters available");
1c901a46
GC		 793}
794
f0b9d786
GC		 795static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
796{
797 u32 hwid = priv->hw->synopsys_uid;
798
799 /* Only check valid Synopsys Id because old MAC chips
800 * have no HW registers where get the ID */
801 if (likely(hwid)) {
802 u32 uid = ((hwid & 0x0000ff00) >> 8);
803 u32 synid = (hwid & 0x000000ff);
804
805 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
806 uid, synid);
807
808 return synid;
809 }
810 return 0;
811}
e7434821 812
19e30c14
GC		 813/**
814 * stmmac_selec_desc_mode
815 * @dev : device pointer
816 * Description: select the Enhanced/Alternate or Normal descriptors */
817static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
818{
819 if (priv->plat->enh_desc) {
820 pr_info(" Enhanced/Alternate descriptors\n");
821 priv->hw->desc = &enh_desc_ops;
822 } else {
823 pr_info(" Normal descriptors\n");
824 priv->hw->desc = &ndesc_ops;
825 }
826}
827
828/**
829 * stmmac_get_hw_features
830 * @priv : private device pointer
831 * Description:
832 * new GMAC chip generations have a new register to indicate the
833 * presence of the optional feature/functions.
834 * This can be also used to override the value passed through the
835 * platform and necessary for old MAC10/100 and GMAC chips.
e7434821
GC		 836 */
837static int stmmac_get_hw_features(struct stmmac_priv *priv)
838{
5e6efe88 839 u32 hw_cap = 0;
3c20f72f 840
5e6efe88
GC		 841 if (priv->hw->dma->get_hw_feature) {
842 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
e7434821 843
1db123fb
RK		 844 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
845 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
846 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
847 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
848 priv->dma_cap.multi_addr =
849 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
850 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
851 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
852 priv->dma_cap.pmt_remote_wake_up =
853 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
854 priv->dma_cap.pmt_magic_frame =
855 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
19e30c14 856 /* MMC */
1db123fb 857 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
e7434821 858 /* IEEE 1588-2002*/
1db123fb
RK		 859 priv->dma_cap.time_stamp =
860 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
e7434821 861 /* IEEE 1588-2008*/
1db123fb
RK		 862 priv->dma_cap.atime_stamp =
863 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 864 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 865 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
866 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 867 /* TX and RX csum */
1db123fb
RK		 868 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
869 priv->dma_cap.rx_coe_type1 =
870 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
871 priv->dma_cap.rx_coe_type2 =
872 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
873 priv->dma_cap.rxfifo_over_2048 =
874 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 875 /* TX and RX number of channels */
1db123fb
RK		 876 priv->dma_cap.number_rx_channel =
877 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
878 priv->dma_cap.number_tx_channel =
879 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
e7434821 880 /* Alternate (enhanced) DESC mode*/
1db123fb
RK		 881 priv->dma_cap.enh_desc =
882 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
e7434821 883
19e30c14 884 }
e7434821
GC		 885
886 return hw_cap;
887}
888
47dd7a54
GC		 889/**
890 * stmmac_open - open entry point of the driver
891 * @dev : pointer to the device structure.
892 * Description:
893 * This function is the open entry point of the driver.
894 * Return value:
895 * 0 on success and an appropriate (-)ve integer as defined in errno.h
896 * file on failure.
897 */
898static int stmmac_open(struct net_device *dev)
899{
900 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 901 int ret;
902
903 /* Check that the MAC address is valid. If its not, refuse
904 * to bring the device up. The user must specify an
905 * address using the following linux command:
906 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
907 if (!is_valid_ether_addr(dev->dev_addr)) {
908 random_ether_addr(dev->dev_addr);
909 pr_warning("%s: generated random MAC address %pM\n", dev->name,
910 dev->dev_addr);
911 }
912
913 stmmac_verify_args();
914
47dd7a54 915#ifdef CONFIG_STMMAC_TIMER
73cfe264 916 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 917 if (unlikely(priv->tm == NULL)) {
2381a55c 918 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 919 return -ENOMEM;
920 }
921 priv->tm->freq = tmrate;
922
73cfe264
GC		 923 /* Test if the external timer can be actually used.
924 * In case of failure continue without timer. */
47dd7a54 925 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 926 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 927 priv->tm->freq = 0;
928 priv->tm->timer_start = stmmac_no_timer_started;
929 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 930 } else
931 priv->tm->enable = 1;
47dd7a54 932#endif
f66ffe28
GC		 933 ret = stmmac_init_phy(dev);
934 if (unlikely(ret)) {
935 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
936 goto open_error;
937 }
47dd7a54 938
19e30c14
GC		 939 stmmac_get_synopsys_id(priv);
940
941 priv->hw_cap_support = stmmac_get_hw_features(priv);
942
943 if (priv->hw_cap_support) {
944 pr_info(" Support DMA HW capability register");
945
946 /* We can override some gmac/dma configuration fields: e.g.
947 * enh_desc, tx_coe (e.g. that are passed through the
948 * platform) with the values from the HW capability
949 * register (if supported).
950 */
951 priv->plat->enh_desc = priv->dma_cap.enh_desc;
952 priv->plat->tx_coe = priv->dma_cap.tx_coe;
953 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
954
955 /* By default disable wol on magic frame if not supported */
956 if (!priv->dma_cap.pmt_magic_frame)
957 priv->wolopts &= ~WAKE_MAGIC;
958
959 } else
960 pr_info(" No HW DMA feature register supported");
961
962 /* Select the enhnaced/normal descriptor structures */
963 stmmac_selec_desc_mode(priv);
964
965 /* PMT module is not integrated in all the MAC devices. */
966 if (priv->plat->pmt) {
967 pr_info(" Remote wake-up capable\n");
968 device_set_wakeup_capable(priv->device, 1);
969 }
970
971 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
972 if (priv->rx_coe)
973 pr_info(" Checksum Offload Engine supported\n");
974 if (priv->plat->tx_coe)
975 pr_info(" Checksum insertion supported\n");
976
47dd7a54
GC		 977 /* Create and initialize the TX/RX descriptors chains. */
978 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
979 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
980 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
981 init_dma_desc_rings(dev);
982
983 /* DMA initialization and SW reset */
f66ffe28
GC		 984 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
985 priv->dma_tx_phy, priv->dma_rx_phy);
986 if (ret < 0) {
47dd7a54 987 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 988 goto open_error;
47dd7a54
GC		 989 }
990
991 /* Copy the MAC addr into the HW */
ad01b7d4 992 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1 993 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 994 if (priv->plat->bus_setup)
995 priv->plat->bus_setup(priv->ioaddr);
47dd7a54 996 /* Initialize the MAC Core */
ad01b7d4 997 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 998
5e982f3b 999 netdev_update_features(dev);
ebbb293f 1000
f66ffe28
GC		 1001 /* Request the IRQ lines */
1002 ret = request_irq(dev->irq, stmmac_interrupt,
1003 IRQF_SHARED, dev->name, dev);
1004 if (unlikely(ret < 0)) {
1005 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1006 __func__, dev->irq, ret);
1007 goto open_error;
1008 }
1009
47dd7a54 1010 /* Enable the MAC Rx/Tx */
19449bfc 1011 stmmac_enable_mac(priv->ioaddr);
47dd7a54
GC		 1012
1013 /* Set the HW DMA mode and the COE */
1014 stmmac_dma_operation_mode(priv);
1015
1016 /* Extra statistics */
1017 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1018 priv->xstats.threshold = tc;
1019
4f795b25 1020 stmmac_mmc_setup(priv);
1c901a46 1021
47dd7a54
GC		 1022 /* Start the ball rolling... */
1023 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 1024 priv->hw->dma->start_tx(priv->ioaddr);
1025 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 1026
1027#ifdef CONFIG_STMMAC_TIMER
1028 priv->tm->timer_start(tmrate);
1029#endif
1030 /* Dump DMA/MAC registers */
1031 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 1032 priv->hw->mac->dump_regs(priv->ioaddr);
1033 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 1034 }
1035
1036 if (priv->phydev)
1037 phy_start(priv->phydev);
1038
1039 napi_enable(&priv->napi);
1040 skb_queue_head_init(&priv->rx_recycle);
1041 netif_start_queue(dev);
f66ffe28 1042
47dd7a54 1043 return 0;
f66ffe28
GC		 1044
1045open_error:
1046#ifdef CONFIG_STMMAC_TIMER
1047 kfree(priv->tm);
1048#endif
1049 if (priv->phydev)
1050 phy_disconnect(priv->phydev);
1051
1052 return ret;
47dd7a54
GC		 1053}
1054
1055/**
1056 * stmmac_release - close entry point of the driver
1057 * @dev : device pointer.
1058 * Description:
1059 * This is the stop entry point of the driver.
1060 */
1061static int stmmac_release(struct net_device *dev)
1062{
1063 struct stmmac_priv *priv = netdev_priv(dev);
1064
1065 /* Stop and disconnect the PHY */
1066 if (priv->phydev) {
1067 phy_stop(priv->phydev);
1068 phy_disconnect(priv->phydev);
1069 priv->phydev = NULL;
1070 }
1071
1072 netif_stop_queue(dev);
1073
1074#ifdef CONFIG_STMMAC_TIMER
1075 /* Stop and release the timer */
1076 stmmac_close_ext_timer();
1077 if (priv->tm != NULL)
1078 kfree(priv->tm);
1079#endif
1080 napi_disable(&priv->napi);
1081 skb_queue_purge(&priv->rx_recycle);
1082
1083 /* Free the IRQ lines */
1084 free_irq(dev->irq, dev);
1085
1086 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1087 priv->hw->dma->stop_tx(priv->ioaddr);
1088 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1089
1090 /* Release and free the Rx/Tx resources */
1091 free_dma_desc_resources(priv);
1092
19449bfc 1093 /* Disable the MAC Rx/Tx */
1094 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1095
1096 netif_carrier_off(dev);
1097
1098 return 0;
1099}
1100
47dd7a54
GC		 1101/**
1102 * stmmac_xmit:
1103 * @skb : the socket buffer
1104 * @dev : device pointer
1105 * Description : Tx entry point of the driver.
1106 */
1107static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1108{
1109 struct stmmac_priv *priv = netdev_priv(dev);
1110 unsigned int txsize = priv->dma_tx_size;
1111 unsigned int entry;
1112 int i, csum_insertion = 0;
1113 int nfrags = skb_shinfo(skb)->nr_frags;
1114 struct dma_desc *desc, *first;
286a8372 1115 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1116
1117 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1118 if (!netif_queue_stopped(dev)) {
1119 netif_stop_queue(dev);
1120 /* This is a hard error, log it. */
1121 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1122 __func__);
1123 }
1124 return NETDEV_TX_BUSY;
1125 }
1126
a9097a96
GC		 1127 spin_lock(&priv->tx_lock);
1128
47dd7a54
GC		 1129 entry = priv->cur_tx % txsize;
1130
1131#ifdef STMMAC_XMIT_DEBUG
1132 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1133 pr_info("stmmac xmit:\n"
1134 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1135 "\tn_frags: %d - ip_summed: %d - %s gso\n",
286a8372 1136 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
47dd7a54
GC		 1137 !skb_is_gso(skb) ? "isn't" : "is");
1138#endif
1139
5e982f3b 1140 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1141
1142 desc = priv->dma_tx + entry;
1143 first = desc;
1144
1145#ifdef STMMAC_XMIT_DEBUG
1146 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1147 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1148 "\t\tn_frags: %d, ip_summed: %d\n",
286a8372 1149 skb->len, nopaged_len, nfrags, skb->ip_summed);
47dd7a54
GC		 1150#endif
1151 priv->tx_skbuff[entry] = skb;
286a8372
GC		 1152
1153 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1154 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
47dd7a54
GC		 1155 desc = priv->dma_tx + entry;
1156 } else {
47dd7a54
GC		 1157 desc->des2 = dma_map_single(priv->device, skb->data,
1158 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1159 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1160 csum_insertion);
47dd7a54
GC		 1161 }
1162
1163 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1164 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1165 int len = skb_frag_size(frag);
47dd7a54
GC		 1166
1167 entry = (++priv->cur_tx) % txsize;
1168 desc = priv->dma_tx + entry;
1169
1170 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1171 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1172 DMA_TO_DEVICE);
47dd7a54 1173 priv->tx_skbuff[entry] = NULL;
db98a0b0 1174 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1175 wmb();
db98a0b0 1176 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1177 }
1178
1179 /* Interrupt on completition only for the latest segment */
db98a0b0 1180 priv->hw->desc->close_tx_desc(desc);
73cfe264 1181
47dd7a54 1182#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1183 /* Clean IC while using timer */
1184 if (likely(priv->tm->enable))
db98a0b0 1185 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1186#endif
eb0dc4bb
SH		 1187
1188 wmb();
1189
47dd7a54 1190 /* To avoid raise condition */
db98a0b0 1191 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1192
1193 priv->cur_tx++;
1194
1195#ifdef STMMAC_XMIT_DEBUG
1196 if (netif_msg_pktdata(priv)) {
1197 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1198 "first=%p, nfrags=%d\n",
1199 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1200 entry, first, nfrags);
1201 display_ring(priv->dma_tx, txsize);
1202 pr_info(">>> frame to be transmitted: ");
1203 print_pkt(skb->data, skb->len);
1204 }
1205#endif
1206 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1207 TX_DBG("%s: stop transmitted packets\n", __func__);
1208 netif_stop_queue(dev);
1209 }
1210
1211 dev->stats.tx_bytes += skb->len;
1212
3e82ce12
RC		 1213 skb_tx_timestamp(skb);
1214
52f64fae
RC		 1215 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1216
a9097a96
GC		 1217 spin_unlock(&priv->tx_lock);
1218
47dd7a54
GC		 1219 return NETDEV_TX_OK;
1220}
1221
1222static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1223{
1224 unsigned int rxsize = priv->dma_rx_size;
1225 int bfsize = priv->dma_buf_sz;
1226 struct dma_desc *p = priv->dma_rx;
1227
1228 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1229 unsigned int entry = priv->dirty_rx % rxsize;
1230 if (likely(priv->rx_skbuff[entry] == NULL)) {
1231 struct sk_buff *skb;
1232
1233 skb = __skb_dequeue(&priv->rx_recycle);
1234 if (skb == NULL)
1235 skb = netdev_alloc_skb_ip_align(priv->dev,
1236 bfsize);
1237
1238 if (unlikely(skb == NULL))
1239 break;
1240
1241 priv->rx_skbuff[entry] = skb;
1242 priv->rx_skbuff_dma[entry] =
1243 dma_map_single(priv->device, skb->data, bfsize,
1244 DMA_FROM_DEVICE);
1245
1246 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
286a8372
GC		 1247
1248 if (unlikely(priv->plat->has_gmac))
1249 priv->hw->ring->refill_desc3(bfsize, p + entry);
1250
47dd7a54
GC		 1251 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1252 }
eb0dc4bb 1253 wmb();
db98a0b0 1254 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1255 }
47dd7a54
GC		 1256}
1257
1258static int stmmac_rx(struct stmmac_priv *priv, int limit)
1259{
1260 unsigned int rxsize = priv->dma_rx_size;
1261 unsigned int entry = priv->cur_rx % rxsize;
1262 unsigned int next_entry;
1263 unsigned int count = 0;
1264 struct dma_desc *p = priv->dma_rx + entry;
1265 struct dma_desc *p_next;
1266
1267#ifdef STMMAC_RX_DEBUG
1268 if (netif_msg_hw(priv)) {
1269 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1270 display_ring(priv->dma_rx, rxsize);
1271 }
1272#endif
1273 count = 0;
db98a0b0 1274 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1275 int status;
1276
1277 if (count >= limit)
1278 break;
1279
1280 count++;
1281
1282 next_entry = (++priv->cur_rx) % rxsize;
1283 p_next = priv->dma_rx + next_entry;
1284 prefetch(p_next);
1285
1286 /* read the status of the incoming frame */
db98a0b0
GC		 1287 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1288 &priv->xstats, p));
47dd7a54
GC		 1289 if (unlikely(status == discard_frame))
1290 priv->dev->stats.rx_errors++;
1291 else {
1292 struct sk_buff *skb;
3eeb2997 1293 int frame_len;
47dd7a54 1294
3eeb2997
GC		 1295 frame_len = priv->hw->desc->get_rx_frame_len(p);
1296 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1297 * Type frames (LLC/LLC-SNAP) */
1298 if (unlikely(status != llc_snap))
1299 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1300#ifdef STMMAC_RX_DEBUG
1301 if (frame_len > ETH_FRAME_LEN)
1302 pr_debug("\tRX frame size %d, COE status: %d\n",
1303 frame_len, status);
1304
1305 if (netif_msg_hw(priv))
1306 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1307 p, entry, p->des2);
1308#endif
1309 skb = priv->rx_skbuff[entry];
1310 if (unlikely(!skb)) {
1311 pr_err("%s: Inconsistent Rx descriptor chain\n",
1312 priv->dev->name);
1313 priv->dev->stats.rx_dropped++;
1314 break;
1315 }
1316 prefetch(skb->data - NET_IP_ALIGN);
1317 priv->rx_skbuff[entry] = NULL;
1318
1319 skb_put(skb, frame_len);
1320 dma_unmap_single(priv->device,
1321 priv->rx_skbuff_dma[entry],
1322 priv->dma_buf_sz, DMA_FROM_DEVICE);
1323#ifdef STMMAC_RX_DEBUG
1324 if (netif_msg_pktdata(priv)) {
1325 pr_info(" frame received (%dbytes)", frame_len);
1326 print_pkt(skb->data, frame_len);
1327 }
1328#endif
1329 skb->protocol = eth_type_trans(skb, priv->dev);
1330
3c20f72f
GC		 1331 if (unlikely(!priv->rx_coe)) {
1332 /* No RX COE for old mac10/100 devices */
bc8acf2c 1333 skb_checksum_none_assert(skb);
47dd7a54
GC		 1334 netif_receive_skb(skb);
1335 } else {
1336 skb->ip_summed = CHECKSUM_UNNECESSARY;
1337 napi_gro_receive(&priv->napi, skb);
1338 }
1339
1340 priv->dev->stats.rx_packets++;
1341 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1342 }
1343 entry = next_entry;
1344 p = p_next; /* use prefetched values */
1345 }
1346
1347 stmmac_rx_refill(priv);
1348
1349 priv->xstats.rx_pkt_n += count;
1350
1351 return count;
1352}
1353
1354/**
1355 * stmmac_poll - stmmac poll method (NAPI)
1356 * @napi : pointer to the napi structure.
1357 * @budget : maximum number of packets that the current CPU can receive from
1358 * all interfaces.
1359 * Description :
1360 * This function implements the the reception process.
1361 * Also it runs the TX completion thread
1362 */
1363static int stmmac_poll(struct napi_struct *napi, int budget)
1364{
1365 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1366 int work_done = 0;
1367
1368 priv->xstats.poll_n++;
1369 stmmac_tx(priv);
1370 work_done = stmmac_rx(priv, budget);
1371
1372 if (work_done < budget) {
1373 napi_complete(napi);
1374 stmmac_enable_irq(priv);
1375 }
1376 return work_done;
1377}
1378
1379/**
1380 * stmmac_tx_timeout
1381 * @dev : Pointer to net device structure
1382 * Description: this function is called when a packet transmission fails to
1383 * complete within a reasonable tmrate. The driver will mark the error in the
1384 * netdev structure and arrange for the device to be reset to a sane state
1385 * in order to transmit a new packet.
1386 */
1387static void stmmac_tx_timeout(struct net_device *dev)
1388{
1389 struct stmmac_priv *priv = netdev_priv(dev);
1390
1391 /* Clear Tx resources and restart transmitting again */
1392 stmmac_tx_err(priv);
47dd7a54
GC		 1393}
1394
1395/* Configuration changes (passed on by ifconfig) */
1396static int stmmac_config(struct net_device *dev, struct ifmap *map)
1397{
1398 if (dev->flags & IFF_UP) /* can't act on a running interface */
1399 return -EBUSY;
1400
1401 /* Don't allow changing the I/O address */
1402 if (map->base_addr != dev->base_addr) {
1403 pr_warning("%s: can't change I/O address\n", dev->name);
1404 return -EOPNOTSUPP;
1405 }
1406
1407 /* Don't allow changing the IRQ */
1408 if (map->irq != dev->irq) {
1409 pr_warning("%s: can't change IRQ number %d\n",
1410 dev->name, dev->irq);
1411 return -EOPNOTSUPP;
1412 }
1413
1414 /* ignore other fields */
1415 return 0;
1416}
1417
1418/**
01789349 1419 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1420 * @dev : pointer to the device structure
1421 * Description:
1422 * This function is a driver entry point which gets called by the kernel
1423 * whenever multicast addresses must be enabled/disabled.
1424 * Return value:
1425 * void.
1426 */
01789349 1427static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1428{
1429 struct stmmac_priv *priv = netdev_priv(dev);
1430
1431 spin_lock(&priv->lock);
db98a0b0 1432 priv->hw->mac->set_filter(dev);
47dd7a54 1433 spin_unlock(&priv->lock);
47dd7a54
GC		 1434}
1435
1436/**
1437 * stmmac_change_mtu - entry point to change MTU size for the device.
1438 * @dev : device pointer.
1439 * @new_mtu : the new MTU size for the device.
1440 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1441 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1442 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1443 * Return value:
1444 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1445 * file on failure.
1446 */
1447static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1448{
1449 struct stmmac_priv *priv = netdev_priv(dev);
1450 int max_mtu;
1451
1452 if (netif_running(dev)) {
1453 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1454 return -EBUSY;
1455 }
1456
48febf7e 1457 if (priv->plat->enh_desc)
47dd7a54
GC		 1458 max_mtu = JUMBO_LEN;
1459 else
45db81e1 1460 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
47dd7a54
GC		 1461
1462 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1463 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1464 return -EINVAL;
1465 }
1466
5e982f3b
MM		 1467 dev->mtu = new_mtu;
1468 netdev_update_features(dev);
1469
1470 return 0;
1471}
1472
c8f44aff
MM		 1473static netdev_features_t stmmac_fix_features(struct net_device *dev,
1474 netdev_features_t features)
5e982f3b
MM		 1475{
1476 struct stmmac_priv *priv = netdev_priv(dev);
1477
1478 if (!priv->rx_coe)
1479 features &= ~NETIF_F_RXCSUM;
1480 if (!priv->plat->tx_coe)
1481 features &= ~NETIF_F_ALL_CSUM;
1482
ebbb293f
GC		 1483 /* Some GMAC devices have a bugged Jumbo frame support that
1484 * needs to have the Tx COE disabled for oversized frames
1485 * (due to limited buffer sizes). In this case we disable
1486 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1487 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1488 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1489
5e982f3b 1490 return features;
47dd7a54
GC		 1491}
1492
1493static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1494{
1495 struct net_device *dev = (struct net_device *)dev_id;
1496 struct stmmac_priv *priv = netdev_priv(dev);
1497
1498 if (unlikely(!dev)) {
1499 pr_err("%s: invalid dev pointer\n", __func__);
1500 return IRQ_NONE;
1501 }
1502
9dfeb4d9 1503 if (priv->plat->has_gmac)
47dd7a54 1504 /* To handle GMAC own interrupts */
ad01b7d4 1505 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1506
1507 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1508
1509 return IRQ_HANDLED;
1510}
1511
1512#ifdef CONFIG_NET_POLL_CONTROLLER
1513/* Polling receive - used by NETCONSOLE and other diagnostic tools
1514 * to allow network I/O with interrupts disabled. */
1515static void stmmac_poll_controller(struct net_device *dev)
1516{
1517 disable_irq(dev->irq);
1518 stmmac_interrupt(dev->irq, dev);
1519 enable_irq(dev->irq);
1520}
1521#endif
1522
1523/**
1524 * stmmac_ioctl - Entry point for the Ioctl
1525 * @dev: Device pointer.
1526 * @rq: An IOCTL specefic structure, that can contain a pointer to
1527 * a proprietary structure used to pass information to the driver.
1528 * @cmd: IOCTL command
1529 * Description:
1530 * Currently there are no special functionality supported in IOCTL, just the
1531 * phy_mii_ioctl(...) can be invoked.
1532 */
1533static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1534{
1535 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1536 int ret;
47dd7a54
GC		 1537
1538 if (!netif_running(dev))
1539 return -EINVAL;
1540
28b04113
RC		 1541 if (!priv->phydev)
1542 return -EINVAL;
1543
28b04113 1544 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
28b04113 1545
47dd7a54
GC		 1546 return ret;
1547}
1548
7ac29055
GC		 1549#ifdef CONFIG_STMMAC_DEBUG_FS
1550static struct dentry *stmmac_fs_dir;
1551static struct dentry *stmmac_rings_status;
e7434821 1552static struct dentry *stmmac_dma_cap;
7ac29055
GC		 1553
1554static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1555{
1556 struct tmp_s {
1557 u64 a;
1558 unsigned int b;
1559 unsigned int c;
1560 };
1561 int i;
1562 struct net_device *dev = seq->private;
1563 struct stmmac_priv *priv = netdev_priv(dev);
1564
1565 seq_printf(seq, "=======================\n");
1566 seq_printf(seq, " RX descriptor ring\n");
1567 seq_printf(seq, "=======================\n");
1568
1569 for (i = 0; i < priv->dma_rx_size; i++) {
1570 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1571 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1572 i, (unsigned int)(x->a),
1573 (unsigned int)((x->a) >> 32), x->b, x->c);
1574 seq_printf(seq, "\n");
1575 }
1576
1577 seq_printf(seq, "\n");
1578 seq_printf(seq, "=======================\n");
1579 seq_printf(seq, " TX descriptor ring\n");
1580 seq_printf(seq, "=======================\n");
1581
1582 for (i = 0; i < priv->dma_tx_size; i++) {
1583 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1584 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1585 i, (unsigned int)(x->a),
1586 (unsigned int)((x->a) >> 32), x->b, x->c);
1587 seq_printf(seq, "\n");
1588 }
1589
1590 return 0;
1591}
1592
1593static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1594{
1595 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1596}
1597
1598static const struct file_operations stmmac_rings_status_fops = {
1599 .owner = THIS_MODULE,
1600 .open = stmmac_sysfs_ring_open,
1601 .read = seq_read,
1602 .llseek = seq_lseek,
1603 .release = seq_release,
1604};
1605
e7434821
GC		 1606static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1607{
1608 struct net_device *dev = seq->private;
1609 struct stmmac_priv *priv = netdev_priv(dev);
1610
19e30c14 1611 if (!priv->hw_cap_support) {
e7434821
GC		 1612 seq_printf(seq, "DMA HW features not supported\n");
1613 return 0;
1614 }
1615
1616 seq_printf(seq, "==============================\n");
1617 seq_printf(seq, "\tDMA HW features\n");
1618 seq_printf(seq, "==============================\n");
1619
1620 seq_printf(seq, "\t10/100 Mbps %s\n",
1621 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1622 seq_printf(seq, "\t1000 Mbps %s\n",
1623 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1624 seq_printf(seq, "\tHalf duple %s\n",
1625 (priv->dma_cap.half_duplex) ? "Y" : "N");
1626 seq_printf(seq, "\tHash Filter: %s\n",
1627 (priv->dma_cap.hash_filter) ? "Y" : "N");
1628 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1629 (priv->dma_cap.multi_addr) ? "Y" : "N");
1630 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1631 (priv->dma_cap.pcs) ? "Y" : "N");
1632 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1633 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1634 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1635 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1636 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1637 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1638 seq_printf(seq, "\tRMON module: %s\n",
1639 (priv->dma_cap.rmon) ? "Y" : "N");
1640 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1641 (priv->dma_cap.time_stamp) ? "Y" : "N");
1642 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1643 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1644 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1645 (priv->dma_cap.eee) ? "Y" : "N");
1646 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1647 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1648 (priv->dma_cap.tx_coe) ? "Y" : "N");
1649 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1650 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1651 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1652 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1653 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1654 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1655 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1656 priv->dma_cap.number_rx_channel);
1657 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1658 priv->dma_cap.number_tx_channel);
1659 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1660 (priv->dma_cap.enh_desc) ? "Y" : "N");
1661
1662 return 0;
1663}
1664
1665static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1666{
1667 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1668}
1669
1670static const struct file_operations stmmac_dma_cap_fops = {
1671 .owner = THIS_MODULE,
1672 .open = stmmac_sysfs_dma_cap_open,
1673 .read = seq_read,
1674 .llseek = seq_lseek,
1675 .release = seq_release,
1676};
1677
7ac29055
GC		 1678static int stmmac_init_fs(struct net_device *dev)
1679{
1680 /* Create debugfs entries */
1681 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1682
1683 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1684 pr_err("ERROR %s, debugfs create directory failed\n",
1685 STMMAC_RESOURCE_NAME);
1686
1687 return -ENOMEM;
1688 }
1689
1690 /* Entry to report DMA RX/TX rings */
1691 stmmac_rings_status = debugfs_create_file("descriptors_status",
1692 S_IRUGO, stmmac_fs_dir, dev,
1693 &stmmac_rings_status_fops);
1694
1695 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1696 pr_info("ERROR creating stmmac ring debugfs file\n");
1697 debugfs_remove(stmmac_fs_dir);
1698
1699 return -ENOMEM;
1700 }
1701
e7434821
GC		 1702 /* Entry to report the DMA HW features */
1703 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1704 dev, &stmmac_dma_cap_fops);
1705
1706 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1707 pr_info("ERROR creating stmmac MMC debugfs file\n");
1708 debugfs_remove(stmmac_rings_status);
1709 debugfs_remove(stmmac_fs_dir);
1710
1711 return -ENOMEM;
1712 }
1713
7ac29055
GC		 1714 return 0;
1715}
1716
1717static void stmmac_exit_fs(void)
1718{
1719 debugfs_remove(stmmac_rings_status);
e7434821 1720 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 1721 debugfs_remove(stmmac_fs_dir);
1722}
1723#endif /* CONFIG_STMMAC_DEBUG_FS */
1724
47dd7a54
GC		 1725static const struct net_device_ops stmmac_netdev_ops = {
1726 .ndo_open = stmmac_open,
1727 .ndo_start_xmit = stmmac_xmit,
1728 .ndo_stop = stmmac_release,
1729 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1730 .ndo_fix_features = stmmac_fix_features,
01789349 1731 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1732 .ndo_tx_timeout = stmmac_tx_timeout,
1733 .ndo_do_ioctl = stmmac_ioctl,
1734 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1735#ifdef CONFIG_NET_POLL_CONTROLLER
1736 .ndo_poll_controller = stmmac_poll_controller,
1737#endif
1738 .ndo_set_mac_address = eth_mac_addr,
1739};
1740
1741/**
1742 * stmmac_probe - Initialization of the adapter .
1743 * @dev : device pointer
1744 * Description: The function initializes the network device structure for
1745 * the STMMAC driver. It also calls the low level routines
1746 * in order to init the HW (i.e. the DMA engine)
1747 */
1748static int stmmac_probe(struct net_device *dev)
1749{
1750 int ret = 0;
1751 struct stmmac_priv *priv = netdev_priv(dev);
1752
1753 ether_setup(dev);
1754
1755 dev->netdev_ops = &stmmac_netdev_ops;
1756 stmmac_set_ethtool_ops(dev);
1757
5e982f3b
MM		 1758 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1759 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
47dd7a54
GC		 1760 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1761#ifdef STMMAC_VLAN_TAG_USED
1762 /* Both mac100 and gmac support receive VLAN tag detection */
1763 dev->features |= NETIF_F_HW_VLAN_RX;
1764#endif
1765 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1766
47dd7a54
GC		 1767 if (flow_ctrl)
1768 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1769
1770 priv->pause = pause;
1771 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1772
1773 /* Get the MAC address */
ad01b7d4
GC		 1774 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1775 dev->dev_addr, 0);
47dd7a54
GC		 1776
1777 if (!is_valid_ether_addr(dev->dev_addr))
1778 pr_warning("\tno valid MAC address;"
1779 "please, use ifconfig or nwhwconfig!\n");
1780
f8e96161 1781 spin_lock_init(&priv->lock);
a9097a96 1782 spin_lock_init(&priv->tx_lock);
f8e96161 1783
47dd7a54
GC		 1784 ret = register_netdev(dev);
1785 if (ret) {
1786 pr_err("%s: ERROR %i registering the device\n",
1787 __func__, ret);
1788 return -ENODEV;
1789 }
1790
1791 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1792 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
79032644 1793 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
47dd7a54 1794
47dd7a54
GC		 1795 return ret;
1796}
1797
1798/**
1799 * stmmac_mac_device_setup
1800 * @dev : device pointer
1801 * Description: select and initialise the mac device (mac100 or Gmac).
1802 */
1803static int stmmac_mac_device_setup(struct net_device *dev)
1804{
1805 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1806
1807 struct mac_device_info *device;
1808
01789349
JP		 1809 if (priv->plat->has_gmac) {
1810 dev->priv_flags |= IFF_UNICAST_FLT;
ad01b7d4 1811 device = dwmac1000_setup(priv->ioaddr);
01789349 1812 } else {
ad01b7d4 1813 device = dwmac100_setup(priv->ioaddr);
01789349 1814 }
3d90c508 1815
1ff21906
DC		 1816 if (!device)
1817 return -ENOMEM;
1818
db98a0b0 1819 priv->hw = device;
286a8372 1820 priv->hw->ring = &ring_mode_ops;
47dd7a54 1821
539c9aa5 1822 if (device_can_wakeup(priv->device)) {
543876c9 1823 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
3172d3af 1824 enable_irq_wake(priv->wol_irq);
539c9aa5 1825 }
47dd7a54
GC		 1826
1827 return 0;
1828}
1829
47dd7a54
GC		 1830/**
1831 * stmmac_dvr_probe
1832 * @pdev: platform device pointer
1833 * Description: the driver is initialized through platform_device.
1834 */
1835static int stmmac_dvr_probe(struct platform_device *pdev)
1836{
1837 int ret = 0;
1838 struct resource *res;
ad01b7d4 1839 void __iomem *addr = NULL;
47dd7a54 1840 struct net_device *ndev = NULL;
293bb1c4 1841 struct stmmac_priv *priv = NULL;
47dd7a54
GC		 1842 struct plat_stmmacenet_data *plat_dat;
1843
1844 pr_info("STMMAC driver:\n\tplatform registration... ");
1845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34a52f36
DC		 1846 if (!res)
1847 return -ENODEV;
ebbb293f 1848 pr_info("\tdone!\n");
47dd7a54 1849
b6222682 1850 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1851 pdev->name)) {
1852 pr_err("%s: ERROR: memory allocation failed"
1853 "cannot get the I/O addr 0x%x\n",
1854 __func__, (unsigned int)res->start);
34a52f36 1855 return -EBUSY;
47dd7a54
GC		 1856 }
1857
7c5365bc 1858 addr = ioremap(res->start, resource_size(res));
47dd7a54 1859 if (!addr) {
7c5365bc 1860 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54 1861 ret = -ENOMEM;
34a52f36 1862 goto out_release_region;
47dd7a54
GC		 1863 }
1864
1865 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1866 if (!ndev) {
1867 pr_err("%s: ERROR: allocating the device\n", __func__);
1868 ret = -ENOMEM;
34a52f36 1869 goto out_unmap;
47dd7a54
GC		 1870 }
1871
1872 SET_NETDEV_DEV(ndev, &pdev->dev);
1873
1874 /* Get the MAC information */
1875 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1876 if (ndev->irq == -ENXIO) {
1877 pr_err("%s: ERROR: MAC IRQ configuration "
1878 "information not found\n", __func__);
34a52f36
DC		 1879 ret = -ENXIO;
1880 goto out_free_ndev;
47dd7a54
GC		 1881 }
1882
1883 priv = netdev_priv(ndev);
1884 priv->device = &(pdev->dev);
1885 priv->dev = ndev;
ee7946a7 1886 plat_dat = pdev->dev.platform_data;
9dfeb4d9
GC		 1887
1888 priv->plat = plat_dat;
1889
ad01b7d4 1890 priv->ioaddr = addr;
47dd7a54 1891
3172d3af
DS		 1892 /*
1893 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1894 * The external wake up irq can be passed through the platform code
1895 * named as "eth_wake_irq"
1896 *
1897 * In case the wake up interrupt is not passed from the platform
1898 * so the driver will continue to use the mac irq (ndev->irq)
1899 */
1900 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1901 if (priv->wol_irq == -ENXIO)
1902 priv->wol_irq = ndev->irq;
1903
47dd7a54
GC		 1904 platform_set_drvdata(pdev, ndev);
1905
1906 /* Set the I/O base addr */
1907 ndev->base_addr = (unsigned long)addr;
1908
293bb1c4
GC		 1909 /* Custom initialisation */
1910 if (priv->plat->init) {
1911 ret = priv->plat->init(pdev);
1912 if (unlikely(ret))
34a52f36 1913 goto out_free_ndev;
293bb1c4 1914 }
ee7946a7 1915
19e30c14 1916 /* MAC HW device detection */
47dd7a54
GC		 1917 ret = stmmac_mac_device_setup(ndev);
1918 if (ret < 0)
34a52f36 1919 goto out_plat_exit;
47dd7a54
GC		 1920
1921 /* Network Device Registration */
1922 ret = stmmac_probe(ndev);
1923 if (ret < 0)
34a52f36 1924 goto out_plat_exit;
47dd7a54 1925
36bcfe7d
GC		 1926 /* Override with kernel parameters if supplied XXX CRS XXX
1927 * this needs to have multiple instances */
1928 if ((phyaddr >= 0) && (phyaddr <= 31))
1929 priv->plat->phy_addr = phyaddr;
47dd7a54 1930
47dd7a54 1931 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1932 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1933 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1934
1935 /* MDIO bus Registration */
9dfeb4d9 1936 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
47dd7a54
GC		 1937 ret = stmmac_mdio_register(ndev);
1938 if (ret < 0)
34a52f36 1939 goto out_unregister;
47dd7a54 1940 pr_debug("registered!\n");
7ac29055
GC		 1941
1942#ifdef CONFIG_STMMAC_DEBUG_FS
1943 ret = stmmac_init_fs(ndev);
1944 if (ret < 0)
1945 pr_warning("\tFailed debugFS registration");
1946#endif
1947
34a52f36 1948 return 0;
47dd7a54 1949
34a52f36
DC		 1950out_unregister:
1951 unregister_netdev(ndev);
1952out_plat_exit:
1953 if (priv->plat->exit)
1954 priv->plat->exit(pdev);
1955out_free_ndev:
1956 free_netdev(ndev);
1957 platform_set_drvdata(pdev, NULL);
1958out_unmap:
1959 iounmap(addr);
1960out_release_region:
1961 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1962
1963 return ret;
1964}
1965
1966/**
1967 * stmmac_dvr_remove
1968 * @pdev: platform device pointer
1969 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1970 * changes the link status, releases the DMA descriptor rings,
1971 * unregisters the MDIO bus and unmaps the allocated memory.
1972 */
1973static int stmmac_dvr_remove(struct platform_device *pdev)
1974{
1975 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1976 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1977 struct resource *res;
1978
1979 pr_info("%s:\n\tremoving driver", __func__);
1980
ad01b7d4
GC		 1981 priv->hw->dma->stop_rx(priv->ioaddr);
1982 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1983
19449bfc 1984 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1985
1986 netif_carrier_off(ndev);
1987
1988 stmmac_mdio_unregister(ndev);
1989
293bb1c4
GC		 1990 if (priv->plat->exit)
1991 priv->plat->exit(pdev);
1992
47dd7a54
GC		 1993 platform_set_drvdata(pdev, NULL);
1994 unregister_netdev(ndev);
1995
ad01b7d4 1996 iounmap((void *)priv->ioaddr);
47dd7a54 1997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1998 release_mem_region(res->start, resource_size(res));
47dd7a54 1999
7ac29055
GC		 2000#ifdef CONFIG_STMMAC_DEBUG_FS
2001 stmmac_exit_fs();
2002#endif
2003
47dd7a54
GC		 2004 free_netdev(ndev);
2005
2006 return 0;
2007}
2008
2009#ifdef CONFIG_PM
874bd42d 2010static int stmmac_suspend(struct device *dev)
47dd7a54 2011{
874bd42d
GC		 2012 struct net_device *ndev = dev_get_drvdata(dev);
2013 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 2014 int dis_ic = 0;
2015
874bd42d 2016 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 2017 return 0;
2018
102463b1
FV		 2019 if (priv->phydev)
2020 phy_stop(priv->phydev);
2021
47dd7a54
GC		 2022 spin_lock(&priv->lock);
2023
874bd42d
GC		 2024 netif_device_detach(ndev);
2025 netif_stop_queue(ndev);
47dd7a54
GC		 2026
2027#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2028 priv->tm->timer_stop();
2029 if (likely(priv->tm->enable))
2030 dis_ic = 1;
47dd7a54 2031#endif
874bd42d
GC		 2032 napi_disable(&priv->napi);
2033
2034 /* Stop TX/RX DMA */
2035 priv->hw->dma->stop_tx(priv->ioaddr);
2036 priv->hw->dma->stop_rx(priv->ioaddr);
2037 /* Clear the Rx/Tx descriptors */
2038 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2039 dis_ic);
2040 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2041
2042 /* Enable Power down mode by programming the PMT regs */
2043 if (device_may_wakeup(priv->device))
2044 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2045 else
2046 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 2047
2048 spin_unlock(&priv->lock);
2049 return 0;
2050}
2051
874bd42d 2052static int stmmac_resume(struct device *dev)
47dd7a54 2053{
874bd42d
GC		 2054 struct net_device *ndev = dev_get_drvdata(dev);
2055 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 2056
874bd42d 2057 if (!netif_running(ndev))
47dd7a54
GC		 2058 return 0;
2059
c4433be6
GC		 2060 spin_lock(&priv->lock);
2061
47dd7a54
GC		 2062 /* Power Down bit, into the PM register, is cleared
2063 * automatically as soon as a magic packet or a Wake-up frame
2064 * is received. Anyway, it's better to manually clear
2065 * this bit because it can generate problems while resuming
2066 * from another devices (e.g. serial console). */
874bd42d 2067 if (device_may_wakeup(priv->device))
543876c9 2068 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54 2069
874bd42d 2070 netif_device_attach(ndev);
47dd7a54
GC		 2071
2072 /* Enable the MAC and DMA */
19449bfc 2073 stmmac_enable_mac(priv->ioaddr);
ad01b7d4
GC		 2074 priv->hw->dma->start_tx(priv->ioaddr);
2075 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 2076
2077#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2078 if (likely(priv->tm->enable))
2079 priv->tm->timer_start(tmrate);
47dd7a54
GC		 2080#endif
2081 napi_enable(&priv->napi);
2082
874bd42d 2083 netif_start_queue(ndev);
47dd7a54 2084
47dd7a54 2085 spin_unlock(&priv->lock);
102463b1
FV		 2086
2087 if (priv->phydev)
2088 phy_start(priv->phydev);
2089
47dd7a54
GC		 2090 return 0;
2091}
47dd7a54 2092
874bd42d
GC		 2093static int stmmac_freeze(struct device *dev)
2094{
2095 struct net_device *ndev = dev_get_drvdata(dev);
2096
2097 if (!ndev || !netif_running(ndev))
2098 return 0;
2099
2100 return stmmac_release(ndev);
2101}
2102
2103static int stmmac_restore(struct device *dev)
2104{
2105 struct net_device *ndev = dev_get_drvdata(dev);
2106
2107 if (!ndev || !netif_running(ndev))
2108 return 0;
2109
2110 return stmmac_open(ndev);
2111}
2112
2113static const struct dev_pm_ops stmmac_pm_ops = {
47dd7a54
GC		 2114 .suspend = stmmac_suspend,
2115 .resume = stmmac_resume,
874bd42d
GC		 2116 .freeze = stmmac_freeze,
2117 .thaw = stmmac_restore,
2118 .restore = stmmac_restore,
2119};
2120#else
2121static const struct dev_pm_ops stmmac_pm_ops;
2122#endif /* CONFIG_PM */
47dd7a54 2123
874bd42d
GC		 2124static struct platform_driver stmmac_driver = {
2125 .probe = stmmac_dvr_probe,
2126 .remove = stmmac_dvr_remove,
2127 .driver = {
2128 .name = STMMAC_RESOURCE_NAME,
2129 .owner = THIS_MODULE,
2130 .pm = &stmmac_pm_ops,
2131 },
47dd7a54
GC		 2132};
2133
47dd7a54
GC		 2134#ifndef MODULE
2135static int __init stmmac_cmdline_opt(char *str)
2136{
2137 char *opt;
2138
2139 if (!str || !*str)
2140 return -EINVAL;
2141 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 2142 if (!strncmp(opt, "debug:", 6)) {
2143 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2144 goto err;
2145 } else if (!strncmp(opt, "phyaddr:", 8)) {
2146 if (strict_strtoul(opt + 8, 0,
2147 (unsigned long *)&phyaddr))
2148 goto err;
2149 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2150 if (strict_strtoul(opt + 11, 0,
2151 (unsigned long *)&dma_txsize))
2152 goto err;
2153 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2154 if (strict_strtoul(opt + 11, 0,
2155 (unsigned long *)&dma_rxsize))
2156 goto err;
2157 } else if (!strncmp(opt, "buf_sz:", 7)) {
2158 if (strict_strtoul(opt + 7, 0,
2159 (unsigned long *)&buf_sz))
2160 goto err;
2161 } else if (!strncmp(opt, "tc:", 3)) {
2162 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2163 goto err;
2164 } else if (!strncmp(opt, "watchdog:", 9)) {
2165 if (strict_strtoul(opt + 9, 0,
2166 (unsigned long *)&watchdog))
2167 goto err;
2168 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2169 if (strict_strtoul(opt + 10, 0,
2170 (unsigned long *)&flow_ctrl))
2171 goto err;
2172 } else if (!strncmp(opt, "pause:", 6)) {
2173 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2174 goto err;
47dd7a54 2175#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 2176 } else if (!strncmp(opt, "tmrate:", 7)) {
2177 if (strict_strtoul(opt + 7, 0,
2178 (unsigned long *)&tmrate))
2179 goto err;
47dd7a54 2180#endif
f3240e28 2181 }
47dd7a54
GC		 2182 }
2183 return 0;
f3240e28
GC		 2184
2185err:
2186 pr_err("%s: ERROR broken module parameter conversion", __func__);
2187 return -EINVAL;
47dd7a54
GC		 2188}
2189
2190__setup("stmmaceth=", stmmac_cmdline_opt);
2191#endif
2192
db62f684 2193module_platform_driver(stmmac_driver);
47dd7a54
GC		 2194
2195MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2196MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2197MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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