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stmmac: support wake up irq from external sources (v3)
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
01789349 45#include <linux/if.h>
47dd7a54
GC		 46#include <linux/if_vlan.h>
47#include <linux/dma-mapping.h>
5a0e3ad6 48#include <linux/slab.h>
70c71606 49#include <linux/prefetch.h>
47dd7a54
GC		 50#include "stmmac.h"
51
52#define STMMAC_RESOURCE_NAME "stmmaceth"
47dd7a54
GC		 53
54#undef STMMAC_DEBUG
55/*#define STMMAC_DEBUG*/
56#ifdef STMMAC_DEBUG
57#define DBG(nlevel, klevel, fmt, args...) \
58 ((void)(netif_msg_##nlevel(priv) && \
59 printk(KERN_##klevel fmt, ## args)))
60#else
61#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
62#endif
63
64#undef STMMAC_RX_DEBUG
65/*#define STMMAC_RX_DEBUG*/
66#ifdef STMMAC_RX_DEBUG
67#define RX_DBG(fmt, args...) printk(fmt, ## args)
68#else
69#define RX_DBG(fmt, args...) do { } while (0)
70#endif
71
72#undef STMMAC_XMIT_DEBUG
73/*#define STMMAC_XMIT_DEBUG*/
74#ifdef STMMAC_TX_DEBUG
75#define TX_DBG(fmt, args...) printk(fmt, ## args)
76#else
77#define TX_DBG(fmt, args...) do { } while (0)
78#endif
79
80#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
81#define JUMBO_LEN 9000
82
83/* Module parameters */
84#define TX_TIMEO 5000 /* default 5 seconds */
85static int watchdog = TX_TIMEO;
86module_param(watchdog, int, S_IRUGO | S_IWUSR);
87MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
88
89static int debug = -1; /* -1: default, 0: no output, 16: all */
90module_param(debug, int, S_IRUGO | S_IWUSR);
91MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
92
93static int phyaddr = -1;
94module_param(phyaddr, int, S_IRUGO);
95MODULE_PARM_DESC(phyaddr, "Physical device address");
96
97#define DMA_TX_SIZE 256
98static int dma_txsize = DMA_TX_SIZE;
99module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
100MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
101
102#define DMA_RX_SIZE 256
103static int dma_rxsize = DMA_RX_SIZE;
104module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
105MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
106
107static int flow_ctrl = FLOW_OFF;
108module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
110
111static int pause = PAUSE_TIME;
112module_param(pause, int, S_IRUGO | S_IWUSR);
113MODULE_PARM_DESC(pause, "Flow Control Pause Time");
114
115#define TC_DEFAULT 64
116static int tc = TC_DEFAULT;
117module_param(tc, int, S_IRUGO | S_IWUSR);
118MODULE_PARM_DESC(tc, "DMA threshold control value");
119
47dd7a54
GC		 120/* Pay attention to tune this parameter; take care of both
121 * hardware capability and network stabitily/performance impact.
122 * Many tests showed that ~4ms latency seems to be good enough. */
123#ifdef CONFIG_STMMAC_TIMER
124#define DEFAULT_PERIODIC_RATE 256
125static int tmrate = DEFAULT_PERIODIC_RATE;
126module_param(tmrate, int, S_IRUGO | S_IWUSR);
127MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
128#endif
129
130#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
131static int buf_sz = DMA_BUFFER_SIZE;
132module_param(buf_sz, int, S_IRUGO | S_IWUSR);
133MODULE_PARM_DESC(buf_sz, "DMA buffer size");
134
47dd7a54
GC		 135static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
136 NETIF_MSG_LINK | NETIF_MSG_IFUP |
137 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
138
139static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54
GC		 140
141/**
142 * stmmac_verify_args - verify the driver parameters.
143 * Description: it verifies if some wrong parameter is passed to the driver.
144 * Note that wrong parameters are replaced with the default values.
145 */
146static void stmmac_verify_args(void)
147{
148 if (unlikely(watchdog < 0))
149 watchdog = TX_TIMEO;
150 if (unlikely(dma_rxsize < 0))
151 dma_rxsize = DMA_RX_SIZE;
152 if (unlikely(dma_txsize < 0))
153 dma_txsize = DMA_TX_SIZE;
154 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
155 buf_sz = DMA_BUFFER_SIZE;
156 if (unlikely(flow_ctrl > 1))
157 flow_ctrl = FLOW_AUTO;
158 else if (likely(flow_ctrl < 0))
159 flow_ctrl = FLOW_OFF;
160 if (unlikely((pause < 0) || (pause > 0xffff)))
161 pause = PAUSE_TIME;
47dd7a54
GC		 162}
163
164#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
165static void print_pkt(unsigned char *buf, int len)
166{
167 int j;
168 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
169 for (j = 0; j < len; j++) {
170 if ((j % 16) == 0)
171 pr_info("\n %03x:", j);
172 pr_info(" %02x", buf[j]);
173 }
174 pr_info("\n");
47dd7a54
GC		 175}
176#endif
177
178/* minimum number of free TX descriptors required to wake up TX process */
179#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
180
181static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
182{
183 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
184}
185
9dfeb4d9
GC		 186/* On some ST platforms, some HW system configuraton registers have to be
187 * set according to the link speed negotiated.
188 */
189static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
190{
191 struct phy_device *phydev = priv->phydev;
192
193 if (likely(priv->plat->fix_mac_speed))
194 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
195 phydev->speed);
196}
197
47dd7a54
GC		 198/**
199 * stmmac_adjust_link
200 * @dev: net device structure
201 * Description: it adjusts the link parameters.
202 */
203static void stmmac_adjust_link(struct net_device *dev)
204{
205 struct stmmac_priv *priv = netdev_priv(dev);
206 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 207 unsigned long flags;
208 int new_state = 0;
209 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
210
211 if (phydev == NULL)
212 return;
213
214 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
215 phydev->addr, phydev->link);
216
217 spin_lock_irqsave(&priv->lock, flags);
218 if (phydev->link) {
ad01b7d4 219 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 220
221 /* Now we make sure that we can be in full duplex mode.
222 * If not, we operate in half-duplex mode. */
223 if (phydev->duplex != priv->oldduplex) {
224 new_state = 1;
225 if (!(phydev->duplex))
db98a0b0 226 ctrl &= ~priv->hw->link.duplex;
47dd7a54 227 else
db98a0b0 228 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 229 priv->oldduplex = phydev->duplex;
230 }
231 /* Flow Control operation */
232 if (phydev->pause)
ad01b7d4 233 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 234 fc, pause_time);
47dd7a54
GC		 235
236 if (phydev->speed != priv->speed) {
237 new_state = 1;
238 switch (phydev->speed) {
239 case 1000:
9dfeb4d9 240 if (likely(priv->plat->has_gmac))
db98a0b0 241 ctrl &= ~priv->hw->link.port;
9dfeb4d9 242 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 243 break;
244 case 100:
245 case 10:
9dfeb4d9 246 if (priv->plat->has_gmac) {
db98a0b0 247 ctrl |= priv->hw->link.port;
47dd7a54 248 if (phydev->speed == SPEED_100) {
db98a0b0 249 ctrl |= priv->hw->link.speed;
47dd7a54 250 } else {
db98a0b0 251 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 252 }
253 } else {
db98a0b0 254 ctrl &= ~priv->hw->link.port;
47dd7a54 255 }
9dfeb4d9 256 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 257 break;
258 default:
259 if (netif_msg_link(priv))
260 pr_warning("%s: Speed (%d) is not 10"
261 " or 100!\n", dev->name, phydev->speed);
262 break;
263 }
264
265 priv->speed = phydev->speed;
266 }
267
ad01b7d4 268 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 269
270 if (!priv->oldlink) {
271 new_state = 1;
272 priv->oldlink = 1;
273 }
274 } else if (priv->oldlink) {
275 new_state = 1;
276 priv->oldlink = 0;
277 priv->speed = 0;
278 priv->oldduplex = -1;
279 }
280
281 if (new_state && netif_msg_link(priv))
282 phy_print_status(phydev);
283
284 spin_unlock_irqrestore(&priv->lock, flags);
285
286 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
287}
288
289/**
290 * stmmac_init_phy - PHY initialization
291 * @dev: net device structure
292 * Description: it initializes the driver's PHY state, and attaches the PHY
293 * to the mac driver.
294 * Return value:
295 * 0 on success
296 */
297static int stmmac_init_phy(struct net_device *dev)
298{
299 struct stmmac_priv *priv = netdev_priv(dev);
300 struct phy_device *phydev;
109cdd66
GC		 301 char phy_id[MII_BUS_ID_SIZE + 3];
302 char bus_id[MII_BUS_ID_SIZE];
47dd7a54
GC		 303
304 priv->oldlink = 0;
305 priv->speed = 0;
306 priv->oldduplex = -1;
307
9dfeb4d9 308 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
109cdd66 309 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 310 priv->plat->phy_addr);
47dd7a54
GC		 311 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
312
313 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
36bcfe7d 314 priv->plat->interface);
47dd7a54
GC		 315
316 if (IS_ERR(phydev)) {
317 pr_err("%s: Could not attach to PHY\n", dev->name);
318 return PTR_ERR(phydev);
319 }
320
321 /*
322 * Broken HW is sometimes missing the pull-up resistor on the
323 * MDIO line, which results in reads to non-existent devices returning
324 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
325 * device as well.
326 * Note: phydev->phy_id is the result of reading the UID PHY registers.
327 */
328 if (phydev->phy_id == 0) {
329 phy_disconnect(phydev);
330 return -ENODEV;
331 }
332 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 333 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 334
335 priv->phydev = phydev;
336
337 return 0;
338}
339
19449bfc 340static inline void stmmac_enable_mac(void __iomem *ioaddr)
47dd7a54
GC		 341{
342 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 343
19449bfc 344 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
47dd7a54
GC		 345 writel(value, ioaddr + MAC_CTRL_REG);
346}
347
19449bfc 348static inline void stmmac_disable_mac(void __iomem *ioaddr)
47dd7a54
GC		 349{
350 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 351
19449bfc 352 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
47dd7a54
GC		 353 writel(value, ioaddr + MAC_CTRL_REG);
354}
355
356/**
357 * display_ring
358 * @p: pointer to the ring.
359 * @size: size of the ring.
360 * Description: display all the descriptors within the ring.
361 */
362static void display_ring(struct dma_desc *p, int size)
363{
364 struct tmp_s {
365 u64 a;
366 unsigned int b;
367 unsigned int c;
368 };
369 int i;
370 for (i = 0; i < size; i++) {
371 struct tmp_s *x = (struct tmp_s *)(p + i);
372 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
373 i, (unsigned int)virt_to_phys(&p[i]),
374 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
375 x->b, x->c);
376 pr_info("\n");
377 }
378}
379
380/**
381 * init_dma_desc_rings - init the RX/TX descriptor rings
382 * @dev: net device structure
383 * Description: this function initializes the DMA RX/TX descriptors
384 * and allocates the socket buffers.
385 */
386static void init_dma_desc_rings(struct net_device *dev)
387{
388 int i;
389 struct stmmac_priv *priv = netdev_priv(dev);
390 struct sk_buff *skb;
391 unsigned int txsize = priv->dma_tx_size;
392 unsigned int rxsize = priv->dma_rx_size;
393 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 394 int buff2_needed = 0, dis_ic = 0;
47dd7a54 395
47dd7a54
GC		 396 /* Set the Buffer size according to the MTU;
397 * indeed, in case of jumbo we need to bump-up the buffer sizes.
398 */
399 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
400 bfsize = BUF_SIZE_16KiB;
401 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
402 bfsize = BUF_SIZE_8KiB;
403 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
404 bfsize = BUF_SIZE_4KiB;
405 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
406 bfsize = BUF_SIZE_2KiB;
407 else
408 bfsize = DMA_BUFFER_SIZE;
409
73cfe264
GC		 410#ifdef CONFIG_STMMAC_TIMER
411 /* Disable interrupts on completion for the reception if timer is on */
412 if (likely(priv->tm->enable))
413 dis_ic = 1;
414#endif
47dd7a54
GC		 415 /* If the MTU exceeds 8k so use the second buffer in the chain */
416 if (bfsize >= BUF_SIZE_8KiB)
417 buff2_needed = 1;
418
419 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
420 txsize, rxsize, bfsize);
421
422 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
423 priv->rx_skbuff =
424 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
425 priv->dma_rx =
426 (struct dma_desc *)dma_alloc_coherent(priv->device,
427 rxsize *
428 sizeof(struct dma_desc),
429 &priv->dma_rx_phy,
430 GFP_KERNEL);
431 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
432 GFP_KERNEL);
433 priv->dma_tx =
434 (struct dma_desc *)dma_alloc_coherent(priv->device,
435 txsize *
436 sizeof(struct dma_desc),
437 &priv->dma_tx_phy,
438 GFP_KERNEL);
439
440 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
441 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
442 return;
443 }
444
445 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
446 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
447 dev->name, priv->dma_rx, priv->dma_tx,
448 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
449
450 /* RX INITIALIZATION */
451 DBG(probe, INFO, "stmmac: SKB addresses:\n"
452 "skb\t\tskb data\tdma data\n");
453
454 for (i = 0; i < rxsize; i++) {
455 struct dma_desc *p = priv->dma_rx + i;
456
457 skb = netdev_alloc_skb_ip_align(dev, bfsize);
458 if (unlikely(skb == NULL)) {
459 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
460 break;
461 }
462 priv->rx_skbuff[i] = skb;
463 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
464 bfsize, DMA_FROM_DEVICE);
465
466 p->des2 = priv->rx_skbuff_dma[i];
467 if (unlikely(buff2_needed))
468 p->des3 = p->des2 + BUF_SIZE_8KiB;
469 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
470 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
471 }
472 priv->cur_rx = 0;
473 priv->dirty_rx = (unsigned int)(i - rxsize);
474 priv->dma_buf_sz = bfsize;
475 buf_sz = bfsize;
476
477 /* TX INITIALIZATION */
478 for (i = 0; i < txsize; i++) {
479 priv->tx_skbuff[i] = NULL;
480 priv->dma_tx[i].des2 = 0;
481 }
482 priv->dirty_tx = 0;
483 priv->cur_tx = 0;
484
485 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 486 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
487 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 488
489 if (netif_msg_hw(priv)) {
490 pr_info("RX descriptor ring:\n");
491 display_ring(priv->dma_rx, rxsize);
492 pr_info("TX descriptor ring:\n");
493 display_ring(priv->dma_tx, txsize);
494 }
47dd7a54
GC		 495}
496
497static void dma_free_rx_skbufs(struct stmmac_priv *priv)
498{
499 int i;
500
501 for (i = 0; i < priv->dma_rx_size; i++) {
502 if (priv->rx_skbuff[i]) {
503 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
504 priv->dma_buf_sz, DMA_FROM_DEVICE);
505 dev_kfree_skb_any(priv->rx_skbuff[i]);
506 }
507 priv->rx_skbuff[i] = NULL;
508 }
47dd7a54
GC		 509}
510
511static void dma_free_tx_skbufs(struct stmmac_priv *priv)
512{
513 int i;
514
515 for (i = 0; i < priv->dma_tx_size; i++) {
516 if (priv->tx_skbuff[i] != NULL) {
517 struct dma_desc *p = priv->dma_tx + i;
518 if (p->des2)
519 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 520 priv->hw->desc->get_tx_len(p),
521 DMA_TO_DEVICE);
47dd7a54
GC		 522 dev_kfree_skb_any(priv->tx_skbuff[i]);
523 priv->tx_skbuff[i] = NULL;
524 }
525 }
47dd7a54
GC		 526}
527
528static void free_dma_desc_resources(struct stmmac_priv *priv)
529{
530 /* Release the DMA TX/RX socket buffers */
531 dma_free_rx_skbufs(priv);
532 dma_free_tx_skbufs(priv);
533
534 /* Free the region of consistent memory previously allocated for
535 * the DMA */
536 dma_free_coherent(priv->device,
537 priv->dma_tx_size * sizeof(struct dma_desc),
538 priv->dma_tx, priv->dma_tx_phy);
539 dma_free_coherent(priv->device,
540 priv->dma_rx_size * sizeof(struct dma_desc),
541 priv->dma_rx, priv->dma_rx_phy);
542 kfree(priv->rx_skbuff_dma);
543 kfree(priv->rx_skbuff);
544 kfree(priv->tx_skbuff);
47dd7a54
GC		 545}
546
47dd7a54
GC		 547/**
548 * stmmac_dma_operation_mode - HW DMA operation mode
549 * @priv : pointer to the private device structure.
550 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 551 * or Store-And-Forward capability.
47dd7a54
GC		 552 */
553static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
554{
61b8013a
SK		 555 if (likely(priv->plat->force_sf_dma_mode ||
556 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
557 /*
558 * In case of GMAC, SF mode can be enabled
559 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 560 * 1) TX COE if actually supported
561 * 2) There is no bugged Jumbo frame support
562 * that needs to not insert csum in the TDES.
563 */
564 priv->hw->dma->dma_mode(priv->ioaddr,
565 SF_DMA_MODE, SF_DMA_MODE);
566 tc = SF_DMA_MODE;
567 } else
568 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 569}
570
47dd7a54
GC		 571/**
572 * stmmac_tx:
573 * @priv: private driver structure
574 * Description: it reclaims resources after transmission completes.
575 */
576static void stmmac_tx(struct stmmac_priv *priv)
577{
578 unsigned int txsize = priv->dma_tx_size;
47dd7a54
GC		 579
580 while (priv->dirty_tx != priv->cur_tx) {
581 int last;
582 unsigned int entry = priv->dirty_tx % txsize;
583 struct sk_buff *skb = priv->tx_skbuff[entry];
584 struct dma_desc *p = priv->dma_tx + entry;
585
586 /* Check if the descriptor is owned by the DMA. */
db98a0b0 587 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 588 break;
589
590 /* Verify tx error by looking at the last segment */
db98a0b0 591 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 592 if (likely(last)) {
593 int tx_error =
db98a0b0
GC		 594 priv->hw->desc->tx_status(&priv->dev->stats,
595 &priv->xstats, p,
ad01b7d4 596 priv->ioaddr);
47dd7a54
GC		 597 if (likely(tx_error == 0)) {
598 priv->dev->stats.tx_packets++;
599 priv->xstats.tx_pkt_n++;
600 } else
601 priv->dev->stats.tx_errors++;
602 }
603 TX_DBG("%s: curr %d, dirty %d\n", __func__,
604 priv->cur_tx, priv->dirty_tx);
605
606 if (likely(p->des2))
607 dma_unmap_single(priv->device, p->des2,
db98a0b0 608 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 609 DMA_TO_DEVICE);
610 if (unlikely(p->des3))
611 p->des3 = 0;
612
613 if (likely(skb != NULL)) {
614 /*
615 * If there's room in the queue (limit it to size)
616 * we add this skb back into the pool,
617 * if it's the right size.
618 */
619 if ((skb_queue_len(&priv->rx_recycle) <
620 priv->dma_rx_size) &&
621 skb_recycle_check(skb, priv->dma_buf_sz))
622 __skb_queue_head(&priv->rx_recycle, skb);
623 else
624 dev_kfree_skb(skb);
625
626 priv->tx_skbuff[entry] = NULL;
627 }
628
db98a0b0 629 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 630
631 entry = (++priv->dirty_tx) % txsize;
632 }
633 if (unlikely(netif_queue_stopped(priv->dev) &&
634 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
635 netif_tx_lock(priv->dev);
636 if (netif_queue_stopped(priv->dev) &&
637 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
638 TX_DBG("%s: restart transmit\n", __func__);
639 netif_wake_queue(priv->dev);
640 }
641 netif_tx_unlock(priv->dev);
642 }
47dd7a54
GC		 643}
644
645static inline void stmmac_enable_irq(struct stmmac_priv *priv)
646{
73cfe264
GC		 647#ifdef CONFIG_STMMAC_TIMER
648 if (likely(priv->tm->enable))
649 priv->tm->timer_start(tmrate);
650 else
47dd7a54 651#endif
ad01b7d4 652 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 653}
654
655static inline void stmmac_disable_irq(struct stmmac_priv *priv)
656{
73cfe264
GC		 657#ifdef CONFIG_STMMAC_TIMER
658 if (likely(priv->tm->enable))
659 priv->tm->timer_stop();
660 else
47dd7a54 661#endif
ad01b7d4 662 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 663}
664
665static int stmmac_has_work(struct stmmac_priv *priv)
666{
667 unsigned int has_work = 0;
668 int rxret, tx_work = 0;
669
db98a0b0 670 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 671 (priv->cur_rx % priv->dma_rx_size));
672
673 if (priv->dirty_tx != priv->cur_tx)
674 tx_work = 1;
675
676 if (likely(!rxret || tx_work))
677 has_work = 1;
678
679 return has_work;
680}
681
682static inline void _stmmac_schedule(struct stmmac_priv *priv)
683{
684 if (likely(stmmac_has_work(priv))) {
685 stmmac_disable_irq(priv);
686 napi_schedule(&priv->napi);
687 }
688}
689
690#ifdef CONFIG_STMMAC_TIMER
691void stmmac_schedule(struct net_device *dev)
692{
693 struct stmmac_priv *priv = netdev_priv(dev);
694
695 priv->xstats.sched_timer_n++;
696
697 _stmmac_schedule(priv);
47dd7a54
GC		 698}
699
700static void stmmac_no_timer_started(unsigned int x)
701{;
702};
703
704static void stmmac_no_timer_stopped(void)
705{;
706};
707#endif
708
709/**
710 * stmmac_tx_err:
711 * @priv: pointer to the private device structure
712 * Description: it cleans the descriptors and restarts the transmission
713 * in case of errors.
714 */
715static void stmmac_tx_err(struct stmmac_priv *priv)
716{
ad01b7d4 717
47dd7a54
GC		 718 netif_stop_queue(priv->dev);
719
ad01b7d4 720 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 721 dma_free_tx_skbufs(priv);
db98a0b0 722 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 723 priv->dirty_tx = 0;
724 priv->cur_tx = 0;
ad01b7d4 725 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 726
727 priv->dev->stats.tx_errors++;
728 netif_wake_queue(priv->dev);
47dd7a54
GC		 729}
730
47dd7a54 731
aec7ff27
GC		 732static void stmmac_dma_interrupt(struct stmmac_priv *priv)
733{
aec7ff27
GC		 734 int status;
735
ad01b7d4 736 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 737 if (likely(status == handle_tx_rx))
738 _stmmac_schedule(priv);
739
740 else if (unlikely(status == tx_hard_error_bump_tc)) {
741 /* Try to bump up the dma threshold on this failure */
742 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
743 tc += 64;
ad01b7d4 744 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 745 priv->xstats.threshold = tc;
47dd7a54 746 }
aec7ff27
GC		 747 } else if (unlikely(status == tx_hard_error))
748 stmmac_tx_err(priv);
47dd7a54
GC		 749}
750
751/**
752 * stmmac_open - open entry point of the driver
753 * @dev : pointer to the device structure.
754 * Description:
755 * This function is the open entry point of the driver.
756 * Return value:
757 * 0 on success and an appropriate (-)ve integer as defined in errno.h
758 * file on failure.
759 */
760static int stmmac_open(struct net_device *dev)
761{
762 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 763 int ret;
764
765 /* Check that the MAC address is valid. If its not, refuse
766 * to bring the device up. The user must specify an
767 * address using the following linux command:
768 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
769 if (!is_valid_ether_addr(dev->dev_addr)) {
770 random_ether_addr(dev->dev_addr);
771 pr_warning("%s: generated random MAC address %pM\n", dev->name,
772 dev->dev_addr);
773 }
774
775 stmmac_verify_args();
776
47dd7a54 777#ifdef CONFIG_STMMAC_TIMER
73cfe264 778 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 779 if (unlikely(priv->tm == NULL)) {
2381a55c 780 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 781 return -ENOMEM;
782 }
783 priv->tm->freq = tmrate;
784
73cfe264
GC		 785 /* Test if the external timer can be actually used.
786 * In case of failure continue without timer. */
47dd7a54 787 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 788 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 789 priv->tm->freq = 0;
790 priv->tm->timer_start = stmmac_no_timer_started;
791 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 792 } else
793 priv->tm->enable = 1;
47dd7a54 794#endif
f66ffe28
GC		 795 ret = stmmac_init_phy(dev);
796 if (unlikely(ret)) {
797 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
798 goto open_error;
799 }
47dd7a54
GC		 800
801 /* Create and initialize the TX/RX descriptors chains. */
802 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
803 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
804 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
805 init_dma_desc_rings(dev);
806
807 /* DMA initialization and SW reset */
f66ffe28
GC		 808 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
809 priv->dma_tx_phy, priv->dma_rx_phy);
810 if (ret < 0) {
47dd7a54 811 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 812 goto open_error;
47dd7a54
GC		 813 }
814
815 /* Copy the MAC addr into the HW */
ad01b7d4 816 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1 817 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 818 if (priv->plat->bus_setup)
819 priv->plat->bus_setup(priv->ioaddr);
47dd7a54 820 /* Initialize the MAC Core */
ad01b7d4 821 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 822
ebbb293f
GC		 823 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
824 if (priv->rx_coe)
825 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
9dfeb4d9 826 if (priv->plat->tx_coe)
ebbb293f 827 pr_info("\tTX Checksum insertion supported\n");
5e982f3b 828 netdev_update_features(dev);
ebbb293f 829
f66ffe28
GC		 830 /* Request the IRQ lines */
831 ret = request_irq(dev->irq, stmmac_interrupt,
832 IRQF_SHARED, dev->name, dev);
833 if (unlikely(ret < 0)) {
834 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
835 __func__, dev->irq, ret);
836 goto open_error;
837 }
838
47dd7a54 839 /* Enable the MAC Rx/Tx */
19449bfc 840 stmmac_enable_mac(priv->ioaddr);
47dd7a54
GC		 841
842 /* Set the HW DMA mode and the COE */
843 stmmac_dma_operation_mode(priv);
844
845 /* Extra statistics */
846 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
847 priv->xstats.threshold = tc;
848
849 /* Start the ball rolling... */
850 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 851 priv->hw->dma->start_tx(priv->ioaddr);
852 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 853
854#ifdef CONFIG_STMMAC_TIMER
855 priv->tm->timer_start(tmrate);
856#endif
857 /* Dump DMA/MAC registers */
858 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 859 priv->hw->mac->dump_regs(priv->ioaddr);
860 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 861 }
862
863 if (priv->phydev)
864 phy_start(priv->phydev);
865
866 napi_enable(&priv->napi);
867 skb_queue_head_init(&priv->rx_recycle);
868 netif_start_queue(dev);
f66ffe28 869
47dd7a54 870 return 0;
f66ffe28
GC		 871
872open_error:
873#ifdef CONFIG_STMMAC_TIMER
874 kfree(priv->tm);
875#endif
876 if (priv->phydev)
877 phy_disconnect(priv->phydev);
878
879 return ret;
47dd7a54
GC		 880}
881
882/**
883 * stmmac_release - close entry point of the driver
884 * @dev : device pointer.
885 * Description:
886 * This is the stop entry point of the driver.
887 */
888static int stmmac_release(struct net_device *dev)
889{
890 struct stmmac_priv *priv = netdev_priv(dev);
891
892 /* Stop and disconnect the PHY */
893 if (priv->phydev) {
894 phy_stop(priv->phydev);
895 phy_disconnect(priv->phydev);
896 priv->phydev = NULL;
897 }
898
899 netif_stop_queue(dev);
900
901#ifdef CONFIG_STMMAC_TIMER
902 /* Stop and release the timer */
903 stmmac_close_ext_timer();
904 if (priv->tm != NULL)
905 kfree(priv->tm);
906#endif
907 napi_disable(&priv->napi);
908 skb_queue_purge(&priv->rx_recycle);
909
910 /* Free the IRQ lines */
911 free_irq(dev->irq, dev);
912
913 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 914 priv->hw->dma->stop_tx(priv->ioaddr);
915 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 916
917 /* Release and free the Rx/Tx resources */
918 free_dma_desc_resources(priv);
919
19449bfc 920 /* Disable the MAC Rx/Tx */
921 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 922
923 netif_carrier_off(dev);
924
925 return 0;
926}
927
47dd7a54
GC		 928static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
929 struct net_device *dev,
930 int csum_insertion)
931{
932 struct stmmac_priv *priv = netdev_priv(dev);
933 unsigned int nopaged_len = skb_headlen(skb);
934 unsigned int txsize = priv->dma_tx_size;
935 unsigned int entry = priv->cur_tx % txsize;
936 struct dma_desc *desc = priv->dma_tx + entry;
937
938 if (nopaged_len > BUF_SIZE_8KiB) {
939
940 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
941
942 desc->des2 = dma_map_single(priv->device, skb->data,
943 BUF_SIZE_8KiB, DMA_TO_DEVICE);
944 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 945 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
946 csum_insertion);
47dd7a54
GC		 947
948 entry = (++priv->cur_tx) % txsize;
949 desc = priv->dma_tx + entry;
950
951 desc->des2 = dma_map_single(priv->device,
952 skb->data + BUF_SIZE_8KiB,
953 buf2_size, DMA_TO_DEVICE);
954 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 955 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
956 csum_insertion);
957 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 958 priv->tx_skbuff[entry] = NULL;
959 } else {
960 desc->des2 = dma_map_single(priv->device, skb->data,
961 nopaged_len, DMA_TO_DEVICE);
962 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 963 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
964 csum_insertion);
47dd7a54
GC		 965 }
966 return entry;
967}
968
969/**
970 * stmmac_xmit:
971 * @skb : the socket buffer
972 * @dev : device pointer
973 * Description : Tx entry point of the driver.
974 */
975static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
976{
977 struct stmmac_priv *priv = netdev_priv(dev);
978 unsigned int txsize = priv->dma_tx_size;
979 unsigned int entry;
980 int i, csum_insertion = 0;
981 int nfrags = skb_shinfo(skb)->nr_frags;
982 struct dma_desc *desc, *first;
983
984 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
985 if (!netif_queue_stopped(dev)) {
986 netif_stop_queue(dev);
987 /* This is a hard error, log it. */
988 pr_err("%s: BUG! Tx Ring full when queue awake\n",
989 __func__);
990 }
991 return NETDEV_TX_BUSY;
992 }
993
994 entry = priv->cur_tx % txsize;
995
996#ifdef STMMAC_XMIT_DEBUG
997 if ((skb->len > ETH_FRAME_LEN) || nfrags)
998 pr_info("stmmac xmit:\n"
999 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1000 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1001 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1002 !skb_is_gso(skb) ? "isn't" : "is");
1003#endif
1004
5e982f3b 1005 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1006
1007 desc = priv->dma_tx + entry;
1008 first = desc;
1009
1010#ifdef STMMAC_XMIT_DEBUG
1011 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1012 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1013 "\t\tn_frags: %d, ip_summed: %d\n",
1014 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1015#endif
1016 priv->tx_skbuff[entry] = skb;
1017 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1018 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1019 desc = priv->dma_tx + entry;
1020 } else {
1021 unsigned int nopaged_len = skb_headlen(skb);
1022 desc->des2 = dma_map_single(priv->device, skb->data,
1023 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1024 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1025 csum_insertion);
47dd7a54
GC		 1026 }
1027
1028 for (i = 0; i < nfrags; i++) {
1029 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1030 int len = frag->size;
1031
1032 entry = (++priv->cur_tx) % txsize;
1033 desc = priv->dma_tx + entry;
1034
1035 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1036 desc->des2 = dma_map_page(priv->device, frag->page,
1037 frag->page_offset,
1038 len, DMA_TO_DEVICE);
1039 priv->tx_skbuff[entry] = NULL;
db98a0b0 1040 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1041 wmb();
db98a0b0 1042 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1043 }
1044
1045 /* Interrupt on completition only for the latest segment */
db98a0b0 1046 priv->hw->desc->close_tx_desc(desc);
73cfe264 1047
47dd7a54 1048#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1049 /* Clean IC while using timer */
1050 if (likely(priv->tm->enable))
db98a0b0 1051 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1052#endif
eb0dc4bb
SH		 1053
1054 wmb();
1055
47dd7a54 1056 /* To avoid raise condition */
db98a0b0 1057 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1058
1059 priv->cur_tx++;
1060
1061#ifdef STMMAC_XMIT_DEBUG
1062 if (netif_msg_pktdata(priv)) {
1063 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1064 "first=%p, nfrags=%d\n",
1065 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1066 entry, first, nfrags);
1067 display_ring(priv->dma_tx, txsize);
1068 pr_info(">>> frame to be transmitted: ");
1069 print_pkt(skb->data, skb->len);
1070 }
1071#endif
1072 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1073 TX_DBG("%s: stop transmitted packets\n", __func__);
1074 netif_stop_queue(dev);
1075 }
1076
1077 dev->stats.tx_bytes += skb->len;
1078
3e82ce12
RC		 1079 skb_tx_timestamp(skb);
1080
52f64fae
RC		 1081 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1082
47dd7a54
GC		 1083 return NETDEV_TX_OK;
1084}
1085
1086static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1087{
1088 unsigned int rxsize = priv->dma_rx_size;
1089 int bfsize = priv->dma_buf_sz;
1090 struct dma_desc *p = priv->dma_rx;
1091
1092 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1093 unsigned int entry = priv->dirty_rx % rxsize;
1094 if (likely(priv->rx_skbuff[entry] == NULL)) {
1095 struct sk_buff *skb;
1096
1097 skb = __skb_dequeue(&priv->rx_recycle);
1098 if (skb == NULL)
1099 skb = netdev_alloc_skb_ip_align(priv->dev,
1100 bfsize);
1101
1102 if (unlikely(skb == NULL))
1103 break;
1104
1105 priv->rx_skbuff[entry] = skb;
1106 priv->rx_skbuff_dma[entry] =
1107 dma_map_single(priv->device, skb->data, bfsize,
1108 DMA_FROM_DEVICE);
1109
1110 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
9dfeb4d9 1111 if (unlikely(priv->plat->has_gmac)) {
47dd7a54
GC		 1112 if (bfsize >= BUF_SIZE_8KiB)
1113 (p + entry)->des3 =
1114 (p + entry)->des2 + BUF_SIZE_8KiB;
1115 }
1116 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1117 }
eb0dc4bb 1118 wmb();
db98a0b0 1119 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1120 }
47dd7a54
GC		 1121}
1122
1123static int stmmac_rx(struct stmmac_priv *priv, int limit)
1124{
1125 unsigned int rxsize = priv->dma_rx_size;
1126 unsigned int entry = priv->cur_rx % rxsize;
1127 unsigned int next_entry;
1128 unsigned int count = 0;
1129 struct dma_desc *p = priv->dma_rx + entry;
1130 struct dma_desc *p_next;
1131
1132#ifdef STMMAC_RX_DEBUG
1133 if (netif_msg_hw(priv)) {
1134 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1135 display_ring(priv->dma_rx, rxsize);
1136 }
1137#endif
1138 count = 0;
db98a0b0 1139 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1140 int status;
1141
1142 if (count >= limit)
1143 break;
1144
1145 count++;
1146
1147 next_entry = (++priv->cur_rx) % rxsize;
1148 p_next = priv->dma_rx + next_entry;
1149 prefetch(p_next);
1150
1151 /* read the status of the incoming frame */
db98a0b0
GC		 1152 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1153 &priv->xstats, p));
47dd7a54
GC		 1154 if (unlikely(status == discard_frame))
1155 priv->dev->stats.rx_errors++;
1156 else {
1157 struct sk_buff *skb;
3eeb2997 1158 int frame_len;
47dd7a54 1159
3eeb2997
GC		 1160 frame_len = priv->hw->desc->get_rx_frame_len(p);
1161 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1162 * Type frames (LLC/LLC-SNAP) */
1163 if (unlikely(status != llc_snap))
1164 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1165#ifdef STMMAC_RX_DEBUG
1166 if (frame_len > ETH_FRAME_LEN)
1167 pr_debug("\tRX frame size %d, COE status: %d\n",
1168 frame_len, status);
1169
1170 if (netif_msg_hw(priv))
1171 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1172 p, entry, p->des2);
1173#endif
1174 skb = priv->rx_skbuff[entry];
1175 if (unlikely(!skb)) {
1176 pr_err("%s: Inconsistent Rx descriptor chain\n",
1177 priv->dev->name);
1178 priv->dev->stats.rx_dropped++;
1179 break;
1180 }
1181 prefetch(skb->data - NET_IP_ALIGN);
1182 priv->rx_skbuff[entry] = NULL;
1183
1184 skb_put(skb, frame_len);
1185 dma_unmap_single(priv->device,
1186 priv->rx_skbuff_dma[entry],
1187 priv->dma_buf_sz, DMA_FROM_DEVICE);
1188#ifdef STMMAC_RX_DEBUG
1189 if (netif_msg_pktdata(priv)) {
1190 pr_info(" frame received (%dbytes)", frame_len);
1191 print_pkt(skb->data, frame_len);
1192 }
1193#endif
1194 skb->protocol = eth_type_trans(skb, priv->dev);
1195
1196 if (unlikely(status == csum_none)) {
1197 /* always for the old mac 10/100 */
bc8acf2c 1198 skb_checksum_none_assert(skb);
47dd7a54
GC		 1199 netif_receive_skb(skb);
1200 } else {
1201 skb->ip_summed = CHECKSUM_UNNECESSARY;
1202 napi_gro_receive(&priv->napi, skb);
1203 }
1204
1205 priv->dev->stats.rx_packets++;
1206 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1207 }
1208 entry = next_entry;
1209 p = p_next; /* use prefetched values */
1210 }
1211
1212 stmmac_rx_refill(priv);
1213
1214 priv->xstats.rx_pkt_n += count;
1215
1216 return count;
1217}
1218
1219/**
1220 * stmmac_poll - stmmac poll method (NAPI)
1221 * @napi : pointer to the napi structure.
1222 * @budget : maximum number of packets that the current CPU can receive from
1223 * all interfaces.
1224 * Description :
1225 * This function implements the the reception process.
1226 * Also it runs the TX completion thread
1227 */
1228static int stmmac_poll(struct napi_struct *napi, int budget)
1229{
1230 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1231 int work_done = 0;
1232
1233 priv->xstats.poll_n++;
1234 stmmac_tx(priv);
1235 work_done = stmmac_rx(priv, budget);
1236
1237 if (work_done < budget) {
1238 napi_complete(napi);
1239 stmmac_enable_irq(priv);
1240 }
1241 return work_done;
1242}
1243
1244/**
1245 * stmmac_tx_timeout
1246 * @dev : Pointer to net device structure
1247 * Description: this function is called when a packet transmission fails to
1248 * complete within a reasonable tmrate. The driver will mark the error in the
1249 * netdev structure and arrange for the device to be reset to a sane state
1250 * in order to transmit a new packet.
1251 */
1252static void stmmac_tx_timeout(struct net_device *dev)
1253{
1254 struct stmmac_priv *priv = netdev_priv(dev);
1255
1256 /* Clear Tx resources and restart transmitting again */
1257 stmmac_tx_err(priv);
47dd7a54
GC		 1258}
1259
1260/* Configuration changes (passed on by ifconfig) */
1261static int stmmac_config(struct net_device *dev, struct ifmap *map)
1262{
1263 if (dev->flags & IFF_UP) /* can't act on a running interface */
1264 return -EBUSY;
1265
1266 /* Don't allow changing the I/O address */
1267 if (map->base_addr != dev->base_addr) {
1268 pr_warning("%s: can't change I/O address\n", dev->name);
1269 return -EOPNOTSUPP;
1270 }
1271
1272 /* Don't allow changing the IRQ */
1273 if (map->irq != dev->irq) {
1274 pr_warning("%s: can't change IRQ number %d\n",
1275 dev->name, dev->irq);
1276 return -EOPNOTSUPP;
1277 }
1278
1279 /* ignore other fields */
1280 return 0;
1281}
1282
1283/**
01789349 1284 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1285 * @dev : pointer to the device structure
1286 * Description:
1287 * This function is a driver entry point which gets called by the kernel
1288 * whenever multicast addresses must be enabled/disabled.
1289 * Return value:
1290 * void.
1291 */
01789349 1292static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1293{
1294 struct stmmac_priv *priv = netdev_priv(dev);
1295
1296 spin_lock(&priv->lock);
db98a0b0 1297 priv->hw->mac->set_filter(dev);
47dd7a54 1298 spin_unlock(&priv->lock);
47dd7a54
GC		 1299}
1300
1301/**
1302 * stmmac_change_mtu - entry point to change MTU size for the device.
1303 * @dev : device pointer.
1304 * @new_mtu : the new MTU size for the device.
1305 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1306 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1307 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1308 * Return value:
1309 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1310 * file on failure.
1311 */
1312static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1313{
1314 struct stmmac_priv *priv = netdev_priv(dev);
1315 int max_mtu;
1316
1317 if (netif_running(dev)) {
1318 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1319 return -EBUSY;
1320 }
1321
9dfeb4d9 1322 if (priv->plat->has_gmac)
47dd7a54
GC		 1323 max_mtu = JUMBO_LEN;
1324 else
1325 max_mtu = ETH_DATA_LEN;
1326
1327 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1328 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1329 return -EINVAL;
1330 }
1331
5e982f3b
MM		 1332 dev->mtu = new_mtu;
1333 netdev_update_features(dev);
1334
1335 return 0;
1336}
1337
1338static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1339{
1340 struct stmmac_priv *priv = netdev_priv(dev);
1341
1342 if (!priv->rx_coe)
1343 features &= ~NETIF_F_RXCSUM;
1344 if (!priv->plat->tx_coe)
1345 features &= ~NETIF_F_ALL_CSUM;
1346
ebbb293f
GC		 1347 /* Some GMAC devices have a bugged Jumbo frame support that
1348 * needs to have the Tx COE disabled for oversized frames
1349 * (due to limited buffer sizes). In this case we disable
1350 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1351 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1352 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1353
5e982f3b 1354 return features;
47dd7a54
GC		 1355}
1356
1357static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1358{
1359 struct net_device *dev = (struct net_device *)dev_id;
1360 struct stmmac_priv *priv = netdev_priv(dev);
1361
1362 if (unlikely(!dev)) {
1363 pr_err("%s: invalid dev pointer\n", __func__);
1364 return IRQ_NONE;
1365 }
1366
9dfeb4d9 1367 if (priv->plat->has_gmac)
47dd7a54 1368 /* To handle GMAC own interrupts */
ad01b7d4 1369 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1370
1371 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1372
1373 return IRQ_HANDLED;
1374}
1375
1376#ifdef CONFIG_NET_POLL_CONTROLLER
1377/* Polling receive - used by NETCONSOLE and other diagnostic tools
1378 * to allow network I/O with interrupts disabled. */
1379static void stmmac_poll_controller(struct net_device *dev)
1380{
1381 disable_irq(dev->irq);
1382 stmmac_interrupt(dev->irq, dev);
1383 enable_irq(dev->irq);
1384}
1385#endif
1386
1387/**
1388 * stmmac_ioctl - Entry point for the Ioctl
1389 * @dev: Device pointer.
1390 * @rq: An IOCTL specefic structure, that can contain a pointer to
1391 * a proprietary structure used to pass information to the driver.
1392 * @cmd: IOCTL command
1393 * Description:
1394 * Currently there are no special functionality supported in IOCTL, just the
1395 * phy_mii_ioctl(...) can be invoked.
1396 */
1397static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1398{
1399 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1400 int ret;
47dd7a54
GC		 1401
1402 if (!netif_running(dev))
1403 return -EINVAL;
1404
28b04113
RC		 1405 if (!priv->phydev)
1406 return -EINVAL;
1407
1408 spin_lock(&priv->lock);
1409 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1410 spin_unlock(&priv->lock);
1411
47dd7a54
GC		 1412 return ret;
1413}
1414
47dd7a54
GC		 1415static const struct net_device_ops stmmac_netdev_ops = {
1416 .ndo_open = stmmac_open,
1417 .ndo_start_xmit = stmmac_xmit,
1418 .ndo_stop = stmmac_release,
1419 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1420 .ndo_fix_features = stmmac_fix_features,
01789349 1421 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1422 .ndo_tx_timeout = stmmac_tx_timeout,
1423 .ndo_do_ioctl = stmmac_ioctl,
1424 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1425#ifdef CONFIG_NET_POLL_CONTROLLER
1426 .ndo_poll_controller = stmmac_poll_controller,
1427#endif
1428 .ndo_set_mac_address = eth_mac_addr,
1429};
1430
1431/**
1432 * stmmac_probe - Initialization of the adapter .
1433 * @dev : device pointer
1434 * Description: The function initializes the network device structure for
1435 * the STMMAC driver. It also calls the low level routines
1436 * in order to init the HW (i.e. the DMA engine)
1437 */
1438static int stmmac_probe(struct net_device *dev)
1439{
1440 int ret = 0;
1441 struct stmmac_priv *priv = netdev_priv(dev);
1442
1443 ether_setup(dev);
1444
1445 dev->netdev_ops = &stmmac_netdev_ops;
1446 stmmac_set_ethtool_ops(dev);
1447
5e982f3b
MM		 1448 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1449 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
47dd7a54
GC		 1450 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1451#ifdef STMMAC_VLAN_TAG_USED
1452 /* Both mac100 and gmac support receive VLAN tag detection */
1453 dev->features |= NETIF_F_HW_VLAN_RX;
1454#endif
1455 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1456
47dd7a54
GC		 1457 if (flow_ctrl)
1458 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1459
1460 priv->pause = pause;
1461 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1462
1463 /* Get the MAC address */
ad01b7d4
GC		 1464 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1465 dev->dev_addr, 0);
47dd7a54
GC		 1466
1467 if (!is_valid_ether_addr(dev->dev_addr))
1468 pr_warning("\tno valid MAC address;"
1469 "please, use ifconfig or nwhwconfig!\n");
1470
f8e96161
VL		 1471 spin_lock_init(&priv->lock);
1472
47dd7a54
GC		 1473 ret = register_netdev(dev);
1474 if (ret) {
1475 pr_err("%s: ERROR %i registering the device\n",
1476 __func__, ret);
1477 return -ENODEV;
1478 }
1479
1480 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1481 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
79032644 1482 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
47dd7a54 1483
47dd7a54
GC		 1484 return ret;
1485}
1486
1487/**
1488 * stmmac_mac_device_setup
1489 * @dev : device pointer
1490 * Description: select and initialise the mac device (mac100 or Gmac).
1491 */
1492static int stmmac_mac_device_setup(struct net_device *dev)
1493{
1494 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1495
1496 struct mac_device_info *device;
1497
01789349
JP		 1498 if (priv->plat->has_gmac) {
1499 dev->priv_flags |= IFF_UNICAST_FLT;
ad01b7d4 1500 device = dwmac1000_setup(priv->ioaddr);
01789349 1501 } else {
ad01b7d4 1502 device = dwmac100_setup(priv->ioaddr);
01789349 1503 }
3d90c508 1504
1ff21906
DC		 1505 if (!device)
1506 return -ENOMEM;
1507
9dfeb4d9 1508 if (priv->plat->enh_desc) {
3d90c508
GC		 1509 device->desc = &enh_desc_ops;
1510 pr_info("\tEnhanced descriptor structure\n");
1511 } else
56b106ae 1512 device->desc = &ndesc_ops;
47dd7a54 1513
db98a0b0 1514 priv->hw = device;
47dd7a54 1515
539c9aa5 1516 if (device_can_wakeup(priv->device)) {
543876c9 1517 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
3172d3af 1518 enable_irq_wake(priv->wol_irq);
539c9aa5 1519 }
47dd7a54
GC		 1520
1521 return 0;
1522}
1523
47dd7a54
GC		 1524/**
1525 * stmmac_dvr_probe
1526 * @pdev: platform device pointer
1527 * Description: the driver is initialized through platform_device.
1528 */
1529static int stmmac_dvr_probe(struct platform_device *pdev)
1530{
1531 int ret = 0;
1532 struct resource *res;
ad01b7d4 1533 void __iomem *addr = NULL;
47dd7a54 1534 struct net_device *ndev = NULL;
293bb1c4 1535 struct stmmac_priv *priv = NULL;
47dd7a54
GC		 1536 struct plat_stmmacenet_data *plat_dat;
1537
1538 pr_info("STMMAC driver:\n\tplatform registration... ");
1539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34a52f36
DC		 1540 if (!res)
1541 return -ENODEV;
ebbb293f 1542 pr_info("\tdone!\n");
47dd7a54 1543
b6222682 1544 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1545 pdev->name)) {
1546 pr_err("%s: ERROR: memory allocation failed"
1547 "cannot get the I/O addr 0x%x\n",
1548 __func__, (unsigned int)res->start);
34a52f36 1549 return -EBUSY;
47dd7a54
GC		 1550 }
1551
7c5365bc 1552 addr = ioremap(res->start, resource_size(res));
47dd7a54 1553 if (!addr) {
7c5365bc 1554 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54 1555 ret = -ENOMEM;
34a52f36 1556 goto out_release_region;
47dd7a54
GC		 1557 }
1558
1559 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1560 if (!ndev) {
1561 pr_err("%s: ERROR: allocating the device\n", __func__);
1562 ret = -ENOMEM;
34a52f36 1563 goto out_unmap;
47dd7a54
GC		 1564 }
1565
1566 SET_NETDEV_DEV(ndev, &pdev->dev);
1567
1568 /* Get the MAC information */
1569 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1570 if (ndev->irq == -ENXIO) {
1571 pr_err("%s: ERROR: MAC IRQ configuration "
1572 "information not found\n", __func__);
34a52f36
DC		 1573 ret = -ENXIO;
1574 goto out_free_ndev;
47dd7a54
GC		 1575 }
1576
1577 priv = netdev_priv(ndev);
1578 priv->device = &(pdev->dev);
1579 priv->dev = ndev;
ee7946a7 1580 plat_dat = pdev->dev.platform_data;
9dfeb4d9
GC		 1581
1582 priv->plat = plat_dat;
1583
ad01b7d4 1584 priv->ioaddr = addr;
47dd7a54 1585
543876c9
GC		 1586 /* PMT module is not integrated in all the MAC devices. */
1587 if (plat_dat->pmt) {
1588 pr_info("\tPMT module supported\n");
1589 device_set_wakeup_capable(&pdev->dev, 1);
1590 }
3172d3af
DS		 1591 /*
1592 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1593 * The external wake up irq can be passed through the platform code
1594 * named as "eth_wake_irq"
1595 *
1596 * In case the wake up interrupt is not passed from the platform
1597 * so the driver will continue to use the mac irq (ndev->irq)
1598 */
1599 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1600 if (priv->wol_irq == -ENXIO)
1601 priv->wol_irq = ndev->irq;
1602
543876c9 1603
47dd7a54
GC		 1604 platform_set_drvdata(pdev, ndev);
1605
1606 /* Set the I/O base addr */
1607 ndev->base_addr = (unsigned long)addr;
1608
293bb1c4
GC		 1609 /* Custom initialisation */
1610 if (priv->plat->init) {
1611 ret = priv->plat->init(pdev);
1612 if (unlikely(ret))
34a52f36 1613 goto out_free_ndev;
293bb1c4 1614 }
ee7946a7 1615
47dd7a54
GC		 1616 /* MAC HW revice detection */
1617 ret = stmmac_mac_device_setup(ndev);
1618 if (ret < 0)
34a52f36 1619 goto out_plat_exit;
47dd7a54
GC		 1620
1621 /* Network Device Registration */
1622 ret = stmmac_probe(ndev);
1623 if (ret < 0)
34a52f36 1624 goto out_plat_exit;
47dd7a54 1625
36bcfe7d
GC		 1626 /* Override with kernel parameters if supplied XXX CRS XXX
1627 * this needs to have multiple instances */
1628 if ((phyaddr >= 0) && (phyaddr <= 31))
1629 priv->plat->phy_addr = phyaddr;
47dd7a54 1630
47dd7a54 1631 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1632 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1633 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1634
1635 /* MDIO bus Registration */
9dfeb4d9 1636 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
47dd7a54
GC		 1637 ret = stmmac_mdio_register(ndev);
1638 if (ret < 0)
34a52f36 1639 goto out_unregister;
47dd7a54 1640 pr_debug("registered!\n");
34a52f36 1641 return 0;
47dd7a54 1642
34a52f36
DC		 1643out_unregister:
1644 unregister_netdev(ndev);
1645out_plat_exit:
1646 if (priv->plat->exit)
1647 priv->plat->exit(pdev);
1648out_free_ndev:
1649 free_netdev(ndev);
1650 platform_set_drvdata(pdev, NULL);
1651out_unmap:
1652 iounmap(addr);
1653out_release_region:
1654 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1655
1656 return ret;
1657}
1658
1659/**
1660 * stmmac_dvr_remove
1661 * @pdev: platform device pointer
1662 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1663 * changes the link status, releases the DMA descriptor rings,
1664 * unregisters the MDIO bus and unmaps the allocated memory.
1665 */
1666static int stmmac_dvr_remove(struct platform_device *pdev)
1667{
1668 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1669 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1670 struct resource *res;
1671
1672 pr_info("%s:\n\tremoving driver", __func__);
1673
ad01b7d4
GC		 1674 priv->hw->dma->stop_rx(priv->ioaddr);
1675 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1676
19449bfc 1677 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1678
1679 netif_carrier_off(ndev);
1680
1681 stmmac_mdio_unregister(ndev);
1682
293bb1c4
GC		 1683 if (priv->plat->exit)
1684 priv->plat->exit(pdev);
1685
47dd7a54
GC		 1686 platform_set_drvdata(pdev, NULL);
1687 unregister_netdev(ndev);
1688
ad01b7d4 1689 iounmap((void *)priv->ioaddr);
47dd7a54 1690 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1691 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1692
1693 free_netdev(ndev);
1694
1695 return 0;
1696}
1697
1698#ifdef CONFIG_PM
874bd42d 1699static int stmmac_suspend(struct device *dev)
47dd7a54 1700{
874bd42d
GC		 1701 struct net_device *ndev = dev_get_drvdata(dev);
1702 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1703 int dis_ic = 0;
1704
874bd42d 1705 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 1706 return 0;
1707
1708 spin_lock(&priv->lock);
1709
874bd42d
GC		 1710 netif_device_detach(ndev);
1711 netif_stop_queue(ndev);
1712 if (priv->phydev)
1713 phy_stop(priv->phydev);
47dd7a54
GC		 1714
1715#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 1716 priv->tm->timer_stop();
1717 if (likely(priv->tm->enable))
1718 dis_ic = 1;
47dd7a54 1719#endif
874bd42d
GC		 1720 napi_disable(&priv->napi);
1721
1722 /* Stop TX/RX DMA */
1723 priv->hw->dma->stop_tx(priv->ioaddr);
1724 priv->hw->dma->stop_rx(priv->ioaddr);
1725 /* Clear the Rx/Tx descriptors */
1726 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1727 dis_ic);
1728 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1729
1730 /* Enable Power down mode by programming the PMT regs */
1731 if (device_may_wakeup(priv->device))
1732 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
1733 else
1734 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1735
1736 spin_unlock(&priv->lock);
1737 return 0;
1738}
1739
874bd42d 1740static int stmmac_resume(struct device *dev)
47dd7a54 1741{
874bd42d
GC		 1742 struct net_device *ndev = dev_get_drvdata(dev);
1743 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 1744
874bd42d 1745 if (!netif_running(ndev))
47dd7a54
GC		 1746 return 0;
1747
c4433be6
GC		 1748 spin_lock(&priv->lock);
1749
47dd7a54
GC		 1750 /* Power Down bit, into the PM register, is cleared
1751 * automatically as soon as a magic packet or a Wake-up frame
1752 * is received. Anyway, it's better to manually clear
1753 * this bit because it can generate problems while resuming
1754 * from another devices (e.g. serial console). */
874bd42d 1755 if (device_may_wakeup(priv->device))
543876c9 1756 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54 1757
874bd42d 1758 netif_device_attach(ndev);
47dd7a54
GC		 1759
1760 /* Enable the MAC and DMA */
19449bfc 1761 stmmac_enable_mac(priv->ioaddr);
ad01b7d4
GC		 1762 priv->hw->dma->start_tx(priv->ioaddr);
1763 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 1764
1765#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 1766 if (likely(priv->tm->enable))
1767 priv->tm->timer_start(tmrate);
47dd7a54
GC		 1768#endif
1769 napi_enable(&priv->napi);
1770
1771 if (priv->phydev)
1772 phy_start(priv->phydev);
1773
874bd42d 1774 netif_start_queue(ndev);
47dd7a54 1775
47dd7a54
GC		 1776 spin_unlock(&priv->lock);
1777 return 0;
1778}
47dd7a54 1779
874bd42d
GC		 1780static int stmmac_freeze(struct device *dev)
1781{
1782 struct net_device *ndev = dev_get_drvdata(dev);
1783
1784 if (!ndev || !netif_running(ndev))
1785 return 0;
1786
1787 return stmmac_release(ndev);
1788}
1789
1790static int stmmac_restore(struct device *dev)
1791{
1792 struct net_device *ndev = dev_get_drvdata(dev);
1793
1794 if (!ndev || !netif_running(ndev))
1795 return 0;
1796
1797 return stmmac_open(ndev);
1798}
1799
1800static const struct dev_pm_ops stmmac_pm_ops = {
47dd7a54
GC		 1801 .suspend = stmmac_suspend,
1802 .resume = stmmac_resume,
874bd42d
GC		 1803 .freeze = stmmac_freeze,
1804 .thaw = stmmac_restore,
1805 .restore = stmmac_restore,
1806};
1807#else
1808static const struct dev_pm_ops stmmac_pm_ops;
1809#endif /* CONFIG_PM */
47dd7a54 1810
874bd42d
GC		 1811static struct platform_driver stmmac_driver = {
1812 .probe = stmmac_dvr_probe,
1813 .remove = stmmac_dvr_remove,
1814 .driver = {
1815 .name = STMMAC_RESOURCE_NAME,
1816 .owner = THIS_MODULE,
1817 .pm = &stmmac_pm_ops,
1818 },
47dd7a54
GC		 1819};
1820
1821/**
1822 * stmmac_init_module - Entry point for the driver
1823 * Description: This function is the entry point for the driver.
1824 */
1825static int __init stmmac_init_module(void)
1826{
1827 int ret;
1828
47dd7a54
GC		 1829 ret = platform_driver_register(&stmmac_driver);
1830 return ret;
1831}
1832
1833/**
1834 * stmmac_cleanup_module - Cleanup routine for the driver
1835 * Description: This function is the cleanup routine for the driver.
1836 */
1837static void __exit stmmac_cleanup_module(void)
1838{
47dd7a54
GC		 1839 platform_driver_unregister(&stmmac_driver);
1840}
1841
1842#ifndef MODULE
1843static int __init stmmac_cmdline_opt(char *str)
1844{
1845 char *opt;
1846
1847 if (!str || !*str)
1848 return -EINVAL;
1849 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 1850 if (!strncmp(opt, "debug:", 6)) {
1851 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
1852 goto err;
1853 } else if (!strncmp(opt, "phyaddr:", 8)) {
1854 if (strict_strtoul(opt + 8, 0,
1855 (unsigned long *)&phyaddr))
1856 goto err;
1857 } else if (!strncmp(opt, "dma_txsize:", 11)) {
1858 if (strict_strtoul(opt + 11, 0,
1859 (unsigned long *)&dma_txsize))
1860 goto err;
1861 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
1862 if (strict_strtoul(opt + 11, 0,
1863 (unsigned long *)&dma_rxsize))
1864 goto err;
1865 } else if (!strncmp(opt, "buf_sz:", 7)) {
1866 if (strict_strtoul(opt + 7, 0,
1867 (unsigned long *)&buf_sz))
1868 goto err;
1869 } else if (!strncmp(opt, "tc:", 3)) {
1870 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
1871 goto err;
1872 } else if (!strncmp(opt, "watchdog:", 9)) {
1873 if (strict_strtoul(opt + 9, 0,
1874 (unsigned long *)&watchdog))
1875 goto err;
1876 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
1877 if (strict_strtoul(opt + 10, 0,
1878 (unsigned long *)&flow_ctrl))
1879 goto err;
1880 } else if (!strncmp(opt, "pause:", 6)) {
1881 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
1882 goto err;
47dd7a54 1883#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 1884 } else if (!strncmp(opt, "tmrate:", 7)) {
1885 if (strict_strtoul(opt + 7, 0,
1886 (unsigned long *)&tmrate))
1887 goto err;
47dd7a54 1888#endif
f3240e28 1889 }
47dd7a54
GC		 1890 }
1891 return 0;
f3240e28
GC		 1892
1893err:
1894 pr_err("%s: ERROR broken module parameter conversion", __func__);
1895 return -EINVAL;
47dd7a54
GC		 1896}
1897
1898__setup("stmmaceth=", stmmac_cmdline_opt);
1899#endif
1900
1901module_init(stmmac_init_module);
1902module_exit(stmmac_cleanup_module);
1903
1904MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
1905MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
1906MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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