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stmmac: allow mmc usage only if feature actually available (V4)
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
01789349 45#include <linux/if.h>
47dd7a54
GC		 46#include <linux/if_vlan.h>
47#include <linux/dma-mapping.h>
5a0e3ad6 48#include <linux/slab.h>
70c71606 49#include <linux/prefetch.h>
47dd7a54 50#include "stmmac.h"
7ac29055
GC		 51#ifdef CONFIG_STMMAC_DEBUG_FS
52#include <linux/debugfs.h>
53#include <linux/seq_file.h>
54#endif
47dd7a54
GC		 55
56#define STMMAC_RESOURCE_NAME "stmmaceth"
47dd7a54
GC		 57
58#undef STMMAC_DEBUG
59/*#define STMMAC_DEBUG*/
60#ifdef STMMAC_DEBUG
61#define DBG(nlevel, klevel, fmt, args...) \
62 ((void)(netif_msg_##nlevel(priv) && \
63 printk(KERN_##klevel fmt, ## args)))
64#else
65#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
66#endif
67
68#undef STMMAC_RX_DEBUG
69/*#define STMMAC_RX_DEBUG*/
70#ifdef STMMAC_RX_DEBUG
71#define RX_DBG(fmt, args...) printk(fmt, ## args)
72#else
73#define RX_DBG(fmt, args...) do { } while (0)
74#endif
75
76#undef STMMAC_XMIT_DEBUG
77/*#define STMMAC_XMIT_DEBUG*/
78#ifdef STMMAC_TX_DEBUG
79#define TX_DBG(fmt, args...) printk(fmt, ## args)
80#else
81#define TX_DBG(fmt, args...) do { } while (0)
82#endif
83
84#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
85#define JUMBO_LEN 9000
86
87/* Module parameters */
88#define TX_TIMEO 5000 /* default 5 seconds */
89static int watchdog = TX_TIMEO;
90module_param(watchdog, int, S_IRUGO | S_IWUSR);
91MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
92
93static int debug = -1; /* -1: default, 0: no output, 16: all */
94module_param(debug, int, S_IRUGO | S_IWUSR);
95MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
96
97static int phyaddr = -1;
98module_param(phyaddr, int, S_IRUGO);
99MODULE_PARM_DESC(phyaddr, "Physical device address");
100
101#define DMA_TX_SIZE 256
102static int dma_txsize = DMA_TX_SIZE;
103module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
104MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
105
106#define DMA_RX_SIZE 256
107static int dma_rxsize = DMA_RX_SIZE;
108module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
110
111static int flow_ctrl = FLOW_OFF;
112module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
113MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
114
115static int pause = PAUSE_TIME;
116module_param(pause, int, S_IRUGO | S_IWUSR);
117MODULE_PARM_DESC(pause, "Flow Control Pause Time");
118
119#define TC_DEFAULT 64
120static int tc = TC_DEFAULT;
121module_param(tc, int, S_IRUGO | S_IWUSR);
122MODULE_PARM_DESC(tc, "DMA threshold control value");
123
47dd7a54
GC		 124/* Pay attention to tune this parameter; take care of both
125 * hardware capability and network stabitily/performance impact.
126 * Many tests showed that ~4ms latency seems to be good enough. */
127#ifdef CONFIG_STMMAC_TIMER
128#define DEFAULT_PERIODIC_RATE 256
129static int tmrate = DEFAULT_PERIODIC_RATE;
130module_param(tmrate, int, S_IRUGO | S_IWUSR);
131MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
132#endif
133
134#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
135static int buf_sz = DMA_BUFFER_SIZE;
136module_param(buf_sz, int, S_IRUGO | S_IWUSR);
137MODULE_PARM_DESC(buf_sz, "DMA buffer size");
138
47dd7a54
GC		 139static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
140 NETIF_MSG_LINK | NETIF_MSG_IFUP |
141 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
142
143static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54
GC		 144
145/**
146 * stmmac_verify_args - verify the driver parameters.
147 * Description: it verifies if some wrong parameter is passed to the driver.
148 * Note that wrong parameters are replaced with the default values.
149 */
150static void stmmac_verify_args(void)
151{
152 if (unlikely(watchdog < 0))
153 watchdog = TX_TIMEO;
154 if (unlikely(dma_rxsize < 0))
155 dma_rxsize = DMA_RX_SIZE;
156 if (unlikely(dma_txsize < 0))
157 dma_txsize = DMA_TX_SIZE;
158 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
159 buf_sz = DMA_BUFFER_SIZE;
160 if (unlikely(flow_ctrl > 1))
161 flow_ctrl = FLOW_AUTO;
162 else if (likely(flow_ctrl < 0))
163 flow_ctrl = FLOW_OFF;
164 if (unlikely((pause < 0) || (pause > 0xffff)))
165 pause = PAUSE_TIME;
47dd7a54
GC		 166}
167
168#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
169static void print_pkt(unsigned char *buf, int len)
170{
171 int j;
172 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
173 for (j = 0; j < len; j++) {
174 if ((j % 16) == 0)
175 pr_info("\n %03x:", j);
176 pr_info(" %02x", buf[j]);
177 }
178 pr_info("\n");
47dd7a54
GC		 179}
180#endif
181
182/* minimum number of free TX descriptors required to wake up TX process */
183#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
184
185static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
186{
187 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
188}
189
9dfeb4d9
GC		 190/* On some ST platforms, some HW system configuraton registers have to be
191 * set according to the link speed negotiated.
192 */
193static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
194{
195 struct phy_device *phydev = priv->phydev;
196
197 if (likely(priv->plat->fix_mac_speed))
198 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
199 phydev->speed);
200}
201
47dd7a54
GC		 202/**
203 * stmmac_adjust_link
204 * @dev: net device structure
205 * Description: it adjusts the link parameters.
206 */
207static void stmmac_adjust_link(struct net_device *dev)
208{
209 struct stmmac_priv *priv = netdev_priv(dev);
210 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 211 unsigned long flags;
212 int new_state = 0;
213 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
214
215 if (phydev == NULL)
216 return;
217
218 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
219 phydev->addr, phydev->link);
220
221 spin_lock_irqsave(&priv->lock, flags);
222 if (phydev->link) {
ad01b7d4 223 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 224
225 /* Now we make sure that we can be in full duplex mode.
226 * If not, we operate in half-duplex mode. */
227 if (phydev->duplex != priv->oldduplex) {
228 new_state = 1;
229 if (!(phydev->duplex))
db98a0b0 230 ctrl &= ~priv->hw->link.duplex;
47dd7a54 231 else
db98a0b0 232 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 233 priv->oldduplex = phydev->duplex;
234 }
235 /* Flow Control operation */
236 if (phydev->pause)
ad01b7d4 237 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 238 fc, pause_time);
47dd7a54
GC		 239
240 if (phydev->speed != priv->speed) {
241 new_state = 1;
242 switch (phydev->speed) {
243 case 1000:
9dfeb4d9 244 if (likely(priv->plat->has_gmac))
db98a0b0 245 ctrl &= ~priv->hw->link.port;
9dfeb4d9 246 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 247 break;
248 case 100:
249 case 10:
9dfeb4d9 250 if (priv->plat->has_gmac) {
db98a0b0 251 ctrl |= priv->hw->link.port;
47dd7a54 252 if (phydev->speed == SPEED_100) {
db98a0b0 253 ctrl |= priv->hw->link.speed;
47dd7a54 254 } else {
db98a0b0 255 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 256 }
257 } else {
db98a0b0 258 ctrl &= ~priv->hw->link.port;
47dd7a54 259 }
9dfeb4d9 260 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 261 break;
262 default:
263 if (netif_msg_link(priv))
264 pr_warning("%s: Speed (%d) is not 10"
265 " or 100!\n", dev->name, phydev->speed);
266 break;
267 }
268
269 priv->speed = phydev->speed;
270 }
271
ad01b7d4 272 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 273
274 if (!priv->oldlink) {
275 new_state = 1;
276 priv->oldlink = 1;
277 }
278 } else if (priv->oldlink) {
279 new_state = 1;
280 priv->oldlink = 0;
281 priv->speed = 0;
282 priv->oldduplex = -1;
283 }
284
285 if (new_state && netif_msg_link(priv))
286 phy_print_status(phydev);
287
288 spin_unlock_irqrestore(&priv->lock, flags);
289
290 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
291}
292
293/**
294 * stmmac_init_phy - PHY initialization
295 * @dev: net device structure
296 * Description: it initializes the driver's PHY state, and attaches the PHY
297 * to the mac driver.
298 * Return value:
299 * 0 on success
300 */
301static int stmmac_init_phy(struct net_device *dev)
302{
303 struct stmmac_priv *priv = netdev_priv(dev);
304 struct phy_device *phydev;
109cdd66
GC		 305 char phy_id[MII_BUS_ID_SIZE + 3];
306 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 307 int interface = priv->plat->interface;
47dd7a54
GC		 308 priv->oldlink = 0;
309 priv->speed = 0;
310 priv->oldduplex = -1;
311
9dfeb4d9 312 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
109cdd66 313 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 314 priv->plat->phy_addr);
47dd7a54
GC		 315 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
316
79ee1dc3 317 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
47dd7a54
GC		 318
319 if (IS_ERR(phydev)) {
320 pr_err("%s: Could not attach to PHY\n", dev->name);
321 return PTR_ERR(phydev);
322 }
323
79ee1dc3
SK		 324 /* Stop Advertising 1000BASE Capability if interface is not GMII */
325 if ((interface) && ((interface == PHY_INTERFACE_MODE_MII) ||
326 (interface == PHY_INTERFACE_MODE_RMII))) {
327 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
328 SUPPORTED_Asym_Pause);
329 priv->phydev->advertising = priv->phydev->supported;
330 }
331
47dd7a54
GC		 332 /*
333 * Broken HW is sometimes missing the pull-up resistor on the
334 * MDIO line, which results in reads to non-existent devices returning
335 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
336 * device as well.
337 * Note: phydev->phy_id is the result of reading the UID PHY registers.
338 */
339 if (phydev->phy_id == 0) {
340 phy_disconnect(phydev);
341 return -ENODEV;
342 }
343 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 344 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 345
346 priv->phydev = phydev;
347
348 return 0;
349}
350
19449bfc 351static inline void stmmac_enable_mac(void __iomem *ioaddr)
47dd7a54
GC		 352{
353 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 354
19449bfc 355 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
47dd7a54
GC		 356 writel(value, ioaddr + MAC_CTRL_REG);
357}
358
19449bfc 359static inline void stmmac_disable_mac(void __iomem *ioaddr)
47dd7a54
GC		 360{
361 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 362
19449bfc 363 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
47dd7a54
GC		 364 writel(value, ioaddr + MAC_CTRL_REG);
365}
366
367/**
368 * display_ring
369 * @p: pointer to the ring.
370 * @size: size of the ring.
371 * Description: display all the descriptors within the ring.
372 */
373static void display_ring(struct dma_desc *p, int size)
374{
375 struct tmp_s {
376 u64 a;
377 unsigned int b;
378 unsigned int c;
379 };
380 int i;
381 for (i = 0; i < size; i++) {
382 struct tmp_s *x = (struct tmp_s *)(p + i);
383 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
384 i, (unsigned int)virt_to_phys(&p[i]),
385 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
386 x->b, x->c);
387 pr_info("\n");
388 }
389}
390
391/**
392 * init_dma_desc_rings - init the RX/TX descriptor rings
393 * @dev: net device structure
394 * Description: this function initializes the DMA RX/TX descriptors
395 * and allocates the socket buffers.
396 */
397static void init_dma_desc_rings(struct net_device *dev)
398{
399 int i;
400 struct stmmac_priv *priv = netdev_priv(dev);
401 struct sk_buff *skb;
402 unsigned int txsize = priv->dma_tx_size;
403 unsigned int rxsize = priv->dma_rx_size;
404 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 405 int buff2_needed = 0, dis_ic = 0;
47dd7a54 406
47dd7a54
GC		 407 /* Set the Buffer size according to the MTU;
408 * indeed, in case of jumbo we need to bump-up the buffer sizes.
409 */
410 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
411 bfsize = BUF_SIZE_16KiB;
412 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
413 bfsize = BUF_SIZE_8KiB;
414 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
415 bfsize = BUF_SIZE_4KiB;
416 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
417 bfsize = BUF_SIZE_2KiB;
418 else
419 bfsize = DMA_BUFFER_SIZE;
420
73cfe264
GC		 421#ifdef CONFIG_STMMAC_TIMER
422 /* Disable interrupts on completion for the reception if timer is on */
423 if (likely(priv->tm->enable))
424 dis_ic = 1;
425#endif
47dd7a54
GC		 426 /* If the MTU exceeds 8k so use the second buffer in the chain */
427 if (bfsize >= BUF_SIZE_8KiB)
428 buff2_needed = 1;
429
430 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
431 txsize, rxsize, bfsize);
432
433 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
434 priv->rx_skbuff =
435 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
436 priv->dma_rx =
437 (struct dma_desc *)dma_alloc_coherent(priv->device,
438 rxsize *
439 sizeof(struct dma_desc),
440 &priv->dma_rx_phy,
441 GFP_KERNEL);
442 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
443 GFP_KERNEL);
444 priv->dma_tx =
445 (struct dma_desc *)dma_alloc_coherent(priv->device,
446 txsize *
447 sizeof(struct dma_desc),
448 &priv->dma_tx_phy,
449 GFP_KERNEL);
450
451 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
452 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
453 return;
454 }
455
456 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
457 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
458 dev->name, priv->dma_rx, priv->dma_tx,
459 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
460
461 /* RX INITIALIZATION */
462 DBG(probe, INFO, "stmmac: SKB addresses:\n"
463 "skb\t\tskb data\tdma data\n");
464
465 for (i = 0; i < rxsize; i++) {
466 struct dma_desc *p = priv->dma_rx + i;
467
468 skb = netdev_alloc_skb_ip_align(dev, bfsize);
469 if (unlikely(skb == NULL)) {
470 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
471 break;
472 }
473 priv->rx_skbuff[i] = skb;
474 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
475 bfsize, DMA_FROM_DEVICE);
476
477 p->des2 = priv->rx_skbuff_dma[i];
478 if (unlikely(buff2_needed))
479 p->des3 = p->des2 + BUF_SIZE_8KiB;
480 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
481 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
482 }
483 priv->cur_rx = 0;
484 priv->dirty_rx = (unsigned int)(i - rxsize);
485 priv->dma_buf_sz = bfsize;
486 buf_sz = bfsize;
487
488 /* TX INITIALIZATION */
489 for (i = 0; i < txsize; i++) {
490 priv->tx_skbuff[i] = NULL;
491 priv->dma_tx[i].des2 = 0;
492 }
493 priv->dirty_tx = 0;
494 priv->cur_tx = 0;
495
496 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 497 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
498 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 499
500 if (netif_msg_hw(priv)) {
501 pr_info("RX descriptor ring:\n");
502 display_ring(priv->dma_rx, rxsize);
503 pr_info("TX descriptor ring:\n");
504 display_ring(priv->dma_tx, txsize);
505 }
47dd7a54
GC		 506}
507
508static void dma_free_rx_skbufs(struct stmmac_priv *priv)
509{
510 int i;
511
512 for (i = 0; i < priv->dma_rx_size; i++) {
513 if (priv->rx_skbuff[i]) {
514 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
515 priv->dma_buf_sz, DMA_FROM_DEVICE);
516 dev_kfree_skb_any(priv->rx_skbuff[i]);
517 }
518 priv->rx_skbuff[i] = NULL;
519 }
47dd7a54
GC		 520}
521
522static void dma_free_tx_skbufs(struct stmmac_priv *priv)
523{
524 int i;
525
526 for (i = 0; i < priv->dma_tx_size; i++) {
527 if (priv->tx_skbuff[i] != NULL) {
528 struct dma_desc *p = priv->dma_tx + i;
529 if (p->des2)
530 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 531 priv->hw->desc->get_tx_len(p),
532 DMA_TO_DEVICE);
47dd7a54
GC		 533 dev_kfree_skb_any(priv->tx_skbuff[i]);
534 priv->tx_skbuff[i] = NULL;
535 }
536 }
47dd7a54
GC		 537}
538
539static void free_dma_desc_resources(struct stmmac_priv *priv)
540{
541 /* Release the DMA TX/RX socket buffers */
542 dma_free_rx_skbufs(priv);
543 dma_free_tx_skbufs(priv);
544
545 /* Free the region of consistent memory previously allocated for
546 * the DMA */
547 dma_free_coherent(priv->device,
548 priv->dma_tx_size * sizeof(struct dma_desc),
549 priv->dma_tx, priv->dma_tx_phy);
550 dma_free_coherent(priv->device,
551 priv->dma_rx_size * sizeof(struct dma_desc),
552 priv->dma_rx, priv->dma_rx_phy);
553 kfree(priv->rx_skbuff_dma);
554 kfree(priv->rx_skbuff);
555 kfree(priv->tx_skbuff);
47dd7a54
GC		 556}
557
47dd7a54
GC		 558/**
559 * stmmac_dma_operation_mode - HW DMA operation mode
560 * @priv : pointer to the private device structure.
561 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 562 * or Store-And-Forward capability.
47dd7a54
GC		 563 */
564static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
565{
61b8013a
SK		 566 if (likely(priv->plat->force_sf_dma_mode ||
567 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
568 /*
569 * In case of GMAC, SF mode can be enabled
570 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 571 * 1) TX COE if actually supported
572 * 2) There is no bugged Jumbo frame support
573 * that needs to not insert csum in the TDES.
574 */
575 priv->hw->dma->dma_mode(priv->ioaddr,
576 SF_DMA_MODE, SF_DMA_MODE);
577 tc = SF_DMA_MODE;
578 } else
579 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 580}
581
47dd7a54
GC		 582/**
583 * stmmac_tx:
584 * @priv: private driver structure
585 * Description: it reclaims resources after transmission completes.
586 */
587static void stmmac_tx(struct stmmac_priv *priv)
588{
589 unsigned int txsize = priv->dma_tx_size;
47dd7a54 590
a9097a96
GC		 591 spin_lock(&priv->tx_lock);
592
47dd7a54
GC		 593 while (priv->dirty_tx != priv->cur_tx) {
594 int last;
595 unsigned int entry = priv->dirty_tx % txsize;
596 struct sk_buff *skb = priv->tx_skbuff[entry];
597 struct dma_desc *p = priv->dma_tx + entry;
598
599 /* Check if the descriptor is owned by the DMA. */
db98a0b0 600 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 601 break;
602
603 /* Verify tx error by looking at the last segment */
db98a0b0 604 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 605 if (likely(last)) {
606 int tx_error =
db98a0b0
GC		 607 priv->hw->desc->tx_status(&priv->dev->stats,
608 &priv->xstats, p,
ad01b7d4 609 priv->ioaddr);
47dd7a54
GC		 610 if (likely(tx_error == 0)) {
611 priv->dev->stats.tx_packets++;
612 priv->xstats.tx_pkt_n++;
613 } else
614 priv->dev->stats.tx_errors++;
615 }
616 TX_DBG("%s: curr %d, dirty %d\n", __func__,
617 priv->cur_tx, priv->dirty_tx);
618
619 if (likely(p->des2))
620 dma_unmap_single(priv->device, p->des2,
db98a0b0 621 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 622 DMA_TO_DEVICE);
623 if (unlikely(p->des3))
624 p->des3 = 0;
625
626 if (likely(skb != NULL)) {
627 /*
628 * If there's room in the queue (limit it to size)
629 * we add this skb back into the pool,
630 * if it's the right size.
631 */
632 if ((skb_queue_len(&priv->rx_recycle) <
633 priv->dma_rx_size) &&
634 skb_recycle_check(skb, priv->dma_buf_sz))
635 __skb_queue_head(&priv->rx_recycle, skb);
636 else
637 dev_kfree_skb(skb);
638
639 priv->tx_skbuff[entry] = NULL;
640 }
641
db98a0b0 642 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 643
644 entry = (++priv->dirty_tx) % txsize;
645 }
646 if (unlikely(netif_queue_stopped(priv->dev) &&
647 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
648 netif_tx_lock(priv->dev);
649 if (netif_queue_stopped(priv->dev) &&
650 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
651 TX_DBG("%s: restart transmit\n", __func__);
652 netif_wake_queue(priv->dev);
653 }
654 netif_tx_unlock(priv->dev);
655 }
a9097a96 656 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 657}
658
659static inline void stmmac_enable_irq(struct stmmac_priv *priv)
660{
73cfe264
GC		 661#ifdef CONFIG_STMMAC_TIMER
662 if (likely(priv->tm->enable))
663 priv->tm->timer_start(tmrate);
664 else
47dd7a54 665#endif
ad01b7d4 666 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 667}
668
669static inline void stmmac_disable_irq(struct stmmac_priv *priv)
670{
73cfe264
GC		 671#ifdef CONFIG_STMMAC_TIMER
672 if (likely(priv->tm->enable))
673 priv->tm->timer_stop();
674 else
47dd7a54 675#endif
ad01b7d4 676 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 677}
678
679static int stmmac_has_work(struct stmmac_priv *priv)
680{
681 unsigned int has_work = 0;
682 int rxret, tx_work = 0;
683
db98a0b0 684 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 685 (priv->cur_rx % priv->dma_rx_size));
686
687 if (priv->dirty_tx != priv->cur_tx)
688 tx_work = 1;
689
690 if (likely(!rxret || tx_work))
691 has_work = 1;
692
693 return has_work;
694}
695
696static inline void _stmmac_schedule(struct stmmac_priv *priv)
697{
698 if (likely(stmmac_has_work(priv))) {
699 stmmac_disable_irq(priv);
700 napi_schedule(&priv->napi);
701 }
702}
703
704#ifdef CONFIG_STMMAC_TIMER
705void stmmac_schedule(struct net_device *dev)
706{
707 struct stmmac_priv *priv = netdev_priv(dev);
708
709 priv->xstats.sched_timer_n++;
710
711 _stmmac_schedule(priv);
47dd7a54
GC		 712}
713
714static void stmmac_no_timer_started(unsigned int x)
715{;
716};
717
718static void stmmac_no_timer_stopped(void)
719{;
720};
721#endif
722
723/**
724 * stmmac_tx_err:
725 * @priv: pointer to the private device structure
726 * Description: it cleans the descriptors and restarts the transmission
727 * in case of errors.
728 */
729static void stmmac_tx_err(struct stmmac_priv *priv)
730{
ad01b7d4 731
47dd7a54
GC		 732 netif_stop_queue(priv->dev);
733
ad01b7d4 734 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 735 dma_free_tx_skbufs(priv);
db98a0b0 736 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 737 priv->dirty_tx = 0;
738 priv->cur_tx = 0;
ad01b7d4 739 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 740
741 priv->dev->stats.tx_errors++;
742 netif_wake_queue(priv->dev);
47dd7a54
GC		 743}
744
47dd7a54 745
aec7ff27
GC		 746static void stmmac_dma_interrupt(struct stmmac_priv *priv)
747{
aec7ff27
GC		 748 int status;
749
ad01b7d4 750 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 751 if (likely(status == handle_tx_rx))
752 _stmmac_schedule(priv);
753
754 else if (unlikely(status == tx_hard_error_bump_tc)) {
755 /* Try to bump up the dma threshold on this failure */
756 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
757 tc += 64;
ad01b7d4 758 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 759 priv->xstats.threshold = tc;
47dd7a54 760 }
aec7ff27
GC		 761 } else if (unlikely(status == tx_hard_error))
762 stmmac_tx_err(priv);
47dd7a54
GC		 763}
764
1c901a46
GC		 765static void stmmac_mmc_setup(struct stmmac_priv *priv)
766{
767 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
768 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
769
770 /* Do not manage MMC IRQ (FIXME) */
771 dwmac_mmc_intr_all_mask(priv->ioaddr);
772 dwmac_mmc_ctrl(priv->ioaddr, mode);
773 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
774}
775
f0b9d786
GC		 776static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
777{
778 u32 hwid = priv->hw->synopsys_uid;
779
780 /* Only check valid Synopsys Id because old MAC chips
781 * have no HW registers where get the ID */
782 if (likely(hwid)) {
783 u32 uid = ((hwid & 0x0000ff00) >> 8);
784 u32 synid = (hwid & 0x000000ff);
785
786 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
787 uid, synid);
788
789 return synid;
790 }
791 return 0;
792}
e7434821
GC		 793
794/* New GMAC chips support a new register to indicate the
795 * presence of the optional feature/functions.
796 */
797static int stmmac_get_hw_features(struct stmmac_priv *priv)
798{
799 u32 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
800
801 if (likely(hw_cap)) {
1db123fb
RK		 802 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
803 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
804 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
805 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
806 priv->dma_cap.multi_addr =
807 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
808 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
809 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
810 priv->dma_cap.pmt_remote_wake_up =
811 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
812 priv->dma_cap.pmt_magic_frame =
813 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
814 /*MMC*/
815 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
e7434821 816 /* IEEE 1588-2002*/
1db123fb
RK		 817 priv->dma_cap.time_stamp =
818 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
e7434821 819 /* IEEE 1588-2008*/
1db123fb
RK		 820 priv->dma_cap.atime_stamp =
821 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 822 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 823 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
824 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 825 /* TX and RX csum */
1db123fb
RK		 826 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
827 priv->dma_cap.rx_coe_type1 =
828 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
829 priv->dma_cap.rx_coe_type2 =
830 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
831 priv->dma_cap.rxfifo_over_2048 =
832 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 833 /* TX and RX number of channels */
1db123fb
RK		 834 priv->dma_cap.number_rx_channel =
835 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
836 priv->dma_cap.number_tx_channel =
837 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
e7434821 838 /* Alternate (enhanced) DESC mode*/
1db123fb
RK		 839 priv->dma_cap.enh_desc =
840 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
e7434821
GC		 841
842 } else
843 pr_debug("\tNo HW DMA feature register supported");
844
845 return hw_cap;
846}
847
47dd7a54
GC		 848/**
849 * stmmac_open - open entry point of the driver
850 * @dev : pointer to the device structure.
851 * Description:
852 * This function is the open entry point of the driver.
853 * Return value:
854 * 0 on success and an appropriate (-)ve integer as defined in errno.h
855 * file on failure.
856 */
857static int stmmac_open(struct net_device *dev)
858{
859 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 860 int ret;
861
862 /* Check that the MAC address is valid. If its not, refuse
863 * to bring the device up. The user must specify an
864 * address using the following linux command:
865 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
866 if (!is_valid_ether_addr(dev->dev_addr)) {
867 random_ether_addr(dev->dev_addr);
868 pr_warning("%s: generated random MAC address %pM\n", dev->name,
869 dev->dev_addr);
870 }
871
872 stmmac_verify_args();
873
47dd7a54 874#ifdef CONFIG_STMMAC_TIMER
73cfe264 875 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 876 if (unlikely(priv->tm == NULL)) {
2381a55c 877 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 878 return -ENOMEM;
879 }
880 priv->tm->freq = tmrate;
881
73cfe264
GC		 882 /* Test if the external timer can be actually used.
883 * In case of failure continue without timer. */
47dd7a54 884 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 885 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 886 priv->tm->freq = 0;
887 priv->tm->timer_start = stmmac_no_timer_started;
888 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 889 } else
890 priv->tm->enable = 1;
47dd7a54 891#endif
f66ffe28
GC		 892 ret = stmmac_init_phy(dev);
893 if (unlikely(ret)) {
894 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
895 goto open_error;
896 }
47dd7a54
GC		 897
898 /* Create and initialize the TX/RX descriptors chains. */
899 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
900 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
901 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
902 init_dma_desc_rings(dev);
903
904 /* DMA initialization and SW reset */
f66ffe28
GC		 905 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
906 priv->dma_tx_phy, priv->dma_rx_phy);
907 if (ret < 0) {
47dd7a54 908 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 909 goto open_error;
47dd7a54
GC		 910 }
911
912 /* Copy the MAC addr into the HW */
ad01b7d4 913 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1 914 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 915 if (priv->plat->bus_setup)
916 priv->plat->bus_setup(priv->ioaddr);
47dd7a54 917 /* Initialize the MAC Core */
ad01b7d4 918 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 919
f0b9d786
GC		 920 stmmac_get_synopsys_id(priv);
921
e7434821
GC		 922 stmmac_get_hw_features(priv);
923
ebbb293f
GC		 924 if (priv->rx_coe)
925 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
9dfeb4d9 926 if (priv->plat->tx_coe)
ebbb293f 927 pr_info("\tTX Checksum insertion supported\n");
5e982f3b 928 netdev_update_features(dev);
ebbb293f 929
f66ffe28
GC		 930 /* Request the IRQ lines */
931 ret = request_irq(dev->irq, stmmac_interrupt,
932 IRQF_SHARED, dev->name, dev);
933 if (unlikely(ret < 0)) {
934 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
935 __func__, dev->irq, ret);
936 goto open_error;
937 }
938
47dd7a54 939 /* Enable the MAC Rx/Tx */
19449bfc 940 stmmac_enable_mac(priv->ioaddr);
47dd7a54
GC		 941
942 /* Set the HW DMA mode and the COE */
943 stmmac_dma_operation_mode(priv);
944
945 /* Extra statistics */
946 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
947 priv->xstats.threshold = tc;
948
38fe7a93
GC		 949 if (priv->dma_cap.rmon)
950 stmmac_mmc_setup(priv);
1c901a46 951
47dd7a54
GC		 952 /* Start the ball rolling... */
953 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 954 priv->hw->dma->start_tx(priv->ioaddr);
955 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 956
957#ifdef CONFIG_STMMAC_TIMER
958 priv->tm->timer_start(tmrate);
959#endif
960 /* Dump DMA/MAC registers */
961 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 962 priv->hw->mac->dump_regs(priv->ioaddr);
963 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 964 }
965
966 if (priv->phydev)
967 phy_start(priv->phydev);
968
969 napi_enable(&priv->napi);
970 skb_queue_head_init(&priv->rx_recycle);
971 netif_start_queue(dev);
f66ffe28 972
47dd7a54 973 return 0;
f66ffe28
GC		 974
975open_error:
976#ifdef CONFIG_STMMAC_TIMER
977 kfree(priv->tm);
978#endif
979 if (priv->phydev)
980 phy_disconnect(priv->phydev);
981
982 return ret;
47dd7a54
GC		 983}
984
985/**
986 * stmmac_release - close entry point of the driver
987 * @dev : device pointer.
988 * Description:
989 * This is the stop entry point of the driver.
990 */
991static int stmmac_release(struct net_device *dev)
992{
993 struct stmmac_priv *priv = netdev_priv(dev);
994
995 /* Stop and disconnect the PHY */
996 if (priv->phydev) {
997 phy_stop(priv->phydev);
998 phy_disconnect(priv->phydev);
999 priv->phydev = NULL;
1000 }
1001
1002 netif_stop_queue(dev);
1003
1004#ifdef CONFIG_STMMAC_TIMER
1005 /* Stop and release the timer */
1006 stmmac_close_ext_timer();
1007 if (priv->tm != NULL)
1008 kfree(priv->tm);
1009#endif
1010 napi_disable(&priv->napi);
1011 skb_queue_purge(&priv->rx_recycle);
1012
1013 /* Free the IRQ lines */
1014 free_irq(dev->irq, dev);
1015
1016 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1017 priv->hw->dma->stop_tx(priv->ioaddr);
1018 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1019
1020 /* Release and free the Rx/Tx resources */
1021 free_dma_desc_resources(priv);
1022
19449bfc 1023 /* Disable the MAC Rx/Tx */
1024 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1025
1026 netif_carrier_off(dev);
1027
1028 return 0;
1029}
1030
47dd7a54
GC		 1031static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1032 struct net_device *dev,
1033 int csum_insertion)
1034{
1035 struct stmmac_priv *priv = netdev_priv(dev);
1036 unsigned int nopaged_len = skb_headlen(skb);
1037 unsigned int txsize = priv->dma_tx_size;
1038 unsigned int entry = priv->cur_tx % txsize;
1039 struct dma_desc *desc = priv->dma_tx + entry;
1040
1041 if (nopaged_len > BUF_SIZE_8KiB) {
1042
1043 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1044
1045 desc->des2 = dma_map_single(priv->device, skb->data,
1046 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1047 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1048 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1049 csum_insertion);
47dd7a54
GC		 1050
1051 entry = (++priv->cur_tx) % txsize;
1052 desc = priv->dma_tx + entry;
1053
1054 desc->des2 = dma_map_single(priv->device,
1055 skb->data + BUF_SIZE_8KiB,
1056 buf2_size, DMA_TO_DEVICE);
1057 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1058 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1059 csum_insertion);
1060 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1061 priv->tx_skbuff[entry] = NULL;
1062 } else {
1063 desc->des2 = dma_map_single(priv->device, skb->data,
1064 nopaged_len, DMA_TO_DEVICE);
1065 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1066 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1067 csum_insertion);
47dd7a54
GC		 1068 }
1069 return entry;
1070}
1071
1072/**
1073 * stmmac_xmit:
1074 * @skb : the socket buffer
1075 * @dev : device pointer
1076 * Description : Tx entry point of the driver.
1077 */
1078static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1079{
1080 struct stmmac_priv *priv = netdev_priv(dev);
1081 unsigned int txsize = priv->dma_tx_size;
1082 unsigned int entry;
1083 int i, csum_insertion = 0;
1084 int nfrags = skb_shinfo(skb)->nr_frags;
1085 struct dma_desc *desc, *first;
1086
1087 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1088 if (!netif_queue_stopped(dev)) {
1089 netif_stop_queue(dev);
1090 /* This is a hard error, log it. */
1091 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1092 __func__);
1093 }
1094 return NETDEV_TX_BUSY;
1095 }
1096
a9097a96
GC		 1097 spin_lock(&priv->tx_lock);
1098
47dd7a54
GC		 1099 entry = priv->cur_tx % txsize;
1100
1101#ifdef STMMAC_XMIT_DEBUG
1102 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1103 pr_info("stmmac xmit:\n"
1104 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1105 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1106 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1107 !skb_is_gso(skb) ? "isn't" : "is");
1108#endif
1109
5e982f3b 1110 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1111
1112 desc = priv->dma_tx + entry;
1113 first = desc;
1114
1115#ifdef STMMAC_XMIT_DEBUG
1116 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1117 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1118 "\t\tn_frags: %d, ip_summed: %d\n",
1119 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1120#endif
1121 priv->tx_skbuff[entry] = skb;
1122 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1123 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1124 desc = priv->dma_tx + entry;
1125 } else {
1126 unsigned int nopaged_len = skb_headlen(skb);
1127 desc->des2 = dma_map_single(priv->device, skb->data,
1128 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1129 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1130 csum_insertion);
47dd7a54
GC		 1131 }
1132
1133 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1134 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1135 int len = skb_frag_size(frag);
47dd7a54
GC		 1136
1137 entry = (++priv->cur_tx) % txsize;
1138 desc = priv->dma_tx + entry;
1139
1140 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1141 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1142 DMA_TO_DEVICE);
47dd7a54 1143 priv->tx_skbuff[entry] = NULL;
db98a0b0 1144 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1145 wmb();
db98a0b0 1146 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1147 }
1148
1149 /* Interrupt on completition only for the latest segment */
db98a0b0 1150 priv->hw->desc->close_tx_desc(desc);
73cfe264 1151
47dd7a54 1152#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1153 /* Clean IC while using timer */
1154 if (likely(priv->tm->enable))
db98a0b0 1155 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1156#endif
eb0dc4bb
SH		 1157
1158 wmb();
1159
47dd7a54 1160 /* To avoid raise condition */
db98a0b0 1161 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1162
1163 priv->cur_tx++;
1164
1165#ifdef STMMAC_XMIT_DEBUG
1166 if (netif_msg_pktdata(priv)) {
1167 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1168 "first=%p, nfrags=%d\n",
1169 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1170 entry, first, nfrags);
1171 display_ring(priv->dma_tx, txsize);
1172 pr_info(">>> frame to be transmitted: ");
1173 print_pkt(skb->data, skb->len);
1174 }
1175#endif
1176 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1177 TX_DBG("%s: stop transmitted packets\n", __func__);
1178 netif_stop_queue(dev);
1179 }
1180
1181 dev->stats.tx_bytes += skb->len;
1182
3e82ce12
RC		 1183 skb_tx_timestamp(skb);
1184
52f64fae
RC		 1185 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1186
a9097a96
GC		 1187 spin_unlock(&priv->tx_lock);
1188
47dd7a54
GC		 1189 return NETDEV_TX_OK;
1190}
1191
1192static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1193{
1194 unsigned int rxsize = priv->dma_rx_size;
1195 int bfsize = priv->dma_buf_sz;
1196 struct dma_desc *p = priv->dma_rx;
1197
1198 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1199 unsigned int entry = priv->dirty_rx % rxsize;
1200 if (likely(priv->rx_skbuff[entry] == NULL)) {
1201 struct sk_buff *skb;
1202
1203 skb = __skb_dequeue(&priv->rx_recycle);
1204 if (skb == NULL)
1205 skb = netdev_alloc_skb_ip_align(priv->dev,
1206 bfsize);
1207
1208 if (unlikely(skb == NULL))
1209 break;
1210
1211 priv->rx_skbuff[entry] = skb;
1212 priv->rx_skbuff_dma[entry] =
1213 dma_map_single(priv->device, skb->data, bfsize,
1214 DMA_FROM_DEVICE);
1215
1216 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
9dfeb4d9 1217 if (unlikely(priv->plat->has_gmac)) {
47dd7a54
GC		 1218 if (bfsize >= BUF_SIZE_8KiB)
1219 (p + entry)->des3 =
1220 (p + entry)->des2 + BUF_SIZE_8KiB;
1221 }
1222 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1223 }
eb0dc4bb 1224 wmb();
db98a0b0 1225 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1226 }
47dd7a54
GC		 1227}
1228
1229static int stmmac_rx(struct stmmac_priv *priv, int limit)
1230{
1231 unsigned int rxsize = priv->dma_rx_size;
1232 unsigned int entry = priv->cur_rx % rxsize;
1233 unsigned int next_entry;
1234 unsigned int count = 0;
1235 struct dma_desc *p = priv->dma_rx + entry;
1236 struct dma_desc *p_next;
1237
1238#ifdef STMMAC_RX_DEBUG
1239 if (netif_msg_hw(priv)) {
1240 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1241 display_ring(priv->dma_rx, rxsize);
1242 }
1243#endif
1244 count = 0;
db98a0b0 1245 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1246 int status;
1247
1248 if (count >= limit)
1249 break;
1250
1251 count++;
1252
1253 next_entry = (++priv->cur_rx) % rxsize;
1254 p_next = priv->dma_rx + next_entry;
1255 prefetch(p_next);
1256
1257 /* read the status of the incoming frame */
db98a0b0
GC		 1258 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1259 &priv->xstats, p));
47dd7a54
GC		 1260 if (unlikely(status == discard_frame))
1261 priv->dev->stats.rx_errors++;
1262 else {
1263 struct sk_buff *skb;
3eeb2997 1264 int frame_len;
47dd7a54 1265
3eeb2997
GC		 1266 frame_len = priv->hw->desc->get_rx_frame_len(p);
1267 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1268 * Type frames (LLC/LLC-SNAP) */
1269 if (unlikely(status != llc_snap))
1270 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1271#ifdef STMMAC_RX_DEBUG
1272 if (frame_len > ETH_FRAME_LEN)
1273 pr_debug("\tRX frame size %d, COE status: %d\n",
1274 frame_len, status);
1275
1276 if (netif_msg_hw(priv))
1277 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1278 p, entry, p->des2);
1279#endif
1280 skb = priv->rx_skbuff[entry];
1281 if (unlikely(!skb)) {
1282 pr_err("%s: Inconsistent Rx descriptor chain\n",
1283 priv->dev->name);
1284 priv->dev->stats.rx_dropped++;
1285 break;
1286 }
1287 prefetch(skb->data - NET_IP_ALIGN);
1288 priv->rx_skbuff[entry] = NULL;
1289
1290 skb_put(skb, frame_len);
1291 dma_unmap_single(priv->device,
1292 priv->rx_skbuff_dma[entry],
1293 priv->dma_buf_sz, DMA_FROM_DEVICE);
1294#ifdef STMMAC_RX_DEBUG
1295 if (netif_msg_pktdata(priv)) {
1296 pr_info(" frame received (%dbytes)", frame_len);
1297 print_pkt(skb->data, frame_len);
1298 }
1299#endif
1300 skb->protocol = eth_type_trans(skb, priv->dev);
1301
1302 if (unlikely(status == csum_none)) {
1303 /* always for the old mac 10/100 */
bc8acf2c 1304 skb_checksum_none_assert(skb);
47dd7a54
GC		 1305 netif_receive_skb(skb);
1306 } else {
1307 skb->ip_summed = CHECKSUM_UNNECESSARY;
1308 napi_gro_receive(&priv->napi, skb);
1309 }
1310
1311 priv->dev->stats.rx_packets++;
1312 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1313 }
1314 entry = next_entry;
1315 p = p_next; /* use prefetched values */
1316 }
1317
1318 stmmac_rx_refill(priv);
1319
1320 priv->xstats.rx_pkt_n += count;
1321
1322 return count;
1323}
1324
1325/**
1326 * stmmac_poll - stmmac poll method (NAPI)
1327 * @napi : pointer to the napi structure.
1328 * @budget : maximum number of packets that the current CPU can receive from
1329 * all interfaces.
1330 * Description :
1331 * This function implements the the reception process.
1332 * Also it runs the TX completion thread
1333 */
1334static int stmmac_poll(struct napi_struct *napi, int budget)
1335{
1336 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1337 int work_done = 0;
1338
1339 priv->xstats.poll_n++;
1340 stmmac_tx(priv);
1341 work_done = stmmac_rx(priv, budget);
1342
1343 if (work_done < budget) {
1344 napi_complete(napi);
1345 stmmac_enable_irq(priv);
1346 }
1347 return work_done;
1348}
1349
1350/**
1351 * stmmac_tx_timeout
1352 * @dev : Pointer to net device structure
1353 * Description: this function is called when a packet transmission fails to
1354 * complete within a reasonable tmrate. The driver will mark the error in the
1355 * netdev structure and arrange for the device to be reset to a sane state
1356 * in order to transmit a new packet.
1357 */
1358static void stmmac_tx_timeout(struct net_device *dev)
1359{
1360 struct stmmac_priv *priv = netdev_priv(dev);
1361
1362 /* Clear Tx resources and restart transmitting again */
1363 stmmac_tx_err(priv);
47dd7a54
GC		 1364}
1365
1366/* Configuration changes (passed on by ifconfig) */
1367static int stmmac_config(struct net_device *dev, struct ifmap *map)
1368{
1369 if (dev->flags & IFF_UP) /* can't act on a running interface */
1370 return -EBUSY;
1371
1372 /* Don't allow changing the I/O address */
1373 if (map->base_addr != dev->base_addr) {
1374 pr_warning("%s: can't change I/O address\n", dev->name);
1375 return -EOPNOTSUPP;
1376 }
1377
1378 /* Don't allow changing the IRQ */
1379 if (map->irq != dev->irq) {
1380 pr_warning("%s: can't change IRQ number %d\n",
1381 dev->name, dev->irq);
1382 return -EOPNOTSUPP;
1383 }
1384
1385 /* ignore other fields */
1386 return 0;
1387}
1388
1389/**
01789349 1390 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1391 * @dev : pointer to the device structure
1392 * Description:
1393 * This function is a driver entry point which gets called by the kernel
1394 * whenever multicast addresses must be enabled/disabled.
1395 * Return value:
1396 * void.
1397 */
01789349 1398static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1399{
1400 struct stmmac_priv *priv = netdev_priv(dev);
1401
1402 spin_lock(&priv->lock);
db98a0b0 1403 priv->hw->mac->set_filter(dev);
47dd7a54 1404 spin_unlock(&priv->lock);
47dd7a54
GC		 1405}
1406
1407/**
1408 * stmmac_change_mtu - entry point to change MTU size for the device.
1409 * @dev : device pointer.
1410 * @new_mtu : the new MTU size for the device.
1411 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1412 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1413 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1414 * Return value:
1415 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1416 * file on failure.
1417 */
1418static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1419{
1420 struct stmmac_priv *priv = netdev_priv(dev);
1421 int max_mtu;
1422
1423 if (netif_running(dev)) {
1424 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1425 return -EBUSY;
1426 }
1427
48febf7e 1428 if (priv->plat->enh_desc)
47dd7a54
GC		 1429 max_mtu = JUMBO_LEN;
1430 else
48febf7e 1431 max_mtu = BUF_SIZE_4KiB;
47dd7a54
GC		 1432
1433 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1434 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1435 return -EINVAL;
1436 }
1437
5e982f3b
MM		 1438 dev->mtu = new_mtu;
1439 netdev_update_features(dev);
1440
1441 return 0;
1442}
1443
1444static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1445{
1446 struct stmmac_priv *priv = netdev_priv(dev);
1447
1448 if (!priv->rx_coe)
1449 features &= ~NETIF_F_RXCSUM;
1450 if (!priv->plat->tx_coe)
1451 features &= ~NETIF_F_ALL_CSUM;
1452
ebbb293f
GC		 1453 /* Some GMAC devices have a bugged Jumbo frame support that
1454 * needs to have the Tx COE disabled for oversized frames
1455 * (due to limited buffer sizes). In this case we disable
1456 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1457 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1458 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1459
5e982f3b 1460 return features;
47dd7a54
GC		 1461}
1462
1463static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1464{
1465 struct net_device *dev = (struct net_device *)dev_id;
1466 struct stmmac_priv *priv = netdev_priv(dev);
1467
1468 if (unlikely(!dev)) {
1469 pr_err("%s: invalid dev pointer\n", __func__);
1470 return IRQ_NONE;
1471 }
1472
9dfeb4d9 1473 if (priv->plat->has_gmac)
47dd7a54 1474 /* To handle GMAC own interrupts */
ad01b7d4 1475 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1476
1477 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1478
1479 return IRQ_HANDLED;
1480}
1481
1482#ifdef CONFIG_NET_POLL_CONTROLLER
1483/* Polling receive - used by NETCONSOLE and other diagnostic tools
1484 * to allow network I/O with interrupts disabled. */
1485static void stmmac_poll_controller(struct net_device *dev)
1486{
1487 disable_irq(dev->irq);
1488 stmmac_interrupt(dev->irq, dev);
1489 enable_irq(dev->irq);
1490}
1491#endif
1492
1493/**
1494 * stmmac_ioctl - Entry point for the Ioctl
1495 * @dev: Device pointer.
1496 * @rq: An IOCTL specefic structure, that can contain a pointer to
1497 * a proprietary structure used to pass information to the driver.
1498 * @cmd: IOCTL command
1499 * Description:
1500 * Currently there are no special functionality supported in IOCTL, just the
1501 * phy_mii_ioctl(...) can be invoked.
1502 */
1503static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1504{
1505 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1506 int ret;
47dd7a54
GC		 1507
1508 if (!netif_running(dev))
1509 return -EINVAL;
1510
28b04113
RC		 1511 if (!priv->phydev)
1512 return -EINVAL;
1513
1514 spin_lock(&priv->lock);
1515 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1516 spin_unlock(&priv->lock);
1517
47dd7a54
GC		 1518 return ret;
1519}
1520
7ac29055
GC		 1521#ifdef CONFIG_STMMAC_DEBUG_FS
1522static struct dentry *stmmac_fs_dir;
1523static struct dentry *stmmac_rings_status;
e7434821 1524static struct dentry *stmmac_dma_cap;
7ac29055
GC		 1525
1526static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1527{
1528 struct tmp_s {
1529 u64 a;
1530 unsigned int b;
1531 unsigned int c;
1532 };
1533 int i;
1534 struct net_device *dev = seq->private;
1535 struct stmmac_priv *priv = netdev_priv(dev);
1536
1537 seq_printf(seq, "=======================\n");
1538 seq_printf(seq, " RX descriptor ring\n");
1539 seq_printf(seq, "=======================\n");
1540
1541 for (i = 0; i < priv->dma_rx_size; i++) {
1542 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1543 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1544 i, (unsigned int)(x->a),
1545 (unsigned int)((x->a) >> 32), x->b, x->c);
1546 seq_printf(seq, "\n");
1547 }
1548
1549 seq_printf(seq, "\n");
1550 seq_printf(seq, "=======================\n");
1551 seq_printf(seq, " TX descriptor ring\n");
1552 seq_printf(seq, "=======================\n");
1553
1554 for (i = 0; i < priv->dma_tx_size; i++) {
1555 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1556 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1557 i, (unsigned int)(x->a),
1558 (unsigned int)((x->a) >> 32), x->b, x->c);
1559 seq_printf(seq, "\n");
1560 }
1561
1562 return 0;
1563}
1564
1565static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1566{
1567 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1568}
1569
1570static const struct file_operations stmmac_rings_status_fops = {
1571 .owner = THIS_MODULE,
1572 .open = stmmac_sysfs_ring_open,
1573 .read = seq_read,
1574 .llseek = seq_lseek,
1575 .release = seq_release,
1576};
1577
e7434821
GC		 1578static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1579{
1580 struct net_device *dev = seq->private;
1581 struct stmmac_priv *priv = netdev_priv(dev);
1582
1583 if (!stmmac_get_hw_features(priv)) {
1584 seq_printf(seq, "DMA HW features not supported\n");
1585 return 0;
1586 }
1587
1588 seq_printf(seq, "==============================\n");
1589 seq_printf(seq, "\tDMA HW features\n");
1590 seq_printf(seq, "==============================\n");
1591
1592 seq_printf(seq, "\t10/100 Mbps %s\n",
1593 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1594 seq_printf(seq, "\t1000 Mbps %s\n",
1595 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1596 seq_printf(seq, "\tHalf duple %s\n",
1597 (priv->dma_cap.half_duplex) ? "Y" : "N");
1598 seq_printf(seq, "\tHash Filter: %s\n",
1599 (priv->dma_cap.hash_filter) ? "Y" : "N");
1600 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1601 (priv->dma_cap.multi_addr) ? "Y" : "N");
1602 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1603 (priv->dma_cap.pcs) ? "Y" : "N");
1604 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1605 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1606 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1607 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1608 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1609 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1610 seq_printf(seq, "\tRMON module: %s\n",
1611 (priv->dma_cap.rmon) ? "Y" : "N");
1612 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1613 (priv->dma_cap.time_stamp) ? "Y" : "N");
1614 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1615 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1616 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1617 (priv->dma_cap.eee) ? "Y" : "N");
1618 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1619 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1620 (priv->dma_cap.tx_coe) ? "Y" : "N");
1621 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1622 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1623 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1624 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1625 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1626 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1627 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1628 priv->dma_cap.number_rx_channel);
1629 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1630 priv->dma_cap.number_tx_channel);
1631 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1632 (priv->dma_cap.enh_desc) ? "Y" : "N");
1633
1634 return 0;
1635}
1636
1637static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1638{
1639 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1640}
1641
1642static const struct file_operations stmmac_dma_cap_fops = {
1643 .owner = THIS_MODULE,
1644 .open = stmmac_sysfs_dma_cap_open,
1645 .read = seq_read,
1646 .llseek = seq_lseek,
1647 .release = seq_release,
1648};
1649
7ac29055
GC		 1650static int stmmac_init_fs(struct net_device *dev)
1651{
1652 /* Create debugfs entries */
1653 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1654
1655 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1656 pr_err("ERROR %s, debugfs create directory failed\n",
1657 STMMAC_RESOURCE_NAME);
1658
1659 return -ENOMEM;
1660 }
1661
1662 /* Entry to report DMA RX/TX rings */
1663 stmmac_rings_status = debugfs_create_file("descriptors_status",
1664 S_IRUGO, stmmac_fs_dir, dev,
1665 &stmmac_rings_status_fops);
1666
1667 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1668 pr_info("ERROR creating stmmac ring debugfs file\n");
1669 debugfs_remove(stmmac_fs_dir);
1670
1671 return -ENOMEM;
1672 }
1673
e7434821
GC		 1674 /* Entry to report the DMA HW features */
1675 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1676 dev, &stmmac_dma_cap_fops);
1677
1678 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1679 pr_info("ERROR creating stmmac MMC debugfs file\n");
1680 debugfs_remove(stmmac_rings_status);
1681 debugfs_remove(stmmac_fs_dir);
1682
1683 return -ENOMEM;
1684 }
1685
7ac29055
GC		 1686 return 0;
1687}
1688
1689static void stmmac_exit_fs(void)
1690{
1691 debugfs_remove(stmmac_rings_status);
e7434821 1692 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 1693 debugfs_remove(stmmac_fs_dir);
1694}
1695#endif /* CONFIG_STMMAC_DEBUG_FS */
1696
47dd7a54
GC		 1697static const struct net_device_ops stmmac_netdev_ops = {
1698 .ndo_open = stmmac_open,
1699 .ndo_start_xmit = stmmac_xmit,
1700 .ndo_stop = stmmac_release,
1701 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1702 .ndo_fix_features = stmmac_fix_features,
01789349 1703 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1704 .ndo_tx_timeout = stmmac_tx_timeout,
1705 .ndo_do_ioctl = stmmac_ioctl,
1706 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1707#ifdef CONFIG_NET_POLL_CONTROLLER
1708 .ndo_poll_controller = stmmac_poll_controller,
1709#endif
1710 .ndo_set_mac_address = eth_mac_addr,
1711};
1712
1713/**
1714 * stmmac_probe - Initialization of the adapter .
1715 * @dev : device pointer
1716 * Description: The function initializes the network device structure for
1717 * the STMMAC driver. It also calls the low level routines
1718 * in order to init the HW (i.e. the DMA engine)
1719 */
1720static int stmmac_probe(struct net_device *dev)
1721{
1722 int ret = 0;
1723 struct stmmac_priv *priv = netdev_priv(dev);
1724
1725 ether_setup(dev);
1726
1727 dev->netdev_ops = &stmmac_netdev_ops;
1728 stmmac_set_ethtool_ops(dev);
1729
5e982f3b
MM		 1730 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1731 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
47dd7a54
GC		 1732 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1733#ifdef STMMAC_VLAN_TAG_USED
1734 /* Both mac100 and gmac support receive VLAN tag detection */
1735 dev->features |= NETIF_F_HW_VLAN_RX;
1736#endif
1737 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1738
47dd7a54
GC		 1739 if (flow_ctrl)
1740 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1741
1742 priv->pause = pause;
1743 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1744
1745 /* Get the MAC address */
ad01b7d4
GC		 1746 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1747 dev->dev_addr, 0);
47dd7a54
GC		 1748
1749 if (!is_valid_ether_addr(dev->dev_addr))
1750 pr_warning("\tno valid MAC address;"
1751 "please, use ifconfig or nwhwconfig!\n");
1752
f8e96161 1753 spin_lock_init(&priv->lock);
a9097a96 1754 spin_lock_init(&priv->tx_lock);
f8e96161 1755
47dd7a54
GC		 1756 ret = register_netdev(dev);
1757 if (ret) {
1758 pr_err("%s: ERROR %i registering the device\n",
1759 __func__, ret);
1760 return -ENODEV;
1761 }
1762
1763 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1764 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
79032644 1765 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
47dd7a54 1766
47dd7a54
GC		 1767 return ret;
1768}
1769
1770/**
1771 * stmmac_mac_device_setup
1772 * @dev : device pointer
1773 * Description: select and initialise the mac device (mac100 or Gmac).
1774 */
1775static int stmmac_mac_device_setup(struct net_device *dev)
1776{
1777 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1778
1779 struct mac_device_info *device;
1780
01789349
JP		 1781 if (priv->plat->has_gmac) {
1782 dev->priv_flags |= IFF_UNICAST_FLT;
ad01b7d4 1783 device = dwmac1000_setup(priv->ioaddr);
01789349 1784 } else {
ad01b7d4 1785 device = dwmac100_setup(priv->ioaddr);
01789349 1786 }
3d90c508 1787
1ff21906
DC		 1788 if (!device)
1789 return -ENOMEM;
1790
9dfeb4d9 1791 if (priv->plat->enh_desc) {
3d90c508
GC		 1792 device->desc = &enh_desc_ops;
1793 pr_info("\tEnhanced descriptor structure\n");
1794 } else
56b106ae 1795 device->desc = &ndesc_ops;
47dd7a54 1796
db98a0b0 1797 priv->hw = device;
47dd7a54 1798
539c9aa5 1799 if (device_can_wakeup(priv->device)) {
543876c9 1800 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
3172d3af 1801 enable_irq_wake(priv->wol_irq);
539c9aa5 1802 }
47dd7a54
GC		 1803
1804 return 0;
1805}
1806
47dd7a54
GC		 1807/**
1808 * stmmac_dvr_probe
1809 * @pdev: platform device pointer
1810 * Description: the driver is initialized through platform_device.
1811 */
1812static int stmmac_dvr_probe(struct platform_device *pdev)
1813{
1814 int ret = 0;
1815 struct resource *res;
ad01b7d4 1816 void __iomem *addr = NULL;
47dd7a54 1817 struct net_device *ndev = NULL;
293bb1c4 1818 struct stmmac_priv *priv = NULL;
47dd7a54
GC		 1819 struct plat_stmmacenet_data *plat_dat;
1820
1821 pr_info("STMMAC driver:\n\tplatform registration... ");
1822 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34a52f36
DC		 1823 if (!res)
1824 return -ENODEV;
ebbb293f 1825 pr_info("\tdone!\n");
47dd7a54 1826
b6222682 1827 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1828 pdev->name)) {
1829 pr_err("%s: ERROR: memory allocation failed"
1830 "cannot get the I/O addr 0x%x\n",
1831 __func__, (unsigned int)res->start);
34a52f36 1832 return -EBUSY;
47dd7a54
GC		 1833 }
1834
7c5365bc 1835 addr = ioremap(res->start, resource_size(res));
47dd7a54 1836 if (!addr) {
7c5365bc 1837 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54 1838 ret = -ENOMEM;
34a52f36 1839 goto out_release_region;
47dd7a54
GC		 1840 }
1841
1842 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1843 if (!ndev) {
1844 pr_err("%s: ERROR: allocating the device\n", __func__);
1845 ret = -ENOMEM;
34a52f36 1846 goto out_unmap;
47dd7a54
GC		 1847 }
1848
1849 SET_NETDEV_DEV(ndev, &pdev->dev);
1850
1851 /* Get the MAC information */
1852 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1853 if (ndev->irq == -ENXIO) {
1854 pr_err("%s: ERROR: MAC IRQ configuration "
1855 "information not found\n", __func__);
34a52f36
DC		 1856 ret = -ENXIO;
1857 goto out_free_ndev;
47dd7a54
GC		 1858 }
1859
1860 priv = netdev_priv(ndev);
1861 priv->device = &(pdev->dev);
1862 priv->dev = ndev;
ee7946a7 1863 plat_dat = pdev->dev.platform_data;
9dfeb4d9
GC		 1864
1865 priv->plat = plat_dat;
1866
ad01b7d4 1867 priv->ioaddr = addr;
47dd7a54 1868
543876c9
GC		 1869 /* PMT module is not integrated in all the MAC devices. */
1870 if (plat_dat->pmt) {
1871 pr_info("\tPMT module supported\n");
1872 device_set_wakeup_capable(&pdev->dev, 1);
1873 }
3172d3af
DS		 1874 /*
1875 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1876 * The external wake up irq can be passed through the platform code
1877 * named as "eth_wake_irq"
1878 *
1879 * In case the wake up interrupt is not passed from the platform
1880 * so the driver will continue to use the mac irq (ndev->irq)
1881 */
1882 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1883 if (priv->wol_irq == -ENXIO)
1884 priv->wol_irq = ndev->irq;
1885
543876c9 1886
47dd7a54
GC		 1887 platform_set_drvdata(pdev, ndev);
1888
1889 /* Set the I/O base addr */
1890 ndev->base_addr = (unsigned long)addr;
1891
293bb1c4
GC		 1892 /* Custom initialisation */
1893 if (priv->plat->init) {
1894 ret = priv->plat->init(pdev);
1895 if (unlikely(ret))
34a52f36 1896 goto out_free_ndev;
293bb1c4 1897 }
ee7946a7 1898
47dd7a54
GC		 1899 /* MAC HW revice detection */
1900 ret = stmmac_mac_device_setup(ndev);
1901 if (ret < 0)
34a52f36 1902 goto out_plat_exit;
47dd7a54
GC		 1903
1904 /* Network Device Registration */
1905 ret = stmmac_probe(ndev);
1906 if (ret < 0)
34a52f36 1907 goto out_plat_exit;
47dd7a54 1908
36bcfe7d
GC		 1909 /* Override with kernel parameters if supplied XXX CRS XXX
1910 * this needs to have multiple instances */
1911 if ((phyaddr >= 0) && (phyaddr <= 31))
1912 priv->plat->phy_addr = phyaddr;
47dd7a54 1913
47dd7a54 1914 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1915 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1916 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1917
1918 /* MDIO bus Registration */
9dfeb4d9 1919 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
47dd7a54
GC		 1920 ret = stmmac_mdio_register(ndev);
1921 if (ret < 0)
34a52f36 1922 goto out_unregister;
47dd7a54 1923 pr_debug("registered!\n");
7ac29055
GC		 1924
1925#ifdef CONFIG_STMMAC_DEBUG_FS
1926 ret = stmmac_init_fs(ndev);
1927 if (ret < 0)
1928 pr_warning("\tFailed debugFS registration");
1929#endif
1930
34a52f36 1931 return 0;
47dd7a54 1932
34a52f36
DC		 1933out_unregister:
1934 unregister_netdev(ndev);
1935out_plat_exit:
1936 if (priv->plat->exit)
1937 priv->plat->exit(pdev);
1938out_free_ndev:
1939 free_netdev(ndev);
1940 platform_set_drvdata(pdev, NULL);
1941out_unmap:
1942 iounmap(addr);
1943out_release_region:
1944 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1945
1946 return ret;
1947}
1948
1949/**
1950 * stmmac_dvr_remove
1951 * @pdev: platform device pointer
1952 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1953 * changes the link status, releases the DMA descriptor rings,
1954 * unregisters the MDIO bus and unmaps the allocated memory.
1955 */
1956static int stmmac_dvr_remove(struct platform_device *pdev)
1957{
1958 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1959 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1960 struct resource *res;
1961
1962 pr_info("%s:\n\tremoving driver", __func__);
1963
ad01b7d4
GC		 1964 priv->hw->dma->stop_rx(priv->ioaddr);
1965 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1966
19449bfc 1967 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1968
1969 netif_carrier_off(ndev);
1970
1971 stmmac_mdio_unregister(ndev);
1972
293bb1c4
GC		 1973 if (priv->plat->exit)
1974 priv->plat->exit(pdev);
1975
47dd7a54
GC		 1976 platform_set_drvdata(pdev, NULL);
1977 unregister_netdev(ndev);
1978
ad01b7d4 1979 iounmap((void *)priv->ioaddr);
47dd7a54 1980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1981 release_mem_region(res->start, resource_size(res));
47dd7a54 1982
7ac29055
GC		 1983#ifdef CONFIG_STMMAC_DEBUG_FS
1984 stmmac_exit_fs();
1985#endif
1986
47dd7a54
GC		 1987 free_netdev(ndev);
1988
1989 return 0;
1990}
1991
1992#ifdef CONFIG_PM
874bd42d 1993static int stmmac_suspend(struct device *dev)
47dd7a54 1994{
874bd42d
GC		 1995 struct net_device *ndev = dev_get_drvdata(dev);
1996 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1997 int dis_ic = 0;
1998
874bd42d 1999 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 2000 return 0;
2001
2002 spin_lock(&priv->lock);
2003
874bd42d
GC		 2004 netif_device_detach(ndev);
2005 netif_stop_queue(ndev);
2006 if (priv->phydev)
2007 phy_stop(priv->phydev);
47dd7a54
GC		 2008
2009#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2010 priv->tm->timer_stop();
2011 if (likely(priv->tm->enable))
2012 dis_ic = 1;
47dd7a54 2013#endif
874bd42d
GC		 2014 napi_disable(&priv->napi);
2015
2016 /* Stop TX/RX DMA */
2017 priv->hw->dma->stop_tx(priv->ioaddr);
2018 priv->hw->dma->stop_rx(priv->ioaddr);
2019 /* Clear the Rx/Tx descriptors */
2020 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2021 dis_ic);
2022 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2023
2024 /* Enable Power down mode by programming the PMT regs */
2025 if (device_may_wakeup(priv->device))
2026 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2027 else
2028 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 2029
2030 spin_unlock(&priv->lock);
2031 return 0;
2032}
2033
874bd42d 2034static int stmmac_resume(struct device *dev)
47dd7a54 2035{
874bd42d
GC		 2036 struct net_device *ndev = dev_get_drvdata(dev);
2037 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 2038
874bd42d 2039 if (!netif_running(ndev))
47dd7a54
GC		 2040 return 0;
2041
c4433be6
GC		 2042 spin_lock(&priv->lock);
2043
47dd7a54
GC		 2044 /* Power Down bit, into the PM register, is cleared
2045 * automatically as soon as a magic packet or a Wake-up frame
2046 * is received. Anyway, it's better to manually clear
2047 * this bit because it can generate problems while resuming
2048 * from another devices (e.g. serial console). */
874bd42d 2049 if (device_may_wakeup(priv->device))
543876c9 2050 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54 2051
874bd42d 2052 netif_device_attach(ndev);
47dd7a54
GC		 2053
2054 /* Enable the MAC and DMA */
19449bfc 2055 stmmac_enable_mac(priv->ioaddr);
ad01b7d4
GC		 2056 priv->hw->dma->start_tx(priv->ioaddr);
2057 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 2058
2059#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2060 if (likely(priv->tm->enable))
2061 priv->tm->timer_start(tmrate);
47dd7a54
GC		 2062#endif
2063 napi_enable(&priv->napi);
2064
2065 if (priv->phydev)
2066 phy_start(priv->phydev);
2067
874bd42d 2068 netif_start_queue(ndev);
47dd7a54 2069
47dd7a54
GC		 2070 spin_unlock(&priv->lock);
2071 return 0;
2072}
47dd7a54 2073
874bd42d
GC		 2074static int stmmac_freeze(struct device *dev)
2075{
2076 struct net_device *ndev = dev_get_drvdata(dev);
2077
2078 if (!ndev || !netif_running(ndev))
2079 return 0;
2080
2081 return stmmac_release(ndev);
2082}
2083
2084static int stmmac_restore(struct device *dev)
2085{
2086 struct net_device *ndev = dev_get_drvdata(dev);
2087
2088 if (!ndev || !netif_running(ndev))
2089 return 0;
2090
2091 return stmmac_open(ndev);
2092}
2093
2094static const struct dev_pm_ops stmmac_pm_ops = {
47dd7a54
GC		 2095 .suspend = stmmac_suspend,
2096 .resume = stmmac_resume,
874bd42d
GC		 2097 .freeze = stmmac_freeze,
2098 .thaw = stmmac_restore,
2099 .restore = stmmac_restore,
2100};
2101#else
2102static const struct dev_pm_ops stmmac_pm_ops;
2103#endif /* CONFIG_PM */
47dd7a54 2104
874bd42d
GC		 2105static struct platform_driver stmmac_driver = {
2106 .probe = stmmac_dvr_probe,
2107 .remove = stmmac_dvr_remove,
2108 .driver = {
2109 .name = STMMAC_RESOURCE_NAME,
2110 .owner = THIS_MODULE,
2111 .pm = &stmmac_pm_ops,
2112 },
47dd7a54
GC		 2113};
2114
2115/**
2116 * stmmac_init_module - Entry point for the driver
2117 * Description: This function is the entry point for the driver.
2118 */
2119static int __init stmmac_init_module(void)
2120{
2121 int ret;
2122
47dd7a54
GC		 2123 ret = platform_driver_register(&stmmac_driver);
2124 return ret;
2125}
2126
2127/**
2128 * stmmac_cleanup_module - Cleanup routine for the driver
2129 * Description: This function is the cleanup routine for the driver.
2130 */
2131static void __exit stmmac_cleanup_module(void)
2132{
47dd7a54
GC		 2133 platform_driver_unregister(&stmmac_driver);
2134}
2135
2136#ifndef MODULE
2137static int __init stmmac_cmdline_opt(char *str)
2138{
2139 char *opt;
2140
2141 if (!str || !*str)
2142 return -EINVAL;
2143 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 2144 if (!strncmp(opt, "debug:", 6)) {
2145 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2146 goto err;
2147 } else if (!strncmp(opt, "phyaddr:", 8)) {
2148 if (strict_strtoul(opt + 8, 0,
2149 (unsigned long *)&phyaddr))
2150 goto err;
2151 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2152 if (strict_strtoul(opt + 11, 0,
2153 (unsigned long *)&dma_txsize))
2154 goto err;
2155 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2156 if (strict_strtoul(opt + 11, 0,
2157 (unsigned long *)&dma_rxsize))
2158 goto err;
2159 } else if (!strncmp(opt, "buf_sz:", 7)) {
2160 if (strict_strtoul(opt + 7, 0,
2161 (unsigned long *)&buf_sz))
2162 goto err;
2163 } else if (!strncmp(opt, "tc:", 3)) {
2164 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2165 goto err;
2166 } else if (!strncmp(opt, "watchdog:", 9)) {
2167 if (strict_strtoul(opt + 9, 0,
2168 (unsigned long *)&watchdog))
2169 goto err;
2170 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2171 if (strict_strtoul(opt + 10, 0,
2172 (unsigned long *)&flow_ctrl))
2173 goto err;
2174 } else if (!strncmp(opt, "pause:", 6)) {
2175 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2176 goto err;
47dd7a54 2177#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 2178 } else if (!strncmp(opt, "tmrate:", 7)) {
2179 if (strict_strtoul(opt + 7, 0,
2180 (unsigned long *)&tmrate))
2181 goto err;
47dd7a54 2182#endif
f3240e28 2183 }
47dd7a54
GC		 2184 }
2185 return 0;
f3240e28
GC		 2186
2187err:
2188 pr_err("%s: ERROR broken module parameter conversion", __func__);
2189 return -EINVAL;
47dd7a54
GC		 2190}
2191
2192__setup("stmmaceth=", stmmac_cmdline_opt);
2193#endif
2194
2195module_init(stmmac_init_module);
2196module_exit(stmmac_cleanup_module);
2197
2198MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2199MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2200MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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