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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
47dd7a54 GC |
31 | #include <linux/kernel.h> |
32 | #include <linux/interrupt.h> | |
47dd7a54 GC |
33 | #include <linux/ip.h> |
34 | #include <linux/tcp.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/if_ether.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/mii.h> | |
01789349 | 40 | #include <linux/if.h> |
47dd7a54 GC |
41 | #include <linux/if_vlan.h> |
42 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
70c71606 | 44 | #include <linux/prefetch.h> |
7ac29055 GC |
45 | #ifdef CONFIG_STMMAC_DEBUG_FS |
46 | #include <linux/debugfs.h> | |
47 | #include <linux/seq_file.h> | |
48 | #endif | |
286a8372 | 49 | #include "stmmac.h" |
47dd7a54 | 50 | |
47dd7a54 GC |
51 | #undef STMMAC_DEBUG |
52 | /*#define STMMAC_DEBUG*/ | |
53 | #ifdef STMMAC_DEBUG | |
54 | #define DBG(nlevel, klevel, fmt, args...) \ | |
55 | ((void)(netif_msg_##nlevel(priv) && \ | |
56 | printk(KERN_##klevel fmt, ## args))) | |
57 | #else | |
58 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
59 | #endif | |
60 | ||
61 | #undef STMMAC_RX_DEBUG | |
62 | /*#define STMMAC_RX_DEBUG*/ | |
63 | #ifdef STMMAC_RX_DEBUG | |
64 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
65 | #else | |
66 | #define RX_DBG(fmt, args...) do { } while (0) | |
67 | #endif | |
68 | ||
69 | #undef STMMAC_XMIT_DEBUG | |
70 | /*#define STMMAC_XMIT_DEBUG*/ | |
71 | #ifdef STMMAC_TX_DEBUG | |
72 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
73 | #else | |
74 | #define TX_DBG(fmt, args...) do { } while (0) | |
75 | #endif | |
76 | ||
77 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
78 | #define JUMBO_LEN 9000 | |
79 | ||
80 | /* Module parameters */ | |
81 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
82 | static int watchdog = TX_TIMEO; | |
83 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
85 | ||
86 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
87 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
88 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
89 | ||
bfab27a1 | 90 | int phyaddr = -1; |
47dd7a54 GC |
91 | module_param(phyaddr, int, S_IRUGO); |
92 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
93 | ||
94 | #define DMA_TX_SIZE 256 | |
95 | static int dma_txsize = DMA_TX_SIZE; | |
96 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
97 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
98 | ||
99 | #define DMA_RX_SIZE 256 | |
100 | static int dma_rxsize = DMA_RX_SIZE; | |
101 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
102 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
103 | ||
104 | static int flow_ctrl = FLOW_OFF; | |
105 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
106 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
107 | ||
108 | static int pause = PAUSE_TIME; | |
109 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
110 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
111 | ||
112 | #define TC_DEFAULT 64 | |
113 | static int tc = TC_DEFAULT; | |
114 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
115 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
116 | ||
47dd7a54 GC |
117 | /* Pay attention to tune this parameter; take care of both |
118 | * hardware capability and network stabitily/performance impact. | |
119 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
120 | #ifdef CONFIG_STMMAC_TIMER | |
121 | #define DEFAULT_PERIODIC_RATE 256 | |
122 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
123 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
124 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
125 | #endif | |
126 | ||
127 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
128 | static int buf_sz = DMA_BUFFER_SIZE; | |
129 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
130 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
131 | ||
47dd7a54 GC |
132 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
133 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
134 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
135 | ||
136 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 | 137 | |
bfab27a1 GC |
138 | #ifdef CONFIG_STMMAC_DEBUG_FS |
139 | static int stmmac_init_fs(struct net_device *dev); | |
140 | static void stmmac_exit_fs(void); | |
141 | #endif | |
142 | ||
47dd7a54 GC |
143 | /** |
144 | * stmmac_verify_args - verify the driver parameters. | |
145 | * Description: it verifies if some wrong parameter is passed to the driver. | |
146 | * Note that wrong parameters are replaced with the default values. | |
147 | */ | |
148 | static void stmmac_verify_args(void) | |
149 | { | |
150 | if (unlikely(watchdog < 0)) | |
151 | watchdog = TX_TIMEO; | |
152 | if (unlikely(dma_rxsize < 0)) | |
153 | dma_rxsize = DMA_RX_SIZE; | |
154 | if (unlikely(dma_txsize < 0)) | |
155 | dma_txsize = DMA_TX_SIZE; | |
156 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
157 | buf_sz = DMA_BUFFER_SIZE; | |
158 | if (unlikely(flow_ctrl > 1)) | |
159 | flow_ctrl = FLOW_AUTO; | |
160 | else if (likely(flow_ctrl < 0)) | |
161 | flow_ctrl = FLOW_OFF; | |
162 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
163 | pause = PAUSE_TIME; | |
47dd7a54 GC |
164 | } |
165 | ||
166 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) | |
167 | static void print_pkt(unsigned char *buf, int len) | |
168 | { | |
169 | int j; | |
170 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
171 | for (j = 0; j < len; j++) { | |
172 | if ((j % 16) == 0) | |
173 | pr_info("\n %03x:", j); | |
174 | pr_info(" %02x", buf[j]); | |
175 | } | |
176 | pr_info("\n"); | |
47dd7a54 GC |
177 | } |
178 | #endif | |
179 | ||
180 | /* minimum number of free TX descriptors required to wake up TX process */ | |
181 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
182 | ||
183 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
184 | { | |
185 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
186 | } | |
187 | ||
9dfeb4d9 GC |
188 | /* On some ST platforms, some HW system configuraton registers have to be |
189 | * set according to the link speed negotiated. | |
190 | */ | |
191 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
192 | { | |
193 | struct phy_device *phydev = priv->phydev; | |
194 | ||
195 | if (likely(priv->plat->fix_mac_speed)) | |
196 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
197 | phydev->speed); | |
198 | } | |
199 | ||
47dd7a54 GC |
200 | /** |
201 | * stmmac_adjust_link | |
202 | * @dev: net device structure | |
203 | * Description: it adjusts the link parameters. | |
204 | */ | |
205 | static void stmmac_adjust_link(struct net_device *dev) | |
206 | { | |
207 | struct stmmac_priv *priv = netdev_priv(dev); | |
208 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
209 | unsigned long flags; |
210 | int new_state = 0; | |
211 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
212 | ||
213 | if (phydev == NULL) | |
214 | return; | |
215 | ||
216 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
217 | phydev->addr, phydev->link); | |
218 | ||
219 | spin_lock_irqsave(&priv->lock, flags); | |
220 | if (phydev->link) { | |
ad01b7d4 | 221 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
222 | |
223 | /* Now we make sure that we can be in full duplex mode. | |
224 | * If not, we operate in half-duplex mode. */ | |
225 | if (phydev->duplex != priv->oldduplex) { | |
226 | new_state = 1; | |
227 | if (!(phydev->duplex)) | |
db98a0b0 | 228 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 229 | else |
db98a0b0 | 230 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
231 | priv->oldduplex = phydev->duplex; |
232 | } | |
233 | /* Flow Control operation */ | |
234 | if (phydev->pause) | |
ad01b7d4 | 235 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 236 | fc, pause_time); |
47dd7a54 GC |
237 | |
238 | if (phydev->speed != priv->speed) { | |
239 | new_state = 1; | |
240 | switch (phydev->speed) { | |
241 | case 1000: | |
9dfeb4d9 | 242 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 243 | ctrl &= ~priv->hw->link.port; |
9dfeb4d9 | 244 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
245 | break; |
246 | case 100: | |
247 | case 10: | |
9dfeb4d9 | 248 | if (priv->plat->has_gmac) { |
db98a0b0 | 249 | ctrl |= priv->hw->link.port; |
47dd7a54 | 250 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 251 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 252 | } else { |
db98a0b0 | 253 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
254 | } |
255 | } else { | |
db98a0b0 | 256 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 257 | } |
9dfeb4d9 | 258 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
259 | break; |
260 | default: | |
261 | if (netif_msg_link(priv)) | |
262 | pr_warning("%s: Speed (%d) is not 10" | |
263 | " or 100!\n", dev->name, phydev->speed); | |
264 | break; | |
265 | } | |
266 | ||
267 | priv->speed = phydev->speed; | |
268 | } | |
269 | ||
ad01b7d4 | 270 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
271 | |
272 | if (!priv->oldlink) { | |
273 | new_state = 1; | |
274 | priv->oldlink = 1; | |
275 | } | |
276 | } else if (priv->oldlink) { | |
277 | new_state = 1; | |
278 | priv->oldlink = 0; | |
279 | priv->speed = 0; | |
280 | priv->oldduplex = -1; | |
281 | } | |
282 | ||
283 | if (new_state && netif_msg_link(priv)) | |
284 | phy_print_status(phydev); | |
285 | ||
286 | spin_unlock_irqrestore(&priv->lock, flags); | |
287 | ||
288 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
289 | } | |
290 | ||
291 | /** | |
292 | * stmmac_init_phy - PHY initialization | |
293 | * @dev: net device structure | |
294 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
295 | * to the mac driver. | |
296 | * Return value: | |
297 | * 0 on success | |
298 | */ | |
299 | static int stmmac_init_phy(struct net_device *dev) | |
300 | { | |
301 | struct stmmac_priv *priv = netdev_priv(dev); | |
302 | struct phy_device *phydev; | |
109cdd66 GC |
303 | char phy_id[MII_BUS_ID_SIZE + 3]; |
304 | char bus_id[MII_BUS_ID_SIZE]; | |
79ee1dc3 | 305 | int interface = priv->plat->interface; |
47dd7a54 GC |
306 | priv->oldlink = 0; |
307 | priv->speed = 0; | |
308 | priv->oldduplex = -1; | |
309 | ||
db8857bf | 310 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id); |
109cdd66 | 311 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 312 | priv->plat->phy_addr); |
47dd7a54 GC |
313 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
314 | ||
79ee1dc3 | 315 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); |
47dd7a54 GC |
316 | |
317 | if (IS_ERR(phydev)) { | |
318 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
319 | return PTR_ERR(phydev); | |
320 | } | |
321 | ||
79ee1dc3 | 322 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 SK |
323 | if ((interface == PHY_INTERFACE_MODE_MII) || |
324 | (interface == PHY_INTERFACE_MODE_RMII)) | |
325 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | | |
326 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 327 | |
47dd7a54 GC |
328 | /* |
329 | * Broken HW is sometimes missing the pull-up resistor on the | |
330 | * MDIO line, which results in reads to non-existent devices returning | |
331 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
332 | * device as well. | |
333 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
334 | */ | |
335 | if (phydev->phy_id == 0) { | |
336 | phy_disconnect(phydev); | |
337 | return -ENODEV; | |
338 | } | |
339 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 340 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
341 | |
342 | priv->phydev = phydev; | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
47dd7a54 GC |
347 | /** |
348 | * display_ring | |
349 | * @p: pointer to the ring. | |
350 | * @size: size of the ring. | |
351 | * Description: display all the descriptors within the ring. | |
352 | */ | |
353 | static void display_ring(struct dma_desc *p, int size) | |
354 | { | |
355 | struct tmp_s { | |
356 | u64 a; | |
357 | unsigned int b; | |
358 | unsigned int c; | |
359 | }; | |
360 | int i; | |
361 | for (i = 0; i < size; i++) { | |
362 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
363 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
364 | i, (unsigned int)virt_to_phys(&p[i]), | |
365 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
366 | x->b, x->c); | |
367 | pr_info("\n"); | |
368 | } | |
369 | } | |
370 | ||
286a8372 GC |
371 | static int stmmac_set_bfsize(int mtu, int bufsize) |
372 | { | |
373 | int ret = bufsize; | |
374 | ||
375 | if (mtu >= BUF_SIZE_4KiB) | |
376 | ret = BUF_SIZE_8KiB; | |
377 | else if (mtu >= BUF_SIZE_2KiB) | |
378 | ret = BUF_SIZE_4KiB; | |
379 | else if (mtu >= DMA_BUFFER_SIZE) | |
380 | ret = BUF_SIZE_2KiB; | |
381 | else | |
382 | ret = DMA_BUFFER_SIZE; | |
383 | ||
384 | return ret; | |
385 | } | |
386 | ||
47dd7a54 GC |
387 | /** |
388 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
389 | * @dev: net device structure | |
390 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
391 | * and allocates the socket buffers. It suppors the chained and ring |
392 | * modes. | |
47dd7a54 GC |
393 | */ |
394 | static void init_dma_desc_rings(struct net_device *dev) | |
395 | { | |
396 | int i; | |
397 | struct stmmac_priv *priv = netdev_priv(dev); | |
398 | struct sk_buff *skb; | |
399 | unsigned int txsize = priv->dma_tx_size; | |
400 | unsigned int rxsize = priv->dma_rx_size; | |
286a8372 GC |
401 | unsigned int bfsize; |
402 | int dis_ic = 0; | |
403 | int des3_as_data_buf = 0; | |
47dd7a54 | 404 | |
286a8372 GC |
405 | /* Set the max buffer size according to the DESC mode |
406 | * and the MTU. Note that RING mode allows 16KiB bsize. */ | |
407 | bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); | |
408 | ||
409 | if (bfsize == BUF_SIZE_16KiB) | |
410 | des3_as_data_buf = 1; | |
47dd7a54 | 411 | else |
286a8372 | 412 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 413 | |
73cfe264 GC |
414 | #ifdef CONFIG_STMMAC_TIMER |
415 | /* Disable interrupts on completion for the reception if timer is on */ | |
416 | if (likely(priv->tm->enable)) | |
417 | dis_ic = 1; | |
418 | #endif | |
47dd7a54 GC |
419 | |
420 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
421 | txsize, rxsize, bfsize); | |
422 | ||
423 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
424 | priv->rx_skbuff = | |
425 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
426 | priv->dma_rx = | |
427 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
428 | rxsize * | |
429 | sizeof(struct dma_desc), | |
430 | &priv->dma_rx_phy, | |
431 | GFP_KERNEL); | |
432 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
433 | GFP_KERNEL); | |
434 | priv->dma_tx = | |
435 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
436 | txsize * | |
437 | sizeof(struct dma_desc), | |
438 | &priv->dma_tx_phy, | |
439 | GFP_KERNEL); | |
440 | ||
441 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
442 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
443 | return; | |
444 | } | |
445 | ||
286a8372 | 446 | DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " |
47dd7a54 GC |
447 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", |
448 | dev->name, priv->dma_rx, priv->dma_tx, | |
449 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
450 | ||
451 | /* RX INITIALIZATION */ | |
452 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
453 | "skb\t\tskb data\tdma data\n"); | |
454 | ||
455 | for (i = 0; i < rxsize; i++) { | |
456 | struct dma_desc *p = priv->dma_rx + i; | |
457 | ||
45db81e1 GC |
458 | skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, |
459 | GFP_KERNEL); | |
47dd7a54 GC |
460 | if (unlikely(skb == NULL)) { |
461 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
462 | break; | |
463 | } | |
45db81e1 | 464 | skb_reserve(skb, NET_IP_ALIGN); |
47dd7a54 GC |
465 | priv->rx_skbuff[i] = skb; |
466 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
467 | bfsize, DMA_FROM_DEVICE); | |
468 | ||
469 | p->des2 = priv->rx_skbuff_dma[i]; | |
286a8372 GC |
470 | |
471 | priv->hw->ring->init_desc3(des3_as_data_buf, p); | |
472 | ||
47dd7a54 GC |
473 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], |
474 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
475 | } | |
476 | priv->cur_rx = 0; | |
477 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
478 | priv->dma_buf_sz = bfsize; | |
479 | buf_sz = bfsize; | |
480 | ||
481 | /* TX INITIALIZATION */ | |
482 | for (i = 0; i < txsize; i++) { | |
483 | priv->tx_skbuff[i] = NULL; | |
484 | priv->dma_tx[i].des2 = 0; | |
485 | } | |
286a8372 GC |
486 | |
487 | /* In case of Chained mode this sets the des3 to the next | |
488 | * element in the chain */ | |
489 | priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); | |
490 | priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); | |
491 | ||
47dd7a54 GC |
492 | priv->dirty_tx = 0; |
493 | priv->cur_tx = 0; | |
494 | ||
495 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
496 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
497 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
498 | |
499 | if (netif_msg_hw(priv)) { | |
500 | pr_info("RX descriptor ring:\n"); | |
501 | display_ring(priv->dma_rx, rxsize); | |
502 | pr_info("TX descriptor ring:\n"); | |
503 | display_ring(priv->dma_tx, txsize); | |
504 | } | |
47dd7a54 GC |
505 | } |
506 | ||
507 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
508 | { | |
509 | int i; | |
510 | ||
511 | for (i = 0; i < priv->dma_rx_size; i++) { | |
512 | if (priv->rx_skbuff[i]) { | |
513 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
514 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
515 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
516 | } | |
517 | priv->rx_skbuff[i] = NULL; | |
518 | } | |
47dd7a54 GC |
519 | } |
520 | ||
521 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
522 | { | |
523 | int i; | |
524 | ||
525 | for (i = 0; i < priv->dma_tx_size; i++) { | |
526 | if (priv->tx_skbuff[i] != NULL) { | |
527 | struct dma_desc *p = priv->dma_tx + i; | |
528 | if (p->des2) | |
529 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
530 | priv->hw->desc->get_tx_len(p), |
531 | DMA_TO_DEVICE); | |
47dd7a54 GC |
532 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
533 | priv->tx_skbuff[i] = NULL; | |
534 | } | |
535 | } | |
47dd7a54 GC |
536 | } |
537 | ||
538 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
539 | { | |
540 | /* Release the DMA TX/RX socket buffers */ | |
541 | dma_free_rx_skbufs(priv); | |
542 | dma_free_tx_skbufs(priv); | |
543 | ||
544 | /* Free the region of consistent memory previously allocated for | |
545 | * the DMA */ | |
546 | dma_free_coherent(priv->device, | |
547 | priv->dma_tx_size * sizeof(struct dma_desc), | |
548 | priv->dma_tx, priv->dma_tx_phy); | |
549 | dma_free_coherent(priv->device, | |
550 | priv->dma_rx_size * sizeof(struct dma_desc), | |
551 | priv->dma_rx, priv->dma_rx_phy); | |
552 | kfree(priv->rx_skbuff_dma); | |
553 | kfree(priv->rx_skbuff); | |
554 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
555 | } |
556 | ||
47dd7a54 GC |
557 | /** |
558 | * stmmac_dma_operation_mode - HW DMA operation mode | |
559 | * @priv : pointer to the private device structure. | |
560 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 561 | * or Store-And-Forward capability. |
47dd7a54 GC |
562 | */ |
563 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
564 | { | |
61b8013a SK |
565 | if (likely(priv->plat->force_sf_dma_mode || |
566 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
567 | /* | |
568 | * In case of GMAC, SF mode can be enabled | |
569 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
570 | * 1) TX COE if actually supported |
571 | * 2) There is no bugged Jumbo frame support | |
572 | * that needs to not insert csum in the TDES. | |
573 | */ | |
574 | priv->hw->dma->dma_mode(priv->ioaddr, | |
575 | SF_DMA_MODE, SF_DMA_MODE); | |
576 | tc = SF_DMA_MODE; | |
577 | } else | |
578 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
579 | } |
580 | ||
47dd7a54 GC |
581 | /** |
582 | * stmmac_tx: | |
583 | * @priv: private driver structure | |
584 | * Description: it reclaims resources after transmission completes. | |
585 | */ | |
586 | static void stmmac_tx(struct stmmac_priv *priv) | |
587 | { | |
588 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 | 589 | |
a9097a96 GC |
590 | spin_lock(&priv->tx_lock); |
591 | ||
47dd7a54 GC |
592 | while (priv->dirty_tx != priv->cur_tx) { |
593 | int last; | |
594 | unsigned int entry = priv->dirty_tx % txsize; | |
595 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
596 | struct dma_desc *p = priv->dma_tx + entry; | |
597 | ||
598 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 599 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
600 | break; |
601 | ||
602 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 603 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
604 | if (likely(last)) { |
605 | int tx_error = | |
db98a0b0 GC |
606 | priv->hw->desc->tx_status(&priv->dev->stats, |
607 | &priv->xstats, p, | |
ad01b7d4 | 608 | priv->ioaddr); |
47dd7a54 GC |
609 | if (likely(tx_error == 0)) { |
610 | priv->dev->stats.tx_packets++; | |
611 | priv->xstats.tx_pkt_n++; | |
612 | } else | |
613 | priv->dev->stats.tx_errors++; | |
614 | } | |
615 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
616 | priv->cur_tx, priv->dirty_tx); | |
617 | ||
618 | if (likely(p->des2)) | |
619 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 620 | priv->hw->desc->get_tx_len(p), |
47dd7a54 | 621 | DMA_TO_DEVICE); |
286a8372 | 622 | priv->hw->ring->clean_desc3(p); |
47dd7a54 GC |
623 | |
624 | if (likely(skb != NULL)) { | |
625 | /* | |
626 | * If there's room in the queue (limit it to size) | |
627 | * we add this skb back into the pool, | |
628 | * if it's the right size. | |
629 | */ | |
630 | if ((skb_queue_len(&priv->rx_recycle) < | |
631 | priv->dma_rx_size) && | |
632 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
633 | __skb_queue_head(&priv->rx_recycle, skb); | |
634 | else | |
635 | dev_kfree_skb(skb); | |
636 | ||
637 | priv->tx_skbuff[entry] = NULL; | |
638 | } | |
639 | ||
db98a0b0 | 640 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 GC |
641 | |
642 | entry = (++priv->dirty_tx) % txsize; | |
643 | } | |
644 | if (unlikely(netif_queue_stopped(priv->dev) && | |
645 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
646 | netif_tx_lock(priv->dev); | |
647 | if (netif_queue_stopped(priv->dev) && | |
648 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
649 | TX_DBG("%s: restart transmit\n", __func__); | |
650 | netif_wake_queue(priv->dev); | |
651 | } | |
652 | netif_tx_unlock(priv->dev); | |
653 | } | |
a9097a96 | 654 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
655 | } |
656 | ||
657 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
658 | { | |
73cfe264 GC |
659 | #ifdef CONFIG_STMMAC_TIMER |
660 | if (likely(priv->tm->enable)) | |
661 | priv->tm->timer_start(tmrate); | |
662 | else | |
47dd7a54 | 663 | #endif |
ad01b7d4 | 664 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
665 | } |
666 | ||
667 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
668 | { | |
73cfe264 GC |
669 | #ifdef CONFIG_STMMAC_TIMER |
670 | if (likely(priv->tm->enable)) | |
671 | priv->tm->timer_stop(); | |
672 | else | |
47dd7a54 | 673 | #endif |
ad01b7d4 | 674 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
675 | } |
676 | ||
677 | static int stmmac_has_work(struct stmmac_priv *priv) | |
678 | { | |
679 | unsigned int has_work = 0; | |
680 | int rxret, tx_work = 0; | |
681 | ||
db98a0b0 | 682 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
683 | (priv->cur_rx % priv->dma_rx_size)); |
684 | ||
685 | if (priv->dirty_tx != priv->cur_tx) | |
686 | tx_work = 1; | |
687 | ||
688 | if (likely(!rxret || tx_work)) | |
689 | has_work = 1; | |
690 | ||
691 | return has_work; | |
692 | } | |
693 | ||
694 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
695 | { | |
696 | if (likely(stmmac_has_work(priv))) { | |
697 | stmmac_disable_irq(priv); | |
698 | napi_schedule(&priv->napi); | |
699 | } | |
700 | } | |
701 | ||
702 | #ifdef CONFIG_STMMAC_TIMER | |
703 | void stmmac_schedule(struct net_device *dev) | |
704 | { | |
705 | struct stmmac_priv *priv = netdev_priv(dev); | |
706 | ||
707 | priv->xstats.sched_timer_n++; | |
708 | ||
709 | _stmmac_schedule(priv); | |
47dd7a54 GC |
710 | } |
711 | ||
712 | static void stmmac_no_timer_started(unsigned int x) | |
713 | {; | |
714 | }; | |
715 | ||
716 | static void stmmac_no_timer_stopped(void) | |
717 | {; | |
718 | }; | |
719 | #endif | |
720 | ||
721 | /** | |
722 | * stmmac_tx_err: | |
723 | * @priv: pointer to the private device structure | |
724 | * Description: it cleans the descriptors and restarts the transmission | |
725 | * in case of errors. | |
726 | */ | |
727 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
728 | { | |
729 | netif_stop_queue(priv->dev); | |
730 | ||
ad01b7d4 | 731 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 732 | dma_free_tx_skbufs(priv); |
db98a0b0 | 733 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
734 | priv->dirty_tx = 0; |
735 | priv->cur_tx = 0; | |
ad01b7d4 | 736 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
737 | |
738 | priv->dev->stats.tx_errors++; | |
739 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
740 | } |
741 | ||
47dd7a54 | 742 | |
aec7ff27 GC |
743 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
744 | { | |
aec7ff27 GC |
745 | int status; |
746 | ||
ad01b7d4 | 747 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
748 | if (likely(status == handle_tx_rx)) |
749 | _stmmac_schedule(priv); | |
750 | ||
751 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
752 | /* Try to bump up the dma threshold on this failure */ | |
753 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
754 | tc += 64; | |
ad01b7d4 | 755 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 756 | priv->xstats.threshold = tc; |
47dd7a54 | 757 | } |
aec7ff27 GC |
758 | } else if (unlikely(status == tx_hard_error)) |
759 | stmmac_tx_err(priv); | |
47dd7a54 GC |
760 | } |
761 | ||
1c901a46 GC |
762 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
763 | { | |
764 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
765 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; | |
766 | ||
4f795b25 GC |
767 | /* Mask MMC irq, counters are managed in SW and registers |
768 | * are cleared on each READ eventually. */ | |
1c901a46 | 769 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
770 | |
771 | if (priv->dma_cap.rmon) { | |
772 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
773 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
774 | } else | |
aae54cff | 775 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
776 | } |
777 | ||
f0b9d786 GC |
778 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
779 | { | |
780 | u32 hwid = priv->hw->synopsys_uid; | |
781 | ||
782 | /* Only check valid Synopsys Id because old MAC chips | |
783 | * have no HW registers where get the ID */ | |
784 | if (likely(hwid)) { | |
785 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
786 | u32 synid = (hwid & 0x000000ff); | |
787 | ||
788 | pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n", | |
789 | uid, synid); | |
790 | ||
791 | return synid; | |
792 | } | |
793 | return 0; | |
794 | } | |
e7434821 | 795 | |
19e30c14 GC |
796 | /** |
797 | * stmmac_selec_desc_mode | |
798 | * @dev : device pointer | |
799 | * Description: select the Enhanced/Alternate or Normal descriptors */ | |
800 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) | |
801 | { | |
802 | if (priv->plat->enh_desc) { | |
803 | pr_info(" Enhanced/Alternate descriptors\n"); | |
804 | priv->hw->desc = &enh_desc_ops; | |
805 | } else { | |
806 | pr_info(" Normal descriptors\n"); | |
807 | priv->hw->desc = &ndesc_ops; | |
808 | } | |
809 | } | |
810 | ||
811 | /** | |
812 | * stmmac_get_hw_features | |
813 | * @priv : private device pointer | |
814 | * Description: | |
815 | * new GMAC chip generations have a new register to indicate the | |
816 | * presence of the optional feature/functions. | |
817 | * This can be also used to override the value passed through the | |
818 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
819 | */ |
820 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
821 | { | |
5e6efe88 | 822 | u32 hw_cap = 0; |
3c20f72f | 823 | |
5e6efe88 GC |
824 | if (priv->hw->dma->get_hw_feature) { |
825 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 826 | |
1db123fb RK |
827 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
828 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
829 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
830 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
831 | priv->dma_cap.multi_addr = | |
832 | (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; | |
833 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; | |
834 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
835 | priv->dma_cap.pmt_remote_wake_up = | |
836 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; | |
837 | priv->dma_cap.pmt_magic_frame = | |
838 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; | |
19e30c14 | 839 | /* MMC */ |
1db123fb | 840 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
e7434821 | 841 | /* IEEE 1588-2002*/ |
1db123fb RK |
842 | priv->dma_cap.time_stamp = |
843 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; | |
e7434821 | 844 | /* IEEE 1588-2008*/ |
1db123fb RK |
845 | priv->dma_cap.atime_stamp = |
846 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; | |
e7434821 | 847 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
848 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
849 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 850 | /* TX and RX csum */ |
1db123fb RK |
851 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
852 | priv->dma_cap.rx_coe_type1 = | |
853 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; | |
854 | priv->dma_cap.rx_coe_type2 = | |
855 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; | |
856 | priv->dma_cap.rxfifo_over_2048 = | |
857 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; | |
e7434821 | 858 | /* TX and RX number of channels */ |
1db123fb RK |
859 | priv->dma_cap.number_rx_channel = |
860 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; | |
861 | priv->dma_cap.number_tx_channel = | |
862 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; | |
e7434821 | 863 | /* Alternate (enhanced) DESC mode*/ |
1db123fb RK |
864 | priv->dma_cap.enh_desc = |
865 | (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
e7434821 | 866 | |
19e30c14 | 867 | } |
e7434821 GC |
868 | |
869 | return hw_cap; | |
870 | } | |
871 | ||
bfab27a1 GC |
872 | /** |
873 | * stmmac_mac_device_setup | |
874 | * @dev : device pointer | |
875 | * Description: this is to attach the GMAC or MAC 10/100 | |
876 | * main core structures that will be completed during the | |
877 | * open step. | |
878 | */ | |
879 | static int stmmac_mac_device_setup(struct net_device *dev) | |
880 | { | |
881 | struct stmmac_priv *priv = netdev_priv(dev); | |
882 | ||
883 | struct mac_device_info *device; | |
884 | ||
885 | if (priv->plat->has_gmac) | |
886 | device = dwmac1000_setup(priv->ioaddr); | |
887 | else | |
888 | device = dwmac100_setup(priv->ioaddr); | |
889 | ||
890 | if (!device) | |
891 | return -ENOMEM; | |
892 | ||
893 | priv->hw = device; | |
894 | priv->hw->ring = &ring_mode_ops; | |
895 | ||
896 | if (device_can_wakeup(priv->device)) { | |
897 | priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ | |
898 | enable_irq_wake(priv->wol_irq); | |
899 | } | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) | |
905 | { | |
906 | /* verify if the MAC address is valid, in case of failures it | |
907 | * generates a random MAC address */ | |
908 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { | |
909 | priv->hw->mac->get_umac_addr((void __iomem *) | |
910 | priv->dev->base_addr, | |
911 | priv->dev->dev_addr, 0); | |
912 | if (!is_valid_ether_addr(priv->dev->dev_addr)) | |
913 | random_ether_addr(priv->dev->dev_addr); | |
914 | } | |
915 | pr_warning("%s: device MAC address %pM\n", priv->dev->name, | |
916 | priv->dev->dev_addr); | |
917 | } | |
918 | ||
47dd7a54 GC |
919 | /** |
920 | * stmmac_open - open entry point of the driver | |
921 | * @dev : pointer to the device structure. | |
922 | * Description: | |
923 | * This function is the open entry point of the driver. | |
924 | * Return value: | |
925 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
926 | * file on failure. | |
927 | */ | |
928 | static int stmmac_open(struct net_device *dev) | |
929 | { | |
930 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
931 | int ret; |
932 | ||
bfab27a1 GC |
933 | /* MAC HW device setup */ |
934 | ret = stmmac_mac_device_setup(dev); | |
935 | if (ret < 0) | |
936 | return ret; | |
937 | ||
938 | stmmac_check_ether_addr(priv); | |
47dd7a54 GC |
939 | |
940 | stmmac_verify_args(); | |
941 | ||
bfab27a1 GC |
942 | /* Override with kernel parameters if supplied XXX CRS XXX |
943 | * this needs to have multiple instances */ | |
944 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
945 | priv->plat->phy_addr = phyaddr; | |
946 | ||
947 | /* MDIO bus Registration */ | |
948 | ret = stmmac_mdio_register(dev); | |
949 | if (ret < 0) { | |
950 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
951 | __func__, priv->plat->bus_id); | |
952 | return ret; | |
953 | } | |
954 | ||
47dd7a54 | 955 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 956 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
e404decb | 957 | if (unlikely(priv->tm == NULL)) |
47dd7a54 | 958 | return -ENOMEM; |
e404decb | 959 | |
47dd7a54 GC |
960 | priv->tm->freq = tmrate; |
961 | ||
73cfe264 GC |
962 | /* Test if the external timer can be actually used. |
963 | * In case of failure continue without timer. */ | |
47dd7a54 | 964 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 965 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
966 | priv->tm->freq = 0; |
967 | priv->tm->timer_start = stmmac_no_timer_started; | |
968 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
969 | } else |
970 | priv->tm->enable = 1; | |
47dd7a54 | 971 | #endif |
f66ffe28 GC |
972 | ret = stmmac_init_phy(dev); |
973 | if (unlikely(ret)) { | |
974 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
975 | goto open_error; | |
976 | } | |
47dd7a54 | 977 | |
19e30c14 GC |
978 | stmmac_get_synopsys_id(priv); |
979 | ||
980 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
981 | ||
982 | if (priv->hw_cap_support) { | |
983 | pr_info(" Support DMA HW capability register"); | |
984 | ||
985 | /* We can override some gmac/dma configuration fields: e.g. | |
986 | * enh_desc, tx_coe (e.g. that are passed through the | |
987 | * platform) with the values from the HW capability | |
988 | * register (if supported). | |
989 | */ | |
990 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
991 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
992 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; | |
993 | ||
994 | /* By default disable wol on magic frame if not supported */ | |
995 | if (!priv->dma_cap.pmt_magic_frame) | |
996 | priv->wolopts &= ~WAKE_MAGIC; | |
997 | ||
998 | } else | |
999 | pr_info(" No HW DMA feature register supported"); | |
1000 | ||
1001 | /* Select the enhnaced/normal descriptor structures */ | |
1002 | stmmac_selec_desc_mode(priv); | |
1003 | ||
1004 | /* PMT module is not integrated in all the MAC devices. */ | |
1005 | if (priv->plat->pmt) { | |
1006 | pr_info(" Remote wake-up capable\n"); | |
1007 | device_set_wakeup_capable(priv->device, 1); | |
1008 | } | |
1009 | ||
1010 | priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr); | |
1011 | if (priv->rx_coe) | |
1012 | pr_info(" Checksum Offload Engine supported\n"); | |
1013 | if (priv->plat->tx_coe) | |
1014 | pr_info(" Checksum insertion supported\n"); | |
1015 | ||
47dd7a54 GC |
1016 | /* Create and initialize the TX/RX descriptors chains. */ |
1017 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
1018 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
1019 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
1020 | init_dma_desc_rings(dev); | |
1021 | ||
1022 | /* DMA initialization and SW reset */ | |
f66ffe28 GC |
1023 | ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl, |
1024 | priv->dma_tx_phy, priv->dma_rx_phy); | |
1025 | if (ret < 0) { | |
47dd7a54 | 1026 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 1027 | goto open_error; |
47dd7a54 GC |
1028 | } |
1029 | ||
1030 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 1031 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
ca5f12c1 | 1032 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
1033 | if (priv->plat->bus_setup) |
1034 | priv->plat->bus_setup(priv->ioaddr); | |
47dd7a54 | 1035 | /* Initialize the MAC Core */ |
ad01b7d4 | 1036 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 1037 | |
5e982f3b | 1038 | netdev_update_features(dev); |
ebbb293f | 1039 | |
f66ffe28 GC |
1040 | /* Request the IRQ lines */ |
1041 | ret = request_irq(dev->irq, stmmac_interrupt, | |
1042 | IRQF_SHARED, dev->name, dev); | |
1043 | if (unlikely(ret < 0)) { | |
1044 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1045 | __func__, dev->irq, ret); | |
1046 | goto open_error; | |
1047 | } | |
1048 | ||
47dd7a54 | 1049 | /* Enable the MAC Rx/Tx */ |
bfab27a1 | 1050 | stmmac_set_mac(priv->ioaddr, true); |
47dd7a54 GC |
1051 | |
1052 | /* Set the HW DMA mode and the COE */ | |
1053 | stmmac_dma_operation_mode(priv); | |
1054 | ||
1055 | /* Extra statistics */ | |
1056 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1057 | priv->xstats.threshold = tc; | |
1058 | ||
4f795b25 | 1059 | stmmac_mmc_setup(priv); |
1c901a46 | 1060 | |
bfab27a1 GC |
1061 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1062 | ret = stmmac_init_fs(dev); | |
1063 | if (ret < 0) | |
1064 | pr_warning("\tFailed debugFS registration"); | |
1065 | #endif | |
47dd7a54 GC |
1066 | /* Start the ball rolling... */ |
1067 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
1068 | priv->hw->dma->start_tx(priv->ioaddr); |
1069 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1070 | |
1071 | #ifdef CONFIG_STMMAC_TIMER | |
1072 | priv->tm->timer_start(tmrate); | |
1073 | #endif | |
1074 | /* Dump DMA/MAC registers */ | |
1075 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
1076 | priv->hw->mac->dump_regs(priv->ioaddr); |
1077 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
1078 | } |
1079 | ||
1080 | if (priv->phydev) | |
1081 | phy_start(priv->phydev); | |
1082 | ||
1083 | napi_enable(&priv->napi); | |
1084 | skb_queue_head_init(&priv->rx_recycle); | |
1085 | netif_start_queue(dev); | |
f66ffe28 | 1086 | |
47dd7a54 | 1087 | return 0; |
f66ffe28 GC |
1088 | |
1089 | open_error: | |
1090 | #ifdef CONFIG_STMMAC_TIMER | |
1091 | kfree(priv->tm); | |
1092 | #endif | |
1093 | if (priv->phydev) | |
1094 | phy_disconnect(priv->phydev); | |
1095 | ||
1096 | return ret; | |
47dd7a54 GC |
1097 | } |
1098 | ||
1099 | /** | |
1100 | * stmmac_release - close entry point of the driver | |
1101 | * @dev : device pointer. | |
1102 | * Description: | |
1103 | * This is the stop entry point of the driver. | |
1104 | */ | |
1105 | static int stmmac_release(struct net_device *dev) | |
1106 | { | |
1107 | struct stmmac_priv *priv = netdev_priv(dev); | |
1108 | ||
1109 | /* Stop and disconnect the PHY */ | |
1110 | if (priv->phydev) { | |
1111 | phy_stop(priv->phydev); | |
1112 | phy_disconnect(priv->phydev); | |
1113 | priv->phydev = NULL; | |
1114 | } | |
1115 | ||
1116 | netif_stop_queue(dev); | |
1117 | ||
1118 | #ifdef CONFIG_STMMAC_TIMER | |
1119 | /* Stop and release the timer */ | |
1120 | stmmac_close_ext_timer(); | |
1121 | if (priv->tm != NULL) | |
1122 | kfree(priv->tm); | |
1123 | #endif | |
1124 | napi_disable(&priv->napi); | |
1125 | skb_queue_purge(&priv->rx_recycle); | |
1126 | ||
1127 | /* Free the IRQ lines */ | |
1128 | free_irq(dev->irq, dev); | |
1129 | ||
1130 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1131 | priv->hw->dma->stop_tx(priv->ioaddr); |
1132 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1133 | |
1134 | /* Release and free the Rx/Tx resources */ | |
1135 | free_dma_desc_resources(priv); | |
1136 | ||
19449bfc | 1137 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1138 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1139 | |
1140 | netif_carrier_off(dev); | |
1141 | ||
bfab27a1 GC |
1142 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1143 | stmmac_exit_fs(); | |
1144 | #endif | |
1145 | stmmac_mdio_unregister(dev); | |
1146 | ||
47dd7a54 GC |
1147 | return 0; |
1148 | } | |
1149 | ||
47dd7a54 GC |
1150 | /** |
1151 | * stmmac_xmit: | |
1152 | * @skb : the socket buffer | |
1153 | * @dev : device pointer | |
1154 | * Description : Tx entry point of the driver. | |
1155 | */ | |
1156 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1157 | { | |
1158 | struct stmmac_priv *priv = netdev_priv(dev); | |
1159 | unsigned int txsize = priv->dma_tx_size; | |
1160 | unsigned int entry; | |
1161 | int i, csum_insertion = 0; | |
1162 | int nfrags = skb_shinfo(skb)->nr_frags; | |
1163 | struct dma_desc *desc, *first; | |
286a8372 | 1164 | unsigned int nopaged_len = skb_headlen(skb); |
47dd7a54 GC |
1165 | |
1166 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1167 | if (!netif_queue_stopped(dev)) { | |
1168 | netif_stop_queue(dev); | |
1169 | /* This is a hard error, log it. */ | |
1170 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
1171 | __func__); | |
1172 | } | |
1173 | return NETDEV_TX_BUSY; | |
1174 | } | |
1175 | ||
a9097a96 GC |
1176 | spin_lock(&priv->tx_lock); |
1177 | ||
47dd7a54 GC |
1178 | entry = priv->cur_tx % txsize; |
1179 | ||
1180 | #ifdef STMMAC_XMIT_DEBUG | |
1181 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1182 | pr_info("stmmac xmit:\n" | |
1183 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1184 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
286a8372 | 1185 | skb, skb->len, nopaged_len, nfrags, skb->ip_summed, |
47dd7a54 GC |
1186 | !skb_is_gso(skb) ? "isn't" : "is"); |
1187 | #endif | |
1188 | ||
5e982f3b | 1189 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1190 | |
1191 | desc = priv->dma_tx + entry; | |
1192 | first = desc; | |
1193 | ||
1194 | #ifdef STMMAC_XMIT_DEBUG | |
1195 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1196 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1197 | "\t\tn_frags: %d, ip_summed: %d\n", | |
286a8372 | 1198 | skb->len, nopaged_len, nfrags, skb->ip_summed); |
47dd7a54 GC |
1199 | #endif |
1200 | priv->tx_skbuff[entry] = skb; | |
286a8372 GC |
1201 | |
1202 | if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { | |
1203 | entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); | |
47dd7a54 GC |
1204 | desc = priv->dma_tx + entry; |
1205 | } else { | |
47dd7a54 GC |
1206 | desc->des2 = dma_map_single(priv->device, skb->data, |
1207 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1208 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1209 | csum_insertion); | |
47dd7a54 GC |
1210 | } |
1211 | ||
1212 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1213 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1214 | int len = skb_frag_size(frag); | |
47dd7a54 GC |
1215 | |
1216 | entry = (++priv->cur_tx) % txsize; | |
1217 | desc = priv->dma_tx + entry; | |
1218 | ||
1219 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
f722380d IC |
1220 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1221 | DMA_TO_DEVICE); | |
47dd7a54 | 1222 | priv->tx_skbuff[entry] = NULL; |
db98a0b0 | 1223 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1224 | wmb(); |
db98a0b0 | 1225 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1226 | } |
1227 | ||
1228 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1229 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1230 | |
47dd7a54 | 1231 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1232 | /* Clean IC while using timer */ |
1233 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1234 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1235 | #endif |
eb0dc4bb SH |
1236 | |
1237 | wmb(); | |
1238 | ||
47dd7a54 | 1239 | /* To avoid raise condition */ |
db98a0b0 | 1240 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1241 | |
1242 | priv->cur_tx++; | |
1243 | ||
1244 | #ifdef STMMAC_XMIT_DEBUG | |
1245 | if (netif_msg_pktdata(priv)) { | |
1246 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1247 | "first=%p, nfrags=%d\n", | |
1248 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1249 | entry, first, nfrags); | |
1250 | display_ring(priv->dma_tx, txsize); | |
1251 | pr_info(">>> frame to be transmitted: "); | |
1252 | print_pkt(skb->data, skb->len); | |
1253 | } | |
1254 | #endif | |
1255 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1256 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1257 | netif_stop_queue(dev); | |
1258 | } | |
1259 | ||
1260 | dev->stats.tx_bytes += skb->len; | |
1261 | ||
3e82ce12 RC |
1262 | skb_tx_timestamp(skb); |
1263 | ||
52f64fae RC |
1264 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1265 | ||
a9097a96 GC |
1266 | spin_unlock(&priv->tx_lock); |
1267 | ||
47dd7a54 GC |
1268 | return NETDEV_TX_OK; |
1269 | } | |
1270 | ||
1271 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1272 | { | |
1273 | unsigned int rxsize = priv->dma_rx_size; | |
1274 | int bfsize = priv->dma_buf_sz; | |
1275 | struct dma_desc *p = priv->dma_rx; | |
1276 | ||
1277 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1278 | unsigned int entry = priv->dirty_rx % rxsize; | |
1279 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1280 | struct sk_buff *skb; | |
1281 | ||
1282 | skb = __skb_dequeue(&priv->rx_recycle); | |
1283 | if (skb == NULL) | |
1284 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1285 | bfsize); | |
1286 | ||
1287 | if (unlikely(skb == NULL)) | |
1288 | break; | |
1289 | ||
1290 | priv->rx_skbuff[entry] = skb; | |
1291 | priv->rx_skbuff_dma[entry] = | |
1292 | dma_map_single(priv->device, skb->data, bfsize, | |
1293 | DMA_FROM_DEVICE); | |
1294 | ||
1295 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
286a8372 GC |
1296 | |
1297 | if (unlikely(priv->plat->has_gmac)) | |
1298 | priv->hw->ring->refill_desc3(bfsize, p + entry); | |
1299 | ||
47dd7a54 GC |
1300 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); |
1301 | } | |
eb0dc4bb | 1302 | wmb(); |
db98a0b0 | 1303 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1304 | } |
47dd7a54 GC |
1305 | } |
1306 | ||
1307 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1308 | { | |
1309 | unsigned int rxsize = priv->dma_rx_size; | |
1310 | unsigned int entry = priv->cur_rx % rxsize; | |
1311 | unsigned int next_entry; | |
1312 | unsigned int count = 0; | |
1313 | struct dma_desc *p = priv->dma_rx + entry; | |
1314 | struct dma_desc *p_next; | |
1315 | ||
1316 | #ifdef STMMAC_RX_DEBUG | |
1317 | if (netif_msg_hw(priv)) { | |
1318 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1319 | display_ring(priv->dma_rx, rxsize); | |
1320 | } | |
1321 | #endif | |
1322 | count = 0; | |
db98a0b0 | 1323 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1324 | int status; |
1325 | ||
1326 | if (count >= limit) | |
1327 | break; | |
1328 | ||
1329 | count++; | |
1330 | ||
1331 | next_entry = (++priv->cur_rx) % rxsize; | |
1332 | p_next = priv->dma_rx + next_entry; | |
1333 | prefetch(p_next); | |
1334 | ||
1335 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1336 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1337 | &priv->xstats, p)); | |
47dd7a54 GC |
1338 | if (unlikely(status == discard_frame)) |
1339 | priv->dev->stats.rx_errors++; | |
1340 | else { | |
1341 | struct sk_buff *skb; | |
3eeb2997 | 1342 | int frame_len; |
47dd7a54 | 1343 | |
3eeb2997 GC |
1344 | frame_len = priv->hw->desc->get_rx_frame_len(p); |
1345 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 | |
1346 | * Type frames (LLC/LLC-SNAP) */ | |
1347 | if (unlikely(status != llc_snap)) | |
1348 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1349 | #ifdef STMMAC_RX_DEBUG |
1350 | if (frame_len > ETH_FRAME_LEN) | |
1351 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1352 | frame_len, status); | |
1353 | ||
1354 | if (netif_msg_hw(priv)) | |
1355 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1356 | p, entry, p->des2); | |
1357 | #endif | |
1358 | skb = priv->rx_skbuff[entry]; | |
1359 | if (unlikely(!skb)) { | |
1360 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1361 | priv->dev->name); | |
1362 | priv->dev->stats.rx_dropped++; | |
1363 | break; | |
1364 | } | |
1365 | prefetch(skb->data - NET_IP_ALIGN); | |
1366 | priv->rx_skbuff[entry] = NULL; | |
1367 | ||
1368 | skb_put(skb, frame_len); | |
1369 | dma_unmap_single(priv->device, | |
1370 | priv->rx_skbuff_dma[entry], | |
1371 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1372 | #ifdef STMMAC_RX_DEBUG | |
1373 | if (netif_msg_pktdata(priv)) { | |
1374 | pr_info(" frame received (%dbytes)", frame_len); | |
1375 | print_pkt(skb->data, frame_len); | |
1376 | } | |
1377 | #endif | |
1378 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1379 | ||
3c20f72f GC |
1380 | if (unlikely(!priv->rx_coe)) { |
1381 | /* No RX COE for old mac10/100 devices */ | |
bc8acf2c | 1382 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1383 | netif_receive_skb(skb); |
1384 | } else { | |
1385 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1386 | napi_gro_receive(&priv->napi, skb); | |
1387 | } | |
1388 | ||
1389 | priv->dev->stats.rx_packets++; | |
1390 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1391 | } |
1392 | entry = next_entry; | |
1393 | p = p_next; /* use prefetched values */ | |
1394 | } | |
1395 | ||
1396 | stmmac_rx_refill(priv); | |
1397 | ||
1398 | priv->xstats.rx_pkt_n += count; | |
1399 | ||
1400 | return count; | |
1401 | } | |
1402 | ||
1403 | /** | |
1404 | * stmmac_poll - stmmac poll method (NAPI) | |
1405 | * @napi : pointer to the napi structure. | |
1406 | * @budget : maximum number of packets that the current CPU can receive from | |
1407 | * all interfaces. | |
1408 | * Description : | |
1409 | * This function implements the the reception process. | |
1410 | * Also it runs the TX completion thread | |
1411 | */ | |
1412 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1413 | { | |
1414 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1415 | int work_done = 0; | |
1416 | ||
1417 | priv->xstats.poll_n++; | |
1418 | stmmac_tx(priv); | |
1419 | work_done = stmmac_rx(priv, budget); | |
1420 | ||
1421 | if (work_done < budget) { | |
1422 | napi_complete(napi); | |
1423 | stmmac_enable_irq(priv); | |
1424 | } | |
1425 | return work_done; | |
1426 | } | |
1427 | ||
1428 | /** | |
1429 | * stmmac_tx_timeout | |
1430 | * @dev : Pointer to net device structure | |
1431 | * Description: this function is called when a packet transmission fails to | |
1432 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1433 | * netdev structure and arrange for the device to be reset to a sane state | |
1434 | * in order to transmit a new packet. | |
1435 | */ | |
1436 | static void stmmac_tx_timeout(struct net_device *dev) | |
1437 | { | |
1438 | struct stmmac_priv *priv = netdev_priv(dev); | |
1439 | ||
1440 | /* Clear Tx resources and restart transmitting again */ | |
1441 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1442 | } |
1443 | ||
1444 | /* Configuration changes (passed on by ifconfig) */ | |
1445 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1446 | { | |
1447 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1448 | return -EBUSY; | |
1449 | ||
1450 | /* Don't allow changing the I/O address */ | |
1451 | if (map->base_addr != dev->base_addr) { | |
1452 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1453 | return -EOPNOTSUPP; | |
1454 | } | |
1455 | ||
1456 | /* Don't allow changing the IRQ */ | |
1457 | if (map->irq != dev->irq) { | |
1458 | pr_warning("%s: can't change IRQ number %d\n", | |
1459 | dev->name, dev->irq); | |
1460 | return -EOPNOTSUPP; | |
1461 | } | |
1462 | ||
1463 | /* ignore other fields */ | |
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | /** | |
01789349 | 1468 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
1469 | * @dev : pointer to the device structure |
1470 | * Description: | |
1471 | * This function is a driver entry point which gets called by the kernel | |
1472 | * whenever multicast addresses must be enabled/disabled. | |
1473 | * Return value: | |
1474 | * void. | |
1475 | */ | |
01789349 | 1476 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
1477 | { |
1478 | struct stmmac_priv *priv = netdev_priv(dev); | |
1479 | ||
1480 | spin_lock(&priv->lock); | |
db98a0b0 | 1481 | priv->hw->mac->set_filter(dev); |
47dd7a54 | 1482 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1483 | } |
1484 | ||
1485 | /** | |
1486 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1487 | * @dev : device pointer. | |
1488 | * @new_mtu : the new MTU size for the device. | |
1489 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1490 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1491 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1492 | * Return value: | |
1493 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1494 | * file on failure. | |
1495 | */ | |
1496 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1497 | { | |
1498 | struct stmmac_priv *priv = netdev_priv(dev); | |
1499 | int max_mtu; | |
1500 | ||
1501 | if (netif_running(dev)) { | |
1502 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1503 | return -EBUSY; | |
1504 | } | |
1505 | ||
48febf7e | 1506 | if (priv->plat->enh_desc) |
47dd7a54 GC |
1507 | max_mtu = JUMBO_LEN; |
1508 | else | |
45db81e1 | 1509 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 GC |
1510 | |
1511 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1512 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1513 | return -EINVAL; | |
1514 | } | |
1515 | ||
5e982f3b MM |
1516 | dev->mtu = new_mtu; |
1517 | netdev_update_features(dev); | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
c8f44aff MM |
1522 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
1523 | netdev_features_t features) | |
5e982f3b MM |
1524 | { |
1525 | struct stmmac_priv *priv = netdev_priv(dev); | |
1526 | ||
1527 | if (!priv->rx_coe) | |
1528 | features &= ~NETIF_F_RXCSUM; | |
1529 | if (!priv->plat->tx_coe) | |
1530 | features &= ~NETIF_F_ALL_CSUM; | |
1531 | ||
ebbb293f GC |
1532 | /* Some GMAC devices have a bugged Jumbo frame support that |
1533 | * needs to have the Tx COE disabled for oversized frames | |
1534 | * (due to limited buffer sizes). In this case we disable | |
1535 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1536 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1537 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1538 | |
5e982f3b | 1539 | return features; |
47dd7a54 GC |
1540 | } |
1541 | ||
1542 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1543 | { | |
1544 | struct net_device *dev = (struct net_device *)dev_id; | |
1545 | struct stmmac_priv *priv = netdev_priv(dev); | |
1546 | ||
1547 | if (unlikely(!dev)) { | |
1548 | pr_err("%s: invalid dev pointer\n", __func__); | |
1549 | return IRQ_NONE; | |
1550 | } | |
1551 | ||
9dfeb4d9 | 1552 | if (priv->plat->has_gmac) |
47dd7a54 | 1553 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1554 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1555 | |
1556 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1557 | |
1558 | return IRQ_HANDLED; | |
1559 | } | |
1560 | ||
1561 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1562 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1563 | * to allow network I/O with interrupts disabled. */ | |
1564 | static void stmmac_poll_controller(struct net_device *dev) | |
1565 | { | |
1566 | disable_irq(dev->irq); | |
1567 | stmmac_interrupt(dev->irq, dev); | |
1568 | enable_irq(dev->irq); | |
1569 | } | |
1570 | #endif | |
1571 | ||
1572 | /** | |
1573 | * stmmac_ioctl - Entry point for the Ioctl | |
1574 | * @dev: Device pointer. | |
1575 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1576 | * a proprietary structure used to pass information to the driver. | |
1577 | * @cmd: IOCTL command | |
1578 | * Description: | |
1579 | * Currently there are no special functionality supported in IOCTL, just the | |
1580 | * phy_mii_ioctl(...) can be invoked. | |
1581 | */ | |
1582 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1583 | { | |
1584 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1585 | int ret; |
47dd7a54 GC |
1586 | |
1587 | if (!netif_running(dev)) | |
1588 | return -EINVAL; | |
1589 | ||
28b04113 RC |
1590 | if (!priv->phydev) |
1591 | return -EINVAL; | |
1592 | ||
28b04113 | 1593 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); |
28b04113 | 1594 | |
47dd7a54 GC |
1595 | return ret; |
1596 | } | |
1597 | ||
7ac29055 GC |
1598 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1599 | static struct dentry *stmmac_fs_dir; | |
1600 | static struct dentry *stmmac_rings_status; | |
e7434821 | 1601 | static struct dentry *stmmac_dma_cap; |
7ac29055 GC |
1602 | |
1603 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) | |
1604 | { | |
1605 | struct tmp_s { | |
1606 | u64 a; | |
1607 | unsigned int b; | |
1608 | unsigned int c; | |
1609 | }; | |
1610 | int i; | |
1611 | struct net_device *dev = seq->private; | |
1612 | struct stmmac_priv *priv = netdev_priv(dev); | |
1613 | ||
1614 | seq_printf(seq, "=======================\n"); | |
1615 | seq_printf(seq, " RX descriptor ring\n"); | |
1616 | seq_printf(seq, "=======================\n"); | |
1617 | ||
1618 | for (i = 0; i < priv->dma_rx_size; i++) { | |
1619 | struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); | |
1620 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1621 | i, (unsigned int)(x->a), | |
1622 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1623 | seq_printf(seq, "\n"); | |
1624 | } | |
1625 | ||
1626 | seq_printf(seq, "\n"); | |
1627 | seq_printf(seq, "=======================\n"); | |
1628 | seq_printf(seq, " TX descriptor ring\n"); | |
1629 | seq_printf(seq, "=======================\n"); | |
1630 | ||
1631 | for (i = 0; i < priv->dma_tx_size; i++) { | |
1632 | struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); | |
1633 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1634 | i, (unsigned int)(x->a), | |
1635 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1636 | seq_printf(seq, "\n"); | |
1637 | } | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
1643 | { | |
1644 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
1645 | } | |
1646 | ||
1647 | static const struct file_operations stmmac_rings_status_fops = { | |
1648 | .owner = THIS_MODULE, | |
1649 | .open = stmmac_sysfs_ring_open, | |
1650 | .read = seq_read, | |
1651 | .llseek = seq_lseek, | |
1652 | .release = seq_release, | |
1653 | }; | |
1654 | ||
e7434821 GC |
1655 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
1656 | { | |
1657 | struct net_device *dev = seq->private; | |
1658 | struct stmmac_priv *priv = netdev_priv(dev); | |
1659 | ||
19e30c14 | 1660 | if (!priv->hw_cap_support) { |
e7434821 GC |
1661 | seq_printf(seq, "DMA HW features not supported\n"); |
1662 | return 0; | |
1663 | } | |
1664 | ||
1665 | seq_printf(seq, "==============================\n"); | |
1666 | seq_printf(seq, "\tDMA HW features\n"); | |
1667 | seq_printf(seq, "==============================\n"); | |
1668 | ||
1669 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
1670 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
1671 | seq_printf(seq, "\t1000 Mbps %s\n", | |
1672 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
1673 | seq_printf(seq, "\tHalf duple %s\n", | |
1674 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
1675 | seq_printf(seq, "\tHash Filter: %s\n", | |
1676 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
1677 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
1678 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
1679 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
1680 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
1681 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
1682 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
1683 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
1684 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
1685 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
1686 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
1687 | seq_printf(seq, "\tRMON module: %s\n", | |
1688 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
1689 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
1690 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
1691 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
1692 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
1693 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
1694 | (priv->dma_cap.eee) ? "Y" : "N"); | |
1695 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
1696 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
1697 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
1698 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
1699 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
1700 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
1701 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
1702 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
1703 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
1704 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
1705 | priv->dma_cap.number_rx_channel); | |
1706 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
1707 | priv->dma_cap.number_tx_channel); | |
1708 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
1709 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
1710 | ||
1711 | return 0; | |
1712 | } | |
1713 | ||
1714 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
1715 | { | |
1716 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
1717 | } | |
1718 | ||
1719 | static const struct file_operations stmmac_dma_cap_fops = { | |
1720 | .owner = THIS_MODULE, | |
1721 | .open = stmmac_sysfs_dma_cap_open, | |
1722 | .read = seq_read, | |
1723 | .llseek = seq_lseek, | |
1724 | .release = seq_release, | |
1725 | }; | |
1726 | ||
7ac29055 GC |
1727 | static int stmmac_init_fs(struct net_device *dev) |
1728 | { | |
1729 | /* Create debugfs entries */ | |
1730 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
1731 | ||
1732 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
1733 | pr_err("ERROR %s, debugfs create directory failed\n", | |
1734 | STMMAC_RESOURCE_NAME); | |
1735 | ||
1736 | return -ENOMEM; | |
1737 | } | |
1738 | ||
1739 | /* Entry to report DMA RX/TX rings */ | |
1740 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
1741 | S_IRUGO, stmmac_fs_dir, dev, | |
1742 | &stmmac_rings_status_fops); | |
1743 | ||
1744 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
1745 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
1746 | debugfs_remove(stmmac_fs_dir); | |
1747 | ||
1748 | return -ENOMEM; | |
1749 | } | |
1750 | ||
e7434821 GC |
1751 | /* Entry to report the DMA HW features */ |
1752 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
1753 | dev, &stmmac_dma_cap_fops); | |
1754 | ||
1755 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
1756 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
1757 | debugfs_remove(stmmac_rings_status); | |
1758 | debugfs_remove(stmmac_fs_dir); | |
1759 | ||
1760 | return -ENOMEM; | |
1761 | } | |
1762 | ||
7ac29055 GC |
1763 | return 0; |
1764 | } | |
1765 | ||
1766 | static void stmmac_exit_fs(void) | |
1767 | { | |
1768 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 1769 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
1770 | debugfs_remove(stmmac_fs_dir); |
1771 | } | |
1772 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
1773 | ||
47dd7a54 GC |
1774 | static const struct net_device_ops stmmac_netdev_ops = { |
1775 | .ndo_open = stmmac_open, | |
1776 | .ndo_start_xmit = stmmac_xmit, | |
1777 | .ndo_stop = stmmac_release, | |
1778 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1779 | .ndo_fix_features = stmmac_fix_features, |
01789349 | 1780 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
1781 | .ndo_tx_timeout = stmmac_tx_timeout, |
1782 | .ndo_do_ioctl = stmmac_ioctl, | |
1783 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1784 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1785 | .ndo_poll_controller = stmmac_poll_controller, | |
1786 | #endif | |
1787 | .ndo_set_mac_address = eth_mac_addr, | |
1788 | }; | |
1789 | ||
1790 | /** | |
bfab27a1 GC |
1791 | * stmmac_dvr_probe |
1792 | * @device: device pointer | |
1793 | * Description: this is the main probe function used to | |
1794 | * call the alloc_etherdev, allocate the priv structure. | |
47dd7a54 | 1795 | */ |
bfab27a1 GC |
1796 | struct stmmac_priv *stmmac_dvr_probe(struct device *device, |
1797 | struct plat_stmmacenet_data *plat_dat) | |
47dd7a54 GC |
1798 | { |
1799 | int ret = 0; | |
bfab27a1 GC |
1800 | struct net_device *ndev = NULL; |
1801 | struct stmmac_priv *priv; | |
47dd7a54 | 1802 | |
bfab27a1 | 1803 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 1804 | if (!ndev) |
bfab27a1 | 1805 | return NULL; |
bfab27a1 GC |
1806 | |
1807 | SET_NETDEV_DEV(ndev, device); | |
1808 | ||
1809 | priv = netdev_priv(ndev); | |
1810 | priv->device = device; | |
1811 | priv->dev = ndev; | |
47dd7a54 | 1812 | |
bfab27a1 | 1813 | ether_setup(ndev); |
47dd7a54 | 1814 | |
bfab27a1 GC |
1815 | ndev->netdev_ops = &stmmac_netdev_ops; |
1816 | stmmac_set_ethtool_ops(ndev); | |
1817 | ||
1818 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
1819 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; | |
1820 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
1821 | #ifdef STMMAC_VLAN_TAG_USED |
1822 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
bfab27a1 | 1823 | ndev->features |= NETIF_F_HW_VLAN_RX; |
47dd7a54 GC |
1824 | #endif |
1825 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1826 | ||
47dd7a54 GC |
1827 | if (flow_ctrl) |
1828 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1829 | ||
1830 | priv->pause = pause; | |
bfab27a1 GC |
1831 | priv->plat = plat_dat; |
1832 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); | |
47dd7a54 | 1833 | |
f8e96161 | 1834 | spin_lock_init(&priv->lock); |
a9097a96 | 1835 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 1836 | |
bfab27a1 | 1837 | ret = register_netdev(ndev); |
47dd7a54 GC |
1838 | if (ret) { |
1839 | pr_err("%s: ERROR %i registering the device\n", | |
1840 | __func__, ret); | |
bfab27a1 | 1841 | goto error; |
47dd7a54 GC |
1842 | } |
1843 | ||
1844 | DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n", | |
bfab27a1 GC |
1845 | ndev->name, (ndev->features & NETIF_F_SG) ? "on" : "off", |
1846 | (ndev->features & NETIF_F_IP_CSUM) ? "on" : "off"); | |
47dd7a54 | 1847 | |
bfab27a1 | 1848 | return priv; |
47dd7a54 | 1849 | |
bfab27a1 GC |
1850 | error: |
1851 | netif_napi_del(&priv->napi); | |
47dd7a54 | 1852 | |
34a52f36 | 1853 | unregister_netdev(ndev); |
34a52f36 | 1854 | free_netdev(ndev); |
47dd7a54 | 1855 | |
bfab27a1 | 1856 | return NULL; |
47dd7a54 GC |
1857 | } |
1858 | ||
1859 | /** | |
1860 | * stmmac_dvr_remove | |
bfab27a1 | 1861 | * @ndev: net device pointer |
47dd7a54 | 1862 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 1863 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 1864 | */ |
bfab27a1 | 1865 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 1866 | { |
aec7ff27 | 1867 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1868 | |
1869 | pr_info("%s:\n\tremoving driver", __func__); | |
1870 | ||
ad01b7d4 GC |
1871 | priv->hw->dma->stop_rx(priv->ioaddr); |
1872 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1873 | |
bfab27a1 | 1874 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 | 1875 | netif_carrier_off(ndev); |
47dd7a54 | 1876 | unregister_netdev(ndev); |
47dd7a54 GC |
1877 | free_netdev(ndev); |
1878 | ||
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | #ifdef CONFIG_PM | |
bfab27a1 | 1883 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 1884 | { |
874bd42d | 1885 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1886 | int dis_ic = 0; |
1887 | ||
874bd42d | 1888 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
1889 | return 0; |
1890 | ||
102463b1 FV |
1891 | if (priv->phydev) |
1892 | phy_stop(priv->phydev); | |
1893 | ||
47dd7a54 GC |
1894 | spin_lock(&priv->lock); |
1895 | ||
874bd42d GC |
1896 | netif_device_detach(ndev); |
1897 | netif_stop_queue(ndev); | |
47dd7a54 GC |
1898 | |
1899 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1900 | priv->tm->timer_stop(); |
1901 | if (likely(priv->tm->enable)) | |
1902 | dis_ic = 1; | |
47dd7a54 | 1903 | #endif |
874bd42d GC |
1904 | napi_disable(&priv->napi); |
1905 | ||
1906 | /* Stop TX/RX DMA */ | |
1907 | priv->hw->dma->stop_tx(priv->ioaddr); | |
1908 | priv->hw->dma->stop_rx(priv->ioaddr); | |
1909 | /* Clear the Rx/Tx descriptors */ | |
1910 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
1911 | dis_ic); | |
1912 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
1913 | ||
1914 | /* Enable Power down mode by programming the PMT regs */ | |
1915 | if (device_may_wakeup(priv->device)) | |
1916 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
1917 | else | |
bfab27a1 | 1918 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1919 | |
1920 | spin_unlock(&priv->lock); | |
1921 | return 0; | |
1922 | } | |
1923 | ||
bfab27a1 | 1924 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 1925 | { |
874bd42d | 1926 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 | 1927 | |
874bd42d | 1928 | if (!netif_running(ndev)) |
47dd7a54 GC |
1929 | return 0; |
1930 | ||
c4433be6 GC |
1931 | spin_lock(&priv->lock); |
1932 | ||
47dd7a54 GC |
1933 | /* Power Down bit, into the PM register, is cleared |
1934 | * automatically as soon as a magic packet or a Wake-up frame | |
1935 | * is received. Anyway, it's better to manually clear | |
1936 | * this bit because it can generate problems while resuming | |
1937 | * from another devices (e.g. serial console). */ | |
874bd42d | 1938 | if (device_may_wakeup(priv->device)) |
543876c9 | 1939 | priv->hw->mac->pmt(priv->ioaddr, 0); |
47dd7a54 | 1940 | |
874bd42d | 1941 | netif_device_attach(ndev); |
47dd7a54 GC |
1942 | |
1943 | /* Enable the MAC and DMA */ | |
bfab27a1 | 1944 | stmmac_set_mac(priv->ioaddr, true); |
ad01b7d4 GC |
1945 | priv->hw->dma->start_tx(priv->ioaddr); |
1946 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1947 | |
1948 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1949 | if (likely(priv->tm->enable)) |
1950 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
1951 | #endif |
1952 | napi_enable(&priv->napi); | |
1953 | ||
874bd42d | 1954 | netif_start_queue(ndev); |
47dd7a54 | 1955 | |
47dd7a54 | 1956 | spin_unlock(&priv->lock); |
102463b1 FV |
1957 | |
1958 | if (priv->phydev) | |
1959 | phy_start(priv->phydev); | |
1960 | ||
47dd7a54 GC |
1961 | return 0; |
1962 | } | |
47dd7a54 | 1963 | |
bfab27a1 | 1964 | int stmmac_freeze(struct net_device *ndev) |
874bd42d | 1965 | { |
874bd42d GC |
1966 | if (!ndev || !netif_running(ndev)) |
1967 | return 0; | |
1968 | ||
1969 | return stmmac_release(ndev); | |
1970 | } | |
1971 | ||
bfab27a1 | 1972 | int stmmac_restore(struct net_device *ndev) |
874bd42d | 1973 | { |
874bd42d GC |
1974 | if (!ndev || !netif_running(ndev)) |
1975 | return 0; | |
1976 | ||
1977 | return stmmac_open(ndev); | |
1978 | } | |
874bd42d | 1979 | #endif /* CONFIG_PM */ |
47dd7a54 | 1980 | |
47dd7a54 GC |
1981 | #ifndef MODULE |
1982 | static int __init stmmac_cmdline_opt(char *str) | |
1983 | { | |
1984 | char *opt; | |
1985 | ||
1986 | if (!str || !*str) | |
1987 | return -EINVAL; | |
1988 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 GC |
1989 | if (!strncmp(opt, "debug:", 6)) { |
1990 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) | |
1991 | goto err; | |
1992 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
1993 | if (strict_strtoul(opt + 8, 0, | |
1994 | (unsigned long *)&phyaddr)) | |
1995 | goto err; | |
1996 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
1997 | if (strict_strtoul(opt + 11, 0, | |
1998 | (unsigned long *)&dma_txsize)) | |
1999 | goto err; | |
2000 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
2001 | if (strict_strtoul(opt + 11, 0, | |
2002 | (unsigned long *)&dma_rxsize)) | |
2003 | goto err; | |
2004 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
2005 | if (strict_strtoul(opt + 7, 0, | |
2006 | (unsigned long *)&buf_sz)) | |
2007 | goto err; | |
2008 | } else if (!strncmp(opt, "tc:", 3)) { | |
2009 | if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) | |
2010 | goto err; | |
2011 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
2012 | if (strict_strtoul(opt + 9, 0, | |
2013 | (unsigned long *)&watchdog)) | |
2014 | goto err; | |
2015 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
2016 | if (strict_strtoul(opt + 10, 0, | |
2017 | (unsigned long *)&flow_ctrl)) | |
2018 | goto err; | |
2019 | } else if (!strncmp(opt, "pause:", 6)) { | |
2020 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) | |
2021 | goto err; | |
47dd7a54 | 2022 | #ifdef CONFIG_STMMAC_TIMER |
f3240e28 GC |
2023 | } else if (!strncmp(opt, "tmrate:", 7)) { |
2024 | if (strict_strtoul(opt + 7, 0, | |
2025 | (unsigned long *)&tmrate)) | |
2026 | goto err; | |
47dd7a54 | 2027 | #endif |
f3240e28 | 2028 | } |
47dd7a54 GC |
2029 | } |
2030 | return 0; | |
f3240e28 GC |
2031 | |
2032 | err: | |
2033 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
2034 | return -EINVAL; | |
47dd7a54 GC |
2035 | } |
2036 | ||
2037 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
2038 | #endif | |
6fc0d0f2 GC |
2039 | |
2040 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); | |
2041 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
2042 | MODULE_LICENSE("GPL"); |