projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
stmmac: update the driver version and doc (V4)
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
01789349 45#include <linux/if.h>
47dd7a54
GC		 46#include <linux/if_vlan.h>
47#include <linux/dma-mapping.h>
5a0e3ad6 48#include <linux/slab.h>
70c71606 49#include <linux/prefetch.h>
47dd7a54 50#include "stmmac.h"
7ac29055
GC		 51#ifdef CONFIG_STMMAC_DEBUG_FS
52#include <linux/debugfs.h>
53#include <linux/seq_file.h>
54#endif
47dd7a54
GC		 55
56#define STMMAC_RESOURCE_NAME "stmmaceth"
47dd7a54
GC		 57
58#undef STMMAC_DEBUG
59/*#define STMMAC_DEBUG*/
60#ifdef STMMAC_DEBUG
61#define DBG(nlevel, klevel, fmt, args...) \
62 ((void)(netif_msg_##nlevel(priv) && \
63 printk(KERN_##klevel fmt, ## args)))
64#else
65#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
66#endif
67
68#undef STMMAC_RX_DEBUG
69/*#define STMMAC_RX_DEBUG*/
70#ifdef STMMAC_RX_DEBUG
71#define RX_DBG(fmt, args...) printk(fmt, ## args)
72#else
73#define RX_DBG(fmt, args...) do { } while (0)
74#endif
75
76#undef STMMAC_XMIT_DEBUG
77/*#define STMMAC_XMIT_DEBUG*/
78#ifdef STMMAC_TX_DEBUG
79#define TX_DBG(fmt, args...) printk(fmt, ## args)
80#else
81#define TX_DBG(fmt, args...) do { } while (0)
82#endif
83
84#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
85#define JUMBO_LEN 9000
86
87/* Module parameters */
88#define TX_TIMEO 5000 /* default 5 seconds */
89static int watchdog = TX_TIMEO;
90module_param(watchdog, int, S_IRUGO | S_IWUSR);
91MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
92
93static int debug = -1; /* -1: default, 0: no output, 16: all */
94module_param(debug, int, S_IRUGO | S_IWUSR);
95MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
96
97static int phyaddr = -1;
98module_param(phyaddr, int, S_IRUGO);
99MODULE_PARM_DESC(phyaddr, "Physical device address");
100
101#define DMA_TX_SIZE 256
102static int dma_txsize = DMA_TX_SIZE;
103module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
104MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
105
106#define DMA_RX_SIZE 256
107static int dma_rxsize = DMA_RX_SIZE;
108module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
110
111static int flow_ctrl = FLOW_OFF;
112module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
113MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
114
115static int pause = PAUSE_TIME;
116module_param(pause, int, S_IRUGO | S_IWUSR);
117MODULE_PARM_DESC(pause, "Flow Control Pause Time");
118
119#define TC_DEFAULT 64
120static int tc = TC_DEFAULT;
121module_param(tc, int, S_IRUGO | S_IWUSR);
122MODULE_PARM_DESC(tc, "DMA threshold control value");
123
47dd7a54
GC		 124/* Pay attention to tune this parameter; take care of both
125 * hardware capability and network stabitily/performance impact.
126 * Many tests showed that ~4ms latency seems to be good enough. */
127#ifdef CONFIG_STMMAC_TIMER
128#define DEFAULT_PERIODIC_RATE 256
129static int tmrate = DEFAULT_PERIODIC_RATE;
130module_param(tmrate, int, S_IRUGO | S_IWUSR);
131MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
132#endif
133
134#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
135static int buf_sz = DMA_BUFFER_SIZE;
136module_param(buf_sz, int, S_IRUGO | S_IWUSR);
137MODULE_PARM_DESC(buf_sz, "DMA buffer size");
138
47dd7a54
GC		 139static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
140 NETIF_MSG_LINK | NETIF_MSG_IFUP |
141 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
142
143static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54
GC		 144
145/**
146 * stmmac_verify_args - verify the driver parameters.
147 * Description: it verifies if some wrong parameter is passed to the driver.
148 * Note that wrong parameters are replaced with the default values.
149 */
150static void stmmac_verify_args(void)
151{
152 if (unlikely(watchdog < 0))
153 watchdog = TX_TIMEO;
154 if (unlikely(dma_rxsize < 0))
155 dma_rxsize = DMA_RX_SIZE;
156 if (unlikely(dma_txsize < 0))
157 dma_txsize = DMA_TX_SIZE;
158 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
159 buf_sz = DMA_BUFFER_SIZE;
160 if (unlikely(flow_ctrl > 1))
161 flow_ctrl = FLOW_AUTO;
162 else if (likely(flow_ctrl < 0))
163 flow_ctrl = FLOW_OFF;
164 if (unlikely((pause < 0) || (pause > 0xffff)))
165 pause = PAUSE_TIME;
47dd7a54
GC		 166}
167
168#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
169static void print_pkt(unsigned char *buf, int len)
170{
171 int j;
172 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
173 for (j = 0; j < len; j++) {
174 if ((j % 16) == 0)
175 pr_info("\n %03x:", j);
176 pr_info(" %02x", buf[j]);
177 }
178 pr_info("\n");
47dd7a54
GC		 179}
180#endif
181
182/* minimum number of free TX descriptors required to wake up TX process */
183#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
184
185static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
186{
187 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
188}
189
9dfeb4d9
GC		 190/* On some ST platforms, some HW system configuraton registers have to be
191 * set according to the link speed negotiated.
192 */
193static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
194{
195 struct phy_device *phydev = priv->phydev;
196
197 if (likely(priv->plat->fix_mac_speed))
198 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
199 phydev->speed);
200}
201
47dd7a54
GC		 202/**
203 * stmmac_adjust_link
204 * @dev: net device structure
205 * Description: it adjusts the link parameters.
206 */
207static void stmmac_adjust_link(struct net_device *dev)
208{
209 struct stmmac_priv *priv = netdev_priv(dev);
210 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 211 unsigned long flags;
212 int new_state = 0;
213 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
214
215 if (phydev == NULL)
216 return;
217
218 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
219 phydev->addr, phydev->link);
220
221 spin_lock_irqsave(&priv->lock, flags);
222 if (phydev->link) {
ad01b7d4 223 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 224
225 /* Now we make sure that we can be in full duplex mode.
226 * If not, we operate in half-duplex mode. */
227 if (phydev->duplex != priv->oldduplex) {
228 new_state = 1;
229 if (!(phydev->duplex))
db98a0b0 230 ctrl &= ~priv->hw->link.duplex;
47dd7a54 231 else
db98a0b0 232 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 233 priv->oldduplex = phydev->duplex;
234 }
235 /* Flow Control operation */
236 if (phydev->pause)
ad01b7d4 237 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 238 fc, pause_time);
47dd7a54
GC		 239
240 if (phydev->speed != priv->speed) {
241 new_state = 1;
242 switch (phydev->speed) {
243 case 1000:
9dfeb4d9 244 if (likely(priv->plat->has_gmac))
db98a0b0 245 ctrl &= ~priv->hw->link.port;
9dfeb4d9 246 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 247 break;
248 case 100:
249 case 10:
9dfeb4d9 250 if (priv->plat->has_gmac) {
db98a0b0 251 ctrl |= priv->hw->link.port;
47dd7a54 252 if (phydev->speed == SPEED_100) {
db98a0b0 253 ctrl |= priv->hw->link.speed;
47dd7a54 254 } else {
db98a0b0 255 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 256 }
257 } else {
db98a0b0 258 ctrl &= ~priv->hw->link.port;
47dd7a54 259 }
9dfeb4d9 260 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 261 break;
262 default:
263 if (netif_msg_link(priv))
264 pr_warning("%s: Speed (%d) is not 10"
265 " or 100!\n", dev->name, phydev->speed);
266 break;
267 }
268
269 priv->speed = phydev->speed;
270 }
271
ad01b7d4 272 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 273
274 if (!priv->oldlink) {
275 new_state = 1;
276 priv->oldlink = 1;
277 }
278 } else if (priv->oldlink) {
279 new_state = 1;
280 priv->oldlink = 0;
281 priv->speed = 0;
282 priv->oldduplex = -1;
283 }
284
285 if (new_state && netif_msg_link(priv))
286 phy_print_status(phydev);
287
288 spin_unlock_irqrestore(&priv->lock, flags);
289
290 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
291}
292
293/**
294 * stmmac_init_phy - PHY initialization
295 * @dev: net device structure
296 * Description: it initializes the driver's PHY state, and attaches the PHY
297 * to the mac driver.
298 * Return value:
299 * 0 on success
300 */
301static int stmmac_init_phy(struct net_device *dev)
302{
303 struct stmmac_priv *priv = netdev_priv(dev);
304 struct phy_device *phydev;
109cdd66
GC		 305 char phy_id[MII_BUS_ID_SIZE + 3];
306 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 307 int interface = priv->plat->interface;
47dd7a54
GC		 308 priv->oldlink = 0;
309 priv->speed = 0;
310 priv->oldduplex = -1;
311
9dfeb4d9 312 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
109cdd66 313 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 314 priv->plat->phy_addr);
47dd7a54
GC		 315 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
316
79ee1dc3 317 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
47dd7a54
GC		 318
319 if (IS_ERR(phydev)) {
320 pr_err("%s: Could not attach to PHY\n", dev->name);
321 return PTR_ERR(phydev);
322 }
323
79ee1dc3
SK		 324 /* Stop Advertising 1000BASE Capability if interface is not GMII */
325 if ((interface) && ((interface == PHY_INTERFACE_MODE_MII) ||
326 (interface == PHY_INTERFACE_MODE_RMII))) {
327 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
328 SUPPORTED_Asym_Pause);
329 priv->phydev->advertising = priv->phydev->supported;
330 }
331
47dd7a54
GC		 332 /*
333 * Broken HW is sometimes missing the pull-up resistor on the
334 * MDIO line, which results in reads to non-existent devices returning
335 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
336 * device as well.
337 * Note: phydev->phy_id is the result of reading the UID PHY registers.
338 */
339 if (phydev->phy_id == 0) {
340 phy_disconnect(phydev);
341 return -ENODEV;
342 }
343 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 344 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 345
346 priv->phydev = phydev;
347
348 return 0;
349}
350
19449bfc 351static inline void stmmac_enable_mac(void __iomem *ioaddr)
47dd7a54
GC		 352{
353 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 354
19449bfc 355 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
47dd7a54
GC		 356 writel(value, ioaddr + MAC_CTRL_REG);
357}
358
19449bfc 359static inline void stmmac_disable_mac(void __iomem *ioaddr)
47dd7a54
GC		 360{
361 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 362
19449bfc 363 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
47dd7a54
GC		 364 writel(value, ioaddr + MAC_CTRL_REG);
365}
366
367/**
368 * display_ring
369 * @p: pointer to the ring.
370 * @size: size of the ring.
371 * Description: display all the descriptors within the ring.
372 */
373static void display_ring(struct dma_desc *p, int size)
374{
375 struct tmp_s {
376 u64 a;
377 unsigned int b;
378 unsigned int c;
379 };
380 int i;
381 for (i = 0; i < size; i++) {
382 struct tmp_s *x = (struct tmp_s *)(p + i);
383 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
384 i, (unsigned int)virt_to_phys(&p[i]),
385 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
386 x->b, x->c);
387 pr_info("\n");
388 }
389}
390
391/**
392 * init_dma_desc_rings - init the RX/TX descriptor rings
393 * @dev: net device structure
394 * Description: this function initializes the DMA RX/TX descriptors
395 * and allocates the socket buffers.
396 */
397static void init_dma_desc_rings(struct net_device *dev)
398{
399 int i;
400 struct stmmac_priv *priv = netdev_priv(dev);
401 struct sk_buff *skb;
402 unsigned int txsize = priv->dma_tx_size;
403 unsigned int rxsize = priv->dma_rx_size;
404 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 405 int buff2_needed = 0, dis_ic = 0;
47dd7a54 406
47dd7a54
GC		 407 /* Set the Buffer size according to the MTU;
408 * indeed, in case of jumbo we need to bump-up the buffer sizes.
409 */
410 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
411 bfsize = BUF_SIZE_16KiB;
412 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
413 bfsize = BUF_SIZE_8KiB;
414 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
415 bfsize = BUF_SIZE_4KiB;
416 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
417 bfsize = BUF_SIZE_2KiB;
418 else
419 bfsize = DMA_BUFFER_SIZE;
420
73cfe264
GC		 421#ifdef CONFIG_STMMAC_TIMER
422 /* Disable interrupts on completion for the reception if timer is on */
423 if (likely(priv->tm->enable))
424 dis_ic = 1;
425#endif
47dd7a54
GC		 426 /* If the MTU exceeds 8k so use the second buffer in the chain */
427 if (bfsize >= BUF_SIZE_8KiB)
428 buff2_needed = 1;
429
430 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
431 txsize, rxsize, bfsize);
432
433 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
434 priv->rx_skbuff =
435 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
436 priv->dma_rx =
437 (struct dma_desc *)dma_alloc_coherent(priv->device,
438 rxsize *
439 sizeof(struct dma_desc),
440 &priv->dma_rx_phy,
441 GFP_KERNEL);
442 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
443 GFP_KERNEL);
444 priv->dma_tx =
445 (struct dma_desc *)dma_alloc_coherent(priv->device,
446 txsize *
447 sizeof(struct dma_desc),
448 &priv->dma_tx_phy,
449 GFP_KERNEL);
450
451 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
452 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
453 return;
454 }
455
456 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
457 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
458 dev->name, priv->dma_rx, priv->dma_tx,
459 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
460
461 /* RX INITIALIZATION */
462 DBG(probe, INFO, "stmmac: SKB addresses:\n"
463 "skb\t\tskb data\tdma data\n");
464
465 for (i = 0; i < rxsize; i++) {
466 struct dma_desc *p = priv->dma_rx + i;
467
468 skb = netdev_alloc_skb_ip_align(dev, bfsize);
469 if (unlikely(skb == NULL)) {
470 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
471 break;
472 }
473 priv->rx_skbuff[i] = skb;
474 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
475 bfsize, DMA_FROM_DEVICE);
476
477 p->des2 = priv->rx_skbuff_dma[i];
478 if (unlikely(buff2_needed))
479 p->des3 = p->des2 + BUF_SIZE_8KiB;
480 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
481 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
482 }
483 priv->cur_rx = 0;
484 priv->dirty_rx = (unsigned int)(i - rxsize);
485 priv->dma_buf_sz = bfsize;
486 buf_sz = bfsize;
487
488 /* TX INITIALIZATION */
489 for (i = 0; i < txsize; i++) {
490 priv->tx_skbuff[i] = NULL;
491 priv->dma_tx[i].des2 = 0;
492 }
493 priv->dirty_tx = 0;
494 priv->cur_tx = 0;
495
496 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 497 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
498 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 499
500 if (netif_msg_hw(priv)) {
501 pr_info("RX descriptor ring:\n");
502 display_ring(priv->dma_rx, rxsize);
503 pr_info("TX descriptor ring:\n");
504 display_ring(priv->dma_tx, txsize);
505 }
47dd7a54
GC		 506}
507
508static void dma_free_rx_skbufs(struct stmmac_priv *priv)
509{
510 int i;
511
512 for (i = 0; i < priv->dma_rx_size; i++) {
513 if (priv->rx_skbuff[i]) {
514 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
515 priv->dma_buf_sz, DMA_FROM_DEVICE);
516 dev_kfree_skb_any(priv->rx_skbuff[i]);
517 }
518 priv->rx_skbuff[i] = NULL;
519 }
47dd7a54
GC		 520}
521
522static void dma_free_tx_skbufs(struct stmmac_priv *priv)
523{
524 int i;
525
526 for (i = 0; i < priv->dma_tx_size; i++) {
527 if (priv->tx_skbuff[i] != NULL) {
528 struct dma_desc *p = priv->dma_tx + i;
529 if (p->des2)
530 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 531 priv->hw->desc->get_tx_len(p),
532 DMA_TO_DEVICE);
47dd7a54
GC		 533 dev_kfree_skb_any(priv->tx_skbuff[i]);
534 priv->tx_skbuff[i] = NULL;
535 }
536 }
47dd7a54
GC		 537}
538
539static void free_dma_desc_resources(struct stmmac_priv *priv)
540{
541 /* Release the DMA TX/RX socket buffers */
542 dma_free_rx_skbufs(priv);
543 dma_free_tx_skbufs(priv);
544
545 /* Free the region of consistent memory previously allocated for
546 * the DMA */
547 dma_free_coherent(priv->device,
548 priv->dma_tx_size * sizeof(struct dma_desc),
549 priv->dma_tx, priv->dma_tx_phy);
550 dma_free_coherent(priv->device,
551 priv->dma_rx_size * sizeof(struct dma_desc),
552 priv->dma_rx, priv->dma_rx_phy);
553 kfree(priv->rx_skbuff_dma);
554 kfree(priv->rx_skbuff);
555 kfree(priv->tx_skbuff);
47dd7a54
GC		 556}
557
47dd7a54
GC		 558/**
559 * stmmac_dma_operation_mode - HW DMA operation mode
560 * @priv : pointer to the private device structure.
561 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 562 * or Store-And-Forward capability.
47dd7a54
GC		 563 */
564static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
565{
61b8013a
SK		 566 if (likely(priv->plat->force_sf_dma_mode ||
567 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
568 /*
569 * In case of GMAC, SF mode can be enabled
570 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 571 * 1) TX COE if actually supported
572 * 2) There is no bugged Jumbo frame support
573 * that needs to not insert csum in the TDES.
574 */
575 priv->hw->dma->dma_mode(priv->ioaddr,
576 SF_DMA_MODE, SF_DMA_MODE);
577 tc = SF_DMA_MODE;
578 } else
579 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 580}
581
47dd7a54
GC		 582/**
583 * stmmac_tx:
584 * @priv: private driver structure
585 * Description: it reclaims resources after transmission completes.
586 */
587static void stmmac_tx(struct stmmac_priv *priv)
588{
589 unsigned int txsize = priv->dma_tx_size;
47dd7a54 590
a9097a96
GC		 591 spin_lock(&priv->tx_lock);
592
47dd7a54
GC		 593 while (priv->dirty_tx != priv->cur_tx) {
594 int last;
595 unsigned int entry = priv->dirty_tx % txsize;
596 struct sk_buff *skb = priv->tx_skbuff[entry];
597 struct dma_desc *p = priv->dma_tx + entry;
598
599 /* Check if the descriptor is owned by the DMA. */
db98a0b0 600 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 601 break;
602
603 /* Verify tx error by looking at the last segment */
db98a0b0 604 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 605 if (likely(last)) {
606 int tx_error =
db98a0b0
GC		 607 priv->hw->desc->tx_status(&priv->dev->stats,
608 &priv->xstats, p,
ad01b7d4 609 priv->ioaddr);
47dd7a54
GC		 610 if (likely(tx_error == 0)) {
611 priv->dev->stats.tx_packets++;
612 priv->xstats.tx_pkt_n++;
613 } else
614 priv->dev->stats.tx_errors++;
615 }
616 TX_DBG("%s: curr %d, dirty %d\n", __func__,
617 priv->cur_tx, priv->dirty_tx);
618
619 if (likely(p->des2))
620 dma_unmap_single(priv->device, p->des2,
db98a0b0 621 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 622 DMA_TO_DEVICE);
623 if (unlikely(p->des3))
624 p->des3 = 0;
625
626 if (likely(skb != NULL)) {
627 /*
628 * If there's room in the queue (limit it to size)
629 * we add this skb back into the pool,
630 * if it's the right size.
631 */
632 if ((skb_queue_len(&priv->rx_recycle) <
633 priv->dma_rx_size) &&
634 skb_recycle_check(skb, priv->dma_buf_sz))
635 __skb_queue_head(&priv->rx_recycle, skb);
636 else
637 dev_kfree_skb(skb);
638
639 priv->tx_skbuff[entry] = NULL;
640 }
641
db98a0b0 642 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 643
644 entry = (++priv->dirty_tx) % txsize;
645 }
646 if (unlikely(netif_queue_stopped(priv->dev) &&
647 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
648 netif_tx_lock(priv->dev);
649 if (netif_queue_stopped(priv->dev) &&
650 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
651 TX_DBG("%s: restart transmit\n", __func__);
652 netif_wake_queue(priv->dev);
653 }
654 netif_tx_unlock(priv->dev);
655 }
a9097a96 656 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 657}
658
659static inline void stmmac_enable_irq(struct stmmac_priv *priv)
660{
73cfe264
GC		 661#ifdef CONFIG_STMMAC_TIMER
662 if (likely(priv->tm->enable))
663 priv->tm->timer_start(tmrate);
664 else
47dd7a54 665#endif
ad01b7d4 666 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 667}
668
669static inline void stmmac_disable_irq(struct stmmac_priv *priv)
670{
73cfe264
GC		 671#ifdef CONFIG_STMMAC_TIMER
672 if (likely(priv->tm->enable))
673 priv->tm->timer_stop();
674 else
47dd7a54 675#endif
ad01b7d4 676 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 677}
678
679static int stmmac_has_work(struct stmmac_priv *priv)
680{
681 unsigned int has_work = 0;
682 int rxret, tx_work = 0;
683
db98a0b0 684 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 685 (priv->cur_rx % priv->dma_rx_size));
686
687 if (priv->dirty_tx != priv->cur_tx)
688 tx_work = 1;
689
690 if (likely(!rxret || tx_work))
691 has_work = 1;
692
693 return has_work;
694}
695
696static inline void _stmmac_schedule(struct stmmac_priv *priv)
697{
698 if (likely(stmmac_has_work(priv))) {
699 stmmac_disable_irq(priv);
700 napi_schedule(&priv->napi);
701 }
702}
703
704#ifdef CONFIG_STMMAC_TIMER
705void stmmac_schedule(struct net_device *dev)
706{
707 struct stmmac_priv *priv = netdev_priv(dev);
708
709 priv->xstats.sched_timer_n++;
710
711 _stmmac_schedule(priv);
47dd7a54
GC		 712}
713
714static void stmmac_no_timer_started(unsigned int x)
715{;
716};
717
718static void stmmac_no_timer_stopped(void)
719{;
720};
721#endif
722
723/**
724 * stmmac_tx_err:
725 * @priv: pointer to the private device structure
726 * Description: it cleans the descriptors and restarts the transmission
727 * in case of errors.
728 */
729static void stmmac_tx_err(struct stmmac_priv *priv)
730{
ad01b7d4 731
47dd7a54
GC		 732 netif_stop_queue(priv->dev);
733
ad01b7d4 734 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 735 dma_free_tx_skbufs(priv);
db98a0b0 736 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 737 priv->dirty_tx = 0;
738 priv->cur_tx = 0;
ad01b7d4 739 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 740
741 priv->dev->stats.tx_errors++;
742 netif_wake_queue(priv->dev);
47dd7a54
GC		 743}
744
47dd7a54 745
aec7ff27
GC		 746static void stmmac_dma_interrupt(struct stmmac_priv *priv)
747{
aec7ff27
GC		 748 int status;
749
ad01b7d4 750 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 751 if (likely(status == handle_tx_rx))
752 _stmmac_schedule(priv);
753
754 else if (unlikely(status == tx_hard_error_bump_tc)) {
755 /* Try to bump up the dma threshold on this failure */
756 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
757 tc += 64;
ad01b7d4 758 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 759 priv->xstats.threshold = tc;
47dd7a54 760 }
aec7ff27
GC		 761 } else if (unlikely(status == tx_hard_error))
762 stmmac_tx_err(priv);
47dd7a54
GC		 763}
764
1c901a46
GC		 765static void stmmac_mmc_setup(struct stmmac_priv *priv)
766{
767 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
768 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
769
770 /* Do not manage MMC IRQ (FIXME) */
771 dwmac_mmc_intr_all_mask(priv->ioaddr);
772 dwmac_mmc_ctrl(priv->ioaddr, mode);
773 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
774}
775
f0b9d786
GC		 776static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
777{
778 u32 hwid = priv->hw->synopsys_uid;
779
780 /* Only check valid Synopsys Id because old MAC chips
781 * have no HW registers where get the ID */
782 if (likely(hwid)) {
783 u32 uid = ((hwid & 0x0000ff00) >> 8);
784 u32 synid = (hwid & 0x000000ff);
785
786 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
787 uid, synid);
788
789 return synid;
790 }
791 return 0;
792}
e7434821
GC		 793
794/* New GMAC chips support a new register to indicate the
795 * presence of the optional feature/functions.
796 */
797static int stmmac_get_hw_features(struct stmmac_priv *priv)
798{
799 u32 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
800
801 if (likely(hw_cap)) {
802 priv->dma_cap.mbps_10_100 = (hw_cap & 0x1);
803 priv->dma_cap.mbps_1000 = (hw_cap & 0x2) >> 1;
804 priv->dma_cap.half_duplex = (hw_cap & 0x4) >> 2;
805 priv->dma_cap.hash_filter = (hw_cap & 0x10) >> 4;
806 priv->dma_cap.multi_addr = (hw_cap & 0x20) >> 5;
807 priv->dma_cap.pcs = (hw_cap & 0x40) >> 6;
808 priv->dma_cap.sma_mdio = (hw_cap & 0x100) >> 8;
809 priv->dma_cap.pmt_remote_wake_up = (hw_cap & 0x200) >> 9;
810 priv->dma_cap.pmt_magic_frame = (hw_cap & 0x400) >> 10;
811 priv->dma_cap.rmon = (hw_cap & 0x800) >> 11; /* MMC */
812 /* IEEE 1588-2002*/
813 priv->dma_cap.time_stamp = (hw_cap & 0x1000) >> 12;
814 /* IEEE 1588-2008*/
815 priv->dma_cap.atime_stamp = (hw_cap & 0x2000) >> 13;
816 /* 802.3az - Energy-Efficient Ethernet (EEE) */
817 priv->dma_cap.eee = (hw_cap & 0x4000) >> 14;
818 priv->dma_cap.av = (hw_cap & 0x8000) >> 15;
819 /* TX and RX csum */
820 priv->dma_cap.tx_coe = (hw_cap & 0x10000) >> 16;
821 priv->dma_cap.rx_coe_type1 = (hw_cap & 0x20000) >> 17;
822 priv->dma_cap.rx_coe_type2 = (hw_cap & 0x40000) >> 18;
823 priv->dma_cap.rxfifo_over_2048 = (hw_cap & 0x80000) >> 19;
824 /* TX and RX number of channels */
825 priv->dma_cap.number_rx_channel = (hw_cap & 0x300000) >> 20;
826 priv->dma_cap.number_tx_channel = (hw_cap & 0xc00000) >> 22;
827 /* Alternate (enhanced) DESC mode*/
828 priv->dma_cap.enh_desc = (hw_cap & 0x1000000) >> 24;
829
830 } else
831 pr_debug("\tNo HW DMA feature register supported");
832
833 return hw_cap;
834}
835
47dd7a54
GC		 836/**
837 * stmmac_open - open entry point of the driver
838 * @dev : pointer to the device structure.
839 * Description:
840 * This function is the open entry point of the driver.
841 * Return value:
842 * 0 on success and an appropriate (-)ve integer as defined in errno.h
843 * file on failure.
844 */
845static int stmmac_open(struct net_device *dev)
846{
847 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 848 int ret;
849
850 /* Check that the MAC address is valid. If its not, refuse
851 * to bring the device up. The user must specify an
852 * address using the following linux command:
853 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
854 if (!is_valid_ether_addr(dev->dev_addr)) {
855 random_ether_addr(dev->dev_addr);
856 pr_warning("%s: generated random MAC address %pM\n", dev->name,
857 dev->dev_addr);
858 }
859
860 stmmac_verify_args();
861
47dd7a54 862#ifdef CONFIG_STMMAC_TIMER
73cfe264 863 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 864 if (unlikely(priv->tm == NULL)) {
2381a55c 865 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 866 return -ENOMEM;
867 }
868 priv->tm->freq = tmrate;
869
73cfe264
GC		 870 /* Test if the external timer can be actually used.
871 * In case of failure continue without timer. */
47dd7a54 872 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 873 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 874 priv->tm->freq = 0;
875 priv->tm->timer_start = stmmac_no_timer_started;
876 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 877 } else
878 priv->tm->enable = 1;
47dd7a54 879#endif
f66ffe28
GC		 880 ret = stmmac_init_phy(dev);
881 if (unlikely(ret)) {
882 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
883 goto open_error;
884 }
47dd7a54
GC		 885
886 /* Create and initialize the TX/RX descriptors chains. */
887 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
888 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
889 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
890 init_dma_desc_rings(dev);
891
892 /* DMA initialization and SW reset */
f66ffe28
GC		 893 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
894 priv->dma_tx_phy, priv->dma_rx_phy);
895 if (ret < 0) {
47dd7a54 896 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 897 goto open_error;
47dd7a54
GC		 898 }
899
900 /* Copy the MAC addr into the HW */
ad01b7d4 901 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1 902 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 903 if (priv->plat->bus_setup)
904 priv->plat->bus_setup(priv->ioaddr);
47dd7a54 905 /* Initialize the MAC Core */
ad01b7d4 906 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 907
f0b9d786
GC		 908 stmmac_get_synopsys_id(priv);
909
e7434821
GC		 910 stmmac_get_hw_features(priv);
911
ebbb293f
GC		 912 if (priv->rx_coe)
913 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
9dfeb4d9 914 if (priv->plat->tx_coe)
ebbb293f 915 pr_info("\tTX Checksum insertion supported\n");
5e982f3b 916 netdev_update_features(dev);
ebbb293f 917
f66ffe28
GC		 918 /* Request the IRQ lines */
919 ret = request_irq(dev->irq, stmmac_interrupt,
920 IRQF_SHARED, dev->name, dev);
921 if (unlikely(ret < 0)) {
922 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
923 __func__, dev->irq, ret);
924 goto open_error;
925 }
926
47dd7a54 927 /* Enable the MAC Rx/Tx */
19449bfc 928 stmmac_enable_mac(priv->ioaddr);
47dd7a54
GC		 929
930 /* Set the HW DMA mode and the COE */
931 stmmac_dma_operation_mode(priv);
932
933 /* Extra statistics */
934 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
935 priv->xstats.threshold = tc;
936
1c901a46
GC		 937 stmmac_mmc_setup(priv);
938
47dd7a54
GC		 939 /* Start the ball rolling... */
940 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 941 priv->hw->dma->start_tx(priv->ioaddr);
942 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 943
944#ifdef CONFIG_STMMAC_TIMER
945 priv->tm->timer_start(tmrate);
946#endif
947 /* Dump DMA/MAC registers */
948 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 949 priv->hw->mac->dump_regs(priv->ioaddr);
950 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 951 }
952
953 if (priv->phydev)
954 phy_start(priv->phydev);
955
956 napi_enable(&priv->napi);
957 skb_queue_head_init(&priv->rx_recycle);
958 netif_start_queue(dev);
f66ffe28 959
47dd7a54 960 return 0;
f66ffe28
GC		 961
962open_error:
963#ifdef CONFIG_STMMAC_TIMER
964 kfree(priv->tm);
965#endif
966 if (priv->phydev)
967 phy_disconnect(priv->phydev);
968
969 return ret;
47dd7a54
GC		 970}
971
972/**
973 * stmmac_release - close entry point of the driver
974 * @dev : device pointer.
975 * Description:
976 * This is the stop entry point of the driver.
977 */
978static int stmmac_release(struct net_device *dev)
979{
980 struct stmmac_priv *priv = netdev_priv(dev);
981
982 /* Stop and disconnect the PHY */
983 if (priv->phydev) {
984 phy_stop(priv->phydev);
985 phy_disconnect(priv->phydev);
986 priv->phydev = NULL;
987 }
988
989 netif_stop_queue(dev);
990
991#ifdef CONFIG_STMMAC_TIMER
992 /* Stop and release the timer */
993 stmmac_close_ext_timer();
994 if (priv->tm != NULL)
995 kfree(priv->tm);
996#endif
997 napi_disable(&priv->napi);
998 skb_queue_purge(&priv->rx_recycle);
999
1000 /* Free the IRQ lines */
1001 free_irq(dev->irq, dev);
1002
1003 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1004 priv->hw->dma->stop_tx(priv->ioaddr);
1005 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1006
1007 /* Release and free the Rx/Tx resources */
1008 free_dma_desc_resources(priv);
1009
19449bfc 1010 /* Disable the MAC Rx/Tx */
1011 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1012
1013 netif_carrier_off(dev);
1014
1015 return 0;
1016}
1017
47dd7a54
GC		 1018static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1019 struct net_device *dev,
1020 int csum_insertion)
1021{
1022 struct stmmac_priv *priv = netdev_priv(dev);
1023 unsigned int nopaged_len = skb_headlen(skb);
1024 unsigned int txsize = priv->dma_tx_size;
1025 unsigned int entry = priv->cur_tx % txsize;
1026 struct dma_desc *desc = priv->dma_tx + entry;
1027
1028 if (nopaged_len > BUF_SIZE_8KiB) {
1029
1030 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1031
1032 desc->des2 = dma_map_single(priv->device, skb->data,
1033 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1034 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1035 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1036 csum_insertion);
47dd7a54
GC		 1037
1038 entry = (++priv->cur_tx) % txsize;
1039 desc = priv->dma_tx + entry;
1040
1041 desc->des2 = dma_map_single(priv->device,
1042 skb->data + BUF_SIZE_8KiB,
1043 buf2_size, DMA_TO_DEVICE);
1044 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1045 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1046 csum_insertion);
1047 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1048 priv->tx_skbuff[entry] = NULL;
1049 } else {
1050 desc->des2 = dma_map_single(priv->device, skb->data,
1051 nopaged_len, DMA_TO_DEVICE);
1052 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1053 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1054 csum_insertion);
47dd7a54
GC		 1055 }
1056 return entry;
1057}
1058
1059/**
1060 * stmmac_xmit:
1061 * @skb : the socket buffer
1062 * @dev : device pointer
1063 * Description : Tx entry point of the driver.
1064 */
1065static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1066{
1067 struct stmmac_priv *priv = netdev_priv(dev);
1068 unsigned int txsize = priv->dma_tx_size;
1069 unsigned int entry;
1070 int i, csum_insertion = 0;
1071 int nfrags = skb_shinfo(skb)->nr_frags;
1072 struct dma_desc *desc, *first;
1073
1074 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1075 if (!netif_queue_stopped(dev)) {
1076 netif_stop_queue(dev);
1077 /* This is a hard error, log it. */
1078 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1079 __func__);
1080 }
1081 return NETDEV_TX_BUSY;
1082 }
1083
a9097a96
GC		 1084 spin_lock(&priv->tx_lock);
1085
47dd7a54
GC		 1086 entry = priv->cur_tx % txsize;
1087
1088#ifdef STMMAC_XMIT_DEBUG
1089 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1090 pr_info("stmmac xmit:\n"
1091 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1092 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1093 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1094 !skb_is_gso(skb) ? "isn't" : "is");
1095#endif
1096
5e982f3b 1097 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1098
1099 desc = priv->dma_tx + entry;
1100 first = desc;
1101
1102#ifdef STMMAC_XMIT_DEBUG
1103 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1104 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1105 "\t\tn_frags: %d, ip_summed: %d\n",
1106 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1107#endif
1108 priv->tx_skbuff[entry] = skb;
1109 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1110 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1111 desc = priv->dma_tx + entry;
1112 } else {
1113 unsigned int nopaged_len = skb_headlen(skb);
1114 desc->des2 = dma_map_single(priv->device, skb->data,
1115 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1116 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1117 csum_insertion);
47dd7a54
GC		 1118 }
1119
1120 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1121 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1122 int len = skb_frag_size(frag);
47dd7a54
GC		 1123
1124 entry = (++priv->cur_tx) % txsize;
1125 desc = priv->dma_tx + entry;
1126
1127 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1128 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1129 DMA_TO_DEVICE);
47dd7a54 1130 priv->tx_skbuff[entry] = NULL;
db98a0b0 1131 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1132 wmb();
db98a0b0 1133 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1134 }
1135
1136 /* Interrupt on completition only for the latest segment */
db98a0b0 1137 priv->hw->desc->close_tx_desc(desc);
73cfe264 1138
47dd7a54 1139#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1140 /* Clean IC while using timer */
1141 if (likely(priv->tm->enable))
db98a0b0 1142 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1143#endif
eb0dc4bb
SH		 1144
1145 wmb();
1146
47dd7a54 1147 /* To avoid raise condition */
db98a0b0 1148 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1149
1150 priv->cur_tx++;
1151
1152#ifdef STMMAC_XMIT_DEBUG
1153 if (netif_msg_pktdata(priv)) {
1154 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1155 "first=%p, nfrags=%d\n",
1156 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1157 entry, first, nfrags);
1158 display_ring(priv->dma_tx, txsize);
1159 pr_info(">>> frame to be transmitted: ");
1160 print_pkt(skb->data, skb->len);
1161 }
1162#endif
1163 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1164 TX_DBG("%s: stop transmitted packets\n", __func__);
1165 netif_stop_queue(dev);
1166 }
1167
1168 dev->stats.tx_bytes += skb->len;
1169
3e82ce12
RC		 1170 skb_tx_timestamp(skb);
1171
52f64fae
RC		 1172 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1173
a9097a96
GC		 1174 spin_unlock(&priv->tx_lock);
1175
47dd7a54
GC		 1176 return NETDEV_TX_OK;
1177}
1178
1179static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1180{
1181 unsigned int rxsize = priv->dma_rx_size;
1182 int bfsize = priv->dma_buf_sz;
1183 struct dma_desc *p = priv->dma_rx;
1184
1185 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1186 unsigned int entry = priv->dirty_rx % rxsize;
1187 if (likely(priv->rx_skbuff[entry] == NULL)) {
1188 struct sk_buff *skb;
1189
1190 skb = __skb_dequeue(&priv->rx_recycle);
1191 if (skb == NULL)
1192 skb = netdev_alloc_skb_ip_align(priv->dev,
1193 bfsize);
1194
1195 if (unlikely(skb == NULL))
1196 break;
1197
1198 priv->rx_skbuff[entry] = skb;
1199 priv->rx_skbuff_dma[entry] =
1200 dma_map_single(priv->device, skb->data, bfsize,
1201 DMA_FROM_DEVICE);
1202
1203 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
9dfeb4d9 1204 if (unlikely(priv->plat->has_gmac)) {
47dd7a54
GC		 1205 if (bfsize >= BUF_SIZE_8KiB)
1206 (p + entry)->des3 =
1207 (p + entry)->des2 + BUF_SIZE_8KiB;
1208 }
1209 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1210 }
eb0dc4bb 1211 wmb();
db98a0b0 1212 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1213 }
47dd7a54
GC		 1214}
1215
1216static int stmmac_rx(struct stmmac_priv *priv, int limit)
1217{
1218 unsigned int rxsize = priv->dma_rx_size;
1219 unsigned int entry = priv->cur_rx % rxsize;
1220 unsigned int next_entry;
1221 unsigned int count = 0;
1222 struct dma_desc *p = priv->dma_rx + entry;
1223 struct dma_desc *p_next;
1224
1225#ifdef STMMAC_RX_DEBUG
1226 if (netif_msg_hw(priv)) {
1227 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1228 display_ring(priv->dma_rx, rxsize);
1229 }
1230#endif
1231 count = 0;
db98a0b0 1232 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1233 int status;
1234
1235 if (count >= limit)
1236 break;
1237
1238 count++;
1239
1240 next_entry = (++priv->cur_rx) % rxsize;
1241 p_next = priv->dma_rx + next_entry;
1242 prefetch(p_next);
1243
1244 /* read the status of the incoming frame */
db98a0b0
GC		 1245 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1246 &priv->xstats, p));
47dd7a54
GC		 1247 if (unlikely(status == discard_frame))
1248 priv->dev->stats.rx_errors++;
1249 else {
1250 struct sk_buff *skb;
3eeb2997 1251 int frame_len;
47dd7a54 1252
3eeb2997
GC		 1253 frame_len = priv->hw->desc->get_rx_frame_len(p);
1254 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1255 * Type frames (LLC/LLC-SNAP) */
1256 if (unlikely(status != llc_snap))
1257 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1258#ifdef STMMAC_RX_DEBUG
1259 if (frame_len > ETH_FRAME_LEN)
1260 pr_debug("\tRX frame size %d, COE status: %d\n",
1261 frame_len, status);
1262
1263 if (netif_msg_hw(priv))
1264 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1265 p, entry, p->des2);
1266#endif
1267 skb = priv->rx_skbuff[entry];
1268 if (unlikely(!skb)) {
1269 pr_err("%s: Inconsistent Rx descriptor chain\n",
1270 priv->dev->name);
1271 priv->dev->stats.rx_dropped++;
1272 break;
1273 }
1274 prefetch(skb->data - NET_IP_ALIGN);
1275 priv->rx_skbuff[entry] = NULL;
1276
1277 skb_put(skb, frame_len);
1278 dma_unmap_single(priv->device,
1279 priv->rx_skbuff_dma[entry],
1280 priv->dma_buf_sz, DMA_FROM_DEVICE);
1281#ifdef STMMAC_RX_DEBUG
1282 if (netif_msg_pktdata(priv)) {
1283 pr_info(" frame received (%dbytes)", frame_len);
1284 print_pkt(skb->data, frame_len);
1285 }
1286#endif
1287 skb->protocol = eth_type_trans(skb, priv->dev);
1288
1289 if (unlikely(status == csum_none)) {
1290 /* always for the old mac 10/100 */
bc8acf2c 1291 skb_checksum_none_assert(skb);
47dd7a54
GC		 1292 netif_receive_skb(skb);
1293 } else {
1294 skb->ip_summed = CHECKSUM_UNNECESSARY;
1295 napi_gro_receive(&priv->napi, skb);
1296 }
1297
1298 priv->dev->stats.rx_packets++;
1299 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1300 }
1301 entry = next_entry;
1302 p = p_next; /* use prefetched values */
1303 }
1304
1305 stmmac_rx_refill(priv);
1306
1307 priv->xstats.rx_pkt_n += count;
1308
1309 return count;
1310}
1311
1312/**
1313 * stmmac_poll - stmmac poll method (NAPI)
1314 * @napi : pointer to the napi structure.
1315 * @budget : maximum number of packets that the current CPU can receive from
1316 * all interfaces.
1317 * Description :
1318 * This function implements the the reception process.
1319 * Also it runs the TX completion thread
1320 */
1321static int stmmac_poll(struct napi_struct *napi, int budget)
1322{
1323 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1324 int work_done = 0;
1325
1326 priv->xstats.poll_n++;
1327 stmmac_tx(priv);
1328 work_done = stmmac_rx(priv, budget);
1329
1330 if (work_done < budget) {
1331 napi_complete(napi);
1332 stmmac_enable_irq(priv);
1333 }
1334 return work_done;
1335}
1336
1337/**
1338 * stmmac_tx_timeout
1339 * @dev : Pointer to net device structure
1340 * Description: this function is called when a packet transmission fails to
1341 * complete within a reasonable tmrate. The driver will mark the error in the
1342 * netdev structure and arrange for the device to be reset to a sane state
1343 * in order to transmit a new packet.
1344 */
1345static void stmmac_tx_timeout(struct net_device *dev)
1346{
1347 struct stmmac_priv *priv = netdev_priv(dev);
1348
1349 /* Clear Tx resources and restart transmitting again */
1350 stmmac_tx_err(priv);
47dd7a54
GC		 1351}
1352
1353/* Configuration changes (passed on by ifconfig) */
1354static int stmmac_config(struct net_device *dev, struct ifmap *map)
1355{
1356 if (dev->flags & IFF_UP) /* can't act on a running interface */
1357 return -EBUSY;
1358
1359 /* Don't allow changing the I/O address */
1360 if (map->base_addr != dev->base_addr) {
1361 pr_warning("%s: can't change I/O address\n", dev->name);
1362 return -EOPNOTSUPP;
1363 }
1364
1365 /* Don't allow changing the IRQ */
1366 if (map->irq != dev->irq) {
1367 pr_warning("%s: can't change IRQ number %d\n",
1368 dev->name, dev->irq);
1369 return -EOPNOTSUPP;
1370 }
1371
1372 /* ignore other fields */
1373 return 0;
1374}
1375
1376/**
01789349 1377 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1378 * @dev : pointer to the device structure
1379 * Description:
1380 * This function is a driver entry point which gets called by the kernel
1381 * whenever multicast addresses must be enabled/disabled.
1382 * Return value:
1383 * void.
1384 */
01789349 1385static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1386{
1387 struct stmmac_priv *priv = netdev_priv(dev);
1388
1389 spin_lock(&priv->lock);
db98a0b0 1390 priv->hw->mac->set_filter(dev);
47dd7a54 1391 spin_unlock(&priv->lock);
47dd7a54
GC		 1392}
1393
1394/**
1395 * stmmac_change_mtu - entry point to change MTU size for the device.
1396 * @dev : device pointer.
1397 * @new_mtu : the new MTU size for the device.
1398 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1399 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1400 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1401 * Return value:
1402 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1403 * file on failure.
1404 */
1405static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1406{
1407 struct stmmac_priv *priv = netdev_priv(dev);
1408 int max_mtu;
1409
1410 if (netif_running(dev)) {
1411 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1412 return -EBUSY;
1413 }
1414
9dfeb4d9 1415 if (priv->plat->has_gmac)
47dd7a54
GC		 1416 max_mtu = JUMBO_LEN;
1417 else
1418 max_mtu = ETH_DATA_LEN;
1419
1420 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1421 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1422 return -EINVAL;
1423 }
1424
5e982f3b
MM		 1425 dev->mtu = new_mtu;
1426 netdev_update_features(dev);
1427
1428 return 0;
1429}
1430
1431static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1432{
1433 struct stmmac_priv *priv = netdev_priv(dev);
1434
1435 if (!priv->rx_coe)
1436 features &= ~NETIF_F_RXCSUM;
1437 if (!priv->plat->tx_coe)
1438 features &= ~NETIF_F_ALL_CSUM;
1439
ebbb293f
GC		 1440 /* Some GMAC devices have a bugged Jumbo frame support that
1441 * needs to have the Tx COE disabled for oversized frames
1442 * (due to limited buffer sizes). In this case we disable
1443 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1444 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1445 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1446
5e982f3b 1447 return features;
47dd7a54
GC		 1448}
1449
1450static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1451{
1452 struct net_device *dev = (struct net_device *)dev_id;
1453 struct stmmac_priv *priv = netdev_priv(dev);
1454
1455 if (unlikely(!dev)) {
1456 pr_err("%s: invalid dev pointer\n", __func__);
1457 return IRQ_NONE;
1458 }
1459
9dfeb4d9 1460 if (priv->plat->has_gmac)
47dd7a54 1461 /* To handle GMAC own interrupts */
ad01b7d4 1462 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1463
1464 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1465
1466 return IRQ_HANDLED;
1467}
1468
1469#ifdef CONFIG_NET_POLL_CONTROLLER
1470/* Polling receive - used by NETCONSOLE and other diagnostic tools
1471 * to allow network I/O with interrupts disabled. */
1472static void stmmac_poll_controller(struct net_device *dev)
1473{
1474 disable_irq(dev->irq);
1475 stmmac_interrupt(dev->irq, dev);
1476 enable_irq(dev->irq);
1477}
1478#endif
1479
1480/**
1481 * stmmac_ioctl - Entry point for the Ioctl
1482 * @dev: Device pointer.
1483 * @rq: An IOCTL specefic structure, that can contain a pointer to
1484 * a proprietary structure used to pass information to the driver.
1485 * @cmd: IOCTL command
1486 * Description:
1487 * Currently there are no special functionality supported in IOCTL, just the
1488 * phy_mii_ioctl(...) can be invoked.
1489 */
1490static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1491{
1492 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1493 int ret;
47dd7a54
GC		 1494
1495 if (!netif_running(dev))
1496 return -EINVAL;
1497
28b04113
RC		 1498 if (!priv->phydev)
1499 return -EINVAL;
1500
1501 spin_lock(&priv->lock);
1502 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1503 spin_unlock(&priv->lock);
1504
47dd7a54
GC		 1505 return ret;
1506}
1507
7ac29055
GC		 1508#ifdef CONFIG_STMMAC_DEBUG_FS
1509static struct dentry *stmmac_fs_dir;
1510static struct dentry *stmmac_rings_status;
e7434821 1511static struct dentry *stmmac_dma_cap;
7ac29055
GC		 1512
1513static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1514{
1515 struct tmp_s {
1516 u64 a;
1517 unsigned int b;
1518 unsigned int c;
1519 };
1520 int i;
1521 struct net_device *dev = seq->private;
1522 struct stmmac_priv *priv = netdev_priv(dev);
1523
1524 seq_printf(seq, "=======================\n");
1525 seq_printf(seq, " RX descriptor ring\n");
1526 seq_printf(seq, "=======================\n");
1527
1528 for (i = 0; i < priv->dma_rx_size; i++) {
1529 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1530 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1531 i, (unsigned int)(x->a),
1532 (unsigned int)((x->a) >> 32), x->b, x->c);
1533 seq_printf(seq, "\n");
1534 }
1535
1536 seq_printf(seq, "\n");
1537 seq_printf(seq, "=======================\n");
1538 seq_printf(seq, " TX descriptor ring\n");
1539 seq_printf(seq, "=======================\n");
1540
1541 for (i = 0; i < priv->dma_tx_size; i++) {
1542 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1543 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1544 i, (unsigned int)(x->a),
1545 (unsigned int)((x->a) >> 32), x->b, x->c);
1546 seq_printf(seq, "\n");
1547 }
1548
1549 return 0;
1550}
1551
1552static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1553{
1554 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1555}
1556
1557static const struct file_operations stmmac_rings_status_fops = {
1558 .owner = THIS_MODULE,
1559 .open = stmmac_sysfs_ring_open,
1560 .read = seq_read,
1561 .llseek = seq_lseek,
1562 .release = seq_release,
1563};
1564
e7434821
GC		 1565static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1566{
1567 struct net_device *dev = seq->private;
1568 struct stmmac_priv *priv = netdev_priv(dev);
1569
1570 if (!stmmac_get_hw_features(priv)) {
1571 seq_printf(seq, "DMA HW features not supported\n");
1572 return 0;
1573 }
1574
1575 seq_printf(seq, "==============================\n");
1576 seq_printf(seq, "\tDMA HW features\n");
1577 seq_printf(seq, "==============================\n");
1578
1579 seq_printf(seq, "\t10/100 Mbps %s\n",
1580 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1581 seq_printf(seq, "\t1000 Mbps %s\n",
1582 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1583 seq_printf(seq, "\tHalf duple %s\n",
1584 (priv->dma_cap.half_duplex) ? "Y" : "N");
1585 seq_printf(seq, "\tHash Filter: %s\n",
1586 (priv->dma_cap.hash_filter) ? "Y" : "N");
1587 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1588 (priv->dma_cap.multi_addr) ? "Y" : "N");
1589 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1590 (priv->dma_cap.pcs) ? "Y" : "N");
1591 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1592 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1593 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1594 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1595 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1596 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1597 seq_printf(seq, "\tRMON module: %s\n",
1598 (priv->dma_cap.rmon) ? "Y" : "N");
1599 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1600 (priv->dma_cap.time_stamp) ? "Y" : "N");
1601 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1602 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1603 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1604 (priv->dma_cap.eee) ? "Y" : "N");
1605 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1606 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1607 (priv->dma_cap.tx_coe) ? "Y" : "N");
1608 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1609 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1610 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1611 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1612 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1613 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1614 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1615 priv->dma_cap.number_rx_channel);
1616 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1617 priv->dma_cap.number_tx_channel);
1618 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1619 (priv->dma_cap.enh_desc) ? "Y" : "N");
1620
1621 return 0;
1622}
1623
1624static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1625{
1626 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1627}
1628
1629static const struct file_operations stmmac_dma_cap_fops = {
1630 .owner = THIS_MODULE,
1631 .open = stmmac_sysfs_dma_cap_open,
1632 .read = seq_read,
1633 .llseek = seq_lseek,
1634 .release = seq_release,
1635};
1636
7ac29055
GC		 1637static int stmmac_init_fs(struct net_device *dev)
1638{
1639 /* Create debugfs entries */
1640 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1641
1642 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1643 pr_err("ERROR %s, debugfs create directory failed\n",
1644 STMMAC_RESOURCE_NAME);
1645
1646 return -ENOMEM;
1647 }
1648
1649 /* Entry to report DMA RX/TX rings */
1650 stmmac_rings_status = debugfs_create_file("descriptors_status",
1651 S_IRUGO, stmmac_fs_dir, dev,
1652 &stmmac_rings_status_fops);
1653
1654 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1655 pr_info("ERROR creating stmmac ring debugfs file\n");
1656 debugfs_remove(stmmac_fs_dir);
1657
1658 return -ENOMEM;
1659 }
1660
e7434821
GC		 1661 /* Entry to report the DMA HW features */
1662 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1663 dev, &stmmac_dma_cap_fops);
1664
1665 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1666 pr_info("ERROR creating stmmac MMC debugfs file\n");
1667 debugfs_remove(stmmac_rings_status);
1668 debugfs_remove(stmmac_fs_dir);
1669
1670 return -ENOMEM;
1671 }
1672
7ac29055
GC		 1673 return 0;
1674}
1675
1676static void stmmac_exit_fs(void)
1677{
1678 debugfs_remove(stmmac_rings_status);
e7434821 1679 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 1680 debugfs_remove(stmmac_fs_dir);
1681}
1682#endif /* CONFIG_STMMAC_DEBUG_FS */
1683
47dd7a54
GC		 1684static const struct net_device_ops stmmac_netdev_ops = {
1685 .ndo_open = stmmac_open,
1686 .ndo_start_xmit = stmmac_xmit,
1687 .ndo_stop = stmmac_release,
1688 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1689 .ndo_fix_features = stmmac_fix_features,
01789349 1690 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1691 .ndo_tx_timeout = stmmac_tx_timeout,
1692 .ndo_do_ioctl = stmmac_ioctl,
1693 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1694#ifdef CONFIG_NET_POLL_CONTROLLER
1695 .ndo_poll_controller = stmmac_poll_controller,
1696#endif
1697 .ndo_set_mac_address = eth_mac_addr,
1698};
1699
1700/**
1701 * stmmac_probe - Initialization of the adapter .
1702 * @dev : device pointer
1703 * Description: The function initializes the network device structure for
1704 * the STMMAC driver. It also calls the low level routines
1705 * in order to init the HW (i.e. the DMA engine)
1706 */
1707static int stmmac_probe(struct net_device *dev)
1708{
1709 int ret = 0;
1710 struct stmmac_priv *priv = netdev_priv(dev);
1711
1712 ether_setup(dev);
1713
1714 dev->netdev_ops = &stmmac_netdev_ops;
1715 stmmac_set_ethtool_ops(dev);
1716
5e982f3b
MM		 1717 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1718 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
47dd7a54
GC		 1719 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1720#ifdef STMMAC_VLAN_TAG_USED
1721 /* Both mac100 and gmac support receive VLAN tag detection */
1722 dev->features |= NETIF_F_HW_VLAN_RX;
1723#endif
1724 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1725
47dd7a54
GC		 1726 if (flow_ctrl)
1727 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1728
1729 priv->pause = pause;
1730 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1731
1732 /* Get the MAC address */
ad01b7d4
GC		 1733 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1734 dev->dev_addr, 0);
47dd7a54
GC		 1735
1736 if (!is_valid_ether_addr(dev->dev_addr))
1737 pr_warning("\tno valid MAC address;"
1738 "please, use ifconfig or nwhwconfig!\n");
1739
f8e96161 1740 spin_lock_init(&priv->lock);
a9097a96 1741 spin_lock_init(&priv->tx_lock);
f8e96161 1742
47dd7a54
GC		 1743 ret = register_netdev(dev);
1744 if (ret) {
1745 pr_err("%s: ERROR %i registering the device\n",
1746 __func__, ret);
1747 return -ENODEV;
1748 }
1749
1750 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1751 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
79032644 1752 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
47dd7a54 1753
47dd7a54
GC		 1754 return ret;
1755}
1756
1757/**
1758 * stmmac_mac_device_setup
1759 * @dev : device pointer
1760 * Description: select and initialise the mac device (mac100 or Gmac).
1761 */
1762static int stmmac_mac_device_setup(struct net_device *dev)
1763{
1764 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1765
1766 struct mac_device_info *device;
1767
01789349
JP		 1768 if (priv->plat->has_gmac) {
1769 dev->priv_flags |= IFF_UNICAST_FLT;
ad01b7d4 1770 device = dwmac1000_setup(priv->ioaddr);
01789349 1771 } else {
ad01b7d4 1772 device = dwmac100_setup(priv->ioaddr);
01789349 1773 }
3d90c508 1774
1ff21906
DC		 1775 if (!device)
1776 return -ENOMEM;
1777
9dfeb4d9 1778 if (priv->plat->enh_desc) {
3d90c508
GC		 1779 device->desc = &enh_desc_ops;
1780 pr_info("\tEnhanced descriptor structure\n");
1781 } else
56b106ae 1782 device->desc = &ndesc_ops;
47dd7a54 1783
db98a0b0 1784 priv->hw = device;
47dd7a54 1785
539c9aa5 1786 if (device_can_wakeup(priv->device)) {
543876c9 1787 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
3172d3af 1788 enable_irq_wake(priv->wol_irq);
539c9aa5 1789 }
47dd7a54
GC		 1790
1791 return 0;
1792}
1793
47dd7a54
GC		 1794/**
1795 * stmmac_dvr_probe
1796 * @pdev: platform device pointer
1797 * Description: the driver is initialized through platform_device.
1798 */
1799static int stmmac_dvr_probe(struct platform_device *pdev)
1800{
1801 int ret = 0;
1802 struct resource *res;
ad01b7d4 1803 void __iomem *addr = NULL;
47dd7a54 1804 struct net_device *ndev = NULL;
293bb1c4 1805 struct stmmac_priv *priv = NULL;
47dd7a54
GC		 1806 struct plat_stmmacenet_data *plat_dat;
1807
1808 pr_info("STMMAC driver:\n\tplatform registration... ");
1809 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34a52f36
DC		 1810 if (!res)
1811 return -ENODEV;
ebbb293f 1812 pr_info("\tdone!\n");
47dd7a54 1813
b6222682 1814 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1815 pdev->name)) {
1816 pr_err("%s: ERROR: memory allocation failed"
1817 "cannot get the I/O addr 0x%x\n",
1818 __func__, (unsigned int)res->start);
34a52f36 1819 return -EBUSY;
47dd7a54
GC		 1820 }
1821
7c5365bc 1822 addr = ioremap(res->start, resource_size(res));
47dd7a54 1823 if (!addr) {
7c5365bc 1824 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54 1825 ret = -ENOMEM;
34a52f36 1826 goto out_release_region;
47dd7a54
GC		 1827 }
1828
1829 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1830 if (!ndev) {
1831 pr_err("%s: ERROR: allocating the device\n", __func__);
1832 ret = -ENOMEM;
34a52f36 1833 goto out_unmap;
47dd7a54
GC		 1834 }
1835
1836 SET_NETDEV_DEV(ndev, &pdev->dev);
1837
1838 /* Get the MAC information */
1839 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1840 if (ndev->irq == -ENXIO) {
1841 pr_err("%s: ERROR: MAC IRQ configuration "
1842 "information not found\n", __func__);
34a52f36
DC		 1843 ret = -ENXIO;
1844 goto out_free_ndev;
47dd7a54
GC		 1845 }
1846
1847 priv = netdev_priv(ndev);
1848 priv->device = &(pdev->dev);
1849 priv->dev = ndev;
ee7946a7 1850 plat_dat = pdev->dev.platform_data;
9dfeb4d9
GC		 1851
1852 priv->plat = plat_dat;
1853
ad01b7d4 1854 priv->ioaddr = addr;
47dd7a54 1855
543876c9
GC		 1856 /* PMT module is not integrated in all the MAC devices. */
1857 if (plat_dat->pmt) {
1858 pr_info("\tPMT module supported\n");
1859 device_set_wakeup_capable(&pdev->dev, 1);
1860 }
3172d3af
DS		 1861 /*
1862 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1863 * The external wake up irq can be passed through the platform code
1864 * named as "eth_wake_irq"
1865 *
1866 * In case the wake up interrupt is not passed from the platform
1867 * so the driver will continue to use the mac irq (ndev->irq)
1868 */
1869 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1870 if (priv->wol_irq == -ENXIO)
1871 priv->wol_irq = ndev->irq;
1872
543876c9 1873
47dd7a54
GC		 1874 platform_set_drvdata(pdev, ndev);
1875
1876 /* Set the I/O base addr */
1877 ndev->base_addr = (unsigned long)addr;
1878
293bb1c4
GC		 1879 /* Custom initialisation */
1880 if (priv->plat->init) {
1881 ret = priv->plat->init(pdev);
1882 if (unlikely(ret))
34a52f36 1883 goto out_free_ndev;
293bb1c4 1884 }
ee7946a7 1885
47dd7a54
GC		 1886 /* MAC HW revice detection */
1887 ret = stmmac_mac_device_setup(ndev);
1888 if (ret < 0)
34a52f36 1889 goto out_plat_exit;
47dd7a54
GC		 1890
1891 /* Network Device Registration */
1892 ret = stmmac_probe(ndev);
1893 if (ret < 0)
34a52f36 1894 goto out_plat_exit;
47dd7a54 1895
36bcfe7d
GC		 1896 /* Override with kernel parameters if supplied XXX CRS XXX
1897 * this needs to have multiple instances */
1898 if ((phyaddr >= 0) && (phyaddr <= 31))
1899 priv->plat->phy_addr = phyaddr;
47dd7a54 1900
47dd7a54 1901 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1902 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1903 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1904
1905 /* MDIO bus Registration */
9dfeb4d9 1906 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
47dd7a54
GC		 1907 ret = stmmac_mdio_register(ndev);
1908 if (ret < 0)
34a52f36 1909 goto out_unregister;
47dd7a54 1910 pr_debug("registered!\n");
7ac29055
GC		 1911
1912#ifdef CONFIG_STMMAC_DEBUG_FS
1913 ret = stmmac_init_fs(ndev);
1914 if (ret < 0)
1915 pr_warning("\tFailed debugFS registration");
1916#endif
1917
34a52f36 1918 return 0;
47dd7a54 1919
34a52f36
DC		 1920out_unregister:
1921 unregister_netdev(ndev);
1922out_plat_exit:
1923 if (priv->plat->exit)
1924 priv->plat->exit(pdev);
1925out_free_ndev:
1926 free_netdev(ndev);
1927 platform_set_drvdata(pdev, NULL);
1928out_unmap:
1929 iounmap(addr);
1930out_release_region:
1931 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1932
1933 return ret;
1934}
1935
1936/**
1937 * stmmac_dvr_remove
1938 * @pdev: platform device pointer
1939 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1940 * changes the link status, releases the DMA descriptor rings,
1941 * unregisters the MDIO bus and unmaps the allocated memory.
1942 */
1943static int stmmac_dvr_remove(struct platform_device *pdev)
1944{
1945 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1946 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1947 struct resource *res;
1948
1949 pr_info("%s:\n\tremoving driver", __func__);
1950
ad01b7d4
GC		 1951 priv->hw->dma->stop_rx(priv->ioaddr);
1952 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1953
19449bfc 1954 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1955
1956 netif_carrier_off(ndev);
1957
1958 stmmac_mdio_unregister(ndev);
1959
293bb1c4
GC		 1960 if (priv->plat->exit)
1961 priv->plat->exit(pdev);
1962
47dd7a54
GC		 1963 platform_set_drvdata(pdev, NULL);
1964 unregister_netdev(ndev);
1965
ad01b7d4 1966 iounmap((void *)priv->ioaddr);
47dd7a54 1967 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1968 release_mem_region(res->start, resource_size(res));
47dd7a54 1969
7ac29055
GC		 1970#ifdef CONFIG_STMMAC_DEBUG_FS
1971 stmmac_exit_fs();
1972#endif
1973
47dd7a54
GC		 1974 free_netdev(ndev);
1975
1976 return 0;
1977}
1978
1979#ifdef CONFIG_PM
874bd42d 1980static int stmmac_suspend(struct device *dev)
47dd7a54 1981{
874bd42d
GC		 1982 struct net_device *ndev = dev_get_drvdata(dev);
1983 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1984 int dis_ic = 0;
1985
874bd42d 1986 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 1987 return 0;
1988
1989 spin_lock(&priv->lock);
1990
874bd42d
GC		 1991 netif_device_detach(ndev);
1992 netif_stop_queue(ndev);
1993 if (priv->phydev)
1994 phy_stop(priv->phydev);
47dd7a54
GC		 1995
1996#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 1997 priv->tm->timer_stop();
1998 if (likely(priv->tm->enable))
1999 dis_ic = 1;
47dd7a54 2000#endif
874bd42d
GC		 2001 napi_disable(&priv->napi);
2002
2003 /* Stop TX/RX DMA */
2004 priv->hw->dma->stop_tx(priv->ioaddr);
2005 priv->hw->dma->stop_rx(priv->ioaddr);
2006 /* Clear the Rx/Tx descriptors */
2007 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2008 dis_ic);
2009 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2010
2011 /* Enable Power down mode by programming the PMT regs */
2012 if (device_may_wakeup(priv->device))
2013 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2014 else
2015 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 2016
2017 spin_unlock(&priv->lock);
2018 return 0;
2019}
2020
874bd42d 2021static int stmmac_resume(struct device *dev)
47dd7a54 2022{
874bd42d
GC		 2023 struct net_device *ndev = dev_get_drvdata(dev);
2024 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 2025
874bd42d 2026 if (!netif_running(ndev))
47dd7a54
GC		 2027 return 0;
2028
c4433be6
GC		 2029 spin_lock(&priv->lock);
2030
47dd7a54
GC		 2031 /* Power Down bit, into the PM register, is cleared
2032 * automatically as soon as a magic packet or a Wake-up frame
2033 * is received. Anyway, it's better to manually clear
2034 * this bit because it can generate problems while resuming
2035 * from another devices (e.g. serial console). */
874bd42d 2036 if (device_may_wakeup(priv->device))
543876c9 2037 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54 2038
874bd42d 2039 netif_device_attach(ndev);
47dd7a54
GC		 2040
2041 /* Enable the MAC and DMA */
19449bfc 2042 stmmac_enable_mac(priv->ioaddr);
ad01b7d4
GC		 2043 priv->hw->dma->start_tx(priv->ioaddr);
2044 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 2045
2046#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2047 if (likely(priv->tm->enable))
2048 priv->tm->timer_start(tmrate);
47dd7a54
GC		 2049#endif
2050 napi_enable(&priv->napi);
2051
2052 if (priv->phydev)
2053 phy_start(priv->phydev);
2054
874bd42d 2055 netif_start_queue(ndev);
47dd7a54 2056
47dd7a54
GC		 2057 spin_unlock(&priv->lock);
2058 return 0;
2059}
47dd7a54 2060
874bd42d
GC		 2061static int stmmac_freeze(struct device *dev)
2062{
2063 struct net_device *ndev = dev_get_drvdata(dev);
2064
2065 if (!ndev || !netif_running(ndev))
2066 return 0;
2067
2068 return stmmac_release(ndev);
2069}
2070
2071static int stmmac_restore(struct device *dev)
2072{
2073 struct net_device *ndev = dev_get_drvdata(dev);
2074
2075 if (!ndev || !netif_running(ndev))
2076 return 0;
2077
2078 return stmmac_open(ndev);
2079}
2080
2081static const struct dev_pm_ops stmmac_pm_ops = {
47dd7a54
GC		 2082 .suspend = stmmac_suspend,
2083 .resume = stmmac_resume,
874bd42d
GC		 2084 .freeze = stmmac_freeze,
2085 .thaw = stmmac_restore,
2086 .restore = stmmac_restore,
2087};
2088#else
2089static const struct dev_pm_ops stmmac_pm_ops;
2090#endif /* CONFIG_PM */
47dd7a54 2091
874bd42d
GC		 2092static struct platform_driver stmmac_driver = {
2093 .probe = stmmac_dvr_probe,
2094 .remove = stmmac_dvr_remove,
2095 .driver = {
2096 .name = STMMAC_RESOURCE_NAME,
2097 .owner = THIS_MODULE,
2098 .pm = &stmmac_pm_ops,
2099 },
47dd7a54
GC		 2100};
2101
2102/**
2103 * stmmac_init_module - Entry point for the driver
2104 * Description: This function is the entry point for the driver.
2105 */
2106static int __init stmmac_init_module(void)
2107{
2108 int ret;
2109
47dd7a54
GC		 2110 ret = platform_driver_register(&stmmac_driver);
2111 return ret;
2112}
2113
2114/**
2115 * stmmac_cleanup_module - Cleanup routine for the driver
2116 * Description: This function is the cleanup routine for the driver.
2117 */
2118static void __exit stmmac_cleanup_module(void)
2119{
47dd7a54
GC		 2120 platform_driver_unregister(&stmmac_driver);
2121}
2122
2123#ifndef MODULE
2124static int __init stmmac_cmdline_opt(char *str)
2125{
2126 char *opt;
2127
2128 if (!str || !*str)
2129 return -EINVAL;
2130 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 2131 if (!strncmp(opt, "debug:", 6)) {
2132 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2133 goto err;
2134 } else if (!strncmp(opt, "phyaddr:", 8)) {
2135 if (strict_strtoul(opt + 8, 0,
2136 (unsigned long *)&phyaddr))
2137 goto err;
2138 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2139 if (strict_strtoul(opt + 11, 0,
2140 (unsigned long *)&dma_txsize))
2141 goto err;
2142 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2143 if (strict_strtoul(opt + 11, 0,
2144 (unsigned long *)&dma_rxsize))
2145 goto err;
2146 } else if (!strncmp(opt, "buf_sz:", 7)) {
2147 if (strict_strtoul(opt + 7, 0,
2148 (unsigned long *)&buf_sz))
2149 goto err;
2150 } else if (!strncmp(opt, "tc:", 3)) {
2151 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2152 goto err;
2153 } else if (!strncmp(opt, "watchdog:", 9)) {
2154 if (strict_strtoul(opt + 9, 0,
2155 (unsigned long *)&watchdog))
2156 goto err;
2157 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2158 if (strict_strtoul(opt + 10, 0,
2159 (unsigned long *)&flow_ctrl))
2160 goto err;
2161 } else if (!strncmp(opt, "pause:", 6)) {
2162 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2163 goto err;
47dd7a54 2164#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 2165 } else if (!strncmp(opt, "tmrate:", 7)) {
2166 if (strict_strtoul(opt + 7, 0,
2167 (unsigned long *)&tmrate))
2168 goto err;
47dd7a54 2169#endif
f3240e28 2170 }
47dd7a54
GC		 2171 }
2172 return 0;
f3240e28
GC		 2173
2174err:
2175 pr_err("%s: ERROR broken module parameter conversion", __func__);
2176 return -EINVAL;
47dd7a54
GC		 2177}
2178
2179__setup("stmmaceth=", stmmac_cmdline_opt);
2180#endif
2181
2182module_init(stmmac_init_module);
2183module_exit(stmmac_cleanup_module);
2184
2185MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2186MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2187MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.367339 seconds and 5 git commands to generate.