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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
6a81c26f | 31 | #include <linux/clk.h> |
47dd7a54 GC |
32 | #include <linux/kernel.h> |
33 | #include <linux/interrupt.h> | |
47dd7a54 GC |
34 | #include <linux/ip.h> |
35 | #include <linux/tcp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/crc32.h> | |
40 | #include <linux/mii.h> | |
01789349 | 41 | #include <linux/if.h> |
47dd7a54 GC |
42 | #include <linux/if_vlan.h> |
43 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
db88f10a | 46 | #include <linux/pinctrl/consumer.h> |
50fb4f74 | 47 | #ifdef CONFIG_DEBUG_FS |
7ac29055 GC |
48 | #include <linux/debugfs.h> |
49 | #include <linux/seq_file.h> | |
50fb4f74 | 50 | #endif /* CONFIG_DEBUG_FS */ |
891434b1 RK |
51 | #include <linux/net_tstamp.h> |
52 | #include "stmmac_ptp.h" | |
286a8372 | 53 | #include "stmmac.h" |
c5e4ddbd | 54 | #include <linux/reset.h> |
5790cf3c | 55 | #include <linux/of_mdio.h> |
19d857c9 | 56 | #include "dwmac1000.h" |
47dd7a54 | 57 | |
47dd7a54 | 58 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
47dd7a54 GC |
59 | |
60 | /* Module parameters */ | |
32ceabca | 61 | #define TX_TIMEO 5000 |
47dd7a54 GC |
62 | static int watchdog = TX_TIMEO; |
63 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
32ceabca | 64 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
47dd7a54 | 65 | |
32ceabca | 66 | static int debug = -1; |
47dd7a54 | 67 | module_param(debug, int, S_IRUGO | S_IWUSR); |
32ceabca | 68 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
47dd7a54 | 69 | |
47d1f71f | 70 | static int phyaddr = -1; |
47dd7a54 GC |
71 | module_param(phyaddr, int, S_IRUGO); |
72 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
73 | ||
e3ad57c9 | 74 | #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) |
47dd7a54 GC |
75 | |
76 | static int flow_ctrl = FLOW_OFF; | |
77 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
78 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
79 | ||
80 | static int pause = PAUSE_TIME; | |
81 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
82 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
83 | ||
84 | #define TC_DEFAULT 64 | |
85 | static int tc = TC_DEFAULT; | |
86 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
87 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
88 | ||
d916701c GC |
89 | #define DEFAULT_BUFSIZE 1536 |
90 | static int buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
91 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
92 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
93 | ||
47dd7a54 GC |
94 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
95 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
96 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
97 | ||
d765955d GC |
98 | #define STMMAC_DEFAULT_LPI_TIMER 1000 |
99 | static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
100 | module_param(eee_timer, int, S_IRUGO | S_IWUSR); | |
101 | MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); | |
f5351ef7 | 102 | #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
d765955d | 103 | |
4a7d666a GC |
104 | /* By default the driver will use the ring mode to manage tx and rx descriptors |
105 | * but passing this value so user can force to use the chain instead of the ring | |
106 | */ | |
107 | static unsigned int chain_mode; | |
108 | module_param(chain_mode, int, S_IRUGO); | |
109 | MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); | |
110 | ||
47dd7a54 | 111 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
47dd7a54 | 112 | |
50fb4f74 | 113 | #ifdef CONFIG_DEBUG_FS |
bfab27a1 | 114 | static int stmmac_init_fs(struct net_device *dev); |
466c5ac8 | 115 | static void stmmac_exit_fs(struct net_device *dev); |
bfab27a1 GC |
116 | #endif |
117 | ||
9125cdd1 GC |
118 | #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
119 | ||
47dd7a54 GC |
120 | /** |
121 | * stmmac_verify_args - verify the driver parameters. | |
732fdf0e GC |
122 | * Description: it checks the driver parameters and set a default in case of |
123 | * errors. | |
47dd7a54 GC |
124 | */ |
125 | static void stmmac_verify_args(void) | |
126 | { | |
127 | if (unlikely(watchdog < 0)) | |
128 | watchdog = TX_TIMEO; | |
d916701c GC |
129 | if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
130 | buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
131 | if (unlikely(flow_ctrl > 1)) |
132 | flow_ctrl = FLOW_AUTO; | |
133 | else if (likely(flow_ctrl < 0)) | |
134 | flow_ctrl = FLOW_OFF; | |
135 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
136 | pause = PAUSE_TIME; | |
d765955d GC |
137 | if (eee_timer < 0) |
138 | eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
47dd7a54 GC |
139 | } |
140 | ||
32ceabca GC |
141 | /** |
142 | * stmmac_clk_csr_set - dynamically set the MDC clock | |
143 | * @priv: driver private structure | |
144 | * Description: this is to dynamically set the MDC clock according to the csr | |
145 | * clock input. | |
146 | * Note: | |
147 | * If a specific clk_csr value is passed from the platform | |
148 | * this means that the CSR Clock Range selection cannot be | |
149 | * changed at run-time and it is fixed (as reported in the driver | |
150 | * documentation). Viceversa the driver will try to set the MDC | |
151 | * clock dynamically according to the actual clock input. | |
152 | */ | |
cd7201f4 GC |
153 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
154 | { | |
cd7201f4 GC |
155 | u32 clk_rate; |
156 | ||
157 | clk_rate = clk_get_rate(priv->stmmac_clk); | |
158 | ||
159 | /* Platform provided default clk_csr would be assumed valid | |
ceb69499 GC |
160 | * for all other cases except for the below mentioned ones. |
161 | * For values higher than the IEEE 802.3 specified frequency | |
162 | * we can not estimate the proper divider as it is not known | |
163 | * the frequency of clk_csr_i. So we do not change the default | |
164 | * divider. | |
165 | */ | |
cd7201f4 GC |
166 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
167 | if (clk_rate < CSR_F_35M) | |
168 | priv->clk_csr = STMMAC_CSR_20_35M; | |
169 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
170 | priv->clk_csr = STMMAC_CSR_35_60M; | |
171 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
172 | priv->clk_csr = STMMAC_CSR_60_100M; | |
173 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
174 | priv->clk_csr = STMMAC_CSR_100_150M; | |
175 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
176 | priv->clk_csr = STMMAC_CSR_150_250M; | |
19d857c9 | 177 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) |
cd7201f4 | 178 | priv->clk_csr = STMMAC_CSR_250_300M; |
ceb69499 | 179 | } |
cd7201f4 GC |
180 | } |
181 | ||
47dd7a54 GC |
182 | static void print_pkt(unsigned char *buf, int len) |
183 | { | |
424c4f78 AS |
184 | pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
185 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); | |
47dd7a54 | 186 | } |
47dd7a54 | 187 | |
47dd7a54 GC |
188 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) |
189 | { | |
e3ad57c9 GC |
190 | unsigned avail; |
191 | ||
192 | if (priv->dirty_tx > priv->cur_tx) | |
193 | avail = priv->dirty_tx - priv->cur_tx - 1; | |
194 | else | |
195 | avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; | |
196 | ||
197 | return avail; | |
198 | } | |
199 | ||
200 | static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) | |
201 | { | |
202 | unsigned dirty; | |
203 | ||
204 | if (priv->dirty_rx <= priv->cur_rx) | |
205 | dirty = priv->cur_rx - priv->dirty_rx; | |
206 | else | |
207 | dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; | |
208 | ||
209 | return dirty; | |
47dd7a54 GC |
210 | } |
211 | ||
32ceabca | 212 | /** |
732fdf0e | 213 | * stmmac_hw_fix_mac_speed - callback for speed selection |
32ceabca GC |
214 | * @priv: driver private structure |
215 | * Description: on some platforms (e.g. ST), some HW system configuraton | |
216 | * registers have to be set according to the link speed negotiated. | |
9dfeb4d9 GC |
217 | */ |
218 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
219 | { | |
220 | struct phy_device *phydev = priv->phydev; | |
221 | ||
222 | if (likely(priv->plat->fix_mac_speed)) | |
ceb69499 | 223 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
9dfeb4d9 GC |
224 | } |
225 | ||
32ceabca | 226 | /** |
732fdf0e | 227 | * stmmac_enable_eee_mode - check and enter in LPI mode |
32ceabca | 228 | * @priv: driver private structure |
732fdf0e GC |
229 | * Description: this function is to verify and enter in LPI mode in case of |
230 | * EEE. | |
32ceabca | 231 | */ |
d765955d GC |
232 | static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
233 | { | |
234 | /* Check and enter in LPI mode */ | |
235 | if ((priv->dirty_tx == priv->cur_tx) && | |
236 | (priv->tx_path_in_lpi_mode == false)) | |
7ed24bbe | 237 | priv->hw->mac->set_eee_mode(priv->hw); |
d765955d GC |
238 | } |
239 | ||
32ceabca | 240 | /** |
732fdf0e | 241 | * stmmac_disable_eee_mode - disable and exit from LPI mode |
32ceabca GC |
242 | * @priv: driver private structure |
243 | * Description: this function is to exit and disable EEE in case of | |
244 | * LPI state is true. This is called by the xmit. | |
245 | */ | |
d765955d GC |
246 | void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
247 | { | |
7ed24bbe | 248 | priv->hw->mac->reset_eee_mode(priv->hw); |
d765955d GC |
249 | del_timer_sync(&priv->eee_ctrl_timer); |
250 | priv->tx_path_in_lpi_mode = false; | |
251 | } | |
252 | ||
253 | /** | |
732fdf0e | 254 | * stmmac_eee_ctrl_timer - EEE TX SW timer. |
d765955d GC |
255 | * @arg : data hook |
256 | * Description: | |
32ceabca | 257 | * if there is no data transfer and if we are not in LPI state, |
d765955d GC |
258 | * then MAC Transmitter can be moved to LPI state. |
259 | */ | |
260 | static void stmmac_eee_ctrl_timer(unsigned long arg) | |
261 | { | |
262 | struct stmmac_priv *priv = (struct stmmac_priv *)arg; | |
263 | ||
264 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 265 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d GC |
266 | } |
267 | ||
268 | /** | |
732fdf0e | 269 | * stmmac_eee_init - init EEE |
32ceabca | 270 | * @priv: driver private structure |
d765955d | 271 | * Description: |
732fdf0e GC |
272 | * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
273 | * can also manage EEE, this function enable the LPI state and start related | |
274 | * timer. | |
d765955d GC |
275 | */ |
276 | bool stmmac_eee_init(struct stmmac_priv *priv) | |
277 | { | |
56b88c25 | 278 | char *phy_bus_name = priv->plat->phy_bus_name; |
4741cf9c | 279 | unsigned long flags; |
d765955d GC |
280 | bool ret = false; |
281 | ||
f5351ef7 GC |
282 | /* Using PCS we cannot dial with the phy registers at this stage |
283 | * so we do not support extra feature like EEE. | |
284 | */ | |
285 | if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || | |
286 | (priv->pcs == STMMAC_PCS_RTBI)) | |
287 | goto out; | |
288 | ||
56b88c25 GC |
289 | /* Never init EEE in case of a switch is attached */ |
290 | if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) | |
291 | goto out; | |
292 | ||
d765955d GC |
293 | /* MAC core supports the EEE feature. */ |
294 | if (priv->dma_cap.eee) { | |
83bf79b6 GC |
295 | int tx_lpi_timer = priv->tx_lpi_timer; |
296 | ||
d765955d | 297 | /* Check if the PHY supports EEE */ |
83bf79b6 GC |
298 | if (phy_init_eee(priv->phydev, 1)) { |
299 | /* To manage at run-time if the EEE cannot be supported | |
300 | * anymore (for example because the lp caps have been | |
301 | * changed). | |
302 | * In that case the driver disable own timers. | |
303 | */ | |
4741cf9c | 304 | spin_lock_irqsave(&priv->lock, flags); |
83bf79b6 GC |
305 | if (priv->eee_active) { |
306 | pr_debug("stmmac: disable EEE\n"); | |
307 | del_timer_sync(&priv->eee_ctrl_timer); | |
7ed24bbe | 308 | priv->hw->mac->set_eee_timer(priv->hw, 0, |
83bf79b6 GC |
309 | tx_lpi_timer); |
310 | } | |
311 | priv->eee_active = 0; | |
4741cf9c | 312 | spin_unlock_irqrestore(&priv->lock, flags); |
d765955d | 313 | goto out; |
83bf79b6 GC |
314 | } |
315 | /* Activate the EEE and start timers */ | |
4741cf9c | 316 | spin_lock_irqsave(&priv->lock, flags); |
f5351ef7 GC |
317 | if (!priv->eee_active) { |
318 | priv->eee_active = 1; | |
ccb36da1 VT |
319 | setup_timer(&priv->eee_ctrl_timer, |
320 | stmmac_eee_ctrl_timer, | |
321 | (unsigned long)priv); | |
322 | mod_timer(&priv->eee_ctrl_timer, | |
323 | STMMAC_LPI_T(eee_timer)); | |
f5351ef7 | 324 | |
7ed24bbe | 325 | priv->hw->mac->set_eee_timer(priv->hw, |
f5351ef7 | 326 | STMMAC_DEFAULT_LIT_LS, |
83bf79b6 | 327 | tx_lpi_timer); |
71965352 GC |
328 | } |
329 | /* Set HW EEE according to the speed */ | |
330 | priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); | |
d765955d | 331 | |
d765955d | 332 | ret = true; |
4741cf9c GC |
333 | spin_unlock_irqrestore(&priv->lock, flags); |
334 | ||
335 | pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); | |
d765955d GC |
336 | } |
337 | out: | |
338 | return ret; | |
339 | } | |
340 | ||
732fdf0e | 341 | /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
32ceabca | 342 | * @priv: driver private structure |
891434b1 RK |
343 | * @entry : descriptor index to be used. |
344 | * @skb : the socket buffer | |
345 | * Description : | |
346 | * This function will read timestamp from the descriptor & pass it to stack. | |
347 | * and also perform some sanity checks. | |
348 | */ | |
349 | static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 350 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
351 | { |
352 | struct skb_shared_hwtstamps shhwtstamp; | |
353 | u64 ns; | |
354 | void *desc = NULL; | |
355 | ||
356 | if (!priv->hwts_tx_en) | |
357 | return; | |
358 | ||
ceb69499 | 359 | /* exit if skb doesn't support hw tstamp */ |
75e4364f | 360 | if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
891434b1 RK |
361 | return; |
362 | ||
363 | if (priv->adv_ts) | |
364 | desc = (priv->dma_etx + entry); | |
365 | else | |
366 | desc = (priv->dma_tx + entry); | |
367 | ||
368 | /* check tx tstamp status */ | |
369 | if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) | |
370 | return; | |
371 | ||
372 | /* get the valid tstamp */ | |
373 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
374 | ||
375 | memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
376 | shhwtstamp.hwtstamp = ns_to_ktime(ns); | |
377 | /* pass tstamp to stack */ | |
378 | skb_tstamp_tx(skb, &shhwtstamp); | |
379 | ||
380 | return; | |
381 | } | |
382 | ||
732fdf0e | 383 | /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
32ceabca | 384 | * @priv: driver private structure |
891434b1 RK |
385 | * @entry : descriptor index to be used. |
386 | * @skb : the socket buffer | |
387 | * Description : | |
388 | * This function will read received packet's timestamp from the descriptor | |
389 | * and pass it to stack. It also perform some sanity checks. | |
390 | */ | |
391 | static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 392 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
393 | { |
394 | struct skb_shared_hwtstamps *shhwtstamp = NULL; | |
395 | u64 ns; | |
396 | void *desc = NULL; | |
397 | ||
398 | if (!priv->hwts_rx_en) | |
399 | return; | |
400 | ||
401 | if (priv->adv_ts) | |
402 | desc = (priv->dma_erx + entry); | |
403 | else | |
404 | desc = (priv->dma_rx + entry); | |
405 | ||
ceb69499 | 406 | /* exit if rx tstamp is not valid */ |
891434b1 RK |
407 | if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) |
408 | return; | |
409 | ||
410 | /* get valid tstamp */ | |
411 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
412 | shhwtstamp = skb_hwtstamps(skb); | |
413 | memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
414 | shhwtstamp->hwtstamp = ns_to_ktime(ns); | |
415 | } | |
416 | ||
417 | /** | |
418 | * stmmac_hwtstamp_ioctl - control hardware timestamping. | |
419 | * @dev: device pointer. | |
420 | * @ifr: An IOCTL specefic structure, that can contain a pointer to | |
421 | * a proprietary structure used to pass information to the driver. | |
422 | * Description: | |
423 | * This function configures the MAC to enable/disable both outgoing(TX) | |
424 | * and incoming(RX) packets time stamping based on user input. | |
425 | * Return Value: | |
426 | * 0 on success and an appropriate -ve integer on failure. | |
427 | */ | |
428 | static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) | |
429 | { | |
430 | struct stmmac_priv *priv = netdev_priv(dev); | |
431 | struct hwtstamp_config config; | |
0a624155 | 432 | struct timespec64 now; |
891434b1 RK |
433 | u64 temp = 0; |
434 | u32 ptp_v2 = 0; | |
435 | u32 tstamp_all = 0; | |
436 | u32 ptp_over_ipv4_udp = 0; | |
437 | u32 ptp_over_ipv6_udp = 0; | |
438 | u32 ptp_over_ethernet = 0; | |
439 | u32 snap_type_sel = 0; | |
440 | u32 ts_master_en = 0; | |
441 | u32 ts_event_en = 0; | |
442 | u32 value = 0; | |
19d857c9 | 443 | u32 sec_inc; |
891434b1 RK |
444 | |
445 | if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { | |
446 | netdev_alert(priv->dev, "No support for HW time stamping\n"); | |
447 | priv->hwts_tx_en = 0; | |
448 | priv->hwts_rx_en = 0; | |
449 | ||
450 | return -EOPNOTSUPP; | |
451 | } | |
452 | ||
453 | if (copy_from_user(&config, ifr->ifr_data, | |
ceb69499 | 454 | sizeof(struct hwtstamp_config))) |
891434b1 RK |
455 | return -EFAULT; |
456 | ||
457 | pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
458 | __func__, config.flags, config.tx_type, config.rx_filter); | |
459 | ||
460 | /* reserved for future extensions */ | |
461 | if (config.flags) | |
462 | return -EINVAL; | |
463 | ||
5f3da328 BH |
464 | if (config.tx_type != HWTSTAMP_TX_OFF && |
465 | config.tx_type != HWTSTAMP_TX_ON) | |
891434b1 | 466 | return -ERANGE; |
891434b1 RK |
467 | |
468 | if (priv->adv_ts) { | |
469 | switch (config.rx_filter) { | |
891434b1 | 470 | case HWTSTAMP_FILTER_NONE: |
ceb69499 | 471 | /* time stamp no incoming packet at all */ |
891434b1 RK |
472 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
473 | break; | |
474 | ||
891434b1 | 475 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
ceb69499 | 476 | /* PTP v1, UDP, any kind of event packet */ |
891434b1 RK |
477 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
478 | /* take time stamp for all event messages */ | |
479 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
480 | ||
481 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
482 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
483 | break; | |
484 | ||
891434b1 | 485 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
ceb69499 | 486 | /* PTP v1, UDP, Sync packet */ |
891434b1 RK |
487 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
488 | /* take time stamp for SYNC messages only */ | |
489 | ts_event_en = PTP_TCR_TSEVNTENA; | |
490 | ||
491 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
492 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
493 | break; | |
494 | ||
891434b1 | 495 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
ceb69499 | 496 | /* PTP v1, UDP, Delay_req packet */ |
891434b1 RK |
497 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
498 | /* take time stamp for Delay_Req messages only */ | |
499 | ts_master_en = PTP_TCR_TSMSTRENA; | |
500 | ts_event_en = PTP_TCR_TSEVNTENA; | |
501 | ||
502 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
503 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
504 | break; | |
505 | ||
891434b1 | 506 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
ceb69499 | 507 | /* PTP v2, UDP, any kind of event packet */ |
891434b1 RK |
508 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
509 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
510 | /* take time stamp for all event messages */ | |
511 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
512 | ||
513 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
514 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
515 | break; | |
516 | ||
891434b1 | 517 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
ceb69499 | 518 | /* PTP v2, UDP, Sync packet */ |
891434b1 RK |
519 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
520 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
521 | /* take time stamp for SYNC messages only */ | |
522 | ts_event_en = PTP_TCR_TSEVNTENA; | |
523 | ||
524 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
525 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
526 | break; | |
527 | ||
891434b1 | 528 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
ceb69499 | 529 | /* PTP v2, UDP, Delay_req packet */ |
891434b1 RK |
530 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
531 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
532 | /* take time stamp for Delay_Req messages only */ | |
533 | ts_master_en = PTP_TCR_TSMSTRENA; | |
534 | ts_event_en = PTP_TCR_TSEVNTENA; | |
535 | ||
536 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
537 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
538 | break; | |
539 | ||
891434b1 | 540 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
ceb69499 | 541 | /* PTP v2/802.AS1 any layer, any kind of event packet */ |
891434b1 RK |
542 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
543 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
544 | /* take time stamp for all event messages */ | |
545 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
546 | ||
547 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
548 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
549 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
550 | break; | |
551 | ||
891434b1 | 552 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
ceb69499 | 553 | /* PTP v2/802.AS1, any layer, Sync packet */ |
891434b1 RK |
554 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
555 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
556 | /* take time stamp for SYNC messages only */ | |
557 | ts_event_en = PTP_TCR_TSEVNTENA; | |
558 | ||
559 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
560 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
561 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
562 | break; | |
563 | ||
891434b1 | 564 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
ceb69499 | 565 | /* PTP v2/802.AS1, any layer, Delay_req packet */ |
891434b1 RK |
566 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
567 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
568 | /* take time stamp for Delay_Req messages only */ | |
569 | ts_master_en = PTP_TCR_TSMSTRENA; | |
570 | ts_event_en = PTP_TCR_TSEVNTENA; | |
571 | ||
572 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
573 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
574 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
575 | break; | |
576 | ||
891434b1 | 577 | case HWTSTAMP_FILTER_ALL: |
ceb69499 | 578 | /* time stamp any incoming packet */ |
891434b1 RK |
579 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
580 | tstamp_all = PTP_TCR_TSENALL; | |
581 | break; | |
582 | ||
583 | default: | |
584 | return -ERANGE; | |
585 | } | |
586 | } else { | |
587 | switch (config.rx_filter) { | |
588 | case HWTSTAMP_FILTER_NONE: | |
589 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
590 | break; | |
591 | default: | |
592 | /* PTP v1, UDP, any kind of event packet */ | |
593 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
594 | break; | |
595 | } | |
596 | } | |
597 | priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); | |
5f3da328 | 598 | priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
891434b1 RK |
599 | |
600 | if (!priv->hwts_tx_en && !priv->hwts_rx_en) | |
601 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); | |
602 | else { | |
603 | value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | | |
ceb69499 GC |
604 | tstamp_all | ptp_v2 | ptp_over_ethernet | |
605 | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | | |
606 | ts_master_en | snap_type_sel); | |
891434b1 RK |
607 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); |
608 | ||
609 | /* program Sub Second Increment reg */ | |
19d857c9 PR |
610 | sec_inc = priv->hw->ptp->config_sub_second_increment( |
611 | priv->ioaddr, priv->clk_ptp_rate); | |
612 | temp = div_u64(1000000000ULL, sec_inc); | |
891434b1 RK |
613 | |
614 | /* calculate default added value: | |
615 | * formula is : | |
616 | * addend = (2^32)/freq_div_ratio; | |
19d857c9 | 617 | * where, freq_div_ratio = 1e9ns/sec_inc |
891434b1 | 618 | */ |
19d857c9 | 619 | temp = (u64)(temp << 32); |
5566401f | 620 | priv->default_addend = div_u64(temp, priv->clk_ptp_rate); |
891434b1 RK |
621 | priv->hw->ptp->config_addend(priv->ioaddr, |
622 | priv->default_addend); | |
623 | ||
624 | /* initialize system time */ | |
0a624155 AB |
625 | ktime_get_real_ts64(&now); |
626 | ||
627 | /* lower 32 bits of tv_sec are safe until y2106 */ | |
628 | priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec, | |
891434b1 RK |
629 | now.tv_nsec); |
630 | } | |
631 | ||
632 | return copy_to_user(ifr->ifr_data, &config, | |
633 | sizeof(struct hwtstamp_config)) ? -EFAULT : 0; | |
634 | } | |
635 | ||
32ceabca | 636 | /** |
732fdf0e | 637 | * stmmac_init_ptp - init PTP |
32ceabca | 638 | * @priv: driver private structure |
732fdf0e | 639 | * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
32ceabca | 640 | * This is done by looking at the HW cap. register. |
732fdf0e | 641 | * This function also registers the ptp driver. |
32ceabca | 642 | */ |
92ba6888 | 643 | static int stmmac_init_ptp(struct stmmac_priv *priv) |
891434b1 | 644 | { |
92ba6888 RK |
645 | if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
646 | return -EOPNOTSUPP; | |
647 | ||
5566401f GC |
648 | /* Fall-back to main clock in case of no PTP ref is passed */ |
649 | priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); | |
650 | if (IS_ERR(priv->clk_ptp_ref)) { | |
651 | priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); | |
652 | priv->clk_ptp_ref = NULL; | |
653 | } else { | |
654 | clk_prepare_enable(priv->clk_ptp_ref); | |
655 | priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); | |
656 | } | |
657 | ||
7cd01399 VB |
658 | priv->adv_ts = 0; |
659 | if (priv->dma_cap.atime_stamp && priv->extend_desc) | |
660 | priv->adv_ts = 1; | |
661 | ||
662 | if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) | |
663 | pr_debug("IEEE 1588-2002 Time Stamp supported\n"); | |
664 | ||
665 | if (netif_msg_hw(priv) && priv->adv_ts) | |
666 | pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); | |
891434b1 RK |
667 | |
668 | priv->hw->ptp = &stmmac_ptp; | |
669 | priv->hwts_tx_en = 0; | |
670 | priv->hwts_rx_en = 0; | |
92ba6888 RK |
671 | |
672 | return stmmac_ptp_register(priv); | |
673 | } | |
674 | ||
675 | static void stmmac_release_ptp(struct stmmac_priv *priv) | |
676 | { | |
5566401f GC |
677 | if (priv->clk_ptp_ref) |
678 | clk_disable_unprepare(priv->clk_ptp_ref); | |
92ba6888 | 679 | stmmac_ptp_unregister(priv); |
891434b1 RK |
680 | } |
681 | ||
47dd7a54 | 682 | /** |
732fdf0e | 683 | * stmmac_adjust_link - adjusts the link parameters |
47dd7a54 | 684 | * @dev: net device structure |
732fdf0e GC |
685 | * Description: this is the helper called by the physical abstraction layer |
686 | * drivers to communicate the phy link status. According the speed and duplex | |
687 | * this driver can invoke registered glue-logic as well. | |
688 | * It also invoke the eee initialization because it could happen when switch | |
689 | * on different networks (that are eee capable). | |
47dd7a54 GC |
690 | */ |
691 | static void stmmac_adjust_link(struct net_device *dev) | |
692 | { | |
693 | struct stmmac_priv *priv = netdev_priv(dev); | |
694 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
695 | unsigned long flags; |
696 | int new_state = 0; | |
697 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
698 | ||
699 | if (phydev == NULL) | |
700 | return; | |
701 | ||
47dd7a54 | 702 | spin_lock_irqsave(&priv->lock, flags); |
d765955d | 703 | |
47dd7a54 | 704 | if (phydev->link) { |
ad01b7d4 | 705 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
706 | |
707 | /* Now we make sure that we can be in full duplex mode. | |
708 | * If not, we operate in half-duplex mode. */ | |
709 | if (phydev->duplex != priv->oldduplex) { | |
710 | new_state = 1; | |
711 | if (!(phydev->duplex)) | |
db98a0b0 | 712 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 713 | else |
db98a0b0 | 714 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
715 | priv->oldduplex = phydev->duplex; |
716 | } | |
717 | /* Flow Control operation */ | |
718 | if (phydev->pause) | |
7ed24bbe | 719 | priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, |
db98a0b0 | 720 | fc, pause_time); |
47dd7a54 GC |
721 | |
722 | if (phydev->speed != priv->speed) { | |
723 | new_state = 1; | |
724 | switch (phydev->speed) { | |
725 | case 1000: | |
9dfeb4d9 | 726 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 727 | ctrl &= ~priv->hw->link.port; |
ceb69499 | 728 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
729 | break; |
730 | case 100: | |
731 | case 10: | |
9dfeb4d9 | 732 | if (priv->plat->has_gmac) { |
db98a0b0 | 733 | ctrl |= priv->hw->link.port; |
47dd7a54 | 734 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 735 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 736 | } else { |
db98a0b0 | 737 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
738 | } |
739 | } else { | |
db98a0b0 | 740 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 741 | } |
9dfeb4d9 | 742 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
743 | break; |
744 | default: | |
745 | if (netif_msg_link(priv)) | |
ceb69499 GC |
746 | pr_warn("%s: Speed (%d) not 10/100\n", |
747 | dev->name, phydev->speed); | |
47dd7a54 GC |
748 | break; |
749 | } | |
750 | ||
751 | priv->speed = phydev->speed; | |
752 | } | |
753 | ||
ad01b7d4 | 754 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
755 | |
756 | if (!priv->oldlink) { | |
757 | new_state = 1; | |
758 | priv->oldlink = 1; | |
759 | } | |
760 | } else if (priv->oldlink) { | |
761 | new_state = 1; | |
762 | priv->oldlink = 0; | |
763 | priv->speed = 0; | |
764 | priv->oldduplex = -1; | |
765 | } | |
766 | ||
767 | if (new_state && netif_msg_link(priv)) | |
768 | phy_print_status(phydev); | |
769 | ||
4741cf9c GC |
770 | spin_unlock_irqrestore(&priv->lock, flags); |
771 | ||
f5351ef7 GC |
772 | /* At this stage, it could be needed to setup the EEE or adjust some |
773 | * MAC related HW registers. | |
774 | */ | |
775 | priv->eee_enabled = stmmac_eee_init(priv); | |
47dd7a54 GC |
776 | } |
777 | ||
32ceabca | 778 | /** |
732fdf0e | 779 | * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
32ceabca GC |
780 | * @priv: driver private structure |
781 | * Description: this is to verify if the HW supports the PCS. | |
782 | * Physical Coding Sublayer (PCS) interface that can be used when the MAC is | |
783 | * configured for the TBI, RTBI, or SGMII PHY interface. | |
784 | */ | |
e58bb43f GC |
785 | static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
786 | { | |
787 | int interface = priv->plat->interface; | |
788 | ||
789 | if (priv->dma_cap.pcs) { | |
0d909dcd BA |
790 | if ((interface == PHY_INTERFACE_MODE_RGMII) || |
791 | (interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
792 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
793 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
e58bb43f GC |
794 | pr_debug("STMMAC: PCS RGMII support enable\n"); |
795 | priv->pcs = STMMAC_PCS_RGMII; | |
0d909dcd | 796 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
e58bb43f GC |
797 | pr_debug("STMMAC: PCS SGMII support enable\n"); |
798 | priv->pcs = STMMAC_PCS_SGMII; | |
799 | } | |
800 | } | |
801 | } | |
802 | ||
47dd7a54 GC |
803 | /** |
804 | * stmmac_init_phy - PHY initialization | |
805 | * @dev: net device structure | |
806 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
807 | * to the mac driver. | |
808 | * Return value: | |
809 | * 0 on success | |
810 | */ | |
811 | static int stmmac_init_phy(struct net_device *dev) | |
812 | { | |
813 | struct stmmac_priv *priv = netdev_priv(dev); | |
814 | struct phy_device *phydev; | |
d765955d | 815 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
109cdd66 | 816 | char bus_id[MII_BUS_ID_SIZE]; |
79ee1dc3 | 817 | int interface = priv->plat->interface; |
9cbadf09 | 818 | int max_speed = priv->plat->max_speed; |
47dd7a54 GC |
819 | priv->oldlink = 0; |
820 | priv->speed = 0; | |
821 | priv->oldduplex = -1; | |
822 | ||
5790cf3c MO |
823 | if (priv->plat->phy_node) { |
824 | phydev = of_phy_connect(dev, priv->plat->phy_node, | |
825 | &stmmac_adjust_link, 0, interface); | |
826 | } else { | |
827 | if (priv->plat->phy_bus_name) | |
828 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", | |
829 | priv->plat->phy_bus_name, priv->plat->bus_id); | |
830 | else | |
831 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", | |
832 | priv->plat->bus_id); | |
833 | ||
834 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, | |
835 | priv->plat->phy_addr); | |
836 | pr_debug("stmmac_init_phy: trying to attach to %s\n", | |
837 | phy_id_fmt); | |
838 | ||
839 | phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, | |
840 | interface); | |
841 | } | |
47dd7a54 | 842 | |
dfc50fca | 843 | if (IS_ERR_OR_NULL(phydev)) { |
47dd7a54 | 844 | pr_err("%s: Could not attach to PHY\n", dev->name); |
dfc50fca AB |
845 | if (!phydev) |
846 | return -ENODEV; | |
847 | ||
47dd7a54 GC |
848 | return PTR_ERR(phydev); |
849 | } | |
850 | ||
79ee1dc3 | 851 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 | 852 | if ((interface == PHY_INTERFACE_MODE_MII) || |
9cbadf09 | 853 | (interface == PHY_INTERFACE_MODE_RMII) || |
a77e4acc | 854 | (max_speed < 1000 && max_speed > 0)) |
c5b9b4e4 SK |
855 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
856 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 857 | |
47dd7a54 GC |
858 | /* |
859 | * Broken HW is sometimes missing the pull-up resistor on the | |
860 | * MDIO line, which results in reads to non-existent devices returning | |
861 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
862 | * device as well. | |
863 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
864 | */ | |
27732381 | 865 | if (!priv->plat->phy_node && phydev->phy_id == 0) { |
47dd7a54 GC |
866 | phy_disconnect(phydev); |
867 | return -ENODEV; | |
868 | } | |
8e99fc5f GC |
869 | |
870 | /* If attached to a switch, there is no reason to poll phy handler */ | |
8ecd80a5 FG |
871 | if (priv->plat->phy_bus_name) |
872 | if (!strcmp(priv->plat->phy_bus_name, "fixed")) | |
873 | phydev->irq = PHY_IGNORE_INTERRUPT; | |
8e99fc5f | 874 | |
47dd7a54 | 875 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" |
36bcfe7d | 876 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
877 | |
878 | priv->phydev = phydev; | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
47dd7a54 | 883 | /** |
732fdf0e | 884 | * stmmac_display_ring - display ring |
32ceabca | 885 | * @head: pointer to the head of the ring passed. |
47dd7a54 | 886 | * @size: size of the ring. |
32ceabca | 887 | * @extend_desc: to verify if extended descriptors are used. |
c24602ef | 888 | * Description: display the control/status and buffer descriptors. |
47dd7a54 | 889 | */ |
c24602ef | 890 | static void stmmac_display_ring(void *head, int size, int extend_desc) |
47dd7a54 | 891 | { |
47dd7a54 | 892 | int i; |
ceb69499 GC |
893 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
894 | struct dma_desc *p = (struct dma_desc *)head; | |
c24602ef | 895 | |
47dd7a54 | 896 | for (i = 0; i < size; i++) { |
c24602ef GC |
897 | u64 x; |
898 | if (extend_desc) { | |
899 | x = *(u64 *) ep; | |
900 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
901 | i, (unsigned int)virt_to_phys(ep), |
902 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
903 | ep->basic.des2, ep->basic.des3); |
904 | ep++; | |
905 | } else { | |
906 | x = *(u64 *) p; | |
907 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", | |
ceb69499 GC |
908 | i, (unsigned int)virt_to_phys(p), |
909 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
910 | p->des2, p->des3); |
911 | p++; | |
912 | } | |
47dd7a54 GC |
913 | pr_info("\n"); |
914 | } | |
915 | } | |
916 | ||
c24602ef GC |
917 | static void stmmac_display_rings(struct stmmac_priv *priv) |
918 | { | |
c24602ef GC |
919 | if (priv->extend_desc) { |
920 | pr_info("Extended RX descriptor ring:\n"); | |
e3ad57c9 | 921 | stmmac_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1); |
c24602ef | 922 | pr_info("Extended TX descriptor ring:\n"); |
e3ad57c9 | 923 | stmmac_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1); |
c24602ef GC |
924 | } else { |
925 | pr_info("RX descriptor ring:\n"); | |
e3ad57c9 | 926 | stmmac_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0); |
c24602ef | 927 | pr_info("TX descriptor ring:\n"); |
e3ad57c9 | 928 | stmmac_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0); |
c24602ef GC |
929 | } |
930 | } | |
931 | ||
286a8372 GC |
932 | static int stmmac_set_bfsize(int mtu, int bufsize) |
933 | { | |
934 | int ret = bufsize; | |
935 | ||
936 | if (mtu >= BUF_SIZE_4KiB) | |
937 | ret = BUF_SIZE_8KiB; | |
938 | else if (mtu >= BUF_SIZE_2KiB) | |
939 | ret = BUF_SIZE_4KiB; | |
d916701c | 940 | else if (mtu > DEFAULT_BUFSIZE) |
286a8372 GC |
941 | ret = BUF_SIZE_2KiB; |
942 | else | |
d916701c | 943 | ret = DEFAULT_BUFSIZE; |
286a8372 GC |
944 | |
945 | return ret; | |
946 | } | |
947 | ||
32ceabca | 948 | /** |
732fdf0e | 949 | * stmmac_clear_descriptors - clear descriptors |
32ceabca GC |
950 | * @priv: driver private structure |
951 | * Description: this function is called to clear the tx and rx descriptors | |
952 | * in case of both basic and extended descriptors are used. | |
953 | */ | |
c24602ef GC |
954 | static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
955 | { | |
956 | int i; | |
c24602ef GC |
957 | |
958 | /* Clear the Rx/Tx descriptors */ | |
e3ad57c9 | 959 | for (i = 0; i < DMA_RX_SIZE; i++) |
c24602ef GC |
960 | if (priv->extend_desc) |
961 | priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, | |
962 | priv->use_riwt, priv->mode, | |
e3ad57c9 | 963 | (i == DMA_RX_SIZE - 1)); |
c24602ef GC |
964 | else |
965 | priv->hw->desc->init_rx_desc(&priv->dma_rx[i], | |
966 | priv->use_riwt, priv->mode, | |
e3ad57c9 GC |
967 | (i == DMA_RX_SIZE - 1)); |
968 | for (i = 0; i < DMA_TX_SIZE; i++) | |
c24602ef GC |
969 | if (priv->extend_desc) |
970 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
971 | priv->mode, | |
e3ad57c9 | 972 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
973 | else |
974 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
975 | priv->mode, | |
e3ad57c9 | 976 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
977 | } |
978 | ||
732fdf0e GC |
979 | /** |
980 | * stmmac_init_rx_buffers - init the RX descriptor buffer. | |
981 | * @priv: driver private structure | |
982 | * @p: descriptor pointer | |
983 | * @i: descriptor index | |
984 | * @flags: gfp flag. | |
985 | * Description: this function is called to allocate a receive buffer, perform | |
986 | * the DMA mapping and init the descriptor. | |
987 | */ | |
c24602ef | 988 | static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
777da230 | 989 | int i, gfp_t flags) |
c24602ef GC |
990 | { |
991 | struct sk_buff *skb; | |
992 | ||
4ec49a37 | 993 | skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); |
56329137 | 994 | if (!skb) { |
c24602ef | 995 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); |
56329137 | 996 | return -ENOMEM; |
c24602ef | 997 | } |
c24602ef GC |
998 | priv->rx_skbuff[i] = skb; |
999 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
1000 | priv->dma_buf_sz, | |
1001 | DMA_FROM_DEVICE); | |
56329137 BZ |
1002 | if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { |
1003 | pr_err("%s: DMA mapping error\n", __func__); | |
1004 | dev_kfree_skb_any(skb); | |
1005 | return -EINVAL; | |
1006 | } | |
c24602ef GC |
1007 | |
1008 | p->des2 = priv->rx_skbuff_dma[i]; | |
1009 | ||
29896a67 | 1010 | if ((priv->hw->mode->init_desc3) && |
c24602ef | 1011 | (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
29896a67 | 1012 | priv->hw->mode->init_desc3(p); |
c24602ef GC |
1013 | |
1014 | return 0; | |
1015 | } | |
1016 | ||
56329137 BZ |
1017 | static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) |
1018 | { | |
1019 | if (priv->rx_skbuff[i]) { | |
1020 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
1021 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1022 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
1023 | } | |
1024 | priv->rx_skbuff[i] = NULL; | |
1025 | } | |
1026 | ||
47dd7a54 GC |
1027 | /** |
1028 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
1029 | * @dev: net device structure | |
732fdf0e GC |
1030 | * @flags: gfp flag. |
1031 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
1032 | * and allocates the socket buffers. It suppors the chained and ring |
1033 | * modes. | |
47dd7a54 | 1034 | */ |
777da230 | 1035 | static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
47dd7a54 GC |
1036 | { |
1037 | int i; | |
1038 | struct stmmac_priv *priv = netdev_priv(dev); | |
4a7d666a | 1039 | unsigned int bfsize = 0; |
56329137 | 1040 | int ret = -ENOMEM; |
47dd7a54 | 1041 | |
29896a67 GC |
1042 | if (priv->hw->mode->set_16kib_bfsize) |
1043 | bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); | |
286a8372 | 1044 | |
4a7d666a | 1045 | if (bfsize < BUF_SIZE_16KiB) |
286a8372 | 1046 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 1047 | |
2618abb7 VB |
1048 | priv->dma_buf_sz = bfsize; |
1049 | ||
83d7af64 | 1050 | if (netif_msg_probe(priv)) { |
c24602ef GC |
1051 | pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, |
1052 | (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); | |
47dd7a54 | 1053 | |
83d7af64 GC |
1054 | /* RX INITIALIZATION */ |
1055 | pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); | |
1056 | } | |
e3ad57c9 | 1057 | for (i = 0; i < DMA_RX_SIZE; i++) { |
c24602ef GC |
1058 | struct dma_desc *p; |
1059 | if (priv->extend_desc) | |
1060 | p = &((priv->dma_erx + i)->basic); | |
1061 | else | |
1062 | p = priv->dma_rx + i; | |
47dd7a54 | 1063 | |
777da230 | 1064 | ret = stmmac_init_rx_buffers(priv, p, i, flags); |
56329137 BZ |
1065 | if (ret) |
1066 | goto err_init_rx_buffers; | |
286a8372 | 1067 | |
83d7af64 GC |
1068 | if (netif_msg_probe(priv)) |
1069 | pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], | |
1070 | priv->rx_skbuff[i]->data, | |
1071 | (unsigned int)priv->rx_skbuff_dma[i]); | |
47dd7a54 GC |
1072 | } |
1073 | priv->cur_rx = 0; | |
e3ad57c9 | 1074 | priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); |
47dd7a54 GC |
1075 | buf_sz = bfsize; |
1076 | ||
c24602ef GC |
1077 | /* Setup the chained descriptor addresses */ |
1078 | if (priv->mode == STMMAC_CHAIN_MODE) { | |
1079 | if (priv->extend_desc) { | |
29896a67 | 1080 | priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, |
e3ad57c9 | 1081 | DMA_RX_SIZE, 1); |
29896a67 | 1082 | priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, |
e3ad57c9 | 1083 | DMA_TX_SIZE, 1); |
c24602ef | 1084 | } else { |
29896a67 | 1085 | priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, |
e3ad57c9 | 1086 | DMA_RX_SIZE, 0); |
29896a67 | 1087 | priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, |
e3ad57c9 | 1088 | DMA_TX_SIZE, 0); |
c24602ef GC |
1089 | } |
1090 | } | |
1091 | ||
47dd7a54 | 1092 | /* TX INITIALIZATION */ |
e3ad57c9 | 1093 | for (i = 0; i < DMA_TX_SIZE; i++) { |
c24602ef GC |
1094 | struct dma_desc *p; |
1095 | if (priv->extend_desc) | |
1096 | p = &((priv->dma_etx + i)->basic); | |
1097 | else | |
1098 | p = priv->dma_tx + i; | |
1099 | p->des2 = 0; | |
362b37be GC |
1100 | priv->tx_skbuff_dma[i].buf = 0; |
1101 | priv->tx_skbuff_dma[i].map_as_page = false; | |
553e2ab3 | 1102 | priv->tx_skbuff_dma[i].len = 0; |
2a6d8e17 | 1103 | priv->tx_skbuff_dma[i].last_segment = false; |
47dd7a54 | 1104 | priv->tx_skbuff[i] = NULL; |
47dd7a54 | 1105 | } |
286a8372 | 1106 | |
47dd7a54 GC |
1107 | priv->dirty_tx = 0; |
1108 | priv->cur_tx = 0; | |
38979574 | 1109 | netdev_reset_queue(priv->dev); |
47dd7a54 | 1110 | |
c24602ef | 1111 | stmmac_clear_descriptors(priv); |
47dd7a54 | 1112 | |
c24602ef GC |
1113 | if (netif_msg_hw(priv)) |
1114 | stmmac_display_rings(priv); | |
56329137 BZ |
1115 | |
1116 | return 0; | |
1117 | err_init_rx_buffers: | |
1118 | while (--i >= 0) | |
1119 | stmmac_free_rx_buffers(priv, i); | |
56329137 | 1120 | return ret; |
47dd7a54 GC |
1121 | } |
1122 | ||
1123 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
1124 | { | |
1125 | int i; | |
1126 | ||
e3ad57c9 | 1127 | for (i = 0; i < DMA_RX_SIZE; i++) |
56329137 | 1128 | stmmac_free_rx_buffers(priv, i); |
47dd7a54 GC |
1129 | } |
1130 | ||
1131 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
1132 | { | |
1133 | int i; | |
1134 | ||
e3ad57c9 | 1135 | for (i = 0; i < DMA_TX_SIZE; i++) { |
75e4364f | 1136 | struct dma_desc *p; |
1137 | ||
1138 | if (priv->extend_desc) | |
1139 | p = &((priv->dma_etx + i)->basic); | |
1140 | else | |
1141 | p = priv->dma_tx + i; | |
1142 | ||
362b37be GC |
1143 | if (priv->tx_skbuff_dma[i].buf) { |
1144 | if (priv->tx_skbuff_dma[i].map_as_page) | |
1145 | dma_unmap_page(priv->device, | |
1146 | priv->tx_skbuff_dma[i].buf, | |
553e2ab3 | 1147 | priv->tx_skbuff_dma[i].len, |
362b37be GC |
1148 | DMA_TO_DEVICE); |
1149 | else | |
1150 | dma_unmap_single(priv->device, | |
1151 | priv->tx_skbuff_dma[i].buf, | |
553e2ab3 | 1152 | priv->tx_skbuff_dma[i].len, |
362b37be | 1153 | DMA_TO_DEVICE); |
75e4364f | 1154 | } |
c24602ef | 1155 | |
75e4364f | 1156 | if (priv->tx_skbuff[i] != NULL) { |
47dd7a54 GC |
1157 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1158 | priv->tx_skbuff[i] = NULL; | |
362b37be GC |
1159 | priv->tx_skbuff_dma[i].buf = 0; |
1160 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 GC |
1161 | } |
1162 | } | |
47dd7a54 GC |
1163 | } |
1164 | ||
732fdf0e GC |
1165 | /** |
1166 | * alloc_dma_desc_resources - alloc TX/RX resources. | |
1167 | * @priv: private structure | |
1168 | * Description: according to which descriptor can be used (extend or basic) | |
1169 | * this function allocates the resources for TX and RX paths. In case of | |
1170 | * reception, for example, it pre-allocated the RX socket buffer in order to | |
1171 | * allow zero-copy mechanism. | |
1172 | */ | |
09f8d696 SK |
1173 | static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
1174 | { | |
09f8d696 SK |
1175 | int ret = -ENOMEM; |
1176 | ||
e3ad57c9 | 1177 | priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), |
09f8d696 SK |
1178 | GFP_KERNEL); |
1179 | if (!priv->rx_skbuff_dma) | |
1180 | return -ENOMEM; | |
1181 | ||
e3ad57c9 | 1182 | priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), |
09f8d696 SK |
1183 | GFP_KERNEL); |
1184 | if (!priv->rx_skbuff) | |
1185 | goto err_rx_skbuff; | |
1186 | ||
e3ad57c9 | 1187 | priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, |
362b37be | 1188 | sizeof(*priv->tx_skbuff_dma), |
09f8d696 SK |
1189 | GFP_KERNEL); |
1190 | if (!priv->tx_skbuff_dma) | |
1191 | goto err_tx_skbuff_dma; | |
1192 | ||
e3ad57c9 | 1193 | priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), |
09f8d696 SK |
1194 | GFP_KERNEL); |
1195 | if (!priv->tx_skbuff) | |
1196 | goto err_tx_skbuff; | |
1197 | ||
1198 | if (priv->extend_desc) { | |
e3ad57c9 | 1199 | priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1200 | sizeof(struct |
1201 | dma_extended_desc), | |
1202 | &priv->dma_rx_phy, | |
1203 | GFP_KERNEL); | |
09f8d696 SK |
1204 | if (!priv->dma_erx) |
1205 | goto err_dma; | |
1206 | ||
e3ad57c9 | 1207 | priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * |
f1590670 AB |
1208 | sizeof(struct |
1209 | dma_extended_desc), | |
1210 | &priv->dma_tx_phy, | |
1211 | GFP_KERNEL); | |
09f8d696 | 1212 | if (!priv->dma_etx) { |
e3ad57c9 | 1213 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1214 | sizeof(struct dma_extended_desc), |
1215 | priv->dma_erx, priv->dma_rx_phy); | |
09f8d696 SK |
1216 | goto err_dma; |
1217 | } | |
1218 | } else { | |
e3ad57c9 | 1219 | priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1220 | sizeof(struct dma_desc), |
1221 | &priv->dma_rx_phy, | |
1222 | GFP_KERNEL); | |
09f8d696 SK |
1223 | if (!priv->dma_rx) |
1224 | goto err_dma; | |
1225 | ||
e3ad57c9 | 1226 | priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * |
f1590670 AB |
1227 | sizeof(struct dma_desc), |
1228 | &priv->dma_tx_phy, | |
1229 | GFP_KERNEL); | |
09f8d696 | 1230 | if (!priv->dma_tx) { |
e3ad57c9 | 1231 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1232 | sizeof(struct dma_desc), |
1233 | priv->dma_rx, priv->dma_rx_phy); | |
09f8d696 SK |
1234 | goto err_dma; |
1235 | } | |
1236 | } | |
1237 | ||
1238 | return 0; | |
1239 | ||
1240 | err_dma: | |
1241 | kfree(priv->tx_skbuff); | |
1242 | err_tx_skbuff: | |
1243 | kfree(priv->tx_skbuff_dma); | |
1244 | err_tx_skbuff_dma: | |
1245 | kfree(priv->rx_skbuff); | |
1246 | err_rx_skbuff: | |
1247 | kfree(priv->rx_skbuff_dma); | |
1248 | return ret; | |
1249 | } | |
1250 | ||
47dd7a54 GC |
1251 | static void free_dma_desc_resources(struct stmmac_priv *priv) |
1252 | { | |
1253 | /* Release the DMA TX/RX socket buffers */ | |
1254 | dma_free_rx_skbufs(priv); | |
1255 | dma_free_tx_skbufs(priv); | |
1256 | ||
ceb69499 | 1257 | /* Free DMA regions of consistent memory previously allocated */ |
c24602ef GC |
1258 | if (!priv->extend_desc) { |
1259 | dma_free_coherent(priv->device, | |
e3ad57c9 | 1260 | DMA_TX_SIZE * sizeof(struct dma_desc), |
c24602ef GC |
1261 | priv->dma_tx, priv->dma_tx_phy); |
1262 | dma_free_coherent(priv->device, | |
e3ad57c9 | 1263 | DMA_RX_SIZE * sizeof(struct dma_desc), |
c24602ef GC |
1264 | priv->dma_rx, priv->dma_rx_phy); |
1265 | } else { | |
e3ad57c9 | 1266 | dma_free_coherent(priv->device, DMA_TX_SIZE * |
c24602ef GC |
1267 | sizeof(struct dma_extended_desc), |
1268 | priv->dma_etx, priv->dma_tx_phy); | |
e3ad57c9 | 1269 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
c24602ef GC |
1270 | sizeof(struct dma_extended_desc), |
1271 | priv->dma_erx, priv->dma_rx_phy); | |
1272 | } | |
47dd7a54 GC |
1273 | kfree(priv->rx_skbuff_dma); |
1274 | kfree(priv->rx_skbuff); | |
cf32deec | 1275 | kfree(priv->tx_skbuff_dma); |
47dd7a54 | 1276 | kfree(priv->tx_skbuff); |
47dd7a54 GC |
1277 | } |
1278 | ||
47dd7a54 GC |
1279 | /** |
1280 | * stmmac_dma_operation_mode - HW DMA operation mode | |
32ceabca | 1281 | * @priv: driver private structure |
732fdf0e GC |
1282 | * Description: it is used for configuring the DMA operation mode register in |
1283 | * order to program the tx/rx DMA thresholds or Store-And-Forward mode. | |
47dd7a54 GC |
1284 | */ |
1285 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
1286 | { | |
f88203a2 VB |
1287 | int rxfifosz = priv->plat->rx_fifo_size; |
1288 | ||
e2a240c7 | 1289 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 | 1290 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); |
e2a240c7 | 1291 | else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { |
61b8013a SK |
1292 | /* |
1293 | * In case of GMAC, SF mode can be enabled | |
1294 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
1295 | * 1) TX COE if actually supported |
1296 | * 2) There is no bugged Jumbo frame support | |
1297 | * that needs to not insert csum in the TDES. | |
1298 | */ | |
f88203a2 VB |
1299 | priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, |
1300 | rxfifosz); | |
b2dec116 | 1301 | priv->xstats.threshold = SF_DMA_MODE; |
ebbb293f | 1302 | } else |
f88203a2 VB |
1303 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, |
1304 | rxfifosz); | |
47dd7a54 GC |
1305 | } |
1306 | ||
47dd7a54 | 1307 | /** |
732fdf0e | 1308 | * stmmac_tx_clean - to manage the transmission completion |
32ceabca | 1309 | * @priv: driver private structure |
732fdf0e | 1310 | * Description: it reclaims the transmit resources after transmission completes. |
47dd7a54 | 1311 | */ |
9125cdd1 | 1312 | static void stmmac_tx_clean(struct stmmac_priv *priv) |
47dd7a54 | 1313 | { |
38979574 | 1314 | unsigned int bytes_compl = 0, pkts_compl = 0; |
e3ad57c9 | 1315 | unsigned int entry = priv->dirty_tx; |
47dd7a54 | 1316 | |
a9097a96 GC |
1317 | spin_lock(&priv->tx_lock); |
1318 | ||
9125cdd1 GC |
1319 | priv->xstats.tx_clean++; |
1320 | ||
e3ad57c9 | 1321 | while (entry != priv->cur_tx) { |
47dd7a54 | 1322 | struct sk_buff *skb = priv->tx_skbuff[entry]; |
c24602ef | 1323 | struct dma_desc *p; |
c363b658 | 1324 | int status; |
c24602ef GC |
1325 | |
1326 | if (priv->extend_desc) | |
ceb69499 | 1327 | p = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1328 | else |
1329 | p = priv->dma_tx + entry; | |
47dd7a54 | 1330 | |
c363b658 | 1331 | status = priv->hw->desc->tx_status(&priv->dev->stats, |
ceb69499 GC |
1332 | &priv->xstats, p, |
1333 | priv->ioaddr); | |
c363b658 FG |
1334 | /* Check if the descriptor is owned by the DMA */ |
1335 | if (unlikely(status & tx_dma_own)) | |
1336 | break; | |
1337 | ||
1338 | /* Just consider the last segment and ...*/ | |
1339 | if (likely(!(status & tx_not_ls))) { | |
1340 | /* ... verify the status error condition */ | |
1341 | if (unlikely(status & tx_err)) { | |
1342 | priv->dev->stats.tx_errors++; | |
1343 | } else { | |
47dd7a54 GC |
1344 | priv->dev->stats.tx_packets++; |
1345 | priv->xstats.tx_pkt_n++; | |
c363b658 | 1346 | } |
891434b1 | 1347 | stmmac_get_tx_hwtstamp(priv, entry, skb); |
47dd7a54 | 1348 | } |
47dd7a54 | 1349 | |
362b37be GC |
1350 | if (likely(priv->tx_skbuff_dma[entry].buf)) { |
1351 | if (priv->tx_skbuff_dma[entry].map_as_page) | |
1352 | dma_unmap_page(priv->device, | |
1353 | priv->tx_skbuff_dma[entry].buf, | |
553e2ab3 | 1354 | priv->tx_skbuff_dma[entry].len, |
362b37be GC |
1355 | DMA_TO_DEVICE); |
1356 | else | |
1357 | dma_unmap_single(priv->device, | |
1358 | priv->tx_skbuff_dma[entry].buf, | |
553e2ab3 | 1359 | priv->tx_skbuff_dma[entry].len, |
362b37be GC |
1360 | DMA_TO_DEVICE); |
1361 | priv->tx_skbuff_dma[entry].buf = 0; | |
1362 | priv->tx_skbuff_dma[entry].map_as_page = false; | |
cf32deec | 1363 | } |
29896a67 | 1364 | priv->hw->mode->clean_desc3(priv, p); |
2a6d8e17 | 1365 | priv->tx_skbuff_dma[entry].last_segment = false; |
96951366 | 1366 | priv->tx_skbuff_dma[entry].is_jumbo = false; |
47dd7a54 GC |
1367 | |
1368 | if (likely(skb != NULL)) { | |
38979574 BG |
1369 | pkts_compl++; |
1370 | bytes_compl += skb->len; | |
7c565c33 | 1371 | dev_consume_skb_any(skb); |
47dd7a54 GC |
1372 | priv->tx_skbuff[entry] = NULL; |
1373 | } | |
1374 | ||
4a7d666a | 1375 | priv->hw->desc->release_tx_desc(p, priv->mode); |
47dd7a54 | 1376 | |
e3ad57c9 | 1377 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
47dd7a54 | 1378 | } |
fbc80823 | 1379 | priv->dirty_tx = entry; |
38979574 BG |
1380 | |
1381 | netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); | |
1382 | ||
47dd7a54 | 1383 | if (unlikely(netif_queue_stopped(priv->dev) && |
e3ad57c9 | 1384 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { |
47dd7a54 GC |
1385 | netif_tx_lock(priv->dev); |
1386 | if (netif_queue_stopped(priv->dev) && | |
e3ad57c9 | 1387 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH) { |
83d7af64 GC |
1388 | if (netif_msg_tx_done(priv)) |
1389 | pr_debug("%s: restart transmit\n", __func__); | |
47dd7a54 GC |
1390 | netif_wake_queue(priv->dev); |
1391 | } | |
1392 | netif_tx_unlock(priv->dev); | |
1393 | } | |
d765955d GC |
1394 | |
1395 | if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { | |
1396 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 1397 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d | 1398 | } |
a9097a96 | 1399 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1400 | } |
1401 | ||
9125cdd1 | 1402 | static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1403 | { |
7284a3f1 | 1404 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1405 | } |
1406 | ||
9125cdd1 | 1407 | static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1408 | { |
7284a3f1 | 1409 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1410 | } |
1411 | ||
47dd7a54 | 1412 | /** |
732fdf0e | 1413 | * stmmac_tx_err - to manage the tx error |
32ceabca | 1414 | * @priv: driver private structure |
47dd7a54 | 1415 | * Description: it cleans the descriptors and restarts the transmission |
732fdf0e | 1416 | * in case of transmission errors. |
47dd7a54 GC |
1417 | */ |
1418 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
1419 | { | |
c24602ef | 1420 | int i; |
47dd7a54 GC |
1421 | netif_stop_queue(priv->dev); |
1422 | ||
ad01b7d4 | 1423 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 1424 | dma_free_tx_skbufs(priv); |
e3ad57c9 | 1425 | for (i = 0; i < DMA_TX_SIZE; i++) |
c24602ef GC |
1426 | if (priv->extend_desc) |
1427 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
1428 | priv->mode, | |
e3ad57c9 | 1429 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
1430 | else |
1431 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
1432 | priv->mode, | |
e3ad57c9 | 1433 | (i == DMA_TX_SIZE - 1)); |
47dd7a54 GC |
1434 | priv->dirty_tx = 0; |
1435 | priv->cur_tx = 0; | |
38979574 | 1436 | netdev_reset_queue(priv->dev); |
ad01b7d4 | 1437 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
1438 | |
1439 | priv->dev->stats.tx_errors++; | |
1440 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
1441 | } |
1442 | ||
32ceabca | 1443 | /** |
732fdf0e | 1444 | * stmmac_dma_interrupt - DMA ISR |
32ceabca GC |
1445 | * @priv: driver private structure |
1446 | * Description: this is the DMA ISR. It is called by the main ISR. | |
732fdf0e GC |
1447 | * It calls the dwmac dma routine and schedule poll method in case of some |
1448 | * work can be done. | |
32ceabca | 1449 | */ |
aec7ff27 GC |
1450 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
1451 | { | |
aec7ff27 | 1452 | int status; |
f88203a2 | 1453 | int rxfifosz = priv->plat->rx_fifo_size; |
aec7ff27 | 1454 | |
ad01b7d4 | 1455 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
9125cdd1 GC |
1456 | if (likely((status & handle_rx)) || (status & handle_tx)) { |
1457 | if (likely(napi_schedule_prep(&priv->napi))) { | |
1458 | stmmac_disable_dma_irq(priv); | |
1459 | __napi_schedule(&priv->napi); | |
1460 | } | |
1461 | } | |
1462 | if (unlikely(status & tx_hard_error_bump_tc)) { | |
aec7ff27 | 1463 | /* Try to bump up the dma threshold on this failure */ |
b2dec116 SZ |
1464 | if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && |
1465 | (tc <= 256)) { | |
aec7ff27 | 1466 | tc += 64; |
c405abe2 | 1467 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 VB |
1468 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, |
1469 | rxfifosz); | |
c405abe2 SZ |
1470 | else |
1471 | priv->hw->dma->dma_mode(priv->ioaddr, tc, | |
f88203a2 | 1472 | SF_DMA_MODE, rxfifosz); |
aec7ff27 | 1473 | priv->xstats.threshold = tc; |
47dd7a54 | 1474 | } |
aec7ff27 GC |
1475 | } else if (unlikely(status == tx_hard_error)) |
1476 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1477 | } |
1478 | ||
32ceabca GC |
1479 | /** |
1480 | * stmmac_mmc_setup: setup the Mac Management Counters (MMC) | |
1481 | * @priv: driver private structure | |
1482 | * Description: this masks the MMC irq, in fact, the counters are managed in SW. | |
1483 | */ | |
1c901a46 GC |
1484 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
1485 | { | |
1486 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
ceb69499 | 1487 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
1c901a46 | 1488 | |
1c901a46 | 1489 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
1490 | |
1491 | if (priv->dma_cap.rmon) { | |
1492 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
1493 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
1494 | } else | |
aae54cff | 1495 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
1496 | } |
1497 | ||
732fdf0e GC |
1498 | /** |
1499 | * stmmac_get_synopsys_id - return the SYINID. | |
1500 | * @priv: driver private structure | |
1501 | * Description: this simple function is to decode and return the SYINID | |
1502 | * starting from the HW core register. | |
1503 | */ | |
f0b9d786 GC |
1504 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
1505 | { | |
1506 | u32 hwid = priv->hw->synopsys_uid; | |
1507 | ||
ceb69499 | 1508 | /* Check Synopsys Id (not available on old chips) */ |
f0b9d786 GC |
1509 | if (likely(hwid)) { |
1510 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
1511 | u32 synid = (hwid & 0x000000ff); | |
1512 | ||
cf3f047b | 1513 | pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", |
f0b9d786 GC |
1514 | uid, synid); |
1515 | ||
1516 | return synid; | |
1517 | } | |
1518 | return 0; | |
1519 | } | |
e7434821 | 1520 | |
19e30c14 | 1521 | /** |
732fdf0e | 1522 | * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors |
32ceabca GC |
1523 | * @priv: driver private structure |
1524 | * Description: select the Enhanced/Alternate or Normal descriptors. | |
732fdf0e GC |
1525 | * In case of Enhanced/Alternate, it checks if the extended descriptors are |
1526 | * supported by the HW capability register. | |
ff3dd78c | 1527 | */ |
19e30c14 GC |
1528 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
1529 | { | |
1530 | if (priv->plat->enh_desc) { | |
1531 | pr_info(" Enhanced/Alternate descriptors\n"); | |
c24602ef GC |
1532 | |
1533 | /* GMAC older than 3.50 has no extended descriptors */ | |
1534 | if (priv->synopsys_id >= DWMAC_CORE_3_50) { | |
1535 | pr_info("\tEnabled extended descriptors\n"); | |
1536 | priv->extend_desc = 1; | |
1537 | } else | |
1538 | pr_warn("Extended descriptors not supported\n"); | |
1539 | ||
19e30c14 GC |
1540 | priv->hw->desc = &enh_desc_ops; |
1541 | } else { | |
1542 | pr_info(" Normal descriptors\n"); | |
1543 | priv->hw->desc = &ndesc_ops; | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | /** | |
732fdf0e | 1548 | * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
32ceabca | 1549 | * @priv: driver private structure |
19e30c14 GC |
1550 | * Description: |
1551 | * new GMAC chip generations have a new register to indicate the | |
1552 | * presence of the optional feature/functions. | |
1553 | * This can be also used to override the value passed through the | |
1554 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
1555 | */ |
1556 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
1557 | { | |
5e6efe88 | 1558 | u32 hw_cap = 0; |
3c20f72f | 1559 | |
5e6efe88 GC |
1560 | if (priv->hw->dma->get_hw_feature) { |
1561 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 1562 | |
1db123fb RK |
1563 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
1564 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
1565 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
1566 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
ceb69499 | 1567 | priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; |
1db123fb RK |
1568 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; |
1569 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
1570 | priv->dma_cap.pmt_remote_wake_up = | |
ceb69499 | 1571 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; |
1db123fb | 1572 | priv->dma_cap.pmt_magic_frame = |
ceb69499 | 1573 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; |
19e30c14 | 1574 | /* MMC */ |
1db123fb | 1575 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
ceb69499 | 1576 | /* IEEE 1588-2002 */ |
1db123fb | 1577 | priv->dma_cap.time_stamp = |
ceb69499 GC |
1578 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; |
1579 | /* IEEE 1588-2008 */ | |
1db123fb | 1580 | priv->dma_cap.atime_stamp = |
ceb69499 | 1581 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; |
e7434821 | 1582 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
1583 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
1584 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 1585 | /* TX and RX csum */ |
1db123fb RK |
1586 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
1587 | priv->dma_cap.rx_coe_type1 = | |
ceb69499 | 1588 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; |
1db123fb | 1589 | priv->dma_cap.rx_coe_type2 = |
ceb69499 | 1590 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; |
1db123fb | 1591 | priv->dma_cap.rxfifo_over_2048 = |
ceb69499 | 1592 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; |
e7434821 | 1593 | /* TX and RX number of channels */ |
1db123fb | 1594 | priv->dma_cap.number_rx_channel = |
ceb69499 | 1595 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; |
1db123fb | 1596 | priv->dma_cap.number_tx_channel = |
ceb69499 GC |
1597 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; |
1598 | /* Alternate (enhanced) DESC mode */ | |
1599 | priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
19e30c14 | 1600 | } |
e7434821 GC |
1601 | |
1602 | return hw_cap; | |
1603 | } | |
1604 | ||
32ceabca | 1605 | /** |
732fdf0e | 1606 | * stmmac_check_ether_addr - check if the MAC addr is valid |
32ceabca GC |
1607 | * @priv: driver private structure |
1608 | * Description: | |
1609 | * it is to verify if the MAC address is valid, in case of failures it | |
1610 | * generates a random MAC address | |
1611 | */ | |
bfab27a1 GC |
1612 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
1613 | { | |
bfab27a1 | 1614 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
7ed24bbe | 1615 | priv->hw->mac->get_umac_addr(priv->hw, |
bfab27a1 | 1616 | priv->dev->dev_addr, 0); |
ceb69499 | 1617 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
f2cedb63 | 1618 | eth_hw_addr_random(priv->dev); |
c88460b7 HG |
1619 | pr_info("%s: device MAC address %pM\n", priv->dev->name, |
1620 | priv->dev->dev_addr); | |
bfab27a1 | 1621 | } |
bfab27a1 GC |
1622 | } |
1623 | ||
32ceabca | 1624 | /** |
732fdf0e | 1625 | * stmmac_init_dma_engine - DMA init. |
32ceabca GC |
1626 | * @priv: driver private structure |
1627 | * Description: | |
1628 | * It inits the DMA invoking the specific MAC/GMAC callback. | |
1629 | * Some DMA parameters can be passed from the platform; | |
1630 | * in case of these are not passed a default is kept for the MAC or GMAC. | |
1631 | */ | |
0f1f88a8 GC |
1632 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
1633 | { | |
afea0365 | 1634 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0; |
b9cde0a8 | 1635 | int mixed_burst = 0; |
c24602ef | 1636 | int atds = 0; |
495db273 | 1637 | int ret = 0; |
0f1f88a8 | 1638 | |
0f1f88a8 GC |
1639 | if (priv->plat->dma_cfg) { |
1640 | pbl = priv->plat->dma_cfg->pbl; | |
1641 | fixed_burst = priv->plat->dma_cfg->fixed_burst; | |
b9cde0a8 | 1642 | mixed_burst = priv->plat->dma_cfg->mixed_burst; |
afea0365 | 1643 | aal = priv->plat->dma_cfg->aal; |
0f1f88a8 GC |
1644 | } |
1645 | ||
c24602ef GC |
1646 | if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
1647 | atds = 1; | |
1648 | ||
495db273 GC |
1649 | ret = priv->hw->dma->reset(priv->ioaddr); |
1650 | if (ret) { | |
1651 | dev_err(priv->device, "Failed to reset the dma\n"); | |
1652 | return ret; | |
1653 | } | |
1654 | ||
1655 | priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, | |
afea0365 GC |
1656 | aal, priv->dma_tx_phy, priv->dma_rx_phy, atds); |
1657 | ||
1658 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && | |
1659 | (priv->plat->axi && priv->hw->dma->axi)) | |
1660 | priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); | |
1661 | ||
495db273 | 1662 | return ret; |
0f1f88a8 GC |
1663 | } |
1664 | ||
9125cdd1 | 1665 | /** |
732fdf0e | 1666 | * stmmac_tx_timer - mitigation sw timer for tx. |
9125cdd1 GC |
1667 | * @data: data pointer |
1668 | * Description: | |
1669 | * This is the timer handler to directly invoke the stmmac_tx_clean. | |
1670 | */ | |
1671 | static void stmmac_tx_timer(unsigned long data) | |
1672 | { | |
1673 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
1674 | ||
1675 | stmmac_tx_clean(priv); | |
1676 | } | |
1677 | ||
1678 | /** | |
732fdf0e | 1679 | * stmmac_init_tx_coalesce - init tx mitigation options. |
32ceabca | 1680 | * @priv: driver private structure |
9125cdd1 GC |
1681 | * Description: |
1682 | * This inits the transmit coalesce parameters: i.e. timer rate, | |
1683 | * timer handler and default threshold used for enabling the | |
1684 | * interrupt on completion bit. | |
1685 | */ | |
1686 | static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) | |
1687 | { | |
1688 | priv->tx_coal_frames = STMMAC_TX_FRAMES; | |
1689 | priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; | |
1690 | init_timer(&priv->txtimer); | |
1691 | priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); | |
1692 | priv->txtimer.data = (unsigned long)priv; | |
1693 | priv->txtimer.function = stmmac_tx_timer; | |
1694 | add_timer(&priv->txtimer); | |
1695 | } | |
1696 | ||
523f11b5 | 1697 | /** |
732fdf0e | 1698 | * stmmac_hw_setup - setup mac in a usable state. |
523f11b5 SK |
1699 | * @dev : pointer to the device structure. |
1700 | * Description: | |
732fdf0e GC |
1701 | * this is the main function to setup the HW in a usable state because the |
1702 | * dma engine is reset, the core registers are configured (e.g. AXI, | |
1703 | * Checksum features, timers). The DMA is ready to start receiving and | |
1704 | * transmitting. | |
523f11b5 SK |
1705 | * Return value: |
1706 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1707 | * file on failure. | |
1708 | */ | |
fe131929 | 1709 | static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
523f11b5 SK |
1710 | { |
1711 | struct stmmac_priv *priv = netdev_priv(dev); | |
1712 | int ret; | |
1713 | ||
523f11b5 SK |
1714 | /* DMA initialization and SW reset */ |
1715 | ret = stmmac_init_dma_engine(priv); | |
1716 | if (ret < 0) { | |
1717 | pr_err("%s: DMA engine initialization failed\n", __func__); | |
1718 | return ret; | |
1719 | } | |
1720 | ||
1721 | /* Copy the MAC addr into the HW */ | |
7ed24bbe | 1722 | priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
523f11b5 SK |
1723 | |
1724 | /* If required, perform hw setup of the bus. */ | |
1725 | if (priv->plat->bus_setup) | |
1726 | priv->plat->bus_setup(priv->ioaddr); | |
1727 | ||
1728 | /* Initialize the MAC Core */ | |
7ed24bbe | 1729 | priv->hw->mac->core_init(priv->hw, dev->mtu); |
523f11b5 | 1730 | |
978aded4 GC |
1731 | ret = priv->hw->mac->rx_ipc(priv->hw); |
1732 | if (!ret) { | |
1733 | pr_warn(" RX IPC Checksum Offload disabled\n"); | |
1734 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; | |
d2afb5bd | 1735 | priv->hw->rx_csum = 0; |
978aded4 GC |
1736 | } |
1737 | ||
523f11b5 SK |
1738 | /* Enable the MAC Rx/Tx */ |
1739 | stmmac_set_mac(priv->ioaddr, true); | |
1740 | ||
1741 | /* Set the HW DMA mode and the COE */ | |
1742 | stmmac_dma_operation_mode(priv); | |
1743 | ||
1744 | stmmac_mmc_setup(priv); | |
1745 | ||
fe131929 HC |
1746 | if (init_ptp) { |
1747 | ret = stmmac_init_ptp(priv); | |
1748 | if (ret && ret != -EOPNOTSUPP) | |
1749 | pr_warn("%s: failed PTP initialisation\n", __func__); | |
1750 | } | |
523f11b5 | 1751 | |
50fb4f74 | 1752 | #ifdef CONFIG_DEBUG_FS |
523f11b5 SK |
1753 | ret = stmmac_init_fs(dev); |
1754 | if (ret < 0) | |
1755 | pr_warn("%s: failed debugFS registration\n", __func__); | |
1756 | #endif | |
1757 | /* Start the ball rolling... */ | |
1758 | pr_debug("%s: DMA RX/TX processes started...\n", dev->name); | |
1759 | priv->hw->dma->start_tx(priv->ioaddr); | |
1760 | priv->hw->dma->start_rx(priv->ioaddr); | |
1761 | ||
1762 | /* Dump DMA/MAC registers */ | |
1763 | if (netif_msg_hw(priv)) { | |
7ed24bbe | 1764 | priv->hw->mac->dump_regs(priv->hw); |
523f11b5 SK |
1765 | priv->hw->dma->dump_regs(priv->ioaddr); |
1766 | } | |
1767 | priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; | |
1768 | ||
523f11b5 SK |
1769 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
1770 | priv->rx_riwt = MAX_DMA_RIWT; | |
1771 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | |
1772 | } | |
1773 | ||
1774 | if (priv->pcs && priv->hw->mac->ctrl_ane) | |
7ed24bbe | 1775 | priv->hw->mac->ctrl_ane(priv->hw, 0); |
523f11b5 SK |
1776 | |
1777 | return 0; | |
1778 | } | |
1779 | ||
47dd7a54 GC |
1780 | /** |
1781 | * stmmac_open - open entry point of the driver | |
1782 | * @dev : pointer to the device structure. | |
1783 | * Description: | |
1784 | * This function is the open entry point of the driver. | |
1785 | * Return value: | |
1786 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1787 | * file on failure. | |
1788 | */ | |
1789 | static int stmmac_open(struct net_device *dev) | |
1790 | { | |
1791 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1792 | int ret; |
1793 | ||
4bfcbd7a FV |
1794 | stmmac_check_ether_addr(priv); |
1795 | ||
4d8f0825 BA |
1796 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
1797 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
1798 | ret = stmmac_init_phy(dev); |
1799 | if (ret) { | |
1800 | pr_err("%s: Cannot attach to PHY (error: %d)\n", | |
1801 | __func__, ret); | |
89df20d9 | 1802 | return ret; |
e58bb43f | 1803 | } |
f66ffe28 | 1804 | } |
47dd7a54 | 1805 | |
523f11b5 SK |
1806 | /* Extra statistics */ |
1807 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1808 | priv->xstats.threshold = tc; | |
1809 | ||
47dd7a54 | 1810 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); |
56329137 | 1811 | |
7262b7b2 | 1812 | ret = alloc_dma_desc_resources(priv); |
09f8d696 SK |
1813 | if (ret < 0) { |
1814 | pr_err("%s: DMA descriptors allocation failed\n", __func__); | |
1815 | goto dma_desc_error; | |
1816 | } | |
1817 | ||
777da230 GC |
1818 | ret = init_dma_desc_rings(dev, GFP_KERNEL); |
1819 | if (ret < 0) { | |
1820 | pr_err("%s: DMA descriptors initialization failed\n", __func__); | |
1821 | goto init_error; | |
1822 | } | |
1823 | ||
fe131929 | 1824 | ret = stmmac_hw_setup(dev, true); |
56329137 | 1825 | if (ret < 0) { |
523f11b5 | 1826 | pr_err("%s: Hw setup failed\n", __func__); |
c9324d18 | 1827 | goto init_error; |
47dd7a54 GC |
1828 | } |
1829 | ||
777da230 GC |
1830 | stmmac_init_tx_coalesce(priv); |
1831 | ||
523f11b5 SK |
1832 | if (priv->phydev) |
1833 | phy_start(priv->phydev); | |
47dd7a54 | 1834 | |
f66ffe28 GC |
1835 | /* Request the IRQ lines */ |
1836 | ret = request_irq(dev->irq, stmmac_interrupt, | |
ceb69499 | 1837 | IRQF_SHARED, dev->name, dev); |
f66ffe28 GC |
1838 | if (unlikely(ret < 0)) { |
1839 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1840 | __func__, dev->irq, ret); | |
c9324d18 | 1841 | goto init_error; |
f66ffe28 GC |
1842 | } |
1843 | ||
7a13f8f5 FV |
1844 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1845 | if (priv->wol_irq != dev->irq) { | |
1846 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1847 | IRQF_SHARED, dev->name, dev); | |
1848 | if (unlikely(ret < 0)) { | |
ceb69499 GC |
1849 | pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", |
1850 | __func__, priv->wol_irq, ret); | |
c9324d18 | 1851 | goto wolirq_error; |
7a13f8f5 FV |
1852 | } |
1853 | } | |
1854 | ||
d765955d | 1855 | /* Request the IRQ lines */ |
d7ec8584 | 1856 | if (priv->lpi_irq > 0) { |
d765955d GC |
1857 | ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
1858 | dev->name, dev); | |
1859 | if (unlikely(ret < 0)) { | |
1860 | pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", | |
1861 | __func__, priv->lpi_irq, ret); | |
c9324d18 | 1862 | goto lpiirq_error; |
d765955d GC |
1863 | } |
1864 | } | |
1865 | ||
47dd7a54 | 1866 | napi_enable(&priv->napi); |
47dd7a54 | 1867 | netif_start_queue(dev); |
f66ffe28 | 1868 | |
47dd7a54 | 1869 | return 0; |
f66ffe28 | 1870 | |
c9324d18 | 1871 | lpiirq_error: |
d765955d GC |
1872 | if (priv->wol_irq != dev->irq) |
1873 | free_irq(priv->wol_irq, dev); | |
c9324d18 | 1874 | wolirq_error: |
7a13f8f5 FV |
1875 | free_irq(dev->irq, dev); |
1876 | ||
c9324d18 GC |
1877 | init_error: |
1878 | free_dma_desc_resources(priv); | |
56329137 | 1879 | dma_desc_error: |
f66ffe28 GC |
1880 | if (priv->phydev) |
1881 | phy_disconnect(priv->phydev); | |
4bfcbd7a | 1882 | |
f66ffe28 | 1883 | return ret; |
47dd7a54 GC |
1884 | } |
1885 | ||
1886 | /** | |
1887 | * stmmac_release - close entry point of the driver | |
1888 | * @dev : device pointer. | |
1889 | * Description: | |
1890 | * This is the stop entry point of the driver. | |
1891 | */ | |
1892 | static int stmmac_release(struct net_device *dev) | |
1893 | { | |
1894 | struct stmmac_priv *priv = netdev_priv(dev); | |
1895 | ||
d765955d GC |
1896 | if (priv->eee_enabled) |
1897 | del_timer_sync(&priv->eee_ctrl_timer); | |
1898 | ||
47dd7a54 GC |
1899 | /* Stop and disconnect the PHY */ |
1900 | if (priv->phydev) { | |
1901 | phy_stop(priv->phydev); | |
1902 | phy_disconnect(priv->phydev); | |
1903 | priv->phydev = NULL; | |
1904 | } | |
1905 | ||
1906 | netif_stop_queue(dev); | |
1907 | ||
47dd7a54 | 1908 | napi_disable(&priv->napi); |
47dd7a54 | 1909 | |
9125cdd1 GC |
1910 | del_timer_sync(&priv->txtimer); |
1911 | ||
47dd7a54 GC |
1912 | /* Free the IRQ lines */ |
1913 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1914 | if (priv->wol_irq != dev->irq) |
1915 | free_irq(priv->wol_irq, dev); | |
d7ec8584 | 1916 | if (priv->lpi_irq > 0) |
d765955d | 1917 | free_irq(priv->lpi_irq, dev); |
47dd7a54 GC |
1918 | |
1919 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1920 | priv->hw->dma->stop_tx(priv->ioaddr); |
1921 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1922 | |
1923 | /* Release and free the Rx/Tx resources */ | |
1924 | free_dma_desc_resources(priv); | |
1925 | ||
19449bfc | 1926 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1927 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1928 | |
1929 | netif_carrier_off(dev); | |
1930 | ||
50fb4f74 | 1931 | #ifdef CONFIG_DEBUG_FS |
466c5ac8 | 1932 | stmmac_exit_fs(dev); |
bfab27a1 | 1933 | #endif |
bfab27a1 | 1934 | |
92ba6888 RK |
1935 | stmmac_release_ptp(priv); |
1936 | ||
47dd7a54 GC |
1937 | return 0; |
1938 | } | |
1939 | ||
47dd7a54 | 1940 | /** |
732fdf0e | 1941 | * stmmac_xmit - Tx entry point of the driver |
47dd7a54 GC |
1942 | * @skb : the socket buffer |
1943 | * @dev : device pointer | |
32ceabca GC |
1944 | * Description : this is the tx entry point of the driver. |
1945 | * It programs the chain or the ring and supports oversized frames | |
1946 | * and SG feature. | |
47dd7a54 GC |
1947 | */ |
1948 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1949 | { | |
1950 | struct stmmac_priv *priv = netdev_priv(dev); | |
0e80bdc9 | 1951 | unsigned int nopaged_len = skb_headlen(skb); |
4a7d666a | 1952 | int i, csum_insertion = 0, is_jumbo = 0; |
47dd7a54 | 1953 | int nfrags = skb_shinfo(skb)->nr_frags; |
0e80bdc9 | 1954 | unsigned int entry, first_entry; |
47dd7a54 | 1955 | struct dma_desc *desc, *first; |
0e80bdc9 | 1956 | unsigned int enh_desc; |
47dd7a54 | 1957 | |
16ee817e FG |
1958 | spin_lock(&priv->tx_lock); |
1959 | ||
47dd7a54 | 1960 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { |
16ee817e | 1961 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1962 | if (!netif_queue_stopped(dev)) { |
1963 | netif_stop_queue(dev); | |
1964 | /* This is a hard error, log it. */ | |
ceb69499 | 1965 | pr_err("%s: Tx Ring full when queue awake\n", __func__); |
47dd7a54 GC |
1966 | } |
1967 | return NETDEV_TX_BUSY; | |
1968 | } | |
1969 | ||
d765955d GC |
1970 | if (priv->tx_path_in_lpi_mode) |
1971 | stmmac_disable_eee_mode(priv); | |
1972 | ||
e3ad57c9 | 1973 | entry = priv->cur_tx; |
0e80bdc9 | 1974 | first_entry = entry; |
47dd7a54 | 1975 | |
5e982f3b | 1976 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 | 1977 | |
0e80bdc9 | 1978 | if (likely(priv->extend_desc)) |
ceb69499 | 1979 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1980 | else |
1981 | desc = priv->dma_tx + entry; | |
1982 | ||
47dd7a54 GC |
1983 | first = desc; |
1984 | ||
0e80bdc9 GC |
1985 | priv->tx_skbuff[first_entry] = skb; |
1986 | ||
1987 | enh_desc = priv->plat->enh_desc; | |
4a7d666a | 1988 | /* To program the descriptors according to the size of the frame */ |
29896a67 GC |
1989 | if (enh_desc) |
1990 | is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); | |
1991 | ||
0e80bdc9 | 1992 | if (unlikely(is_jumbo)) { |
29896a67 | 1993 | entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); |
362b37be GC |
1994 | if (unlikely(entry < 0)) |
1995 | goto dma_map_err; | |
29896a67 | 1996 | } |
47dd7a54 GC |
1997 | |
1998 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1999 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2000 | int len = skb_frag_size(frag); | |
be434d50 | 2001 | bool last_segment = (i == (nfrags - 1)); |
47dd7a54 | 2002 | |
e3ad57c9 GC |
2003 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
2004 | ||
0e80bdc9 | 2005 | if (likely(priv->extend_desc)) |
ceb69499 | 2006 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
2007 | else |
2008 | desc = priv->dma_tx + entry; | |
47dd7a54 | 2009 | |
f722380d IC |
2010 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
2011 | DMA_TO_DEVICE); | |
362b37be GC |
2012 | if (dma_mapping_error(priv->device, desc->des2)) |
2013 | goto dma_map_err; /* should reuse desc w/o issues */ | |
2014 | ||
0e80bdc9 | 2015 | priv->tx_skbuff[entry] = NULL; |
362b37be GC |
2016 | priv->tx_skbuff_dma[entry].buf = desc->des2; |
2017 | priv->tx_skbuff_dma[entry].map_as_page = true; | |
553e2ab3 | 2018 | priv->tx_skbuff_dma[entry].len = len; |
0e80bdc9 GC |
2019 | priv->tx_skbuff_dma[entry].last_segment = last_segment; |
2020 | ||
2021 | /* Prepare the descriptor and set the own bit too */ | |
4a7d666a | 2022 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
be434d50 | 2023 | priv->mode, 1, last_segment); |
47dd7a54 GC |
2024 | } |
2025 | ||
e3ad57c9 GC |
2026 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
2027 | ||
2028 | priv->cur_tx = entry; | |
47dd7a54 | 2029 | |
47dd7a54 | 2030 | if (netif_msg_pktdata(priv)) { |
0e80bdc9 GC |
2031 | pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", |
2032 | __func__, priv->cur_tx, priv->dirty_tx, first_entry, | |
2033 | entry, first, nfrags); | |
83d7af64 | 2034 | |
c24602ef | 2035 | if (priv->extend_desc) |
e3ad57c9 GC |
2036 | stmmac_display_ring((void *)priv->dma_etx, |
2037 | DMA_TX_SIZE, 1); | |
c24602ef | 2038 | else |
e3ad57c9 GC |
2039 | stmmac_display_ring((void *)priv->dma_tx, |
2040 | DMA_TX_SIZE, 0); | |
c24602ef | 2041 | |
83d7af64 | 2042 | pr_debug(">>> frame to be transmitted: "); |
47dd7a54 GC |
2043 | print_pkt(skb->data, skb->len); |
2044 | } | |
0e80bdc9 | 2045 | |
47dd7a54 | 2046 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { |
83d7af64 GC |
2047 | if (netif_msg_hw(priv)) |
2048 | pr_debug("%s: stop transmitted packets\n", __func__); | |
47dd7a54 GC |
2049 | netif_stop_queue(dev); |
2050 | } | |
2051 | ||
2052 | dev->stats.tx_bytes += skb->len; | |
2053 | ||
0e80bdc9 GC |
2054 | /* According to the coalesce parameter the IC bit for the latest |
2055 | * segment is reset and the timer re-started to clean the tx status. | |
2056 | * This approach takes care about the fragments: desc is the first | |
2057 | * element in case of no SG. | |
2058 | */ | |
2059 | priv->tx_count_frames += nfrags + 1; | |
2060 | if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { | |
2061 | mod_timer(&priv->txtimer, | |
2062 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2063 | } else { | |
2064 | priv->tx_count_frames = 0; | |
2065 | priv->hw->desc->set_tx_ic(desc); | |
2066 | priv->xstats.tx_set_ic_bit++; | |
891434b1 RK |
2067 | } |
2068 | ||
2069 | if (!priv->hwts_tx_en) | |
2070 | skb_tx_timestamp(skb); | |
3e82ce12 | 2071 | |
0e80bdc9 GC |
2072 | /* Ready to fill the first descriptor and set the OWN bit w/o any |
2073 | * problems because all the descriptors are actually ready to be | |
2074 | * passed to the DMA engine. | |
2075 | */ | |
2076 | if (likely(!is_jumbo)) { | |
2077 | bool last_segment = (nfrags == 0); | |
2078 | ||
2079 | first->des2 = dma_map_single(priv->device, skb->data, | |
2080 | nopaged_len, DMA_TO_DEVICE); | |
2081 | if (dma_mapping_error(priv->device, first->des2)) | |
2082 | goto dma_map_err; | |
2083 | ||
2084 | priv->tx_skbuff_dma[first_entry].buf = first->des2; | |
2085 | priv->tx_skbuff_dma[first_entry].len = nopaged_len; | |
2086 | priv->tx_skbuff_dma[first_entry].last_segment = last_segment; | |
2087 | ||
2088 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2089 | priv->hwts_tx_en)) { | |
2090 | /* declare that device is doing timestamping */ | |
2091 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2092 | priv->hw->desc->enable_tx_timestamp(first); | |
2093 | } | |
2094 | ||
2095 | /* Prepare the first descriptor setting the OWN bit too */ | |
2096 | priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, | |
2097 | csum_insertion, priv->mode, 1, | |
2098 | last_segment); | |
2099 | ||
2100 | /* The own bit must be the latest setting done when prepare the | |
2101 | * descriptor and then barrier is needed to make sure that | |
2102 | * all is coherent before granting the DMA engine. | |
2103 | */ | |
2104 | smp_wmb(); | |
2105 | } | |
2106 | ||
38979574 | 2107 | netdev_sent_queue(dev, skb->len); |
52f64fae RC |
2108 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
2109 | ||
a9097a96 | 2110 | spin_unlock(&priv->tx_lock); |
362b37be | 2111 | return NETDEV_TX_OK; |
a9097a96 | 2112 | |
362b37be | 2113 | dma_map_err: |
758a0ab5 | 2114 | spin_unlock(&priv->tx_lock); |
362b37be GC |
2115 | dev_err(priv->device, "Tx dma map failed\n"); |
2116 | dev_kfree_skb(skb); | |
2117 | priv->dev->stats.tx_dropped++; | |
47dd7a54 GC |
2118 | return NETDEV_TX_OK; |
2119 | } | |
2120 | ||
b9381985 VB |
2121 | static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) |
2122 | { | |
2123 | struct ethhdr *ehdr; | |
2124 | u16 vlanid; | |
2125 | ||
2126 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == | |
2127 | NETIF_F_HW_VLAN_CTAG_RX && | |
2128 | !__vlan_get_tag(skb, &vlanid)) { | |
2129 | /* pop the vlan tag */ | |
2130 | ehdr = (struct ethhdr *)skb->data; | |
2131 | memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); | |
2132 | skb_pull(skb, VLAN_HLEN); | |
2133 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); | |
2134 | } | |
2135 | } | |
2136 | ||
2137 | ||
32ceabca | 2138 | /** |
732fdf0e | 2139 | * stmmac_rx_refill - refill used skb preallocated buffers |
32ceabca GC |
2140 | * @priv: driver private structure |
2141 | * Description : this is to reallocate the skb for the reception process | |
2142 | * that is based on zero-copy. | |
2143 | */ | |
47dd7a54 GC |
2144 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) |
2145 | { | |
47dd7a54 | 2146 | int bfsize = priv->dma_buf_sz; |
e3ad57c9 GC |
2147 | unsigned int entry = priv->dirty_rx; |
2148 | int dirty = stmmac_rx_dirty(priv); | |
47dd7a54 | 2149 | |
e3ad57c9 | 2150 | while (dirty-- > 0) { |
c24602ef GC |
2151 | struct dma_desc *p; |
2152 | ||
2153 | if (priv->extend_desc) | |
ceb69499 | 2154 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef GC |
2155 | else |
2156 | p = priv->dma_rx + entry; | |
2157 | ||
47dd7a54 GC |
2158 | if (likely(priv->rx_skbuff[entry] == NULL)) { |
2159 | struct sk_buff *skb; | |
2160 | ||
acb600de | 2161 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
47dd7a54 GC |
2162 | |
2163 | if (unlikely(skb == NULL)) | |
2164 | break; | |
2165 | ||
2166 | priv->rx_skbuff[entry] = skb; | |
2167 | priv->rx_skbuff_dma[entry] = | |
2168 | dma_map_single(priv->device, skb->data, bfsize, | |
2169 | DMA_FROM_DEVICE); | |
362b37be GC |
2170 | if (dma_mapping_error(priv->device, |
2171 | priv->rx_skbuff_dma[entry])) { | |
2172 | dev_err(priv->device, "Rx dma map failed\n"); | |
2173 | dev_kfree_skb(skb); | |
2174 | break; | |
2175 | } | |
c24602ef | 2176 | p->des2 = priv->rx_skbuff_dma[entry]; |
286a8372 | 2177 | |
29896a67 | 2178 | priv->hw->mode->refill_desc3(priv, p); |
286a8372 | 2179 | |
83d7af64 GC |
2180 | if (netif_msg_rx_status(priv)) |
2181 | pr_debug("\trefill entry #%d\n", entry); | |
47dd7a54 | 2182 | } |
eb0dc4bb | 2183 | wmb(); |
c24602ef | 2184 | priv->hw->desc->set_rx_owner(p); |
8e839891 | 2185 | wmb(); |
e3ad57c9 GC |
2186 | |
2187 | entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); | |
47dd7a54 | 2188 | } |
e3ad57c9 | 2189 | priv->dirty_rx = entry; |
47dd7a54 GC |
2190 | } |
2191 | ||
32ceabca | 2192 | /** |
732fdf0e | 2193 | * stmmac_rx - manage the receive process |
32ceabca GC |
2194 | * @priv: driver private structure |
2195 | * @limit: napi bugget. | |
2196 | * Description : this the function called by the napi poll method. | |
2197 | * It gets all the frames inside the ring. | |
2198 | */ | |
47dd7a54 GC |
2199 | static int stmmac_rx(struct stmmac_priv *priv, int limit) |
2200 | { | |
e3ad57c9 | 2201 | unsigned int entry = priv->cur_rx; |
47dd7a54 GC |
2202 | unsigned int next_entry; |
2203 | unsigned int count = 0; | |
d2afb5bd | 2204 | int coe = priv->hw->rx_csum; |
47dd7a54 | 2205 | |
83d7af64 GC |
2206 | if (netif_msg_rx_status(priv)) { |
2207 | pr_debug("%s: descriptor ring:\n", __func__); | |
c24602ef | 2208 | if (priv->extend_desc) |
e3ad57c9 GC |
2209 | stmmac_display_ring((void *)priv->dma_erx, |
2210 | DMA_RX_SIZE, 1); | |
c24602ef | 2211 | else |
e3ad57c9 GC |
2212 | stmmac_display_ring((void *)priv->dma_rx, |
2213 | DMA_RX_SIZE, 0); | |
47dd7a54 | 2214 | } |
c24602ef | 2215 | while (count < limit) { |
47dd7a54 | 2216 | int status; |
9401bb5c | 2217 | struct dma_desc *p; |
47dd7a54 | 2218 | |
c24602ef | 2219 | if (priv->extend_desc) |
ceb69499 | 2220 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef | 2221 | else |
ceb69499 | 2222 | p = priv->dma_rx + entry; |
c24602ef | 2223 | |
c1fa3212 FG |
2224 | /* read the status of the incoming frame */ |
2225 | status = priv->hw->desc->rx_status(&priv->dev->stats, | |
2226 | &priv->xstats, p); | |
2227 | /* check if managed by the DMA otherwise go ahead */ | |
2228 | if (unlikely(status & dma_own)) | |
47dd7a54 GC |
2229 | break; |
2230 | ||
2231 | count++; | |
2232 | ||
e3ad57c9 GC |
2233 | priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); |
2234 | next_entry = priv->cur_rx; | |
2235 | ||
c24602ef | 2236 | if (priv->extend_desc) |
9401bb5c | 2237 | prefetch(priv->dma_erx + next_entry); |
c24602ef | 2238 | else |
9401bb5c | 2239 | prefetch(priv->dma_rx + next_entry); |
47dd7a54 | 2240 | |
c24602ef GC |
2241 | if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) |
2242 | priv->hw->desc->rx_extended_status(&priv->dev->stats, | |
2243 | &priv->xstats, | |
2244 | priv->dma_erx + | |
2245 | entry); | |
891434b1 | 2246 | if (unlikely(status == discard_frame)) { |
47dd7a54 | 2247 | priv->dev->stats.rx_errors++; |
891434b1 RK |
2248 | if (priv->hwts_rx_en && !priv->extend_desc) { |
2249 | /* DESC2 & DESC3 will be overwitten by device | |
2250 | * with timestamp value, hence reinitialize | |
2251 | * them in stmmac_rx_refill() function so that | |
2252 | * device can reuse it. | |
2253 | */ | |
2254 | priv->rx_skbuff[entry] = NULL; | |
2255 | dma_unmap_single(priv->device, | |
ceb69499 GC |
2256 | priv->rx_skbuff_dma[entry], |
2257 | priv->dma_buf_sz, | |
2258 | DMA_FROM_DEVICE); | |
891434b1 RK |
2259 | } |
2260 | } else { | |
47dd7a54 | 2261 | struct sk_buff *skb; |
3eeb2997 | 2262 | int frame_len; |
47dd7a54 | 2263 | |
ceb69499 GC |
2264 | frame_len = priv->hw->desc->get_rx_frame_len(p, coe); |
2265 | ||
e527c4a7 GC |
2266 | /* check if frame_len fits the preallocated memory */ |
2267 | if (frame_len > priv->dma_buf_sz) { | |
2268 | priv->dev->stats.rx_length_errors++; | |
2269 | break; | |
2270 | } | |
2271 | ||
3eeb2997 | 2272 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
ceb69499 GC |
2273 | * Type frames (LLC/LLC-SNAP) |
2274 | */ | |
3eeb2997 GC |
2275 | if (unlikely(status != llc_snap)) |
2276 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 | 2277 | |
83d7af64 | 2278 | if (netif_msg_rx_status(priv)) { |
47dd7a54 | 2279 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", |
ceb69499 | 2280 | p, entry, p->des2); |
83d7af64 GC |
2281 | if (frame_len > ETH_FRAME_LEN) |
2282 | pr_debug("\tframe size %d, COE: %d\n", | |
2283 | frame_len, status); | |
2284 | } | |
47dd7a54 GC |
2285 | skb = priv->rx_skbuff[entry]; |
2286 | if (unlikely(!skb)) { | |
2287 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
ceb69499 | 2288 | priv->dev->name); |
47dd7a54 GC |
2289 | priv->dev->stats.rx_dropped++; |
2290 | break; | |
2291 | } | |
2292 | prefetch(skb->data - NET_IP_ALIGN); | |
2293 | priv->rx_skbuff[entry] = NULL; | |
2294 | ||
891434b1 RK |
2295 | stmmac_get_rx_hwtstamp(priv, entry, skb); |
2296 | ||
47dd7a54 GC |
2297 | skb_put(skb, frame_len); |
2298 | dma_unmap_single(priv->device, | |
2299 | priv->rx_skbuff_dma[entry], | |
2300 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
83d7af64 | 2301 | |
47dd7a54 | 2302 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 2303 | pr_debug("frame received (%dbytes)", frame_len); |
47dd7a54 GC |
2304 | print_pkt(skb->data, frame_len); |
2305 | } | |
83d7af64 | 2306 | |
b9381985 VB |
2307 | stmmac_rx_vlan(priv->dev, skb); |
2308 | ||
47dd7a54 GC |
2309 | skb->protocol = eth_type_trans(skb, priv->dev); |
2310 | ||
ceb69499 | 2311 | if (unlikely(!coe)) |
bc8acf2c | 2312 | skb_checksum_none_assert(skb); |
62a2ab93 | 2313 | else |
47dd7a54 | 2314 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
62a2ab93 GC |
2315 | |
2316 | napi_gro_receive(&priv->napi, skb); | |
47dd7a54 GC |
2317 | |
2318 | priv->dev->stats.rx_packets++; | |
2319 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
2320 | } |
2321 | entry = next_entry; | |
47dd7a54 GC |
2322 | } |
2323 | ||
2324 | stmmac_rx_refill(priv); | |
2325 | ||
2326 | priv->xstats.rx_pkt_n += count; | |
2327 | ||
2328 | return count; | |
2329 | } | |
2330 | ||
2331 | /** | |
2332 | * stmmac_poll - stmmac poll method (NAPI) | |
2333 | * @napi : pointer to the napi structure. | |
2334 | * @budget : maximum number of packets that the current CPU can receive from | |
2335 | * all interfaces. | |
2336 | * Description : | |
9125cdd1 | 2337 | * To look at the incoming frames and clear the tx resources. |
47dd7a54 GC |
2338 | */ |
2339 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
2340 | { | |
2341 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
2342 | int work_done = 0; | |
2343 | ||
9125cdd1 GC |
2344 | priv->xstats.napi_poll++; |
2345 | stmmac_tx_clean(priv); | |
47dd7a54 | 2346 | |
9125cdd1 | 2347 | work_done = stmmac_rx(priv, budget); |
47dd7a54 GC |
2348 | if (work_done < budget) { |
2349 | napi_complete(napi); | |
9125cdd1 | 2350 | stmmac_enable_dma_irq(priv); |
47dd7a54 GC |
2351 | } |
2352 | return work_done; | |
2353 | } | |
2354 | ||
2355 | /** | |
2356 | * stmmac_tx_timeout | |
2357 | * @dev : Pointer to net device structure | |
2358 | * Description: this function is called when a packet transmission fails to | |
7284a3f1 | 2359 | * complete within a reasonable time. The driver will mark the error in the |
47dd7a54 GC |
2360 | * netdev structure and arrange for the device to be reset to a sane state |
2361 | * in order to transmit a new packet. | |
2362 | */ | |
2363 | static void stmmac_tx_timeout(struct net_device *dev) | |
2364 | { | |
2365 | struct stmmac_priv *priv = netdev_priv(dev); | |
2366 | ||
2367 | /* Clear Tx resources and restart transmitting again */ | |
2368 | stmmac_tx_err(priv); | |
47dd7a54 GC |
2369 | } |
2370 | ||
47dd7a54 | 2371 | /** |
01789349 | 2372 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
2373 | * @dev : pointer to the device structure |
2374 | * Description: | |
2375 | * This function is a driver entry point which gets called by the kernel | |
2376 | * whenever multicast addresses must be enabled/disabled. | |
2377 | * Return value: | |
2378 | * void. | |
2379 | */ | |
01789349 | 2380 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
2381 | { |
2382 | struct stmmac_priv *priv = netdev_priv(dev); | |
2383 | ||
3b57de95 | 2384 | priv->hw->mac->set_filter(priv->hw, dev); |
47dd7a54 GC |
2385 | } |
2386 | ||
2387 | /** | |
2388 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
2389 | * @dev : device pointer. | |
2390 | * @new_mtu : the new MTU size for the device. | |
2391 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
2392 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
2393 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
2394 | * Return value: | |
2395 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
2396 | * file on failure. | |
2397 | */ | |
2398 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
2399 | { | |
2400 | struct stmmac_priv *priv = netdev_priv(dev); | |
2401 | int max_mtu; | |
2402 | ||
2403 | if (netif_running(dev)) { | |
2404 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
2405 | return -EBUSY; | |
2406 | } | |
2407 | ||
48febf7e | 2408 | if (priv->plat->enh_desc) |
47dd7a54 GC |
2409 | max_mtu = JUMBO_LEN; |
2410 | else | |
45db81e1 | 2411 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 | 2412 | |
2618abb7 VB |
2413 | if (priv->plat->maxmtu < max_mtu) |
2414 | max_mtu = priv->plat->maxmtu; | |
2415 | ||
47dd7a54 GC |
2416 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { |
2417 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
2418 | return -EINVAL; | |
2419 | } | |
2420 | ||
5e982f3b MM |
2421 | dev->mtu = new_mtu; |
2422 | netdev_update_features(dev); | |
2423 | ||
2424 | return 0; | |
2425 | } | |
2426 | ||
c8f44aff | 2427 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
ceb69499 | 2428 | netdev_features_t features) |
5e982f3b MM |
2429 | { |
2430 | struct stmmac_priv *priv = netdev_priv(dev); | |
2431 | ||
38912bdb | 2432 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 2433 | features &= ~NETIF_F_RXCSUM; |
d2afb5bd | 2434 | |
5e982f3b | 2435 | if (!priv->plat->tx_coe) |
a188222b | 2436 | features &= ~NETIF_F_CSUM_MASK; |
5e982f3b | 2437 | |
ebbb293f GC |
2438 | /* Some GMAC devices have a bugged Jumbo frame support that |
2439 | * needs to have the Tx COE disabled for oversized frames | |
2440 | * (due to limited buffer sizes). In this case we disable | |
ceb69499 GC |
2441 | * the TX csum insertionin the TDES and not use SF. |
2442 | */ | |
5e982f3b | 2443 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
a188222b | 2444 | features &= ~NETIF_F_CSUM_MASK; |
ebbb293f | 2445 | |
5e982f3b | 2446 | return features; |
47dd7a54 GC |
2447 | } |
2448 | ||
d2afb5bd GC |
2449 | static int stmmac_set_features(struct net_device *netdev, |
2450 | netdev_features_t features) | |
2451 | { | |
2452 | struct stmmac_priv *priv = netdev_priv(netdev); | |
2453 | ||
2454 | /* Keep the COE Type in case of csum is supporting */ | |
2455 | if (features & NETIF_F_RXCSUM) | |
2456 | priv->hw->rx_csum = priv->plat->rx_coe; | |
2457 | else | |
2458 | priv->hw->rx_csum = 0; | |
2459 | /* No check needed because rx_coe has been set before and it will be | |
2460 | * fixed in case of issue. | |
2461 | */ | |
2462 | priv->hw->mac->rx_ipc(priv->hw); | |
2463 | ||
2464 | return 0; | |
2465 | } | |
2466 | ||
32ceabca GC |
2467 | /** |
2468 | * stmmac_interrupt - main ISR | |
2469 | * @irq: interrupt number. | |
2470 | * @dev_id: to pass the net device pointer. | |
2471 | * Description: this is the main driver interrupt service routine. | |
732fdf0e GC |
2472 | * It can call: |
2473 | * o DMA service routine (to manage incoming frame reception and transmission | |
2474 | * status) | |
2475 | * o Core interrupts to manage: remote wake-up, management counter, LPI | |
2476 | * interrupts. | |
32ceabca | 2477 | */ |
47dd7a54 GC |
2478 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) |
2479 | { | |
2480 | struct net_device *dev = (struct net_device *)dev_id; | |
2481 | struct stmmac_priv *priv = netdev_priv(dev); | |
2482 | ||
89f7f2cf SK |
2483 | if (priv->irq_wake) |
2484 | pm_wakeup_event(priv->device, 0); | |
2485 | ||
47dd7a54 GC |
2486 | if (unlikely(!dev)) { |
2487 | pr_err("%s: invalid dev pointer\n", __func__); | |
2488 | return IRQ_NONE; | |
2489 | } | |
2490 | ||
d765955d GC |
2491 | /* To handle GMAC own interrupts */ |
2492 | if (priv->plat->has_gmac) { | |
7ed24bbe | 2493 | int status = priv->hw->mac->host_irq_status(priv->hw, |
0982a0f6 | 2494 | &priv->xstats); |
d765955d | 2495 | if (unlikely(status)) { |
d765955d | 2496 | /* For LPI we need to save the tx status */ |
0982a0f6 | 2497 | if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) |
d765955d | 2498 | priv->tx_path_in_lpi_mode = true; |
0982a0f6 | 2499 | if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) |
d765955d | 2500 | priv->tx_path_in_lpi_mode = false; |
d765955d GC |
2501 | } |
2502 | } | |
aec7ff27 | 2503 | |
d765955d | 2504 | /* To handle DMA interrupts */ |
aec7ff27 | 2505 | stmmac_dma_interrupt(priv); |
47dd7a54 GC |
2506 | |
2507 | return IRQ_HANDLED; | |
2508 | } | |
2509 | ||
2510 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2511 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
ceb69499 GC |
2512 | * to allow network I/O with interrupts disabled. |
2513 | */ | |
47dd7a54 GC |
2514 | static void stmmac_poll_controller(struct net_device *dev) |
2515 | { | |
2516 | disable_irq(dev->irq); | |
2517 | stmmac_interrupt(dev->irq, dev); | |
2518 | enable_irq(dev->irq); | |
2519 | } | |
2520 | #endif | |
2521 | ||
2522 | /** | |
2523 | * stmmac_ioctl - Entry point for the Ioctl | |
2524 | * @dev: Device pointer. | |
2525 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
2526 | * a proprietary structure used to pass information to the driver. | |
2527 | * @cmd: IOCTL command | |
2528 | * Description: | |
32ceabca | 2529 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
47dd7a54 GC |
2530 | */ |
2531 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2532 | { | |
2533 | struct stmmac_priv *priv = netdev_priv(dev); | |
891434b1 | 2534 | int ret = -EOPNOTSUPP; |
47dd7a54 GC |
2535 | |
2536 | if (!netif_running(dev)) | |
2537 | return -EINVAL; | |
2538 | ||
891434b1 RK |
2539 | switch (cmd) { |
2540 | case SIOCGMIIPHY: | |
2541 | case SIOCGMIIREG: | |
2542 | case SIOCSMIIREG: | |
2543 | if (!priv->phydev) | |
2544 | return -EINVAL; | |
2545 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
2546 | break; | |
2547 | case SIOCSHWTSTAMP: | |
2548 | ret = stmmac_hwtstamp_ioctl(dev, rq); | |
2549 | break; | |
2550 | default: | |
2551 | break; | |
2552 | } | |
28b04113 | 2553 | |
47dd7a54 GC |
2554 | return ret; |
2555 | } | |
2556 | ||
50fb4f74 | 2557 | #ifdef CONFIG_DEBUG_FS |
7ac29055 | 2558 | static struct dentry *stmmac_fs_dir; |
7ac29055 | 2559 | |
c24602ef | 2560 | static void sysfs_display_ring(void *head, int size, int extend_desc, |
ceb69499 | 2561 | struct seq_file *seq) |
7ac29055 | 2562 | { |
7ac29055 | 2563 | int i; |
ceb69499 GC |
2564 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
2565 | struct dma_desc *p = (struct dma_desc *)head; | |
7ac29055 | 2566 | |
c24602ef GC |
2567 | for (i = 0; i < size; i++) { |
2568 | u64 x; | |
2569 | if (extend_desc) { | |
2570 | x = *(u64 *) ep; | |
2571 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2572 | i, (unsigned int)virt_to_phys(ep), |
2573 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2574 | ep->basic.des2, ep->basic.des3); |
2575 | ep++; | |
2576 | } else { | |
2577 | x = *(u64 *) p; | |
2578 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2579 | i, (unsigned int)virt_to_phys(ep), |
2580 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2581 | p->des2, p->des3); |
2582 | p++; | |
2583 | } | |
7ac29055 GC |
2584 | seq_printf(seq, "\n"); |
2585 | } | |
c24602ef | 2586 | } |
7ac29055 | 2587 | |
c24602ef GC |
2588 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) |
2589 | { | |
2590 | struct net_device *dev = seq->private; | |
2591 | struct stmmac_priv *priv = netdev_priv(dev); | |
7ac29055 | 2592 | |
c24602ef GC |
2593 | if (priv->extend_desc) { |
2594 | seq_printf(seq, "Extended RX descriptor ring:\n"); | |
e3ad57c9 | 2595 | sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); |
c24602ef | 2596 | seq_printf(seq, "Extended TX descriptor ring:\n"); |
e3ad57c9 | 2597 | sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); |
c24602ef GC |
2598 | } else { |
2599 | seq_printf(seq, "RX descriptor ring:\n"); | |
e3ad57c9 | 2600 | sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); |
c24602ef | 2601 | seq_printf(seq, "TX descriptor ring:\n"); |
e3ad57c9 | 2602 | sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); |
7ac29055 GC |
2603 | } |
2604 | ||
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
2609 | { | |
2610 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
2611 | } | |
2612 | ||
2613 | static const struct file_operations stmmac_rings_status_fops = { | |
2614 | .owner = THIS_MODULE, | |
2615 | .open = stmmac_sysfs_ring_open, | |
2616 | .read = seq_read, | |
2617 | .llseek = seq_lseek, | |
74863948 | 2618 | .release = single_release, |
7ac29055 GC |
2619 | }; |
2620 | ||
e7434821 GC |
2621 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
2622 | { | |
2623 | struct net_device *dev = seq->private; | |
2624 | struct stmmac_priv *priv = netdev_priv(dev); | |
2625 | ||
19e30c14 | 2626 | if (!priv->hw_cap_support) { |
e7434821 GC |
2627 | seq_printf(seq, "DMA HW features not supported\n"); |
2628 | return 0; | |
2629 | } | |
2630 | ||
2631 | seq_printf(seq, "==============================\n"); | |
2632 | seq_printf(seq, "\tDMA HW features\n"); | |
2633 | seq_printf(seq, "==============================\n"); | |
2634 | ||
2635 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
2636 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
2637 | seq_printf(seq, "\t1000 Mbps %s\n", | |
2638 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
2639 | seq_printf(seq, "\tHalf duple %s\n", | |
2640 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
2641 | seq_printf(seq, "\tHash Filter: %s\n", | |
2642 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
2643 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
2644 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
2645 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
2646 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
2647 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
2648 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
2649 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
2650 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
2651 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
2652 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
2653 | seq_printf(seq, "\tRMON module: %s\n", | |
2654 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
2655 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
2656 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
2657 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
2658 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
2659 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
2660 | (priv->dma_cap.eee) ? "Y" : "N"); | |
2661 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
2662 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
2663 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
2664 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
2665 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
2666 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
2667 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
2668 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
2669 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
2670 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
2671 | priv->dma_cap.number_rx_channel); | |
2672 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
2673 | priv->dma_cap.number_tx_channel); | |
2674 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
2675 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
2676 | ||
2677 | return 0; | |
2678 | } | |
2679 | ||
2680 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
2681 | { | |
2682 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
2683 | } | |
2684 | ||
2685 | static const struct file_operations stmmac_dma_cap_fops = { | |
2686 | .owner = THIS_MODULE, | |
2687 | .open = stmmac_sysfs_dma_cap_open, | |
2688 | .read = seq_read, | |
2689 | .llseek = seq_lseek, | |
74863948 | 2690 | .release = single_release, |
e7434821 GC |
2691 | }; |
2692 | ||
7ac29055 GC |
2693 | static int stmmac_init_fs(struct net_device *dev) |
2694 | { | |
466c5ac8 MO |
2695 | struct stmmac_priv *priv = netdev_priv(dev); |
2696 | ||
2697 | /* Create per netdev entries */ | |
2698 | priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); | |
7ac29055 | 2699 | |
466c5ac8 MO |
2700 | if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { |
2701 | pr_err("ERROR %s/%s, debugfs create directory failed\n", | |
2702 | STMMAC_RESOURCE_NAME, dev->name); | |
7ac29055 GC |
2703 | |
2704 | return -ENOMEM; | |
2705 | } | |
2706 | ||
2707 | /* Entry to report DMA RX/TX rings */ | |
466c5ac8 MO |
2708 | priv->dbgfs_rings_status = |
2709 | debugfs_create_file("descriptors_status", S_IRUGO, | |
2710 | priv->dbgfs_dir, dev, | |
2711 | &stmmac_rings_status_fops); | |
7ac29055 | 2712 | |
466c5ac8 | 2713 | if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { |
7ac29055 | 2714 | pr_info("ERROR creating stmmac ring debugfs file\n"); |
466c5ac8 | 2715 | debugfs_remove_recursive(priv->dbgfs_dir); |
7ac29055 GC |
2716 | |
2717 | return -ENOMEM; | |
2718 | } | |
2719 | ||
e7434821 | 2720 | /* Entry to report the DMA HW features */ |
466c5ac8 MO |
2721 | priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, |
2722 | priv->dbgfs_dir, | |
2723 | dev, &stmmac_dma_cap_fops); | |
e7434821 | 2724 | |
466c5ac8 | 2725 | if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { |
e7434821 | 2726 | pr_info("ERROR creating stmmac MMC debugfs file\n"); |
466c5ac8 | 2727 | debugfs_remove_recursive(priv->dbgfs_dir); |
e7434821 GC |
2728 | |
2729 | return -ENOMEM; | |
2730 | } | |
2731 | ||
7ac29055 GC |
2732 | return 0; |
2733 | } | |
2734 | ||
466c5ac8 | 2735 | static void stmmac_exit_fs(struct net_device *dev) |
7ac29055 | 2736 | { |
466c5ac8 MO |
2737 | struct stmmac_priv *priv = netdev_priv(dev); |
2738 | ||
2739 | debugfs_remove_recursive(priv->dbgfs_dir); | |
7ac29055 | 2740 | } |
50fb4f74 | 2741 | #endif /* CONFIG_DEBUG_FS */ |
7ac29055 | 2742 | |
47dd7a54 GC |
2743 | static const struct net_device_ops stmmac_netdev_ops = { |
2744 | .ndo_open = stmmac_open, | |
2745 | .ndo_start_xmit = stmmac_xmit, | |
2746 | .ndo_stop = stmmac_release, | |
2747 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 2748 | .ndo_fix_features = stmmac_fix_features, |
d2afb5bd | 2749 | .ndo_set_features = stmmac_set_features, |
01789349 | 2750 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
2751 | .ndo_tx_timeout = stmmac_tx_timeout, |
2752 | .ndo_do_ioctl = stmmac_ioctl, | |
47dd7a54 GC |
2753 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2754 | .ndo_poll_controller = stmmac_poll_controller, | |
2755 | #endif | |
2756 | .ndo_set_mac_address = eth_mac_addr, | |
2757 | }; | |
2758 | ||
cf3f047b GC |
2759 | /** |
2760 | * stmmac_hw_init - Init the MAC device | |
32ceabca | 2761 | * @priv: driver private structure |
732fdf0e GC |
2762 | * Description: this function is to configure the MAC device according to |
2763 | * some platform parameters or the HW capability register. It prepares the | |
2764 | * driver to use either ring or chain modes and to setup either enhanced or | |
2765 | * normal descriptors. | |
cf3f047b GC |
2766 | */ |
2767 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
2768 | { | |
cf3f047b GC |
2769 | struct mac_device_info *mac; |
2770 | ||
2771 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
2772 | if (priv->plat->has_gmac) { |
2773 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3b57de95 VB |
2774 | mac = dwmac1000_setup(priv->ioaddr, |
2775 | priv->plat->multicast_filter_bins, | |
2776 | priv->plat->unicast_filter_entries); | |
03f2eecd | 2777 | } else { |
cf3f047b | 2778 | mac = dwmac100_setup(priv->ioaddr); |
03f2eecd | 2779 | } |
cf3f047b GC |
2780 | if (!mac) |
2781 | return -ENOMEM; | |
2782 | ||
2783 | priv->hw = mac; | |
2784 | ||
cf3f047b | 2785 | /* Get and dump the chip ID */ |
cffb13f4 | 2786 | priv->synopsys_id = stmmac_get_synopsys_id(priv); |
cf3f047b | 2787 | |
4a7d666a | 2788 | /* To use the chained or ring mode */ |
ceb69499 | 2789 | if (chain_mode) { |
29896a67 | 2790 | priv->hw->mode = &chain_mode_ops; |
4a7d666a GC |
2791 | pr_info(" Chain mode enabled\n"); |
2792 | priv->mode = STMMAC_CHAIN_MODE; | |
2793 | } else { | |
29896a67 | 2794 | priv->hw->mode = &ring_mode_ops; |
4a7d666a GC |
2795 | pr_info(" Ring mode enabled\n"); |
2796 | priv->mode = STMMAC_RING_MODE; | |
2797 | } | |
2798 | ||
cf3f047b GC |
2799 | /* Get the HW capability (new GMAC newer than 3.50a) */ |
2800 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
2801 | if (priv->hw_cap_support) { | |
2802 | pr_info(" DMA HW capability register supported"); | |
2803 | ||
2804 | /* We can override some gmac/dma configuration fields: e.g. | |
2805 | * enh_desc, tx_coe (e.g. that are passed through the | |
2806 | * platform) with the values from the HW capability | |
2807 | * register (if supported). | |
2808 | */ | |
2809 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 2810 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
38912bdb | 2811 | |
dec2165f SZ |
2812 | /* TXCOE doesn't work in thresh DMA mode */ |
2813 | if (priv->plat->force_thresh_dma_mode) | |
2814 | priv->plat->tx_coe = 0; | |
2815 | else | |
2816 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
38912bdb DS |
2817 | |
2818 | if (priv->dma_cap.rx_coe_type2) | |
2819 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
2820 | else if (priv->dma_cap.rx_coe_type1) | |
2821 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
2822 | ||
cf3f047b GC |
2823 | } else |
2824 | pr_info(" No HW DMA feature register supported"); | |
2825 | ||
61369d02 BA |
2826 | /* To use alternate (extended) or normal descriptor structures */ |
2827 | stmmac_selec_desc_mode(priv); | |
2828 | ||
d2afb5bd GC |
2829 | if (priv->plat->rx_coe) { |
2830 | priv->hw->rx_csum = priv->plat->rx_coe; | |
38912bdb DS |
2831 | pr_info(" RX Checksum Offload Engine supported (type %d)\n", |
2832 | priv->plat->rx_coe); | |
d2afb5bd | 2833 | } |
cf3f047b GC |
2834 | if (priv->plat->tx_coe) |
2835 | pr_info(" TX Checksum insertion supported\n"); | |
2836 | ||
2837 | if (priv->plat->pmt) { | |
2838 | pr_info(" Wake-Up On Lan supported\n"); | |
2839 | device_set_wakeup_capable(priv->device, 1); | |
2840 | } | |
2841 | ||
c24602ef | 2842 | return 0; |
cf3f047b GC |
2843 | } |
2844 | ||
47dd7a54 | 2845 | /** |
bfab27a1 GC |
2846 | * stmmac_dvr_probe |
2847 | * @device: device pointer | |
ff3dd78c | 2848 | * @plat_dat: platform data pointer |
e56788cf | 2849 | * @res: stmmac resource pointer |
bfab27a1 GC |
2850 | * Description: this is the main probe function used to |
2851 | * call the alloc_etherdev, allocate the priv structure. | |
9afec6ef | 2852 | * Return: |
15ffac73 | 2853 | * returns 0 on success, otherwise errno. |
47dd7a54 | 2854 | */ |
15ffac73 JE |
2855 | int stmmac_dvr_probe(struct device *device, |
2856 | struct plat_stmmacenet_data *plat_dat, | |
2857 | struct stmmac_resources *res) | |
47dd7a54 GC |
2858 | { |
2859 | int ret = 0; | |
bfab27a1 GC |
2860 | struct net_device *ndev = NULL; |
2861 | struct stmmac_priv *priv; | |
47dd7a54 | 2862 | |
bfab27a1 | 2863 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 2864 | if (!ndev) |
15ffac73 | 2865 | return -ENOMEM; |
bfab27a1 GC |
2866 | |
2867 | SET_NETDEV_DEV(ndev, device); | |
2868 | ||
2869 | priv = netdev_priv(ndev); | |
2870 | priv->device = device; | |
2871 | priv->dev = ndev; | |
47dd7a54 | 2872 | |
bfab27a1 | 2873 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
2874 | priv->pause = pause; |
2875 | priv->plat = plat_dat; | |
e56788cf JE |
2876 | priv->ioaddr = res->addr; |
2877 | priv->dev->base_addr = (unsigned long)res->addr; | |
2878 | ||
2879 | priv->dev->irq = res->irq; | |
2880 | priv->wol_irq = res->wol_irq; | |
2881 | priv->lpi_irq = res->lpi_irq; | |
2882 | ||
2883 | if (res->mac) | |
2884 | memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); | |
cf3f047b | 2885 | |
a7a62685 | 2886 | dev_set_drvdata(device, priv->dev); |
803f8fc4 | 2887 | |
cf3f047b GC |
2888 | /* Verify driver arguments */ |
2889 | stmmac_verify_args(); | |
bfab27a1 | 2890 | |
cf3f047b | 2891 | /* Override with kernel parameters if supplied XXX CRS XXX |
ceb69499 GC |
2892 | * this needs to have multiple instances |
2893 | */ | |
cf3f047b GC |
2894 | if ((phyaddr >= 0) && (phyaddr <= 31)) |
2895 | priv->plat->phy_addr = phyaddr; | |
2896 | ||
62866e98 CYT |
2897 | priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); |
2898 | if (IS_ERR(priv->stmmac_clk)) { | |
2899 | dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", | |
2900 | __func__); | |
c5bb86c3 KHL |
2901 | /* If failed to obtain stmmac_clk and specific clk_csr value |
2902 | * is NOT passed from the platform, probe fail. | |
2903 | */ | |
2904 | if (!priv->plat->clk_csr) { | |
2905 | ret = PTR_ERR(priv->stmmac_clk); | |
2906 | goto error_clk_get; | |
2907 | } else { | |
2908 | priv->stmmac_clk = NULL; | |
2909 | } | |
62866e98 CYT |
2910 | } |
2911 | clk_prepare_enable(priv->stmmac_clk); | |
2912 | ||
5f9755d2 AB |
2913 | priv->pclk = devm_clk_get(priv->device, "pclk"); |
2914 | if (IS_ERR(priv->pclk)) { | |
2915 | if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { | |
2916 | ret = -EPROBE_DEFER; | |
2917 | goto error_pclk_get; | |
2918 | } | |
2919 | priv->pclk = NULL; | |
2920 | } | |
2921 | clk_prepare_enable(priv->pclk); | |
2922 | ||
c5e4ddbd CYT |
2923 | priv->stmmac_rst = devm_reset_control_get(priv->device, |
2924 | STMMAC_RESOURCE_NAME); | |
2925 | if (IS_ERR(priv->stmmac_rst)) { | |
2926 | if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { | |
2927 | ret = -EPROBE_DEFER; | |
2928 | goto error_hw_init; | |
2929 | } | |
2930 | dev_info(priv->device, "no reset control found\n"); | |
2931 | priv->stmmac_rst = NULL; | |
2932 | } | |
2933 | if (priv->stmmac_rst) | |
2934 | reset_control_deassert(priv->stmmac_rst); | |
2935 | ||
cf3f047b | 2936 | /* Init MAC and get the capabilities */ |
c24602ef GC |
2937 | ret = stmmac_hw_init(priv); |
2938 | if (ret) | |
62866e98 | 2939 | goto error_hw_init; |
cf3f047b GC |
2940 | |
2941 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 2942 | |
cf3f047b GC |
2943 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2944 | NETIF_F_RXCSUM; | |
bfab27a1 GC |
2945 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
2946 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
2947 | #ifdef STMMAC_VLAN_TAG_USED |
2948 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
f646968f | 2949 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; |
47dd7a54 GC |
2950 | #endif |
2951 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
2952 | ||
47dd7a54 GC |
2953 | if (flow_ctrl) |
2954 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
2955 | ||
62a2ab93 GC |
2956 | /* Rx Watchdog is available in the COREs newer than the 3.40. |
2957 | * In some case, for example on bugged HW this feature | |
2958 | * has to be disable and this can be done by passing the | |
2959 | * riwt_off field from the platform. | |
2960 | */ | |
2961 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { | |
2962 | priv->use_riwt = 1; | |
2963 | pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); | |
2964 | } | |
2965 | ||
bfab27a1 | 2966 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 2967 | |
f8e96161 | 2968 | spin_lock_init(&priv->lock); |
a9097a96 | 2969 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 2970 | |
bfab27a1 | 2971 | ret = register_netdev(ndev); |
47dd7a54 | 2972 | if (ret) { |
cf3f047b | 2973 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
6a81c26f | 2974 | goto error_netdev_register; |
47dd7a54 GC |
2975 | } |
2976 | ||
cd7201f4 GC |
2977 | /* If a specific clk_csr value is passed from the platform |
2978 | * this means that the CSR Clock Range selection cannot be | |
2979 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
2980 | * set the MDC clock dynamically according to the csr actual | |
2981 | * clock input. | |
2982 | */ | |
2983 | if (!priv->plat->clk_csr) | |
2984 | stmmac_clk_csr_set(priv); | |
2985 | else | |
2986 | priv->clk_csr = priv->plat->clk_csr; | |
2987 | ||
e58bb43f GC |
2988 | stmmac_check_pcs_mode(priv); |
2989 | ||
4d8f0825 BA |
2990 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
2991 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
2992 | /* MDIO bus Registration */ |
2993 | ret = stmmac_mdio_register(ndev); | |
2994 | if (ret < 0) { | |
2995 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
2996 | __func__, priv->plat->bus_id); | |
2997 | goto error_mdio_register; | |
2998 | } | |
4bfcbd7a FV |
2999 | } |
3000 | ||
15ffac73 | 3001 | return 0; |
47dd7a54 | 3002 | |
6a81c26f | 3003 | error_mdio_register: |
34a52f36 | 3004 | unregister_netdev(ndev); |
6a81c26f VK |
3005 | error_netdev_register: |
3006 | netif_napi_del(&priv->napi); | |
62866e98 | 3007 | error_hw_init: |
5f9755d2 AB |
3008 | clk_disable_unprepare(priv->pclk); |
3009 | error_pclk_get: | |
62866e98 CYT |
3010 | clk_disable_unprepare(priv->stmmac_clk); |
3011 | error_clk_get: | |
34a52f36 | 3012 | free_netdev(ndev); |
47dd7a54 | 3013 | |
15ffac73 | 3014 | return ret; |
47dd7a54 | 3015 | } |
b2e2f0c7 | 3016 | EXPORT_SYMBOL_GPL(stmmac_dvr_probe); |
47dd7a54 GC |
3017 | |
3018 | /** | |
3019 | * stmmac_dvr_remove | |
bfab27a1 | 3020 | * @ndev: net device pointer |
47dd7a54 | 3021 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 3022 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 3023 | */ |
bfab27a1 | 3024 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 3025 | { |
aec7ff27 | 3026 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
3027 | |
3028 | pr_info("%s:\n\tremoving driver", __func__); | |
3029 | ||
ad01b7d4 GC |
3030 | priv->hw->dma->stop_rx(priv->ioaddr); |
3031 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 3032 | |
bfab27a1 | 3033 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 | 3034 | netif_carrier_off(ndev); |
47dd7a54 | 3035 | unregister_netdev(ndev); |
c5e4ddbd CYT |
3036 | if (priv->stmmac_rst) |
3037 | reset_control_assert(priv->stmmac_rst); | |
5f9755d2 | 3038 | clk_disable_unprepare(priv->pclk); |
62866e98 | 3039 | clk_disable_unprepare(priv->stmmac_clk); |
e743471f BD |
3040 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
3041 | priv->pcs != STMMAC_PCS_RTBI) | |
3042 | stmmac_mdio_unregister(ndev); | |
47dd7a54 GC |
3043 | free_netdev(ndev); |
3044 | ||
3045 | return 0; | |
3046 | } | |
b2e2f0c7 | 3047 | EXPORT_SYMBOL_GPL(stmmac_dvr_remove); |
47dd7a54 | 3048 | |
732fdf0e GC |
3049 | /** |
3050 | * stmmac_suspend - suspend callback | |
3051 | * @ndev: net device pointer | |
3052 | * Description: this is the function to suspend the device and it is called | |
3053 | * by the platform driver to stop the network queue, release the resources, | |
3054 | * program the PMT register (for WoL), clean and release driver resources. | |
3055 | */ | |
bfab27a1 | 3056 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 3057 | { |
874bd42d | 3058 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3059 | unsigned long flags; |
47dd7a54 | 3060 | |
874bd42d | 3061 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
3062 | return 0; |
3063 | ||
102463b1 FV |
3064 | if (priv->phydev) |
3065 | phy_stop(priv->phydev); | |
3066 | ||
f8c5a875 | 3067 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 3068 | |
874bd42d GC |
3069 | netif_device_detach(ndev); |
3070 | netif_stop_queue(ndev); | |
47dd7a54 | 3071 | |
874bd42d GC |
3072 | napi_disable(&priv->napi); |
3073 | ||
3074 | /* Stop TX/RX DMA */ | |
3075 | priv->hw->dma->stop_tx(priv->ioaddr); | |
3076 | priv->hw->dma->stop_rx(priv->ioaddr); | |
c24602ef | 3077 | |
874bd42d | 3078 | /* Enable Power down mode by programming the PMT regs */ |
89f7f2cf | 3079 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3080 | priv->hw->mac->pmt(priv->hw, priv->wolopts); |
89f7f2cf SK |
3081 | priv->irq_wake = 1; |
3082 | } else { | |
bfab27a1 | 3083 | stmmac_set_mac(priv->ioaddr, false); |
db88f10a | 3084 | pinctrl_pm_select_sleep_state(priv->device); |
ba1377ff | 3085 | /* Disable clock in case of PWM is off */ |
5f9755d2 | 3086 | clk_disable(priv->pclk); |
777da230 | 3087 | clk_disable(priv->stmmac_clk); |
ba1377ff | 3088 | } |
f8c5a875 | 3089 | spin_unlock_irqrestore(&priv->lock, flags); |
2d871aa0 VB |
3090 | |
3091 | priv->oldlink = 0; | |
3092 | priv->speed = 0; | |
3093 | priv->oldduplex = -1; | |
47dd7a54 GC |
3094 | return 0; |
3095 | } | |
b2e2f0c7 | 3096 | EXPORT_SYMBOL_GPL(stmmac_suspend); |
47dd7a54 | 3097 | |
732fdf0e GC |
3098 | /** |
3099 | * stmmac_resume - resume callback | |
3100 | * @ndev: net device pointer | |
3101 | * Description: when resume this function is invoked to setup the DMA and CORE | |
3102 | * in a usable state. | |
3103 | */ | |
bfab27a1 | 3104 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 3105 | { |
874bd42d | 3106 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3107 | unsigned long flags; |
47dd7a54 | 3108 | |
874bd42d | 3109 | if (!netif_running(ndev)) |
47dd7a54 GC |
3110 | return 0; |
3111 | ||
f8c5a875 | 3112 | spin_lock_irqsave(&priv->lock, flags); |
c4433be6 | 3113 | |
47dd7a54 GC |
3114 | /* Power Down bit, into the PM register, is cleared |
3115 | * automatically as soon as a magic packet or a Wake-up frame | |
3116 | * is received. Anyway, it's better to manually clear | |
3117 | * this bit because it can generate problems while resuming | |
ceb69499 GC |
3118 | * from another devices (e.g. serial console). |
3119 | */ | |
623997fb | 3120 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3121 | priv->hw->mac->pmt(priv->hw, 0); |
89f7f2cf | 3122 | priv->irq_wake = 0; |
623997fb | 3123 | } else { |
db88f10a | 3124 | pinctrl_pm_select_default_state(priv->device); |
ba1377ff | 3125 | /* enable the clk prevously disabled */ |
777da230 | 3126 | clk_enable(priv->stmmac_clk); |
5f9755d2 | 3127 | clk_enable(priv->pclk); |
623997fb SK |
3128 | /* reset the phy so that it's ready */ |
3129 | if (priv->mii) | |
3130 | stmmac_mdio_reset(priv->mii); | |
3131 | } | |
47dd7a54 | 3132 | |
874bd42d | 3133 | netif_device_attach(ndev); |
47dd7a54 | 3134 | |
ae79a639 GC |
3135 | priv->cur_rx = 0; |
3136 | priv->dirty_rx = 0; | |
3137 | priv->dirty_tx = 0; | |
3138 | priv->cur_tx = 0; | |
3139 | stmmac_clear_descriptors(priv); | |
3140 | ||
fe131929 | 3141 | stmmac_hw_setup(ndev, false); |
777da230 | 3142 | stmmac_init_tx_coalesce(priv); |
ac316c78 | 3143 | stmmac_set_rx_mode(ndev); |
47dd7a54 | 3144 | |
47dd7a54 GC |
3145 | napi_enable(&priv->napi); |
3146 | ||
874bd42d | 3147 | netif_start_queue(ndev); |
47dd7a54 | 3148 | |
f8c5a875 | 3149 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 FV |
3150 | |
3151 | if (priv->phydev) | |
3152 | phy_start(priv->phydev); | |
3153 | ||
47dd7a54 GC |
3154 | return 0; |
3155 | } | |
b2e2f0c7 | 3156 | EXPORT_SYMBOL_GPL(stmmac_resume); |
ba27ec66 | 3157 | |
47dd7a54 GC |
3158 | #ifndef MODULE |
3159 | static int __init stmmac_cmdline_opt(char *str) | |
3160 | { | |
3161 | char *opt; | |
3162 | ||
3163 | if (!str || !*str) | |
3164 | return -EINVAL; | |
3165 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 | 3166 | if (!strncmp(opt, "debug:", 6)) { |
ea2ab871 | 3167 | if (kstrtoint(opt + 6, 0, &debug)) |
f3240e28 GC |
3168 | goto err; |
3169 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
ea2ab871 | 3170 | if (kstrtoint(opt + 8, 0, &phyaddr)) |
f3240e28 | 3171 | goto err; |
f3240e28 | 3172 | } else if (!strncmp(opt, "buf_sz:", 7)) { |
ea2ab871 | 3173 | if (kstrtoint(opt + 7, 0, &buf_sz)) |
f3240e28 GC |
3174 | goto err; |
3175 | } else if (!strncmp(opt, "tc:", 3)) { | |
ea2ab871 | 3176 | if (kstrtoint(opt + 3, 0, &tc)) |
f3240e28 GC |
3177 | goto err; |
3178 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
ea2ab871 | 3179 | if (kstrtoint(opt + 9, 0, &watchdog)) |
f3240e28 GC |
3180 | goto err; |
3181 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
ea2ab871 | 3182 | if (kstrtoint(opt + 10, 0, &flow_ctrl)) |
f3240e28 GC |
3183 | goto err; |
3184 | } else if (!strncmp(opt, "pause:", 6)) { | |
ea2ab871 | 3185 | if (kstrtoint(opt + 6, 0, &pause)) |
f3240e28 | 3186 | goto err; |
506f669c | 3187 | } else if (!strncmp(opt, "eee_timer:", 10)) { |
d765955d GC |
3188 | if (kstrtoint(opt + 10, 0, &eee_timer)) |
3189 | goto err; | |
4a7d666a GC |
3190 | } else if (!strncmp(opt, "chain_mode:", 11)) { |
3191 | if (kstrtoint(opt + 11, 0, &chain_mode)) | |
3192 | goto err; | |
f3240e28 | 3193 | } |
47dd7a54 GC |
3194 | } |
3195 | return 0; | |
f3240e28 GC |
3196 | |
3197 | err: | |
3198 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
3199 | return -EINVAL; | |
47dd7a54 GC |
3200 | } |
3201 | ||
3202 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
ceb69499 | 3203 | #endif /* MODULE */ |
6fc0d0f2 | 3204 | |
466c5ac8 MO |
3205 | static int __init stmmac_init(void) |
3206 | { | |
3207 | #ifdef CONFIG_DEBUG_FS | |
3208 | /* Create debugfs main directory if it doesn't exist yet */ | |
3209 | if (!stmmac_fs_dir) { | |
3210 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
3211 | ||
3212 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
3213 | pr_err("ERROR %s, debugfs create directory failed\n", | |
3214 | STMMAC_RESOURCE_NAME); | |
3215 | ||
3216 | return -ENOMEM; | |
3217 | } | |
3218 | } | |
3219 | #endif | |
3220 | ||
3221 | return 0; | |
3222 | } | |
3223 | ||
3224 | static void __exit stmmac_exit(void) | |
3225 | { | |
3226 | #ifdef CONFIG_DEBUG_FS | |
3227 | debugfs_remove_recursive(stmmac_fs_dir); | |
3228 | #endif | |
3229 | } | |
3230 | ||
3231 | module_init(stmmac_init) | |
3232 | module_exit(stmmac_exit) | |
3233 | ||
6fc0d0f2 GC |
3234 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); |
3235 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
3236 | MODULE_LICENSE("GPL"); |