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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/interrupt.h> | |
47dd7a54 GC |
35 | #include <linux/etherdevice.h> |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/ip.h> | |
38 | #include <linux/tcp.h> | |
39 | #include <linux/skbuff.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_ether.h> | |
42 | #include <linux/crc32.h> | |
43 | #include <linux/mii.h> | |
01789349 | 44 | #include <linux/if.h> |
47dd7a54 GC |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 47 | #include <linux/slab.h> |
70c71606 | 48 | #include <linux/prefetch.h> |
7ac29055 GC |
49 | #ifdef CONFIG_STMMAC_DEBUG_FS |
50 | #include <linux/debugfs.h> | |
51 | #include <linux/seq_file.h> | |
52 | #endif | |
286a8372 | 53 | #include "stmmac.h" |
47dd7a54 GC |
54 | |
55 | #define STMMAC_RESOURCE_NAME "stmmaceth" | |
47dd7a54 GC |
56 | |
57 | #undef STMMAC_DEBUG | |
58 | /*#define STMMAC_DEBUG*/ | |
59 | #ifdef STMMAC_DEBUG | |
60 | #define DBG(nlevel, klevel, fmt, args...) \ | |
61 | ((void)(netif_msg_##nlevel(priv) && \ | |
62 | printk(KERN_##klevel fmt, ## args))) | |
63 | #else | |
64 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
65 | #endif | |
66 | ||
67 | #undef STMMAC_RX_DEBUG | |
68 | /*#define STMMAC_RX_DEBUG*/ | |
69 | #ifdef STMMAC_RX_DEBUG | |
70 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
71 | #else | |
72 | #define RX_DBG(fmt, args...) do { } while (0) | |
73 | #endif | |
74 | ||
75 | #undef STMMAC_XMIT_DEBUG | |
76 | /*#define STMMAC_XMIT_DEBUG*/ | |
77 | #ifdef STMMAC_TX_DEBUG | |
78 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
79 | #else | |
80 | #define TX_DBG(fmt, args...) do { } while (0) | |
81 | #endif | |
82 | ||
83 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
84 | #define JUMBO_LEN 9000 | |
85 | ||
86 | /* Module parameters */ | |
87 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
88 | static int watchdog = TX_TIMEO; | |
89 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
90 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
91 | ||
92 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
93 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
94 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
95 | ||
96 | static int phyaddr = -1; | |
97 | module_param(phyaddr, int, S_IRUGO); | |
98 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
99 | ||
100 | #define DMA_TX_SIZE 256 | |
101 | static int dma_txsize = DMA_TX_SIZE; | |
102 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
103 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
104 | ||
105 | #define DMA_RX_SIZE 256 | |
106 | static int dma_rxsize = DMA_RX_SIZE; | |
107 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
108 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
109 | ||
110 | static int flow_ctrl = FLOW_OFF; | |
111 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
112 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
113 | ||
114 | static int pause = PAUSE_TIME; | |
115 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
116 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
117 | ||
118 | #define TC_DEFAULT 64 | |
119 | static int tc = TC_DEFAULT; | |
120 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
121 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
122 | ||
47dd7a54 GC |
123 | /* Pay attention to tune this parameter; take care of both |
124 | * hardware capability and network stabitily/performance impact. | |
125 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
126 | #ifdef CONFIG_STMMAC_TIMER | |
127 | #define DEFAULT_PERIODIC_RATE 256 | |
128 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
129 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
130 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
131 | #endif | |
132 | ||
133 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
134 | static int buf_sz = DMA_BUFFER_SIZE; | |
135 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
136 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
137 | ||
47dd7a54 GC |
138 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
139 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
140 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
141 | ||
142 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 GC |
143 | |
144 | /** | |
145 | * stmmac_verify_args - verify the driver parameters. | |
146 | * Description: it verifies if some wrong parameter is passed to the driver. | |
147 | * Note that wrong parameters are replaced with the default values. | |
148 | */ | |
149 | static void stmmac_verify_args(void) | |
150 | { | |
151 | if (unlikely(watchdog < 0)) | |
152 | watchdog = TX_TIMEO; | |
153 | if (unlikely(dma_rxsize < 0)) | |
154 | dma_rxsize = DMA_RX_SIZE; | |
155 | if (unlikely(dma_txsize < 0)) | |
156 | dma_txsize = DMA_TX_SIZE; | |
157 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
158 | buf_sz = DMA_BUFFER_SIZE; | |
159 | if (unlikely(flow_ctrl > 1)) | |
160 | flow_ctrl = FLOW_AUTO; | |
161 | else if (likely(flow_ctrl < 0)) | |
162 | flow_ctrl = FLOW_OFF; | |
163 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
164 | pause = PAUSE_TIME; | |
47dd7a54 GC |
165 | } |
166 | ||
167 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) | |
168 | static void print_pkt(unsigned char *buf, int len) | |
169 | { | |
170 | int j; | |
171 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
172 | for (j = 0; j < len; j++) { | |
173 | if ((j % 16) == 0) | |
174 | pr_info("\n %03x:", j); | |
175 | pr_info(" %02x", buf[j]); | |
176 | } | |
177 | pr_info("\n"); | |
47dd7a54 GC |
178 | } |
179 | #endif | |
180 | ||
181 | /* minimum number of free TX descriptors required to wake up TX process */ | |
182 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
183 | ||
184 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
185 | { | |
186 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
187 | } | |
188 | ||
9dfeb4d9 GC |
189 | /* On some ST platforms, some HW system configuraton registers have to be |
190 | * set according to the link speed negotiated. | |
191 | */ | |
192 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
193 | { | |
194 | struct phy_device *phydev = priv->phydev; | |
195 | ||
196 | if (likely(priv->plat->fix_mac_speed)) | |
197 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
198 | phydev->speed); | |
199 | } | |
200 | ||
47dd7a54 GC |
201 | /** |
202 | * stmmac_adjust_link | |
203 | * @dev: net device structure | |
204 | * Description: it adjusts the link parameters. | |
205 | */ | |
206 | static void stmmac_adjust_link(struct net_device *dev) | |
207 | { | |
208 | struct stmmac_priv *priv = netdev_priv(dev); | |
209 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
210 | unsigned long flags; |
211 | int new_state = 0; | |
212 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
213 | ||
214 | if (phydev == NULL) | |
215 | return; | |
216 | ||
217 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
218 | phydev->addr, phydev->link); | |
219 | ||
220 | spin_lock_irqsave(&priv->lock, flags); | |
221 | if (phydev->link) { | |
ad01b7d4 | 222 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
223 | |
224 | /* Now we make sure that we can be in full duplex mode. | |
225 | * If not, we operate in half-duplex mode. */ | |
226 | if (phydev->duplex != priv->oldduplex) { | |
227 | new_state = 1; | |
228 | if (!(phydev->duplex)) | |
db98a0b0 | 229 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 230 | else |
db98a0b0 | 231 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
232 | priv->oldduplex = phydev->duplex; |
233 | } | |
234 | /* Flow Control operation */ | |
235 | if (phydev->pause) | |
ad01b7d4 | 236 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 237 | fc, pause_time); |
47dd7a54 GC |
238 | |
239 | if (phydev->speed != priv->speed) { | |
240 | new_state = 1; | |
241 | switch (phydev->speed) { | |
242 | case 1000: | |
9dfeb4d9 | 243 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 244 | ctrl &= ~priv->hw->link.port; |
9dfeb4d9 | 245 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
246 | break; |
247 | case 100: | |
248 | case 10: | |
9dfeb4d9 | 249 | if (priv->plat->has_gmac) { |
db98a0b0 | 250 | ctrl |= priv->hw->link.port; |
47dd7a54 | 251 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 252 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 253 | } else { |
db98a0b0 | 254 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
255 | } |
256 | } else { | |
db98a0b0 | 257 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 258 | } |
9dfeb4d9 | 259 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
260 | break; |
261 | default: | |
262 | if (netif_msg_link(priv)) | |
263 | pr_warning("%s: Speed (%d) is not 10" | |
264 | " or 100!\n", dev->name, phydev->speed); | |
265 | break; | |
266 | } | |
267 | ||
268 | priv->speed = phydev->speed; | |
269 | } | |
270 | ||
ad01b7d4 | 271 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
272 | |
273 | if (!priv->oldlink) { | |
274 | new_state = 1; | |
275 | priv->oldlink = 1; | |
276 | } | |
277 | } else if (priv->oldlink) { | |
278 | new_state = 1; | |
279 | priv->oldlink = 0; | |
280 | priv->speed = 0; | |
281 | priv->oldduplex = -1; | |
282 | } | |
283 | ||
284 | if (new_state && netif_msg_link(priv)) | |
285 | phy_print_status(phydev); | |
286 | ||
287 | spin_unlock_irqrestore(&priv->lock, flags); | |
288 | ||
289 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
290 | } | |
291 | ||
292 | /** | |
293 | * stmmac_init_phy - PHY initialization | |
294 | * @dev: net device structure | |
295 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
296 | * to the mac driver. | |
297 | * Return value: | |
298 | * 0 on success | |
299 | */ | |
300 | static int stmmac_init_phy(struct net_device *dev) | |
301 | { | |
302 | struct stmmac_priv *priv = netdev_priv(dev); | |
303 | struct phy_device *phydev; | |
109cdd66 GC |
304 | char phy_id[MII_BUS_ID_SIZE + 3]; |
305 | char bus_id[MII_BUS_ID_SIZE]; | |
79ee1dc3 | 306 | int interface = priv->plat->interface; |
47dd7a54 GC |
307 | priv->oldlink = 0; |
308 | priv->speed = 0; | |
309 | priv->oldduplex = -1; | |
310 | ||
9dfeb4d9 | 311 | snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id); |
109cdd66 | 312 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 313 | priv->plat->phy_addr); |
47dd7a54 GC |
314 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
315 | ||
79ee1dc3 | 316 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); |
47dd7a54 GC |
317 | |
318 | if (IS_ERR(phydev)) { | |
319 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
320 | return PTR_ERR(phydev); | |
321 | } | |
322 | ||
79ee1dc3 | 323 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 SK |
324 | if ((interface == PHY_INTERFACE_MODE_MII) || |
325 | (interface == PHY_INTERFACE_MODE_RMII)) | |
326 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | | |
327 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 328 | |
47dd7a54 GC |
329 | /* |
330 | * Broken HW is sometimes missing the pull-up resistor on the | |
331 | * MDIO line, which results in reads to non-existent devices returning | |
332 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
333 | * device as well. | |
334 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
335 | */ | |
336 | if (phydev->phy_id == 0) { | |
337 | phy_disconnect(phydev); | |
338 | return -ENODEV; | |
339 | } | |
340 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 341 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
342 | |
343 | priv->phydev = phydev; | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
19449bfc | 348 | static inline void stmmac_enable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
349 | { |
350 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 351 | |
19449bfc | 352 | value |= MAC_RNABLE_RX | MAC_ENABLE_TX; |
47dd7a54 GC |
353 | writel(value, ioaddr + MAC_CTRL_REG); |
354 | } | |
355 | ||
19449bfc | 356 | static inline void stmmac_disable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
357 | { |
358 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 359 | |
19449bfc | 360 | value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); |
47dd7a54 GC |
361 | writel(value, ioaddr + MAC_CTRL_REG); |
362 | } | |
363 | ||
364 | /** | |
365 | * display_ring | |
366 | * @p: pointer to the ring. | |
367 | * @size: size of the ring. | |
368 | * Description: display all the descriptors within the ring. | |
369 | */ | |
370 | static void display_ring(struct dma_desc *p, int size) | |
371 | { | |
372 | struct tmp_s { | |
373 | u64 a; | |
374 | unsigned int b; | |
375 | unsigned int c; | |
376 | }; | |
377 | int i; | |
378 | for (i = 0; i < size; i++) { | |
379 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
380 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
381 | i, (unsigned int)virt_to_phys(&p[i]), | |
382 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
383 | x->b, x->c); | |
384 | pr_info("\n"); | |
385 | } | |
386 | } | |
387 | ||
286a8372 GC |
388 | static int stmmac_set_bfsize(int mtu, int bufsize) |
389 | { | |
390 | int ret = bufsize; | |
391 | ||
392 | if (mtu >= BUF_SIZE_4KiB) | |
393 | ret = BUF_SIZE_8KiB; | |
394 | else if (mtu >= BUF_SIZE_2KiB) | |
395 | ret = BUF_SIZE_4KiB; | |
396 | else if (mtu >= DMA_BUFFER_SIZE) | |
397 | ret = BUF_SIZE_2KiB; | |
398 | else | |
399 | ret = DMA_BUFFER_SIZE; | |
400 | ||
401 | return ret; | |
402 | } | |
403 | ||
47dd7a54 GC |
404 | /** |
405 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
406 | * @dev: net device structure | |
407 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
408 | * and allocates the socket buffers. It suppors the chained and ring |
409 | * modes. | |
47dd7a54 GC |
410 | */ |
411 | static void init_dma_desc_rings(struct net_device *dev) | |
412 | { | |
413 | int i; | |
414 | struct stmmac_priv *priv = netdev_priv(dev); | |
415 | struct sk_buff *skb; | |
416 | unsigned int txsize = priv->dma_tx_size; | |
417 | unsigned int rxsize = priv->dma_rx_size; | |
286a8372 GC |
418 | unsigned int bfsize; |
419 | int dis_ic = 0; | |
420 | int des3_as_data_buf = 0; | |
47dd7a54 | 421 | |
286a8372 GC |
422 | /* Set the max buffer size according to the DESC mode |
423 | * and the MTU. Note that RING mode allows 16KiB bsize. */ | |
424 | bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); | |
425 | ||
426 | if (bfsize == BUF_SIZE_16KiB) | |
427 | des3_as_data_buf = 1; | |
47dd7a54 | 428 | else |
286a8372 | 429 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 430 | |
73cfe264 GC |
431 | #ifdef CONFIG_STMMAC_TIMER |
432 | /* Disable interrupts on completion for the reception if timer is on */ | |
433 | if (likely(priv->tm->enable)) | |
434 | dis_ic = 1; | |
435 | #endif | |
47dd7a54 GC |
436 | |
437 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
438 | txsize, rxsize, bfsize); | |
439 | ||
440 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
441 | priv->rx_skbuff = | |
442 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
443 | priv->dma_rx = | |
444 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
445 | rxsize * | |
446 | sizeof(struct dma_desc), | |
447 | &priv->dma_rx_phy, | |
448 | GFP_KERNEL); | |
449 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
450 | GFP_KERNEL); | |
451 | priv->dma_tx = | |
452 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
453 | txsize * | |
454 | sizeof(struct dma_desc), | |
455 | &priv->dma_tx_phy, | |
456 | GFP_KERNEL); | |
457 | ||
458 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
459 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
460 | return; | |
461 | } | |
462 | ||
286a8372 | 463 | DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " |
47dd7a54 GC |
464 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", |
465 | dev->name, priv->dma_rx, priv->dma_tx, | |
466 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
467 | ||
468 | /* RX INITIALIZATION */ | |
469 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
470 | "skb\t\tskb data\tdma data\n"); | |
471 | ||
472 | for (i = 0; i < rxsize; i++) { | |
473 | struct dma_desc *p = priv->dma_rx + i; | |
474 | ||
45db81e1 GC |
475 | skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, |
476 | GFP_KERNEL); | |
47dd7a54 GC |
477 | if (unlikely(skb == NULL)) { |
478 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
479 | break; | |
480 | } | |
45db81e1 | 481 | skb_reserve(skb, NET_IP_ALIGN); |
47dd7a54 GC |
482 | priv->rx_skbuff[i] = skb; |
483 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
484 | bfsize, DMA_FROM_DEVICE); | |
485 | ||
486 | p->des2 = priv->rx_skbuff_dma[i]; | |
286a8372 GC |
487 | |
488 | priv->hw->ring->init_desc3(des3_as_data_buf, p); | |
489 | ||
47dd7a54 GC |
490 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], |
491 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
492 | } | |
493 | priv->cur_rx = 0; | |
494 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
495 | priv->dma_buf_sz = bfsize; | |
496 | buf_sz = bfsize; | |
497 | ||
498 | /* TX INITIALIZATION */ | |
499 | for (i = 0; i < txsize; i++) { | |
500 | priv->tx_skbuff[i] = NULL; | |
501 | priv->dma_tx[i].des2 = 0; | |
502 | } | |
286a8372 GC |
503 | |
504 | /* In case of Chained mode this sets the des3 to the next | |
505 | * element in the chain */ | |
506 | priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); | |
507 | priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); | |
508 | ||
47dd7a54 GC |
509 | priv->dirty_tx = 0; |
510 | priv->cur_tx = 0; | |
511 | ||
512 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
513 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
514 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
515 | |
516 | if (netif_msg_hw(priv)) { | |
517 | pr_info("RX descriptor ring:\n"); | |
518 | display_ring(priv->dma_rx, rxsize); | |
519 | pr_info("TX descriptor ring:\n"); | |
520 | display_ring(priv->dma_tx, txsize); | |
521 | } | |
47dd7a54 GC |
522 | } |
523 | ||
524 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
525 | { | |
526 | int i; | |
527 | ||
528 | for (i = 0; i < priv->dma_rx_size; i++) { | |
529 | if (priv->rx_skbuff[i]) { | |
530 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
531 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
532 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
533 | } | |
534 | priv->rx_skbuff[i] = NULL; | |
535 | } | |
47dd7a54 GC |
536 | } |
537 | ||
538 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
539 | { | |
540 | int i; | |
541 | ||
542 | for (i = 0; i < priv->dma_tx_size; i++) { | |
543 | if (priv->tx_skbuff[i] != NULL) { | |
544 | struct dma_desc *p = priv->dma_tx + i; | |
545 | if (p->des2) | |
546 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
547 | priv->hw->desc->get_tx_len(p), |
548 | DMA_TO_DEVICE); | |
47dd7a54 GC |
549 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
550 | priv->tx_skbuff[i] = NULL; | |
551 | } | |
552 | } | |
47dd7a54 GC |
553 | } |
554 | ||
555 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
556 | { | |
557 | /* Release the DMA TX/RX socket buffers */ | |
558 | dma_free_rx_skbufs(priv); | |
559 | dma_free_tx_skbufs(priv); | |
560 | ||
561 | /* Free the region of consistent memory previously allocated for | |
562 | * the DMA */ | |
563 | dma_free_coherent(priv->device, | |
564 | priv->dma_tx_size * sizeof(struct dma_desc), | |
565 | priv->dma_tx, priv->dma_tx_phy); | |
566 | dma_free_coherent(priv->device, | |
567 | priv->dma_rx_size * sizeof(struct dma_desc), | |
568 | priv->dma_rx, priv->dma_rx_phy); | |
569 | kfree(priv->rx_skbuff_dma); | |
570 | kfree(priv->rx_skbuff); | |
571 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
572 | } |
573 | ||
47dd7a54 GC |
574 | /** |
575 | * stmmac_dma_operation_mode - HW DMA operation mode | |
576 | * @priv : pointer to the private device structure. | |
577 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 578 | * or Store-And-Forward capability. |
47dd7a54 GC |
579 | */ |
580 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
581 | { | |
61b8013a SK |
582 | if (likely(priv->plat->force_sf_dma_mode || |
583 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
584 | /* | |
585 | * In case of GMAC, SF mode can be enabled | |
586 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
587 | * 1) TX COE if actually supported |
588 | * 2) There is no bugged Jumbo frame support | |
589 | * that needs to not insert csum in the TDES. | |
590 | */ | |
591 | priv->hw->dma->dma_mode(priv->ioaddr, | |
592 | SF_DMA_MODE, SF_DMA_MODE); | |
593 | tc = SF_DMA_MODE; | |
594 | } else | |
595 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
596 | } |
597 | ||
47dd7a54 GC |
598 | /** |
599 | * stmmac_tx: | |
600 | * @priv: private driver structure | |
601 | * Description: it reclaims resources after transmission completes. | |
602 | */ | |
603 | static void stmmac_tx(struct stmmac_priv *priv) | |
604 | { | |
605 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 | 606 | |
a9097a96 GC |
607 | spin_lock(&priv->tx_lock); |
608 | ||
47dd7a54 GC |
609 | while (priv->dirty_tx != priv->cur_tx) { |
610 | int last; | |
611 | unsigned int entry = priv->dirty_tx % txsize; | |
612 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
613 | struct dma_desc *p = priv->dma_tx + entry; | |
614 | ||
615 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 616 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
617 | break; |
618 | ||
619 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 620 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
621 | if (likely(last)) { |
622 | int tx_error = | |
db98a0b0 GC |
623 | priv->hw->desc->tx_status(&priv->dev->stats, |
624 | &priv->xstats, p, | |
ad01b7d4 | 625 | priv->ioaddr); |
47dd7a54 GC |
626 | if (likely(tx_error == 0)) { |
627 | priv->dev->stats.tx_packets++; | |
628 | priv->xstats.tx_pkt_n++; | |
629 | } else | |
630 | priv->dev->stats.tx_errors++; | |
631 | } | |
632 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
633 | priv->cur_tx, priv->dirty_tx); | |
634 | ||
635 | if (likely(p->des2)) | |
636 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 637 | priv->hw->desc->get_tx_len(p), |
47dd7a54 | 638 | DMA_TO_DEVICE); |
286a8372 | 639 | priv->hw->ring->clean_desc3(p); |
47dd7a54 GC |
640 | |
641 | if (likely(skb != NULL)) { | |
642 | /* | |
643 | * If there's room in the queue (limit it to size) | |
644 | * we add this skb back into the pool, | |
645 | * if it's the right size. | |
646 | */ | |
647 | if ((skb_queue_len(&priv->rx_recycle) < | |
648 | priv->dma_rx_size) && | |
649 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
650 | __skb_queue_head(&priv->rx_recycle, skb); | |
651 | else | |
652 | dev_kfree_skb(skb); | |
653 | ||
654 | priv->tx_skbuff[entry] = NULL; | |
655 | } | |
656 | ||
db98a0b0 | 657 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 GC |
658 | |
659 | entry = (++priv->dirty_tx) % txsize; | |
660 | } | |
661 | if (unlikely(netif_queue_stopped(priv->dev) && | |
662 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
663 | netif_tx_lock(priv->dev); | |
664 | if (netif_queue_stopped(priv->dev) && | |
665 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
666 | TX_DBG("%s: restart transmit\n", __func__); | |
667 | netif_wake_queue(priv->dev); | |
668 | } | |
669 | netif_tx_unlock(priv->dev); | |
670 | } | |
a9097a96 | 671 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
672 | } |
673 | ||
674 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
675 | { | |
73cfe264 GC |
676 | #ifdef CONFIG_STMMAC_TIMER |
677 | if (likely(priv->tm->enable)) | |
678 | priv->tm->timer_start(tmrate); | |
679 | else | |
47dd7a54 | 680 | #endif |
ad01b7d4 | 681 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
682 | } |
683 | ||
684 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
685 | { | |
73cfe264 GC |
686 | #ifdef CONFIG_STMMAC_TIMER |
687 | if (likely(priv->tm->enable)) | |
688 | priv->tm->timer_stop(); | |
689 | else | |
47dd7a54 | 690 | #endif |
ad01b7d4 | 691 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
692 | } |
693 | ||
694 | static int stmmac_has_work(struct stmmac_priv *priv) | |
695 | { | |
696 | unsigned int has_work = 0; | |
697 | int rxret, tx_work = 0; | |
698 | ||
db98a0b0 | 699 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
700 | (priv->cur_rx % priv->dma_rx_size)); |
701 | ||
702 | if (priv->dirty_tx != priv->cur_tx) | |
703 | tx_work = 1; | |
704 | ||
705 | if (likely(!rxret || tx_work)) | |
706 | has_work = 1; | |
707 | ||
708 | return has_work; | |
709 | } | |
710 | ||
711 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
712 | { | |
713 | if (likely(stmmac_has_work(priv))) { | |
714 | stmmac_disable_irq(priv); | |
715 | napi_schedule(&priv->napi); | |
716 | } | |
717 | } | |
718 | ||
719 | #ifdef CONFIG_STMMAC_TIMER | |
720 | void stmmac_schedule(struct net_device *dev) | |
721 | { | |
722 | struct stmmac_priv *priv = netdev_priv(dev); | |
723 | ||
724 | priv->xstats.sched_timer_n++; | |
725 | ||
726 | _stmmac_schedule(priv); | |
47dd7a54 GC |
727 | } |
728 | ||
729 | static void stmmac_no_timer_started(unsigned int x) | |
730 | {; | |
731 | }; | |
732 | ||
733 | static void stmmac_no_timer_stopped(void) | |
734 | {; | |
735 | }; | |
736 | #endif | |
737 | ||
738 | /** | |
739 | * stmmac_tx_err: | |
740 | * @priv: pointer to the private device structure | |
741 | * Description: it cleans the descriptors and restarts the transmission | |
742 | * in case of errors. | |
743 | */ | |
744 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
745 | { | |
746 | netif_stop_queue(priv->dev); | |
747 | ||
ad01b7d4 | 748 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 749 | dma_free_tx_skbufs(priv); |
db98a0b0 | 750 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
751 | priv->dirty_tx = 0; |
752 | priv->cur_tx = 0; | |
ad01b7d4 | 753 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
754 | |
755 | priv->dev->stats.tx_errors++; | |
756 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
757 | } |
758 | ||
47dd7a54 | 759 | |
aec7ff27 GC |
760 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
761 | { | |
aec7ff27 GC |
762 | int status; |
763 | ||
ad01b7d4 | 764 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
765 | if (likely(status == handle_tx_rx)) |
766 | _stmmac_schedule(priv); | |
767 | ||
768 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
769 | /* Try to bump up the dma threshold on this failure */ | |
770 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
771 | tc += 64; | |
ad01b7d4 | 772 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 773 | priv->xstats.threshold = tc; |
47dd7a54 | 774 | } |
aec7ff27 GC |
775 | } else if (unlikely(status == tx_hard_error)) |
776 | stmmac_tx_err(priv); | |
47dd7a54 GC |
777 | } |
778 | ||
1c901a46 GC |
779 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
780 | { | |
781 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
782 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; | |
783 | ||
784 | /* Do not manage MMC IRQ (FIXME) */ | |
785 | dwmac_mmc_intr_all_mask(priv->ioaddr); | |
786 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
787 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
788 | } | |
789 | ||
f0b9d786 GC |
790 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
791 | { | |
792 | u32 hwid = priv->hw->synopsys_uid; | |
793 | ||
794 | /* Only check valid Synopsys Id because old MAC chips | |
795 | * have no HW registers where get the ID */ | |
796 | if (likely(hwid)) { | |
797 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
798 | u32 synid = (hwid & 0x000000ff); | |
799 | ||
800 | pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n", | |
801 | uid, synid); | |
802 | ||
803 | return synid; | |
804 | } | |
805 | return 0; | |
806 | } | |
e7434821 | 807 | |
19e30c14 GC |
808 | /** |
809 | * stmmac_selec_desc_mode | |
810 | * @dev : device pointer | |
811 | * Description: select the Enhanced/Alternate or Normal descriptors */ | |
812 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) | |
813 | { | |
814 | if (priv->plat->enh_desc) { | |
815 | pr_info(" Enhanced/Alternate descriptors\n"); | |
816 | priv->hw->desc = &enh_desc_ops; | |
817 | } else { | |
818 | pr_info(" Normal descriptors\n"); | |
819 | priv->hw->desc = &ndesc_ops; | |
820 | } | |
821 | } | |
822 | ||
823 | /** | |
824 | * stmmac_get_hw_features | |
825 | * @priv : private device pointer | |
826 | * Description: | |
827 | * new GMAC chip generations have a new register to indicate the | |
828 | * presence of the optional feature/functions. | |
829 | * This can be also used to override the value passed through the | |
830 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
831 | */ |
832 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
833 | { | |
5e6efe88 | 834 | u32 hw_cap = 0; |
3c20f72f | 835 | |
5e6efe88 GC |
836 | if (priv->hw->dma->get_hw_feature) { |
837 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 838 | |
1db123fb RK |
839 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
840 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
841 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
842 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
843 | priv->dma_cap.multi_addr = | |
844 | (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; | |
845 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; | |
846 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
847 | priv->dma_cap.pmt_remote_wake_up = | |
848 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; | |
849 | priv->dma_cap.pmt_magic_frame = | |
850 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; | |
19e30c14 | 851 | /* MMC */ |
1db123fb | 852 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
e7434821 | 853 | /* IEEE 1588-2002*/ |
1db123fb RK |
854 | priv->dma_cap.time_stamp = |
855 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; | |
e7434821 | 856 | /* IEEE 1588-2008*/ |
1db123fb RK |
857 | priv->dma_cap.atime_stamp = |
858 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; | |
e7434821 | 859 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
860 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
861 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 862 | /* TX and RX csum */ |
1db123fb RK |
863 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
864 | priv->dma_cap.rx_coe_type1 = | |
865 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; | |
866 | priv->dma_cap.rx_coe_type2 = | |
867 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; | |
868 | priv->dma_cap.rxfifo_over_2048 = | |
869 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; | |
e7434821 | 870 | /* TX and RX number of channels */ |
1db123fb RK |
871 | priv->dma_cap.number_rx_channel = |
872 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; | |
873 | priv->dma_cap.number_tx_channel = | |
874 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; | |
e7434821 | 875 | /* Alternate (enhanced) DESC mode*/ |
1db123fb RK |
876 | priv->dma_cap.enh_desc = |
877 | (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
e7434821 | 878 | |
19e30c14 | 879 | } |
e7434821 GC |
880 | |
881 | return hw_cap; | |
882 | } | |
883 | ||
47dd7a54 GC |
884 | /** |
885 | * stmmac_open - open entry point of the driver | |
886 | * @dev : pointer to the device structure. | |
887 | * Description: | |
888 | * This function is the open entry point of the driver. | |
889 | * Return value: | |
890 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
891 | * file on failure. | |
892 | */ | |
893 | static int stmmac_open(struct net_device *dev) | |
894 | { | |
895 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
896 | int ret; |
897 | ||
898 | /* Check that the MAC address is valid. If its not, refuse | |
899 | * to bring the device up. The user must specify an | |
900 | * address using the following linux command: | |
901 | * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */ | |
902 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
903 | random_ether_addr(dev->dev_addr); | |
904 | pr_warning("%s: generated random MAC address %pM\n", dev->name, | |
905 | dev->dev_addr); | |
906 | } | |
907 | ||
908 | stmmac_verify_args(); | |
909 | ||
47dd7a54 | 910 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 911 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
47dd7a54 | 912 | if (unlikely(priv->tm == NULL)) { |
2381a55c | 913 | pr_err("%s: ERROR: timer memory alloc failed\n", __func__); |
47dd7a54 GC |
914 | return -ENOMEM; |
915 | } | |
916 | priv->tm->freq = tmrate; | |
917 | ||
73cfe264 GC |
918 | /* Test if the external timer can be actually used. |
919 | * In case of failure continue without timer. */ | |
47dd7a54 | 920 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 921 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
922 | priv->tm->freq = 0; |
923 | priv->tm->timer_start = stmmac_no_timer_started; | |
924 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
925 | } else |
926 | priv->tm->enable = 1; | |
47dd7a54 | 927 | #endif |
f66ffe28 GC |
928 | ret = stmmac_init_phy(dev); |
929 | if (unlikely(ret)) { | |
930 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
931 | goto open_error; | |
932 | } | |
47dd7a54 | 933 | |
19e30c14 GC |
934 | stmmac_get_synopsys_id(priv); |
935 | ||
936 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
937 | ||
938 | if (priv->hw_cap_support) { | |
939 | pr_info(" Support DMA HW capability register"); | |
940 | ||
941 | /* We can override some gmac/dma configuration fields: e.g. | |
942 | * enh_desc, tx_coe (e.g. that are passed through the | |
943 | * platform) with the values from the HW capability | |
944 | * register (if supported). | |
945 | */ | |
946 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
947 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
948 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; | |
949 | ||
950 | /* By default disable wol on magic frame if not supported */ | |
951 | if (!priv->dma_cap.pmt_magic_frame) | |
952 | priv->wolopts &= ~WAKE_MAGIC; | |
953 | ||
954 | } else | |
955 | pr_info(" No HW DMA feature register supported"); | |
956 | ||
957 | /* Select the enhnaced/normal descriptor structures */ | |
958 | stmmac_selec_desc_mode(priv); | |
959 | ||
960 | /* PMT module is not integrated in all the MAC devices. */ | |
961 | if (priv->plat->pmt) { | |
962 | pr_info(" Remote wake-up capable\n"); | |
963 | device_set_wakeup_capable(priv->device, 1); | |
964 | } | |
965 | ||
966 | priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr); | |
967 | if (priv->rx_coe) | |
968 | pr_info(" Checksum Offload Engine supported\n"); | |
969 | if (priv->plat->tx_coe) | |
970 | pr_info(" Checksum insertion supported\n"); | |
971 | ||
47dd7a54 GC |
972 | /* Create and initialize the TX/RX descriptors chains. */ |
973 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
974 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
975 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
976 | init_dma_desc_rings(dev); | |
977 | ||
978 | /* DMA initialization and SW reset */ | |
f66ffe28 GC |
979 | ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl, |
980 | priv->dma_tx_phy, priv->dma_rx_phy); | |
981 | if (ret < 0) { | |
47dd7a54 | 982 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 983 | goto open_error; |
47dd7a54 GC |
984 | } |
985 | ||
986 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 987 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
ca5f12c1 | 988 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
989 | if (priv->plat->bus_setup) |
990 | priv->plat->bus_setup(priv->ioaddr); | |
47dd7a54 | 991 | /* Initialize the MAC Core */ |
ad01b7d4 | 992 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 993 | |
5e982f3b | 994 | netdev_update_features(dev); |
ebbb293f | 995 | |
f66ffe28 GC |
996 | /* Request the IRQ lines */ |
997 | ret = request_irq(dev->irq, stmmac_interrupt, | |
998 | IRQF_SHARED, dev->name, dev); | |
999 | if (unlikely(ret < 0)) { | |
1000 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1001 | __func__, dev->irq, ret); | |
1002 | goto open_error; | |
1003 | } | |
1004 | ||
47dd7a54 | 1005 | /* Enable the MAC Rx/Tx */ |
19449bfc | 1006 | stmmac_enable_mac(priv->ioaddr); |
47dd7a54 GC |
1007 | |
1008 | /* Set the HW DMA mode and the COE */ | |
1009 | stmmac_dma_operation_mode(priv); | |
1010 | ||
1011 | /* Extra statistics */ | |
1012 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1013 | priv->xstats.threshold = tc; | |
1014 | ||
38fe7a93 GC |
1015 | if (priv->dma_cap.rmon) |
1016 | stmmac_mmc_setup(priv); | |
1c901a46 | 1017 | |
47dd7a54 GC |
1018 | /* Start the ball rolling... */ |
1019 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
1020 | priv->hw->dma->start_tx(priv->ioaddr); |
1021 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1022 | |
1023 | #ifdef CONFIG_STMMAC_TIMER | |
1024 | priv->tm->timer_start(tmrate); | |
1025 | #endif | |
1026 | /* Dump DMA/MAC registers */ | |
1027 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
1028 | priv->hw->mac->dump_regs(priv->ioaddr); |
1029 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
1030 | } |
1031 | ||
1032 | if (priv->phydev) | |
1033 | phy_start(priv->phydev); | |
1034 | ||
1035 | napi_enable(&priv->napi); | |
1036 | skb_queue_head_init(&priv->rx_recycle); | |
1037 | netif_start_queue(dev); | |
f66ffe28 | 1038 | |
47dd7a54 | 1039 | return 0; |
f66ffe28 GC |
1040 | |
1041 | open_error: | |
1042 | #ifdef CONFIG_STMMAC_TIMER | |
1043 | kfree(priv->tm); | |
1044 | #endif | |
1045 | if (priv->phydev) | |
1046 | phy_disconnect(priv->phydev); | |
1047 | ||
1048 | return ret; | |
47dd7a54 GC |
1049 | } |
1050 | ||
1051 | /** | |
1052 | * stmmac_release - close entry point of the driver | |
1053 | * @dev : device pointer. | |
1054 | * Description: | |
1055 | * This is the stop entry point of the driver. | |
1056 | */ | |
1057 | static int stmmac_release(struct net_device *dev) | |
1058 | { | |
1059 | struct stmmac_priv *priv = netdev_priv(dev); | |
1060 | ||
1061 | /* Stop and disconnect the PHY */ | |
1062 | if (priv->phydev) { | |
1063 | phy_stop(priv->phydev); | |
1064 | phy_disconnect(priv->phydev); | |
1065 | priv->phydev = NULL; | |
1066 | } | |
1067 | ||
1068 | netif_stop_queue(dev); | |
1069 | ||
1070 | #ifdef CONFIG_STMMAC_TIMER | |
1071 | /* Stop and release the timer */ | |
1072 | stmmac_close_ext_timer(); | |
1073 | if (priv->tm != NULL) | |
1074 | kfree(priv->tm); | |
1075 | #endif | |
1076 | napi_disable(&priv->napi); | |
1077 | skb_queue_purge(&priv->rx_recycle); | |
1078 | ||
1079 | /* Free the IRQ lines */ | |
1080 | free_irq(dev->irq, dev); | |
1081 | ||
1082 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1083 | priv->hw->dma->stop_tx(priv->ioaddr); |
1084 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1085 | |
1086 | /* Release and free the Rx/Tx resources */ | |
1087 | free_dma_desc_resources(priv); | |
1088 | ||
19449bfc | 1089 | /* Disable the MAC Rx/Tx */ |
1090 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
1091 | |
1092 | netif_carrier_off(dev); | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
47dd7a54 GC |
1097 | /** |
1098 | * stmmac_xmit: | |
1099 | * @skb : the socket buffer | |
1100 | * @dev : device pointer | |
1101 | * Description : Tx entry point of the driver. | |
1102 | */ | |
1103 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1104 | { | |
1105 | struct stmmac_priv *priv = netdev_priv(dev); | |
1106 | unsigned int txsize = priv->dma_tx_size; | |
1107 | unsigned int entry; | |
1108 | int i, csum_insertion = 0; | |
1109 | int nfrags = skb_shinfo(skb)->nr_frags; | |
1110 | struct dma_desc *desc, *first; | |
286a8372 | 1111 | unsigned int nopaged_len = skb_headlen(skb); |
47dd7a54 GC |
1112 | |
1113 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1114 | if (!netif_queue_stopped(dev)) { | |
1115 | netif_stop_queue(dev); | |
1116 | /* This is a hard error, log it. */ | |
1117 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
1118 | __func__); | |
1119 | } | |
1120 | return NETDEV_TX_BUSY; | |
1121 | } | |
1122 | ||
a9097a96 GC |
1123 | spin_lock(&priv->tx_lock); |
1124 | ||
47dd7a54 GC |
1125 | entry = priv->cur_tx % txsize; |
1126 | ||
1127 | #ifdef STMMAC_XMIT_DEBUG | |
1128 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1129 | pr_info("stmmac xmit:\n" | |
1130 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1131 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
286a8372 | 1132 | skb, skb->len, nopaged_len, nfrags, skb->ip_summed, |
47dd7a54 GC |
1133 | !skb_is_gso(skb) ? "isn't" : "is"); |
1134 | #endif | |
1135 | ||
5e982f3b | 1136 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1137 | |
1138 | desc = priv->dma_tx + entry; | |
1139 | first = desc; | |
1140 | ||
1141 | #ifdef STMMAC_XMIT_DEBUG | |
1142 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1143 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1144 | "\t\tn_frags: %d, ip_summed: %d\n", | |
286a8372 | 1145 | skb->len, nopaged_len, nfrags, skb->ip_summed); |
47dd7a54 GC |
1146 | #endif |
1147 | priv->tx_skbuff[entry] = skb; | |
286a8372 GC |
1148 | |
1149 | if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { | |
1150 | entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); | |
47dd7a54 GC |
1151 | desc = priv->dma_tx + entry; |
1152 | } else { | |
47dd7a54 GC |
1153 | desc->des2 = dma_map_single(priv->device, skb->data, |
1154 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1155 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1156 | csum_insertion); | |
47dd7a54 GC |
1157 | } |
1158 | ||
1159 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1160 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1161 | int len = skb_frag_size(frag); | |
47dd7a54 GC |
1162 | |
1163 | entry = (++priv->cur_tx) % txsize; | |
1164 | desc = priv->dma_tx + entry; | |
1165 | ||
1166 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
f722380d IC |
1167 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1168 | DMA_TO_DEVICE); | |
47dd7a54 | 1169 | priv->tx_skbuff[entry] = NULL; |
db98a0b0 | 1170 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1171 | wmb(); |
db98a0b0 | 1172 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1173 | } |
1174 | ||
1175 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1176 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1177 | |
47dd7a54 | 1178 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1179 | /* Clean IC while using timer */ |
1180 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1181 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1182 | #endif |
eb0dc4bb SH |
1183 | |
1184 | wmb(); | |
1185 | ||
47dd7a54 | 1186 | /* To avoid raise condition */ |
db98a0b0 | 1187 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1188 | |
1189 | priv->cur_tx++; | |
1190 | ||
1191 | #ifdef STMMAC_XMIT_DEBUG | |
1192 | if (netif_msg_pktdata(priv)) { | |
1193 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1194 | "first=%p, nfrags=%d\n", | |
1195 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1196 | entry, first, nfrags); | |
1197 | display_ring(priv->dma_tx, txsize); | |
1198 | pr_info(">>> frame to be transmitted: "); | |
1199 | print_pkt(skb->data, skb->len); | |
1200 | } | |
1201 | #endif | |
1202 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1203 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1204 | netif_stop_queue(dev); | |
1205 | } | |
1206 | ||
1207 | dev->stats.tx_bytes += skb->len; | |
1208 | ||
3e82ce12 RC |
1209 | skb_tx_timestamp(skb); |
1210 | ||
52f64fae RC |
1211 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1212 | ||
a9097a96 GC |
1213 | spin_unlock(&priv->tx_lock); |
1214 | ||
47dd7a54 GC |
1215 | return NETDEV_TX_OK; |
1216 | } | |
1217 | ||
1218 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1219 | { | |
1220 | unsigned int rxsize = priv->dma_rx_size; | |
1221 | int bfsize = priv->dma_buf_sz; | |
1222 | struct dma_desc *p = priv->dma_rx; | |
1223 | ||
1224 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1225 | unsigned int entry = priv->dirty_rx % rxsize; | |
1226 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1227 | struct sk_buff *skb; | |
1228 | ||
1229 | skb = __skb_dequeue(&priv->rx_recycle); | |
1230 | if (skb == NULL) | |
1231 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1232 | bfsize); | |
1233 | ||
1234 | if (unlikely(skb == NULL)) | |
1235 | break; | |
1236 | ||
1237 | priv->rx_skbuff[entry] = skb; | |
1238 | priv->rx_skbuff_dma[entry] = | |
1239 | dma_map_single(priv->device, skb->data, bfsize, | |
1240 | DMA_FROM_DEVICE); | |
1241 | ||
1242 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
286a8372 GC |
1243 | |
1244 | if (unlikely(priv->plat->has_gmac)) | |
1245 | priv->hw->ring->refill_desc3(bfsize, p + entry); | |
1246 | ||
47dd7a54 GC |
1247 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); |
1248 | } | |
eb0dc4bb | 1249 | wmb(); |
db98a0b0 | 1250 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1251 | } |
47dd7a54 GC |
1252 | } |
1253 | ||
1254 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1255 | { | |
1256 | unsigned int rxsize = priv->dma_rx_size; | |
1257 | unsigned int entry = priv->cur_rx % rxsize; | |
1258 | unsigned int next_entry; | |
1259 | unsigned int count = 0; | |
1260 | struct dma_desc *p = priv->dma_rx + entry; | |
1261 | struct dma_desc *p_next; | |
1262 | ||
1263 | #ifdef STMMAC_RX_DEBUG | |
1264 | if (netif_msg_hw(priv)) { | |
1265 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1266 | display_ring(priv->dma_rx, rxsize); | |
1267 | } | |
1268 | #endif | |
1269 | count = 0; | |
db98a0b0 | 1270 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1271 | int status; |
1272 | ||
1273 | if (count >= limit) | |
1274 | break; | |
1275 | ||
1276 | count++; | |
1277 | ||
1278 | next_entry = (++priv->cur_rx) % rxsize; | |
1279 | p_next = priv->dma_rx + next_entry; | |
1280 | prefetch(p_next); | |
1281 | ||
1282 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1283 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1284 | &priv->xstats, p)); | |
47dd7a54 GC |
1285 | if (unlikely(status == discard_frame)) |
1286 | priv->dev->stats.rx_errors++; | |
1287 | else { | |
1288 | struct sk_buff *skb; | |
3eeb2997 | 1289 | int frame_len; |
47dd7a54 | 1290 | |
3eeb2997 GC |
1291 | frame_len = priv->hw->desc->get_rx_frame_len(p); |
1292 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 | |
1293 | * Type frames (LLC/LLC-SNAP) */ | |
1294 | if (unlikely(status != llc_snap)) | |
1295 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1296 | #ifdef STMMAC_RX_DEBUG |
1297 | if (frame_len > ETH_FRAME_LEN) | |
1298 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1299 | frame_len, status); | |
1300 | ||
1301 | if (netif_msg_hw(priv)) | |
1302 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1303 | p, entry, p->des2); | |
1304 | #endif | |
1305 | skb = priv->rx_skbuff[entry]; | |
1306 | if (unlikely(!skb)) { | |
1307 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1308 | priv->dev->name); | |
1309 | priv->dev->stats.rx_dropped++; | |
1310 | break; | |
1311 | } | |
1312 | prefetch(skb->data - NET_IP_ALIGN); | |
1313 | priv->rx_skbuff[entry] = NULL; | |
1314 | ||
1315 | skb_put(skb, frame_len); | |
1316 | dma_unmap_single(priv->device, | |
1317 | priv->rx_skbuff_dma[entry], | |
1318 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1319 | #ifdef STMMAC_RX_DEBUG | |
1320 | if (netif_msg_pktdata(priv)) { | |
1321 | pr_info(" frame received (%dbytes)", frame_len); | |
1322 | print_pkt(skb->data, frame_len); | |
1323 | } | |
1324 | #endif | |
1325 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1326 | ||
3c20f72f GC |
1327 | if (unlikely(!priv->rx_coe)) { |
1328 | /* No RX COE for old mac10/100 devices */ | |
bc8acf2c | 1329 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1330 | netif_receive_skb(skb); |
1331 | } else { | |
1332 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1333 | napi_gro_receive(&priv->napi, skb); | |
1334 | } | |
1335 | ||
1336 | priv->dev->stats.rx_packets++; | |
1337 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1338 | } |
1339 | entry = next_entry; | |
1340 | p = p_next; /* use prefetched values */ | |
1341 | } | |
1342 | ||
1343 | stmmac_rx_refill(priv); | |
1344 | ||
1345 | priv->xstats.rx_pkt_n += count; | |
1346 | ||
1347 | return count; | |
1348 | } | |
1349 | ||
1350 | /** | |
1351 | * stmmac_poll - stmmac poll method (NAPI) | |
1352 | * @napi : pointer to the napi structure. | |
1353 | * @budget : maximum number of packets that the current CPU can receive from | |
1354 | * all interfaces. | |
1355 | * Description : | |
1356 | * This function implements the the reception process. | |
1357 | * Also it runs the TX completion thread | |
1358 | */ | |
1359 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1360 | { | |
1361 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1362 | int work_done = 0; | |
1363 | ||
1364 | priv->xstats.poll_n++; | |
1365 | stmmac_tx(priv); | |
1366 | work_done = stmmac_rx(priv, budget); | |
1367 | ||
1368 | if (work_done < budget) { | |
1369 | napi_complete(napi); | |
1370 | stmmac_enable_irq(priv); | |
1371 | } | |
1372 | return work_done; | |
1373 | } | |
1374 | ||
1375 | /** | |
1376 | * stmmac_tx_timeout | |
1377 | * @dev : Pointer to net device structure | |
1378 | * Description: this function is called when a packet transmission fails to | |
1379 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1380 | * netdev structure and arrange for the device to be reset to a sane state | |
1381 | * in order to transmit a new packet. | |
1382 | */ | |
1383 | static void stmmac_tx_timeout(struct net_device *dev) | |
1384 | { | |
1385 | struct stmmac_priv *priv = netdev_priv(dev); | |
1386 | ||
1387 | /* Clear Tx resources and restart transmitting again */ | |
1388 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1389 | } |
1390 | ||
1391 | /* Configuration changes (passed on by ifconfig) */ | |
1392 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1393 | { | |
1394 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1395 | return -EBUSY; | |
1396 | ||
1397 | /* Don't allow changing the I/O address */ | |
1398 | if (map->base_addr != dev->base_addr) { | |
1399 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1400 | return -EOPNOTSUPP; | |
1401 | } | |
1402 | ||
1403 | /* Don't allow changing the IRQ */ | |
1404 | if (map->irq != dev->irq) { | |
1405 | pr_warning("%s: can't change IRQ number %d\n", | |
1406 | dev->name, dev->irq); | |
1407 | return -EOPNOTSUPP; | |
1408 | } | |
1409 | ||
1410 | /* ignore other fields */ | |
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | /** | |
01789349 | 1415 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
1416 | * @dev : pointer to the device structure |
1417 | * Description: | |
1418 | * This function is a driver entry point which gets called by the kernel | |
1419 | * whenever multicast addresses must be enabled/disabled. | |
1420 | * Return value: | |
1421 | * void. | |
1422 | */ | |
01789349 | 1423 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
1424 | { |
1425 | struct stmmac_priv *priv = netdev_priv(dev); | |
1426 | ||
1427 | spin_lock(&priv->lock); | |
db98a0b0 | 1428 | priv->hw->mac->set_filter(dev); |
47dd7a54 | 1429 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1430 | } |
1431 | ||
1432 | /** | |
1433 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1434 | * @dev : device pointer. | |
1435 | * @new_mtu : the new MTU size for the device. | |
1436 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1437 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1438 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1439 | * Return value: | |
1440 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1441 | * file on failure. | |
1442 | */ | |
1443 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1444 | { | |
1445 | struct stmmac_priv *priv = netdev_priv(dev); | |
1446 | int max_mtu; | |
1447 | ||
1448 | if (netif_running(dev)) { | |
1449 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1450 | return -EBUSY; | |
1451 | } | |
1452 | ||
48febf7e | 1453 | if (priv->plat->enh_desc) |
47dd7a54 GC |
1454 | max_mtu = JUMBO_LEN; |
1455 | else | |
45db81e1 | 1456 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 GC |
1457 | |
1458 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1459 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1460 | return -EINVAL; | |
1461 | } | |
1462 | ||
5e982f3b MM |
1463 | dev->mtu = new_mtu; |
1464 | netdev_update_features(dev); | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | static u32 stmmac_fix_features(struct net_device *dev, u32 features) | |
1470 | { | |
1471 | struct stmmac_priv *priv = netdev_priv(dev); | |
1472 | ||
1473 | if (!priv->rx_coe) | |
1474 | features &= ~NETIF_F_RXCSUM; | |
1475 | if (!priv->plat->tx_coe) | |
1476 | features &= ~NETIF_F_ALL_CSUM; | |
1477 | ||
ebbb293f GC |
1478 | /* Some GMAC devices have a bugged Jumbo frame support that |
1479 | * needs to have the Tx COE disabled for oversized frames | |
1480 | * (due to limited buffer sizes). In this case we disable | |
1481 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1482 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1483 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1484 | |
5e982f3b | 1485 | return features; |
47dd7a54 GC |
1486 | } |
1487 | ||
1488 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1489 | { | |
1490 | struct net_device *dev = (struct net_device *)dev_id; | |
1491 | struct stmmac_priv *priv = netdev_priv(dev); | |
1492 | ||
1493 | if (unlikely(!dev)) { | |
1494 | pr_err("%s: invalid dev pointer\n", __func__); | |
1495 | return IRQ_NONE; | |
1496 | } | |
1497 | ||
9dfeb4d9 | 1498 | if (priv->plat->has_gmac) |
47dd7a54 | 1499 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1500 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1501 | |
1502 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1503 | |
1504 | return IRQ_HANDLED; | |
1505 | } | |
1506 | ||
1507 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1508 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1509 | * to allow network I/O with interrupts disabled. */ | |
1510 | static void stmmac_poll_controller(struct net_device *dev) | |
1511 | { | |
1512 | disable_irq(dev->irq); | |
1513 | stmmac_interrupt(dev->irq, dev); | |
1514 | enable_irq(dev->irq); | |
1515 | } | |
1516 | #endif | |
1517 | ||
1518 | /** | |
1519 | * stmmac_ioctl - Entry point for the Ioctl | |
1520 | * @dev: Device pointer. | |
1521 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1522 | * a proprietary structure used to pass information to the driver. | |
1523 | * @cmd: IOCTL command | |
1524 | * Description: | |
1525 | * Currently there are no special functionality supported in IOCTL, just the | |
1526 | * phy_mii_ioctl(...) can be invoked. | |
1527 | */ | |
1528 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1529 | { | |
1530 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1531 | int ret; |
47dd7a54 GC |
1532 | |
1533 | if (!netif_running(dev)) | |
1534 | return -EINVAL; | |
1535 | ||
28b04113 RC |
1536 | if (!priv->phydev) |
1537 | return -EINVAL; | |
1538 | ||
28b04113 | 1539 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); |
28b04113 | 1540 | |
47dd7a54 GC |
1541 | return ret; |
1542 | } | |
1543 | ||
7ac29055 GC |
1544 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1545 | static struct dentry *stmmac_fs_dir; | |
1546 | static struct dentry *stmmac_rings_status; | |
e7434821 | 1547 | static struct dentry *stmmac_dma_cap; |
7ac29055 GC |
1548 | |
1549 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) | |
1550 | { | |
1551 | struct tmp_s { | |
1552 | u64 a; | |
1553 | unsigned int b; | |
1554 | unsigned int c; | |
1555 | }; | |
1556 | int i; | |
1557 | struct net_device *dev = seq->private; | |
1558 | struct stmmac_priv *priv = netdev_priv(dev); | |
1559 | ||
1560 | seq_printf(seq, "=======================\n"); | |
1561 | seq_printf(seq, " RX descriptor ring\n"); | |
1562 | seq_printf(seq, "=======================\n"); | |
1563 | ||
1564 | for (i = 0; i < priv->dma_rx_size; i++) { | |
1565 | struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); | |
1566 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1567 | i, (unsigned int)(x->a), | |
1568 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1569 | seq_printf(seq, "\n"); | |
1570 | } | |
1571 | ||
1572 | seq_printf(seq, "\n"); | |
1573 | seq_printf(seq, "=======================\n"); | |
1574 | seq_printf(seq, " TX descriptor ring\n"); | |
1575 | seq_printf(seq, "=======================\n"); | |
1576 | ||
1577 | for (i = 0; i < priv->dma_tx_size; i++) { | |
1578 | struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); | |
1579 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1580 | i, (unsigned int)(x->a), | |
1581 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1582 | seq_printf(seq, "\n"); | |
1583 | } | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
1589 | { | |
1590 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
1591 | } | |
1592 | ||
1593 | static const struct file_operations stmmac_rings_status_fops = { | |
1594 | .owner = THIS_MODULE, | |
1595 | .open = stmmac_sysfs_ring_open, | |
1596 | .read = seq_read, | |
1597 | .llseek = seq_lseek, | |
1598 | .release = seq_release, | |
1599 | }; | |
1600 | ||
e7434821 GC |
1601 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
1602 | { | |
1603 | struct net_device *dev = seq->private; | |
1604 | struct stmmac_priv *priv = netdev_priv(dev); | |
1605 | ||
19e30c14 | 1606 | if (!priv->hw_cap_support) { |
e7434821 GC |
1607 | seq_printf(seq, "DMA HW features not supported\n"); |
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | seq_printf(seq, "==============================\n"); | |
1612 | seq_printf(seq, "\tDMA HW features\n"); | |
1613 | seq_printf(seq, "==============================\n"); | |
1614 | ||
1615 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
1616 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
1617 | seq_printf(seq, "\t1000 Mbps %s\n", | |
1618 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
1619 | seq_printf(seq, "\tHalf duple %s\n", | |
1620 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
1621 | seq_printf(seq, "\tHash Filter: %s\n", | |
1622 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
1623 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
1624 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
1625 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
1626 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
1627 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
1628 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
1629 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
1630 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
1631 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
1632 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
1633 | seq_printf(seq, "\tRMON module: %s\n", | |
1634 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
1635 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
1636 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
1637 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
1638 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
1639 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
1640 | (priv->dma_cap.eee) ? "Y" : "N"); | |
1641 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
1642 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
1643 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
1644 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
1645 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
1646 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
1647 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
1648 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
1649 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
1650 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
1651 | priv->dma_cap.number_rx_channel); | |
1652 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
1653 | priv->dma_cap.number_tx_channel); | |
1654 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
1655 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
1661 | { | |
1662 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
1663 | } | |
1664 | ||
1665 | static const struct file_operations stmmac_dma_cap_fops = { | |
1666 | .owner = THIS_MODULE, | |
1667 | .open = stmmac_sysfs_dma_cap_open, | |
1668 | .read = seq_read, | |
1669 | .llseek = seq_lseek, | |
1670 | .release = seq_release, | |
1671 | }; | |
1672 | ||
7ac29055 GC |
1673 | static int stmmac_init_fs(struct net_device *dev) |
1674 | { | |
1675 | /* Create debugfs entries */ | |
1676 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
1677 | ||
1678 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
1679 | pr_err("ERROR %s, debugfs create directory failed\n", | |
1680 | STMMAC_RESOURCE_NAME); | |
1681 | ||
1682 | return -ENOMEM; | |
1683 | } | |
1684 | ||
1685 | /* Entry to report DMA RX/TX rings */ | |
1686 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
1687 | S_IRUGO, stmmac_fs_dir, dev, | |
1688 | &stmmac_rings_status_fops); | |
1689 | ||
1690 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
1691 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
1692 | debugfs_remove(stmmac_fs_dir); | |
1693 | ||
1694 | return -ENOMEM; | |
1695 | } | |
1696 | ||
e7434821 GC |
1697 | /* Entry to report the DMA HW features */ |
1698 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
1699 | dev, &stmmac_dma_cap_fops); | |
1700 | ||
1701 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
1702 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
1703 | debugfs_remove(stmmac_rings_status); | |
1704 | debugfs_remove(stmmac_fs_dir); | |
1705 | ||
1706 | return -ENOMEM; | |
1707 | } | |
1708 | ||
7ac29055 GC |
1709 | return 0; |
1710 | } | |
1711 | ||
1712 | static void stmmac_exit_fs(void) | |
1713 | { | |
1714 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 1715 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
1716 | debugfs_remove(stmmac_fs_dir); |
1717 | } | |
1718 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
1719 | ||
47dd7a54 GC |
1720 | static const struct net_device_ops stmmac_netdev_ops = { |
1721 | .ndo_open = stmmac_open, | |
1722 | .ndo_start_xmit = stmmac_xmit, | |
1723 | .ndo_stop = stmmac_release, | |
1724 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1725 | .ndo_fix_features = stmmac_fix_features, |
01789349 | 1726 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
1727 | .ndo_tx_timeout = stmmac_tx_timeout, |
1728 | .ndo_do_ioctl = stmmac_ioctl, | |
1729 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1730 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1731 | .ndo_poll_controller = stmmac_poll_controller, | |
1732 | #endif | |
1733 | .ndo_set_mac_address = eth_mac_addr, | |
1734 | }; | |
1735 | ||
1736 | /** | |
1737 | * stmmac_probe - Initialization of the adapter . | |
1738 | * @dev : device pointer | |
1739 | * Description: The function initializes the network device structure for | |
1740 | * the STMMAC driver. It also calls the low level routines | |
1741 | * in order to init the HW (i.e. the DMA engine) | |
1742 | */ | |
1743 | static int stmmac_probe(struct net_device *dev) | |
1744 | { | |
1745 | int ret = 0; | |
1746 | struct stmmac_priv *priv = netdev_priv(dev); | |
1747 | ||
1748 | ether_setup(dev); | |
1749 | ||
1750 | dev->netdev_ops = &stmmac_netdev_ops; | |
1751 | stmmac_set_ethtool_ops(dev); | |
1752 | ||
5e982f3b MM |
1753 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
1754 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; | |
47dd7a54 GC |
1755 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
1756 | #ifdef STMMAC_VLAN_TAG_USED | |
1757 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
1758 | dev->features |= NETIF_F_HW_VLAN_RX; | |
1759 | #endif | |
1760 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1761 | ||
47dd7a54 GC |
1762 | if (flow_ctrl) |
1763 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1764 | ||
1765 | priv->pause = pause; | |
1766 | netif_napi_add(dev, &priv->napi, stmmac_poll, 64); | |
1767 | ||
1768 | /* Get the MAC address */ | |
ad01b7d4 GC |
1769 | priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr, |
1770 | dev->dev_addr, 0); | |
47dd7a54 GC |
1771 | |
1772 | if (!is_valid_ether_addr(dev->dev_addr)) | |
1773 | pr_warning("\tno valid MAC address;" | |
1774 | "please, use ifconfig or nwhwconfig!\n"); | |
1775 | ||
f8e96161 | 1776 | spin_lock_init(&priv->lock); |
a9097a96 | 1777 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 1778 | |
47dd7a54 GC |
1779 | ret = register_netdev(dev); |
1780 | if (ret) { | |
1781 | pr_err("%s: ERROR %i registering the device\n", | |
1782 | __func__, ret); | |
1783 | return -ENODEV; | |
1784 | } | |
1785 | ||
1786 | DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n", | |
1787 | dev->name, (dev->features & NETIF_F_SG) ? "on" : "off", | |
79032644 | 1788 | (dev->features & NETIF_F_IP_CSUM) ? "on" : "off"); |
47dd7a54 | 1789 | |
47dd7a54 GC |
1790 | return ret; |
1791 | } | |
1792 | ||
1793 | /** | |
1794 | * stmmac_mac_device_setup | |
1795 | * @dev : device pointer | |
1796 | * Description: select and initialise the mac device (mac100 or Gmac). | |
1797 | */ | |
1798 | static int stmmac_mac_device_setup(struct net_device *dev) | |
1799 | { | |
1800 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1801 | |
1802 | struct mac_device_info *device; | |
1803 | ||
01789349 JP |
1804 | if (priv->plat->has_gmac) { |
1805 | dev->priv_flags |= IFF_UNICAST_FLT; | |
ad01b7d4 | 1806 | device = dwmac1000_setup(priv->ioaddr); |
01789349 | 1807 | } else { |
ad01b7d4 | 1808 | device = dwmac100_setup(priv->ioaddr); |
01789349 | 1809 | } |
3d90c508 | 1810 | |
1ff21906 DC |
1811 | if (!device) |
1812 | return -ENOMEM; | |
1813 | ||
db98a0b0 | 1814 | priv->hw = device; |
286a8372 | 1815 | priv->hw->ring = &ring_mode_ops; |
47dd7a54 | 1816 | |
539c9aa5 | 1817 | if (device_can_wakeup(priv->device)) { |
543876c9 | 1818 | priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ |
3172d3af | 1819 | enable_irq_wake(priv->wol_irq); |
539c9aa5 | 1820 | } |
47dd7a54 GC |
1821 | |
1822 | return 0; | |
1823 | } | |
1824 | ||
47dd7a54 GC |
1825 | /** |
1826 | * stmmac_dvr_probe | |
1827 | * @pdev: platform device pointer | |
1828 | * Description: the driver is initialized through platform_device. | |
1829 | */ | |
1830 | static int stmmac_dvr_probe(struct platform_device *pdev) | |
1831 | { | |
1832 | int ret = 0; | |
1833 | struct resource *res; | |
ad01b7d4 | 1834 | void __iomem *addr = NULL; |
47dd7a54 | 1835 | struct net_device *ndev = NULL; |
293bb1c4 | 1836 | struct stmmac_priv *priv = NULL; |
47dd7a54 GC |
1837 | struct plat_stmmacenet_data *plat_dat; |
1838 | ||
1839 | pr_info("STMMAC driver:\n\tplatform registration... "); | |
1840 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
34a52f36 DC |
1841 | if (!res) |
1842 | return -ENODEV; | |
ebbb293f | 1843 | pr_info("\tdone!\n"); |
47dd7a54 | 1844 | |
b6222682 | 1845 | if (!request_mem_region(res->start, resource_size(res), |
47dd7a54 GC |
1846 | pdev->name)) { |
1847 | pr_err("%s: ERROR: memory allocation failed" | |
1848 | "cannot get the I/O addr 0x%x\n", | |
1849 | __func__, (unsigned int)res->start); | |
34a52f36 | 1850 | return -EBUSY; |
47dd7a54 GC |
1851 | } |
1852 | ||
7c5365bc | 1853 | addr = ioremap(res->start, resource_size(res)); |
47dd7a54 | 1854 | if (!addr) { |
7c5365bc | 1855 | pr_err("%s: ERROR: memory mapping failed\n", __func__); |
47dd7a54 | 1856 | ret = -ENOMEM; |
34a52f36 | 1857 | goto out_release_region; |
47dd7a54 GC |
1858 | } |
1859 | ||
1860 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); | |
1861 | if (!ndev) { | |
1862 | pr_err("%s: ERROR: allocating the device\n", __func__); | |
1863 | ret = -ENOMEM; | |
34a52f36 | 1864 | goto out_unmap; |
47dd7a54 GC |
1865 | } |
1866 | ||
1867 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1868 | ||
1869 | /* Get the MAC information */ | |
1870 | ndev->irq = platform_get_irq_byname(pdev, "macirq"); | |
1871 | if (ndev->irq == -ENXIO) { | |
1872 | pr_err("%s: ERROR: MAC IRQ configuration " | |
1873 | "information not found\n", __func__); | |
34a52f36 DC |
1874 | ret = -ENXIO; |
1875 | goto out_free_ndev; | |
47dd7a54 GC |
1876 | } |
1877 | ||
1878 | priv = netdev_priv(ndev); | |
1879 | priv->device = &(pdev->dev); | |
1880 | priv->dev = ndev; | |
ee7946a7 | 1881 | plat_dat = pdev->dev.platform_data; |
9dfeb4d9 GC |
1882 | |
1883 | priv->plat = plat_dat; | |
1884 | ||
ad01b7d4 | 1885 | priv->ioaddr = addr; |
47dd7a54 | 1886 | |
3172d3af DS |
1887 | /* |
1888 | * On some platforms e.g. SPEAr the wake up irq differs from the mac irq | |
1889 | * The external wake up irq can be passed through the platform code | |
1890 | * named as "eth_wake_irq" | |
1891 | * | |
1892 | * In case the wake up interrupt is not passed from the platform | |
1893 | * so the driver will continue to use the mac irq (ndev->irq) | |
1894 | */ | |
1895 | priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq"); | |
1896 | if (priv->wol_irq == -ENXIO) | |
1897 | priv->wol_irq = ndev->irq; | |
1898 | ||
47dd7a54 GC |
1899 | platform_set_drvdata(pdev, ndev); |
1900 | ||
1901 | /* Set the I/O base addr */ | |
1902 | ndev->base_addr = (unsigned long)addr; | |
1903 | ||
293bb1c4 GC |
1904 | /* Custom initialisation */ |
1905 | if (priv->plat->init) { | |
1906 | ret = priv->plat->init(pdev); | |
1907 | if (unlikely(ret)) | |
34a52f36 | 1908 | goto out_free_ndev; |
293bb1c4 | 1909 | } |
ee7946a7 | 1910 | |
19e30c14 | 1911 | /* MAC HW device detection */ |
47dd7a54 GC |
1912 | ret = stmmac_mac_device_setup(ndev); |
1913 | if (ret < 0) | |
34a52f36 | 1914 | goto out_plat_exit; |
47dd7a54 GC |
1915 | |
1916 | /* Network Device Registration */ | |
1917 | ret = stmmac_probe(ndev); | |
1918 | if (ret < 0) | |
34a52f36 | 1919 | goto out_plat_exit; |
47dd7a54 | 1920 | |
36bcfe7d GC |
1921 | /* Override with kernel parameters if supplied XXX CRS XXX |
1922 | * this needs to have multiple instances */ | |
1923 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
1924 | priv->plat->phy_addr = phyaddr; | |
47dd7a54 | 1925 | |
47dd7a54 | 1926 | pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n" |
1f0f6388 DM |
1927 | "\tIO base addr: 0x%p)\n", ndev->name, pdev->name, |
1928 | pdev->id, ndev->irq, addr); | |
47dd7a54 GC |
1929 | |
1930 | /* MDIO bus Registration */ | |
9dfeb4d9 | 1931 | pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id); |
47dd7a54 GC |
1932 | ret = stmmac_mdio_register(ndev); |
1933 | if (ret < 0) | |
34a52f36 | 1934 | goto out_unregister; |
47dd7a54 | 1935 | pr_debug("registered!\n"); |
7ac29055 GC |
1936 | |
1937 | #ifdef CONFIG_STMMAC_DEBUG_FS | |
1938 | ret = stmmac_init_fs(ndev); | |
1939 | if (ret < 0) | |
1940 | pr_warning("\tFailed debugFS registration"); | |
1941 | #endif | |
1942 | ||
34a52f36 | 1943 | return 0; |
47dd7a54 | 1944 | |
34a52f36 DC |
1945 | out_unregister: |
1946 | unregister_netdev(ndev); | |
1947 | out_plat_exit: | |
1948 | if (priv->plat->exit) | |
1949 | priv->plat->exit(pdev); | |
1950 | out_free_ndev: | |
1951 | free_netdev(ndev); | |
1952 | platform_set_drvdata(pdev, NULL); | |
1953 | out_unmap: | |
1954 | iounmap(addr); | |
1955 | out_release_region: | |
1956 | release_mem_region(res->start, resource_size(res)); | |
47dd7a54 GC |
1957 | |
1958 | return ret; | |
1959 | } | |
1960 | ||
1961 | /** | |
1962 | * stmmac_dvr_remove | |
1963 | * @pdev: platform device pointer | |
1964 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX | |
1965 | * changes the link status, releases the DMA descriptor rings, | |
1966 | * unregisters the MDIO bus and unmaps the allocated memory. | |
1967 | */ | |
1968 | static int stmmac_dvr_remove(struct platform_device *pdev) | |
1969 | { | |
1970 | struct net_device *ndev = platform_get_drvdata(pdev); | |
aec7ff27 | 1971 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1972 | struct resource *res; |
1973 | ||
1974 | pr_info("%s:\n\tremoving driver", __func__); | |
1975 | ||
ad01b7d4 GC |
1976 | priv->hw->dma->stop_rx(priv->ioaddr); |
1977 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1978 | |
19449bfc | 1979 | stmmac_disable_mac(priv->ioaddr); |
47dd7a54 GC |
1980 | |
1981 | netif_carrier_off(ndev); | |
1982 | ||
1983 | stmmac_mdio_unregister(ndev); | |
1984 | ||
293bb1c4 GC |
1985 | if (priv->plat->exit) |
1986 | priv->plat->exit(pdev); | |
1987 | ||
47dd7a54 GC |
1988 | platform_set_drvdata(pdev, NULL); |
1989 | unregister_netdev(ndev); | |
1990 | ||
ad01b7d4 | 1991 | iounmap((void *)priv->ioaddr); |
47dd7a54 | 1992 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7c5365bc | 1993 | release_mem_region(res->start, resource_size(res)); |
47dd7a54 | 1994 | |
7ac29055 GC |
1995 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1996 | stmmac_exit_fs(); | |
1997 | #endif | |
1998 | ||
47dd7a54 GC |
1999 | free_netdev(ndev); |
2000 | ||
2001 | return 0; | |
2002 | } | |
2003 | ||
2004 | #ifdef CONFIG_PM | |
874bd42d | 2005 | static int stmmac_suspend(struct device *dev) |
47dd7a54 | 2006 | { |
874bd42d GC |
2007 | struct net_device *ndev = dev_get_drvdata(dev); |
2008 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 GC |
2009 | int dis_ic = 0; |
2010 | ||
874bd42d | 2011 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
2012 | return 0; |
2013 | ||
102463b1 FV |
2014 | if (priv->phydev) |
2015 | phy_stop(priv->phydev); | |
2016 | ||
47dd7a54 GC |
2017 | spin_lock(&priv->lock); |
2018 | ||
874bd42d GC |
2019 | netif_device_detach(ndev); |
2020 | netif_stop_queue(ndev); | |
47dd7a54 GC |
2021 | |
2022 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2023 | priv->tm->timer_stop(); |
2024 | if (likely(priv->tm->enable)) | |
2025 | dis_ic = 1; | |
47dd7a54 | 2026 | #endif |
874bd42d GC |
2027 | napi_disable(&priv->napi); |
2028 | ||
2029 | /* Stop TX/RX DMA */ | |
2030 | priv->hw->dma->stop_tx(priv->ioaddr); | |
2031 | priv->hw->dma->stop_rx(priv->ioaddr); | |
2032 | /* Clear the Rx/Tx descriptors */ | |
2033 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
2034 | dis_ic); | |
2035 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
2036 | ||
2037 | /* Enable Power down mode by programming the PMT regs */ | |
2038 | if (device_may_wakeup(priv->device)) | |
2039 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
2040 | else | |
2041 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
2042 | |
2043 | spin_unlock(&priv->lock); | |
2044 | return 0; | |
2045 | } | |
2046 | ||
874bd42d | 2047 | static int stmmac_resume(struct device *dev) |
47dd7a54 | 2048 | { |
874bd42d GC |
2049 | struct net_device *ndev = dev_get_drvdata(dev); |
2050 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 | 2051 | |
874bd42d | 2052 | if (!netif_running(ndev)) |
47dd7a54 GC |
2053 | return 0; |
2054 | ||
c4433be6 GC |
2055 | spin_lock(&priv->lock); |
2056 | ||
47dd7a54 GC |
2057 | /* Power Down bit, into the PM register, is cleared |
2058 | * automatically as soon as a magic packet or a Wake-up frame | |
2059 | * is received. Anyway, it's better to manually clear | |
2060 | * this bit because it can generate problems while resuming | |
2061 | * from another devices (e.g. serial console). */ | |
874bd42d | 2062 | if (device_may_wakeup(priv->device)) |
543876c9 | 2063 | priv->hw->mac->pmt(priv->ioaddr, 0); |
47dd7a54 | 2064 | |
874bd42d | 2065 | netif_device_attach(ndev); |
47dd7a54 GC |
2066 | |
2067 | /* Enable the MAC and DMA */ | |
19449bfc | 2068 | stmmac_enable_mac(priv->ioaddr); |
ad01b7d4 GC |
2069 | priv->hw->dma->start_tx(priv->ioaddr); |
2070 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
2071 | |
2072 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2073 | if (likely(priv->tm->enable)) |
2074 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
2075 | #endif |
2076 | napi_enable(&priv->napi); | |
2077 | ||
874bd42d | 2078 | netif_start_queue(ndev); |
47dd7a54 | 2079 | |
47dd7a54 | 2080 | spin_unlock(&priv->lock); |
102463b1 FV |
2081 | |
2082 | if (priv->phydev) | |
2083 | phy_start(priv->phydev); | |
2084 | ||
47dd7a54 GC |
2085 | return 0; |
2086 | } | |
47dd7a54 | 2087 | |
874bd42d GC |
2088 | static int stmmac_freeze(struct device *dev) |
2089 | { | |
2090 | struct net_device *ndev = dev_get_drvdata(dev); | |
2091 | ||
2092 | if (!ndev || !netif_running(ndev)) | |
2093 | return 0; | |
2094 | ||
2095 | return stmmac_release(ndev); | |
2096 | } | |
2097 | ||
2098 | static int stmmac_restore(struct device *dev) | |
2099 | { | |
2100 | struct net_device *ndev = dev_get_drvdata(dev); | |
2101 | ||
2102 | if (!ndev || !netif_running(ndev)) | |
2103 | return 0; | |
2104 | ||
2105 | return stmmac_open(ndev); | |
2106 | } | |
2107 | ||
2108 | static const struct dev_pm_ops stmmac_pm_ops = { | |
47dd7a54 GC |
2109 | .suspend = stmmac_suspend, |
2110 | .resume = stmmac_resume, | |
874bd42d GC |
2111 | .freeze = stmmac_freeze, |
2112 | .thaw = stmmac_restore, | |
2113 | .restore = stmmac_restore, | |
2114 | }; | |
2115 | #else | |
2116 | static const struct dev_pm_ops stmmac_pm_ops; | |
2117 | #endif /* CONFIG_PM */ | |
47dd7a54 | 2118 | |
874bd42d GC |
2119 | static struct platform_driver stmmac_driver = { |
2120 | .probe = stmmac_dvr_probe, | |
2121 | .remove = stmmac_dvr_remove, | |
2122 | .driver = { | |
2123 | .name = STMMAC_RESOURCE_NAME, | |
2124 | .owner = THIS_MODULE, | |
2125 | .pm = &stmmac_pm_ops, | |
2126 | }, | |
47dd7a54 GC |
2127 | }; |
2128 | ||
2129 | /** | |
2130 | * stmmac_init_module - Entry point for the driver | |
2131 | * Description: This function is the entry point for the driver. | |
2132 | */ | |
2133 | static int __init stmmac_init_module(void) | |
2134 | { | |
2135 | int ret; | |
2136 | ||
47dd7a54 GC |
2137 | ret = platform_driver_register(&stmmac_driver); |
2138 | return ret; | |
2139 | } | |
2140 | ||
2141 | /** | |
2142 | * stmmac_cleanup_module - Cleanup routine for the driver | |
2143 | * Description: This function is the cleanup routine for the driver. | |
2144 | */ | |
2145 | static void __exit stmmac_cleanup_module(void) | |
2146 | { | |
47dd7a54 GC |
2147 | platform_driver_unregister(&stmmac_driver); |
2148 | } | |
2149 | ||
2150 | #ifndef MODULE | |
2151 | static int __init stmmac_cmdline_opt(char *str) | |
2152 | { | |
2153 | char *opt; | |
2154 | ||
2155 | if (!str || !*str) | |
2156 | return -EINVAL; | |
2157 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 GC |
2158 | if (!strncmp(opt, "debug:", 6)) { |
2159 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) | |
2160 | goto err; | |
2161 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
2162 | if (strict_strtoul(opt + 8, 0, | |
2163 | (unsigned long *)&phyaddr)) | |
2164 | goto err; | |
2165 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
2166 | if (strict_strtoul(opt + 11, 0, | |
2167 | (unsigned long *)&dma_txsize)) | |
2168 | goto err; | |
2169 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
2170 | if (strict_strtoul(opt + 11, 0, | |
2171 | (unsigned long *)&dma_rxsize)) | |
2172 | goto err; | |
2173 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
2174 | if (strict_strtoul(opt + 7, 0, | |
2175 | (unsigned long *)&buf_sz)) | |
2176 | goto err; | |
2177 | } else if (!strncmp(opt, "tc:", 3)) { | |
2178 | if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) | |
2179 | goto err; | |
2180 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
2181 | if (strict_strtoul(opt + 9, 0, | |
2182 | (unsigned long *)&watchdog)) | |
2183 | goto err; | |
2184 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
2185 | if (strict_strtoul(opt + 10, 0, | |
2186 | (unsigned long *)&flow_ctrl)) | |
2187 | goto err; | |
2188 | } else if (!strncmp(opt, "pause:", 6)) { | |
2189 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) | |
2190 | goto err; | |
47dd7a54 | 2191 | #ifdef CONFIG_STMMAC_TIMER |
f3240e28 GC |
2192 | } else if (!strncmp(opt, "tmrate:", 7)) { |
2193 | if (strict_strtoul(opt + 7, 0, | |
2194 | (unsigned long *)&tmrate)) | |
2195 | goto err; | |
47dd7a54 | 2196 | #endif |
f3240e28 | 2197 | } |
47dd7a54 GC |
2198 | } |
2199 | return 0; | |
f3240e28 GC |
2200 | |
2201 | err: | |
2202 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
2203 | return -EINVAL; | |
47dd7a54 GC |
2204 | } |
2205 | ||
2206 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
2207 | #endif | |
2208 | ||
2209 | module_init(stmmac_init_module); | |
2210 | module_exit(stmmac_cleanup_module); | |
2211 | ||
2212 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver"); | |
2213 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
2214 | MODULE_LICENSE("GPL"); |