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stmmac: MDC clock dynamically based on the csr clock input
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
47dd7a54
GC		 31#include <linux/kernel.h>
32#include <linux/interrupt.h>
47dd7a54
GC		 33#include <linux/ip.h>
34#include <linux/tcp.h>
35#include <linux/skbuff.h>
36#include <linux/ethtool.h>
37#include <linux/if_ether.h>
38#include <linux/crc32.h>
39#include <linux/mii.h>
01789349 40#include <linux/if.h>
47dd7a54
GC		 41#include <linux/if_vlan.h>
42#include <linux/dma-mapping.h>
5a0e3ad6 43#include <linux/slab.h>
70c71606 44#include <linux/prefetch.h>
7ac29055
GC		 45#ifdef CONFIG_STMMAC_DEBUG_FS
46#include <linux/debugfs.h>
47#include <linux/seq_file.h>
48#endif
286a8372 49#include "stmmac.h"
47dd7a54 50
47dd7a54
GC		 51#undef STMMAC_DEBUG
52/*#define STMMAC_DEBUG*/
53#ifdef STMMAC_DEBUG
54#define DBG(nlevel, klevel, fmt, args...) \
55 ((void)(netif_msg_##nlevel(priv) && \
56 printk(KERN_##klevel fmt, ## args)))
57#else
58#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
59#endif
60
61#undef STMMAC_RX_DEBUG
62/*#define STMMAC_RX_DEBUG*/
63#ifdef STMMAC_RX_DEBUG
64#define RX_DBG(fmt, args...) printk(fmt, ## args)
65#else
66#define RX_DBG(fmt, args...) do { } while (0)
67#endif
68
69#undef STMMAC_XMIT_DEBUG
70/*#define STMMAC_XMIT_DEBUG*/
71#ifdef STMMAC_TX_DEBUG
72#define TX_DBG(fmt, args...) printk(fmt, ## args)
73#else
74#define TX_DBG(fmt, args...) do { } while (0)
75#endif
76
77#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
78#define JUMBO_LEN 9000
79
80/* Module parameters */
81#define TX_TIMEO 5000 /* default 5 seconds */
82static int watchdog = TX_TIMEO;
83module_param(watchdog, int, S_IRUGO | S_IWUSR);
84MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
85
86static int debug = -1; /* -1: default, 0: no output, 16: all */
87module_param(debug, int, S_IRUGO | S_IWUSR);
88MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
89
bfab27a1 90int phyaddr = -1;
47dd7a54
GC		 91module_param(phyaddr, int, S_IRUGO);
92MODULE_PARM_DESC(phyaddr, "Physical device address");
93
94#define DMA_TX_SIZE 256
95static int dma_txsize = DMA_TX_SIZE;
96module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
97MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
98
99#define DMA_RX_SIZE 256
100static int dma_rxsize = DMA_RX_SIZE;
101module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
102MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
103
104static int flow_ctrl = FLOW_OFF;
105module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
106MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
107
108static int pause = PAUSE_TIME;
109module_param(pause, int, S_IRUGO | S_IWUSR);
110MODULE_PARM_DESC(pause, "Flow Control Pause Time");
111
112#define TC_DEFAULT 64
113static int tc = TC_DEFAULT;
114module_param(tc, int, S_IRUGO | S_IWUSR);
115MODULE_PARM_DESC(tc, "DMA threshold control value");
116
47dd7a54
GC		 117/* Pay attention to tune this parameter; take care of both
118 * hardware capability and network stabitily/performance impact.
119 * Many tests showed that ~4ms latency seems to be good enough. */
120#ifdef CONFIG_STMMAC_TIMER
121#define DEFAULT_PERIODIC_RATE 256
122static int tmrate = DEFAULT_PERIODIC_RATE;
123module_param(tmrate, int, S_IRUGO | S_IWUSR);
124MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
125#endif
126
127#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
128static int buf_sz = DMA_BUFFER_SIZE;
129module_param(buf_sz, int, S_IRUGO | S_IWUSR);
130MODULE_PARM_DESC(buf_sz, "DMA buffer size");
131
47dd7a54
GC		 132static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
133 NETIF_MSG_LINK | NETIF_MSG_IFUP |
134 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
135
136static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54 137
bfab27a1
GC		 138#ifdef CONFIG_STMMAC_DEBUG_FS
139static int stmmac_init_fs(struct net_device *dev);
140static void stmmac_exit_fs(void);
141#endif
142
47dd7a54
GC		 143/**
144 * stmmac_verify_args - verify the driver parameters.
145 * Description: it verifies if some wrong parameter is passed to the driver.
146 * Note that wrong parameters are replaced with the default values.
147 */
148static void stmmac_verify_args(void)
149{
150 if (unlikely(watchdog < 0))
151 watchdog = TX_TIMEO;
152 if (unlikely(dma_rxsize < 0))
153 dma_rxsize = DMA_RX_SIZE;
154 if (unlikely(dma_txsize < 0))
155 dma_txsize = DMA_TX_SIZE;
156 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
157 buf_sz = DMA_BUFFER_SIZE;
158 if (unlikely(flow_ctrl > 1))
159 flow_ctrl = FLOW_AUTO;
160 else if (likely(flow_ctrl < 0))
161 flow_ctrl = FLOW_OFF;
162 if (unlikely((pause < 0) || (pause > 0xffff)))
163 pause = PAUSE_TIME;
47dd7a54
GC		 164}
165
cd7201f4
GC		 166static void stmmac_clk_csr_set(struct stmmac_priv *priv)
167{
168#ifdef CONFIG_HAVE_CLK
169 u32 clk_rate;
170
171 clk_rate = clk_get_rate(priv->stmmac_clk);
172
173 /* Platform provided default clk_csr would be assumed valid
174 * for all other cases except for the below mentioned ones. */
175 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
176 if (clk_rate < CSR_F_35M)
177 priv->clk_csr = STMMAC_CSR_20_35M;
178 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
179 priv->clk_csr = STMMAC_CSR_35_60M;
180 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
181 priv->clk_csr = STMMAC_CSR_60_100M;
182 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
183 priv->clk_csr = STMMAC_CSR_100_150M;
184 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
185 priv->clk_csr = STMMAC_CSR_150_250M;
186 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
187 priv->clk_csr = STMMAC_CSR_250_300M;
188 } /* For values higher than the IEEE 802.3 specified frequency
189 * we can not estimate the proper divider as it is not known
190 * the frequency of clk_csr_i. So we do not change the default
191 * divider. */
192#endif
193}
194
47dd7a54
GC		 195#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
196static void print_pkt(unsigned char *buf, int len)
197{
198 int j;
199 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
200 for (j = 0; j < len; j++) {
201 if ((j % 16) == 0)
202 pr_info("\n %03x:", j);
203 pr_info(" %02x", buf[j]);
204 }
205 pr_info("\n");
47dd7a54
GC		 206}
207#endif
208
209/* minimum number of free TX descriptors required to wake up TX process */
210#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
211
212static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
213{
214 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
215}
216
9dfeb4d9
GC		 217/* On some ST platforms, some HW system configuraton registers have to be
218 * set according to the link speed negotiated.
219 */
220static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
221{
222 struct phy_device *phydev = priv->phydev;
223
224 if (likely(priv->plat->fix_mac_speed))
225 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
226 phydev->speed);
227}
228
47dd7a54
GC		 229/**
230 * stmmac_adjust_link
231 * @dev: net device structure
232 * Description: it adjusts the link parameters.
233 */
234static void stmmac_adjust_link(struct net_device *dev)
235{
236 struct stmmac_priv *priv = netdev_priv(dev);
237 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 238 unsigned long flags;
239 int new_state = 0;
240 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
241
242 if (phydev == NULL)
243 return;
244
245 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
246 phydev->addr, phydev->link);
247
248 spin_lock_irqsave(&priv->lock, flags);
249 if (phydev->link) {
ad01b7d4 250 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 251
252 /* Now we make sure that we can be in full duplex mode.
253 * If not, we operate in half-duplex mode. */
254 if (phydev->duplex != priv->oldduplex) {
255 new_state = 1;
256 if (!(phydev->duplex))
db98a0b0 257 ctrl &= ~priv->hw->link.duplex;
47dd7a54 258 else
db98a0b0 259 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 260 priv->oldduplex = phydev->duplex;
261 }
262 /* Flow Control operation */
263 if (phydev->pause)
ad01b7d4 264 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 265 fc, pause_time);
47dd7a54
GC		 266
267 if (phydev->speed != priv->speed) {
268 new_state = 1;
269 switch (phydev->speed) {
270 case 1000:
9dfeb4d9 271 if (likely(priv->plat->has_gmac))
db98a0b0 272 ctrl &= ~priv->hw->link.port;
cf3f047b 273 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 274 break;
275 case 100:
276 case 10:
9dfeb4d9 277 if (priv->plat->has_gmac) {
db98a0b0 278 ctrl |= priv->hw->link.port;
47dd7a54 279 if (phydev->speed == SPEED_100) {
db98a0b0 280 ctrl |= priv->hw->link.speed;
47dd7a54 281 } else {
db98a0b0 282 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 283 }
284 } else {
db98a0b0 285 ctrl &= ~priv->hw->link.port;
47dd7a54 286 }
9dfeb4d9 287 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 288 break;
289 default:
290 if (netif_msg_link(priv))
291 pr_warning("%s: Speed (%d) is not 10"
292 " or 100!\n", dev->name, phydev->speed);
293 break;
294 }
295
296 priv->speed = phydev->speed;
297 }
298
ad01b7d4 299 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 300
301 if (!priv->oldlink) {
302 new_state = 1;
303 priv->oldlink = 1;
304 }
305 } else if (priv->oldlink) {
306 new_state = 1;
307 priv->oldlink = 0;
308 priv->speed = 0;
309 priv->oldduplex = -1;
310 }
311
312 if (new_state && netif_msg_link(priv))
313 phy_print_status(phydev);
314
315 spin_unlock_irqrestore(&priv->lock, flags);
316
317 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
318}
319
320/**
321 * stmmac_init_phy - PHY initialization
322 * @dev: net device structure
323 * Description: it initializes the driver's PHY state, and attaches the PHY
324 * to the mac driver.
325 * Return value:
326 * 0 on success
327 */
328static int stmmac_init_phy(struct net_device *dev)
329{
330 struct stmmac_priv *priv = netdev_priv(dev);
331 struct phy_device *phydev;
109cdd66
GC		 332 char phy_id[MII_BUS_ID_SIZE + 3];
333 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 334 int interface = priv->plat->interface;
47dd7a54
GC		 335 priv->oldlink = 0;
336 priv->speed = 0;
337 priv->oldduplex = -1;
338
f142af2e
SK		 339 if (priv->plat->phy_bus_name)
340 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
341 priv->plat->phy_bus_name, priv->plat->bus_id);
342 else
343 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
344 priv->plat->bus_id);
345
109cdd66 346 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 347 priv->plat->phy_addr);
47dd7a54
GC		 348 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
349
79ee1dc3 350 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
47dd7a54
GC		 351
352 if (IS_ERR(phydev)) {
353 pr_err("%s: Could not attach to PHY\n", dev->name);
354 return PTR_ERR(phydev);
355 }
356
79ee1dc3 357 /* Stop Advertising 1000BASE Capability if interface is not GMII */
c5b9b4e4
SK		 358 if ((interface == PHY_INTERFACE_MODE_MII) ||
359 (interface == PHY_INTERFACE_MODE_RMII))
360 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
361 SUPPORTED_1000baseT_Full);
79ee1dc3 362
47dd7a54
GC		 363 /*
364 * Broken HW is sometimes missing the pull-up resistor on the
365 * MDIO line, which results in reads to non-existent devices returning
366 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
367 * device as well.
368 * Note: phydev->phy_id is the result of reading the UID PHY registers.
369 */
370 if (phydev->phy_id == 0) {
371 phy_disconnect(phydev);
372 return -ENODEV;
373 }
374 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 375 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 376
377 priv->phydev = phydev;
378
379 return 0;
380}
381
47dd7a54
GC		 382/**
383 * display_ring
384 * @p: pointer to the ring.
385 * @size: size of the ring.
386 * Description: display all the descriptors within the ring.
387 */
388static void display_ring(struct dma_desc *p, int size)
389{
390 struct tmp_s {
391 u64 a;
392 unsigned int b;
393 unsigned int c;
394 };
395 int i;
396 for (i = 0; i < size; i++) {
397 struct tmp_s *x = (struct tmp_s *)(p + i);
398 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
399 i, (unsigned int)virt_to_phys(&p[i]),
400 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
401 x->b, x->c);
402 pr_info("\n");
403 }
404}
405
286a8372
GC		 406static int stmmac_set_bfsize(int mtu, int bufsize)
407{
408 int ret = bufsize;
409
410 if (mtu >= BUF_SIZE_4KiB)
411 ret = BUF_SIZE_8KiB;
412 else if (mtu >= BUF_SIZE_2KiB)
413 ret = BUF_SIZE_4KiB;
414 else if (mtu >= DMA_BUFFER_SIZE)
415 ret = BUF_SIZE_2KiB;
416 else
417 ret = DMA_BUFFER_SIZE;
418
419 return ret;
420}
421
47dd7a54
GC		 422/**
423 * init_dma_desc_rings - init the RX/TX descriptor rings
424 * @dev: net device structure
425 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 426 * and allocates the socket buffers. It suppors the chained and ring
427 * modes.
47dd7a54
GC		 428 */
429static void init_dma_desc_rings(struct net_device *dev)
430{
431 int i;
432 struct stmmac_priv *priv = netdev_priv(dev);
433 struct sk_buff *skb;
434 unsigned int txsize = priv->dma_tx_size;
435 unsigned int rxsize = priv->dma_rx_size;
286a8372
GC		 436 unsigned int bfsize;
437 int dis_ic = 0;
438 int des3_as_data_buf = 0;
47dd7a54 439
286a8372
GC		 440 /* Set the max buffer size according to the DESC mode
441 * and the MTU. Note that RING mode allows 16KiB bsize. */
442 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
443
444 if (bfsize == BUF_SIZE_16KiB)
445 des3_as_data_buf = 1;
47dd7a54 446 else
286a8372 447 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 448
73cfe264
GC		 449#ifdef CONFIG_STMMAC_TIMER
450 /* Disable interrupts on completion for the reception if timer is on */
451 if (likely(priv->tm->enable))
452 dis_ic = 1;
453#endif
47dd7a54
GC		 454
455 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
456 txsize, rxsize, bfsize);
457
458 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
459 priv->rx_skbuff =
460 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
461 priv->dma_rx =
462 (struct dma_desc *)dma_alloc_coherent(priv->device,
463 rxsize *
464 sizeof(struct dma_desc),
465 &priv->dma_rx_phy,
466 GFP_KERNEL);
467 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
468 GFP_KERNEL);
469 priv->dma_tx =
470 (struct dma_desc *)dma_alloc_coherent(priv->device,
471 txsize *
472 sizeof(struct dma_desc),
473 &priv->dma_tx_phy,
474 GFP_KERNEL);
475
476 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
477 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
478 return;
479 }
480
286a8372 481 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
47dd7a54
GC		 482 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
483 dev->name, priv->dma_rx, priv->dma_tx,
484 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
485
486 /* RX INITIALIZATION */
487 DBG(probe, INFO, "stmmac: SKB addresses:\n"
488 "skb\t\tskb data\tdma data\n");
489
490 for (i = 0; i < rxsize; i++) {
491 struct dma_desc *p = priv->dma_rx + i;
492
45db81e1
GC		 493 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
494 GFP_KERNEL);
47dd7a54
GC		 495 if (unlikely(skb == NULL)) {
496 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
497 break;
498 }
45db81e1 499 skb_reserve(skb, NET_IP_ALIGN);
47dd7a54
GC		 500 priv->rx_skbuff[i] = skb;
501 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
502 bfsize, DMA_FROM_DEVICE);
503
504 p->des2 = priv->rx_skbuff_dma[i];
286a8372
GC		 505
506 priv->hw->ring->init_desc3(des3_as_data_buf, p);
507
47dd7a54
GC		 508 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
509 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
510 }
511 priv->cur_rx = 0;
512 priv->dirty_rx = (unsigned int)(i - rxsize);
513 priv->dma_buf_sz = bfsize;
514 buf_sz = bfsize;
515
516 /* TX INITIALIZATION */
517 for (i = 0; i < txsize; i++) {
518 priv->tx_skbuff[i] = NULL;
519 priv->dma_tx[i].des2 = 0;
520 }
286a8372
GC		 521
522 /* In case of Chained mode this sets the des3 to the next
523 * element in the chain */
524 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
525 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
526
47dd7a54
GC		 527 priv->dirty_tx = 0;
528 priv->cur_tx = 0;
529
530 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 531 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
532 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 533
534 if (netif_msg_hw(priv)) {
535 pr_info("RX descriptor ring:\n");
536 display_ring(priv->dma_rx, rxsize);
537 pr_info("TX descriptor ring:\n");
538 display_ring(priv->dma_tx, txsize);
539 }
47dd7a54
GC		 540}
541
542static void dma_free_rx_skbufs(struct stmmac_priv *priv)
543{
544 int i;
545
546 for (i = 0; i < priv->dma_rx_size; i++) {
547 if (priv->rx_skbuff[i]) {
548 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
549 priv->dma_buf_sz, DMA_FROM_DEVICE);
550 dev_kfree_skb_any(priv->rx_skbuff[i]);
551 }
552 priv->rx_skbuff[i] = NULL;
553 }
47dd7a54
GC		 554}
555
556static void dma_free_tx_skbufs(struct stmmac_priv *priv)
557{
558 int i;
559
560 for (i = 0; i < priv->dma_tx_size; i++) {
561 if (priv->tx_skbuff[i] != NULL) {
562 struct dma_desc *p = priv->dma_tx + i;
563 if (p->des2)
564 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 565 priv->hw->desc->get_tx_len(p),
566 DMA_TO_DEVICE);
47dd7a54
GC		 567 dev_kfree_skb_any(priv->tx_skbuff[i]);
568 priv->tx_skbuff[i] = NULL;
569 }
570 }
47dd7a54
GC		 571}
572
573static void free_dma_desc_resources(struct stmmac_priv *priv)
574{
575 /* Release the DMA TX/RX socket buffers */
576 dma_free_rx_skbufs(priv);
577 dma_free_tx_skbufs(priv);
578
579 /* Free the region of consistent memory previously allocated for
580 * the DMA */
581 dma_free_coherent(priv->device,
582 priv->dma_tx_size * sizeof(struct dma_desc),
583 priv->dma_tx, priv->dma_tx_phy);
584 dma_free_coherent(priv->device,
585 priv->dma_rx_size * sizeof(struct dma_desc),
586 priv->dma_rx, priv->dma_rx_phy);
587 kfree(priv->rx_skbuff_dma);
588 kfree(priv->rx_skbuff);
589 kfree(priv->tx_skbuff);
47dd7a54
GC		 590}
591
47dd7a54
GC		 592/**
593 * stmmac_dma_operation_mode - HW DMA operation mode
594 * @priv : pointer to the private device structure.
595 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 596 * or Store-And-Forward capability.
47dd7a54
GC		 597 */
598static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
599{
61b8013a
SK		 600 if (likely(priv->plat->force_sf_dma_mode ||
601 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
602 /*
603 * In case of GMAC, SF mode can be enabled
604 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 605 * 1) TX COE if actually supported
606 * 2) There is no bugged Jumbo frame support
607 * that needs to not insert csum in the TDES.
608 */
609 priv->hw->dma->dma_mode(priv->ioaddr,
610 SF_DMA_MODE, SF_DMA_MODE);
611 tc = SF_DMA_MODE;
612 } else
613 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 614}
615
47dd7a54
GC		 616/**
617 * stmmac_tx:
618 * @priv: private driver structure
619 * Description: it reclaims resources after transmission completes.
620 */
621static void stmmac_tx(struct stmmac_priv *priv)
622{
623 unsigned int txsize = priv->dma_tx_size;
47dd7a54 624
a9097a96
GC		 625 spin_lock(&priv->tx_lock);
626
47dd7a54
GC		 627 while (priv->dirty_tx != priv->cur_tx) {
628 int last;
629 unsigned int entry = priv->dirty_tx % txsize;
630 struct sk_buff *skb = priv->tx_skbuff[entry];
631 struct dma_desc *p = priv->dma_tx + entry;
632
633 /* Check if the descriptor is owned by the DMA. */
db98a0b0 634 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 635 break;
636
637 /* Verify tx error by looking at the last segment */
db98a0b0 638 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 639 if (likely(last)) {
640 int tx_error =
db98a0b0
GC		 641 priv->hw->desc->tx_status(&priv->dev->stats,
642 &priv->xstats, p,
ad01b7d4 643 priv->ioaddr);
47dd7a54
GC		 644 if (likely(tx_error == 0)) {
645 priv->dev->stats.tx_packets++;
646 priv->xstats.tx_pkt_n++;
647 } else
648 priv->dev->stats.tx_errors++;
649 }
650 TX_DBG("%s: curr %d, dirty %d\n", __func__,
651 priv->cur_tx, priv->dirty_tx);
652
653 if (likely(p->des2))
654 dma_unmap_single(priv->device, p->des2,
db98a0b0 655 priv->hw->desc->get_tx_len(p),
47dd7a54 656 DMA_TO_DEVICE);
286a8372 657 priv->hw->ring->clean_desc3(p);
47dd7a54
GC		 658
659 if (likely(skb != NULL)) {
660 /*
661 * If there's room in the queue (limit it to size)
662 * we add this skb back into the pool,
663 * if it's the right size.
664 */
665 if ((skb_queue_len(&priv->rx_recycle) <
666 priv->dma_rx_size) &&
667 skb_recycle_check(skb, priv->dma_buf_sz))
668 __skb_queue_head(&priv->rx_recycle, skb);
669 else
670 dev_kfree_skb(skb);
671
672 priv->tx_skbuff[entry] = NULL;
673 }
674
db98a0b0 675 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 676
677 entry = (++priv->dirty_tx) % txsize;
678 }
679 if (unlikely(netif_queue_stopped(priv->dev) &&
680 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
681 netif_tx_lock(priv->dev);
682 if (netif_queue_stopped(priv->dev) &&
683 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
684 TX_DBG("%s: restart transmit\n", __func__);
685 netif_wake_queue(priv->dev);
686 }
687 netif_tx_unlock(priv->dev);
688 }
a9097a96 689 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 690}
691
692static inline void stmmac_enable_irq(struct stmmac_priv *priv)
693{
73cfe264
GC		 694#ifdef CONFIG_STMMAC_TIMER
695 if (likely(priv->tm->enable))
696 priv->tm->timer_start(tmrate);
697 else
47dd7a54 698#endif
ad01b7d4 699 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 700}
701
702static inline void stmmac_disable_irq(struct stmmac_priv *priv)
703{
73cfe264
GC		 704#ifdef CONFIG_STMMAC_TIMER
705 if (likely(priv->tm->enable))
706 priv->tm->timer_stop();
707 else
47dd7a54 708#endif
ad01b7d4 709 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 710}
711
712static int stmmac_has_work(struct stmmac_priv *priv)
713{
714 unsigned int has_work = 0;
715 int rxret, tx_work = 0;
716
db98a0b0 717 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 718 (priv->cur_rx % priv->dma_rx_size));
719
720 if (priv->dirty_tx != priv->cur_tx)
721 tx_work = 1;
722
723 if (likely(!rxret || tx_work))
724 has_work = 1;
725
726 return has_work;
727}
728
729static inline void _stmmac_schedule(struct stmmac_priv *priv)
730{
731 if (likely(stmmac_has_work(priv))) {
732 stmmac_disable_irq(priv);
733 napi_schedule(&priv->napi);
734 }
735}
736
737#ifdef CONFIG_STMMAC_TIMER
738void stmmac_schedule(struct net_device *dev)
739{
740 struct stmmac_priv *priv = netdev_priv(dev);
741
742 priv->xstats.sched_timer_n++;
743
744 _stmmac_schedule(priv);
47dd7a54
GC		 745}
746
747static void stmmac_no_timer_started(unsigned int x)
748{;
749};
750
751static void stmmac_no_timer_stopped(void)
752{;
753};
754#endif
755
756/**
757 * stmmac_tx_err:
758 * @priv: pointer to the private device structure
759 * Description: it cleans the descriptors and restarts the transmission
760 * in case of errors.
761 */
762static void stmmac_tx_err(struct stmmac_priv *priv)
763{
764 netif_stop_queue(priv->dev);
765
ad01b7d4 766 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 767 dma_free_tx_skbufs(priv);
db98a0b0 768 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 769 priv->dirty_tx = 0;
770 priv->cur_tx = 0;
ad01b7d4 771 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 772
773 priv->dev->stats.tx_errors++;
774 netif_wake_queue(priv->dev);
47dd7a54
GC		 775}
776
47dd7a54 777
aec7ff27
GC		 778static void stmmac_dma_interrupt(struct stmmac_priv *priv)
779{
aec7ff27
GC		 780 int status;
781
ad01b7d4 782 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 783 if (likely(status == handle_tx_rx))
784 _stmmac_schedule(priv);
785
786 else if (unlikely(status == tx_hard_error_bump_tc)) {
787 /* Try to bump up the dma threshold on this failure */
788 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
789 tc += 64;
ad01b7d4 790 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 791 priv->xstats.threshold = tc;
47dd7a54 792 }
aec7ff27
GC		 793 } else if (unlikely(status == tx_hard_error))
794 stmmac_tx_err(priv);
47dd7a54
GC		 795}
796
1c901a46
GC		 797static void stmmac_mmc_setup(struct stmmac_priv *priv)
798{
799 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
800 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
801
4f795b25
GC		 802 /* Mask MMC irq, counters are managed in SW and registers
803 * are cleared on each READ eventually. */
1c901a46 804 dwmac_mmc_intr_all_mask(priv->ioaddr);
4f795b25
GC		 805
806 if (priv->dma_cap.rmon) {
807 dwmac_mmc_ctrl(priv->ioaddr, mode);
808 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
809 } else
aae54cff 810 pr_info(" No MAC Management Counters available\n");
1c901a46
GC		 811}
812
f0b9d786
GC		 813static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
814{
815 u32 hwid = priv->hw->synopsys_uid;
816
817 /* Only check valid Synopsys Id because old MAC chips
818 * have no HW registers where get the ID */
819 if (likely(hwid)) {
820 u32 uid = ((hwid & 0x0000ff00) >> 8);
821 u32 synid = (hwid & 0x000000ff);
822
cf3f047b 823 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
f0b9d786
GC		 824 uid, synid);
825
826 return synid;
827 }
828 return 0;
829}
e7434821 830
19e30c14
GC		 831/**
832 * stmmac_selec_desc_mode
833 * @dev : device pointer
834 * Description: select the Enhanced/Alternate or Normal descriptors */
835static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
836{
837 if (priv->plat->enh_desc) {
838 pr_info(" Enhanced/Alternate descriptors\n");
839 priv->hw->desc = &enh_desc_ops;
840 } else {
841 pr_info(" Normal descriptors\n");
842 priv->hw->desc = &ndesc_ops;
843 }
844}
845
846/**
847 * stmmac_get_hw_features
848 * @priv : private device pointer
849 * Description:
850 * new GMAC chip generations have a new register to indicate the
851 * presence of the optional feature/functions.
852 * This can be also used to override the value passed through the
853 * platform and necessary for old MAC10/100 and GMAC chips.
e7434821
GC		 854 */
855static int stmmac_get_hw_features(struct stmmac_priv *priv)
856{
5e6efe88 857 u32 hw_cap = 0;
3c20f72f 858
5e6efe88
GC		 859 if (priv->hw->dma->get_hw_feature) {
860 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
e7434821 861
1db123fb
RK		 862 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
863 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
864 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
865 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
866 priv->dma_cap.multi_addr =
867 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
868 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
869 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
870 priv->dma_cap.pmt_remote_wake_up =
871 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
872 priv->dma_cap.pmt_magic_frame =
873 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
19e30c14 874 /* MMC */
1db123fb 875 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
e7434821 876 /* IEEE 1588-2002*/
1db123fb
RK		 877 priv->dma_cap.time_stamp =
878 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
e7434821 879 /* IEEE 1588-2008*/
1db123fb
RK		 880 priv->dma_cap.atime_stamp =
881 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 882 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 883 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
884 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 885 /* TX and RX csum */
1db123fb
RK		 886 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
887 priv->dma_cap.rx_coe_type1 =
888 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
889 priv->dma_cap.rx_coe_type2 =
890 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
891 priv->dma_cap.rxfifo_over_2048 =
892 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 893 /* TX and RX number of channels */
1db123fb
RK		 894 priv->dma_cap.number_rx_channel =
895 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
896 priv->dma_cap.number_tx_channel =
897 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
e7434821 898 /* Alternate (enhanced) DESC mode*/
1db123fb
RK		 899 priv->dma_cap.enh_desc =
900 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
e7434821 901
19e30c14 902 }
e7434821
GC		 903
904 return hw_cap;
905}
906
bfab27a1
GC		 907static void stmmac_check_ether_addr(struct stmmac_priv *priv)
908{
909 /* verify if the MAC address is valid, in case of failures it
910 * generates a random MAC address */
911 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
912 priv->hw->mac->get_umac_addr((void __iomem *)
913 priv->dev->base_addr,
914 priv->dev->dev_addr, 0);
915 if (!is_valid_ether_addr(priv->dev->dev_addr))
f2cedb63 916 eth_hw_addr_random(priv->dev);
bfab27a1
GC		 917 }
918 pr_warning("%s: device MAC address %pM\n", priv->dev->name,
919 priv->dev->dev_addr);
920}
921
47dd7a54
GC		 922/**
923 * stmmac_open - open entry point of the driver
924 * @dev : pointer to the device structure.
925 * Description:
926 * This function is the open entry point of the driver.
927 * Return value:
928 * 0 on success and an appropriate (-)ve integer as defined in errno.h
929 * file on failure.
930 */
931static int stmmac_open(struct net_device *dev)
932{
933 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 934 int ret;
935
ba1377ff
GC		 936 stmmac_clk_enable(priv);
937
bfab27a1 938 stmmac_check_ether_addr(priv);
47dd7a54 939
bfab27a1
GC		 940 /* MDIO bus Registration */
941 ret = stmmac_mdio_register(dev);
942 if (ret < 0) {
943 pr_debug("%s: MDIO bus (id: %d) registration failed",
944 __func__, priv->plat->bus_id);
ba1377ff 945 goto open_clk_dis;
bfab27a1
GC		 946 }
947
47dd7a54 948#ifdef CONFIG_STMMAC_TIMER
73cfe264 949 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
ba1377ff
GC		 950 if (unlikely(priv->tm == NULL)) {
951 ret = -ENOMEM;
952 goto open_clk_dis;
953 }
e404decb 954
47dd7a54
GC		 955 priv->tm->freq = tmrate;
956
73cfe264
GC		 957 /* Test if the external timer can be actually used.
958 * In case of failure continue without timer. */
47dd7a54 959 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 960 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 961 priv->tm->freq = 0;
962 priv->tm->timer_start = stmmac_no_timer_started;
963 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 964 } else
965 priv->tm->enable = 1;
47dd7a54 966#endif
f66ffe28
GC		 967 ret = stmmac_init_phy(dev);
968 if (unlikely(ret)) {
969 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
970 goto open_error;
971 }
47dd7a54
GC		 972
973 /* Create and initialize the TX/RX descriptors chains. */
974 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
975 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
976 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
977 init_dma_desc_rings(dev);
978
979 /* DMA initialization and SW reset */
8327eb65
DS		 980 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg->pbl,
981 priv->plat->dma_cfg->fixed_burst,
982 priv->plat->dma_cfg->burst_len,
f66ffe28
GC		 983 priv->dma_tx_phy, priv->dma_rx_phy);
984 if (ret < 0) {
47dd7a54 985 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 986 goto open_error;
47dd7a54
GC		 987 }
988
989 /* Copy the MAC addr into the HW */
ad01b7d4 990 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
cf3f047b 991
ca5f12c1 992 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 993 if (priv->plat->bus_setup)
994 priv->plat->bus_setup(priv->ioaddr);
cf3f047b 995
47dd7a54 996 /* Initialize the MAC Core */
ad01b7d4 997 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 998
f66ffe28
GC		 999 /* Request the IRQ lines */
1000 ret = request_irq(dev->irq, stmmac_interrupt,
1001 IRQF_SHARED, dev->name, dev);
1002 if (unlikely(ret < 0)) {
1003 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1004 __func__, dev->irq, ret);
1005 goto open_error;
1006 }
1007
7a13f8f5
FV		 1008 /* Request the Wake IRQ in case of another line is used for WoL */
1009 if (priv->wol_irq != dev->irq) {
1010 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1011 IRQF_SHARED, dev->name, dev);
1012 if (unlikely(ret < 0)) {
1013 pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1014 "(error: %d)\n", __func__, priv->wol_irq, ret);
1015 goto open_error_wolirq;
1016 }
1017 }
1018
47dd7a54 1019 /* Enable the MAC Rx/Tx */
bfab27a1 1020 stmmac_set_mac(priv->ioaddr, true);
47dd7a54
GC		 1021
1022 /* Set the HW DMA mode and the COE */
1023 stmmac_dma_operation_mode(priv);
1024
1025 /* Extra statistics */
1026 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1027 priv->xstats.threshold = tc;
1028
4f795b25 1029 stmmac_mmc_setup(priv);
1c901a46 1030
bfab27a1
GC		 1031#ifdef CONFIG_STMMAC_DEBUG_FS
1032 ret = stmmac_init_fs(dev);
1033 if (ret < 0)
cf3f047b 1034 pr_warning("%s: failed debugFS registration\n", __func__);
bfab27a1 1035#endif
47dd7a54
GC		 1036 /* Start the ball rolling... */
1037 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 1038 priv->hw->dma->start_tx(priv->ioaddr);
1039 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 1040
1041#ifdef CONFIG_STMMAC_TIMER
1042 priv->tm->timer_start(tmrate);
1043#endif
cf3f047b 1044
47dd7a54
GC		 1045 /* Dump DMA/MAC registers */
1046 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 1047 priv->hw->mac->dump_regs(priv->ioaddr);
1048 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 1049 }
1050
1051 if (priv->phydev)
1052 phy_start(priv->phydev);
1053
1054 napi_enable(&priv->napi);
1055 skb_queue_head_init(&priv->rx_recycle);
1056 netif_start_queue(dev);
f66ffe28 1057
47dd7a54 1058 return 0;
f66ffe28 1059
7a13f8f5
FV		 1060open_error_wolirq:
1061 free_irq(dev->irq, dev);
1062
f66ffe28
GC		 1063open_error:
1064#ifdef CONFIG_STMMAC_TIMER
1065 kfree(priv->tm);
1066#endif
1067 if (priv->phydev)
1068 phy_disconnect(priv->phydev);
1069
ba1377ff
GC		 1070open_clk_dis:
1071 stmmac_clk_disable(priv);
f66ffe28 1072 return ret;
47dd7a54
GC		 1073}
1074
1075/**
1076 * stmmac_release - close entry point of the driver
1077 * @dev : device pointer.
1078 * Description:
1079 * This is the stop entry point of the driver.
1080 */
1081static int stmmac_release(struct net_device *dev)
1082{
1083 struct stmmac_priv *priv = netdev_priv(dev);
1084
1085 /* Stop and disconnect the PHY */
1086 if (priv->phydev) {
1087 phy_stop(priv->phydev);
1088 phy_disconnect(priv->phydev);
1089 priv->phydev = NULL;
1090 }
1091
1092 netif_stop_queue(dev);
1093
1094#ifdef CONFIG_STMMAC_TIMER
1095 /* Stop and release the timer */
1096 stmmac_close_ext_timer();
1097 if (priv->tm != NULL)
1098 kfree(priv->tm);
1099#endif
1100 napi_disable(&priv->napi);
1101 skb_queue_purge(&priv->rx_recycle);
1102
1103 /* Free the IRQ lines */
1104 free_irq(dev->irq, dev);
7a13f8f5
FV		 1105 if (priv->wol_irq != dev->irq)
1106 free_irq(priv->wol_irq, dev);
47dd7a54
GC		 1107
1108 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1109 priv->hw->dma->stop_tx(priv->ioaddr);
1110 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1111
1112 /* Release and free the Rx/Tx resources */
1113 free_dma_desc_resources(priv);
1114
19449bfc 1115 /* Disable the MAC Rx/Tx */
bfab27a1 1116 stmmac_set_mac(priv->ioaddr, false);
47dd7a54
GC		 1117
1118 netif_carrier_off(dev);
1119
bfab27a1
GC		 1120#ifdef CONFIG_STMMAC_DEBUG_FS
1121 stmmac_exit_fs();
1122#endif
1123 stmmac_mdio_unregister(dev);
ba1377ff 1124 stmmac_clk_disable(priv);
bfab27a1 1125
47dd7a54
GC		 1126 return 0;
1127}
1128
47dd7a54
GC		 1129/**
1130 * stmmac_xmit:
1131 * @skb : the socket buffer
1132 * @dev : device pointer
1133 * Description : Tx entry point of the driver.
1134 */
1135static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1136{
1137 struct stmmac_priv *priv = netdev_priv(dev);
1138 unsigned int txsize = priv->dma_tx_size;
1139 unsigned int entry;
1140 int i, csum_insertion = 0;
1141 int nfrags = skb_shinfo(skb)->nr_frags;
1142 struct dma_desc *desc, *first;
286a8372 1143 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1144
1145 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1146 if (!netif_queue_stopped(dev)) {
1147 netif_stop_queue(dev);
1148 /* This is a hard error, log it. */
1149 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1150 __func__);
1151 }
1152 return NETDEV_TX_BUSY;
1153 }
1154
a9097a96
GC		 1155 spin_lock(&priv->tx_lock);
1156
47dd7a54
GC		 1157 entry = priv->cur_tx % txsize;
1158
1159#ifdef STMMAC_XMIT_DEBUG
1160 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1161 pr_info("stmmac xmit:\n"
1162 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1163 "\tn_frags: %d - ip_summed: %d - %s gso\n",
286a8372 1164 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
47dd7a54
GC		 1165 !skb_is_gso(skb) ? "isn't" : "is");
1166#endif
1167
5e982f3b 1168 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1169
1170 desc = priv->dma_tx + entry;
1171 first = desc;
1172
1173#ifdef STMMAC_XMIT_DEBUG
1174 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1175 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1176 "\t\tn_frags: %d, ip_summed: %d\n",
286a8372 1177 skb->len, nopaged_len, nfrags, skb->ip_summed);
47dd7a54
GC		 1178#endif
1179 priv->tx_skbuff[entry] = skb;
286a8372
GC		 1180
1181 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1182 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
47dd7a54
GC		 1183 desc = priv->dma_tx + entry;
1184 } else {
47dd7a54
GC		 1185 desc->des2 = dma_map_single(priv->device, skb->data,
1186 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1187 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1188 csum_insertion);
47dd7a54
GC		 1189 }
1190
1191 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1192 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1193 int len = skb_frag_size(frag);
47dd7a54
GC		 1194
1195 entry = (++priv->cur_tx) % txsize;
1196 desc = priv->dma_tx + entry;
1197
1198 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1199 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1200 DMA_TO_DEVICE);
47dd7a54 1201 priv->tx_skbuff[entry] = NULL;
db98a0b0 1202 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1203 wmb();
db98a0b0 1204 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1205 }
1206
1207 /* Interrupt on completition only for the latest segment */
db98a0b0 1208 priv->hw->desc->close_tx_desc(desc);
73cfe264 1209
47dd7a54 1210#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1211 /* Clean IC while using timer */
1212 if (likely(priv->tm->enable))
db98a0b0 1213 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1214#endif
eb0dc4bb
SH		 1215
1216 wmb();
1217
47dd7a54 1218 /* To avoid raise condition */
db98a0b0 1219 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1220
1221 priv->cur_tx++;
1222
1223#ifdef STMMAC_XMIT_DEBUG
1224 if (netif_msg_pktdata(priv)) {
1225 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1226 "first=%p, nfrags=%d\n",
1227 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1228 entry, first, nfrags);
1229 display_ring(priv->dma_tx, txsize);
1230 pr_info(">>> frame to be transmitted: ");
1231 print_pkt(skb->data, skb->len);
1232 }
1233#endif
1234 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1235 TX_DBG("%s: stop transmitted packets\n", __func__);
1236 netif_stop_queue(dev);
1237 }
1238
1239 dev->stats.tx_bytes += skb->len;
1240
3e82ce12
RC		 1241 skb_tx_timestamp(skb);
1242
52f64fae
RC		 1243 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1244
a9097a96
GC		 1245 spin_unlock(&priv->tx_lock);
1246
47dd7a54
GC		 1247 return NETDEV_TX_OK;
1248}
1249
1250static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1251{
1252 unsigned int rxsize = priv->dma_rx_size;
1253 int bfsize = priv->dma_buf_sz;
1254 struct dma_desc *p = priv->dma_rx;
1255
1256 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1257 unsigned int entry = priv->dirty_rx % rxsize;
1258 if (likely(priv->rx_skbuff[entry] == NULL)) {
1259 struct sk_buff *skb;
1260
1261 skb = __skb_dequeue(&priv->rx_recycle);
1262 if (skb == NULL)
1263 skb = netdev_alloc_skb_ip_align(priv->dev,
1264 bfsize);
1265
1266 if (unlikely(skb == NULL))
1267 break;
1268
1269 priv->rx_skbuff[entry] = skb;
1270 priv->rx_skbuff_dma[entry] =
1271 dma_map_single(priv->device, skb->data, bfsize,
1272 DMA_FROM_DEVICE);
1273
1274 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
286a8372
GC		 1275
1276 if (unlikely(priv->plat->has_gmac))
1277 priv->hw->ring->refill_desc3(bfsize, p + entry);
1278
47dd7a54
GC		 1279 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1280 }
eb0dc4bb 1281 wmb();
db98a0b0 1282 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1283 }
47dd7a54
GC		 1284}
1285
1286static int stmmac_rx(struct stmmac_priv *priv, int limit)
1287{
1288 unsigned int rxsize = priv->dma_rx_size;
1289 unsigned int entry = priv->cur_rx % rxsize;
1290 unsigned int next_entry;
1291 unsigned int count = 0;
1292 struct dma_desc *p = priv->dma_rx + entry;
1293 struct dma_desc *p_next;
1294
1295#ifdef STMMAC_RX_DEBUG
1296 if (netif_msg_hw(priv)) {
1297 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1298 display_ring(priv->dma_rx, rxsize);
1299 }
1300#endif
1301 count = 0;
db98a0b0 1302 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1303 int status;
1304
1305 if (count >= limit)
1306 break;
1307
1308 count++;
1309
1310 next_entry = (++priv->cur_rx) % rxsize;
1311 p_next = priv->dma_rx + next_entry;
1312 prefetch(p_next);
1313
1314 /* read the status of the incoming frame */
db98a0b0
GC		 1315 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1316 &priv->xstats, p));
47dd7a54
GC		 1317 if (unlikely(status == discard_frame))
1318 priv->dev->stats.rx_errors++;
1319 else {
1320 struct sk_buff *skb;
3eeb2997 1321 int frame_len;
47dd7a54 1322
38912bdb
DS		 1323 frame_len = priv->hw->desc->get_rx_frame_len(p,
1324 priv->plat->rx_coe);
3eeb2997
GC		 1325 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1326 * Type frames (LLC/LLC-SNAP) */
1327 if (unlikely(status != llc_snap))
1328 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1329#ifdef STMMAC_RX_DEBUG
1330 if (frame_len > ETH_FRAME_LEN)
1331 pr_debug("\tRX frame size %d, COE status: %d\n",
1332 frame_len, status);
1333
1334 if (netif_msg_hw(priv))
1335 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1336 p, entry, p->des2);
1337#endif
1338 skb = priv->rx_skbuff[entry];
1339 if (unlikely(!skb)) {
1340 pr_err("%s: Inconsistent Rx descriptor chain\n",
1341 priv->dev->name);
1342 priv->dev->stats.rx_dropped++;
1343 break;
1344 }
1345 prefetch(skb->data - NET_IP_ALIGN);
1346 priv->rx_skbuff[entry] = NULL;
1347
1348 skb_put(skb, frame_len);
1349 dma_unmap_single(priv->device,
1350 priv->rx_skbuff_dma[entry],
1351 priv->dma_buf_sz, DMA_FROM_DEVICE);
1352#ifdef STMMAC_RX_DEBUG
1353 if (netif_msg_pktdata(priv)) {
1354 pr_info(" frame received (%dbytes)", frame_len);
1355 print_pkt(skb->data, frame_len);
1356 }
1357#endif
1358 skb->protocol = eth_type_trans(skb, priv->dev);
1359
38912bdb 1360 if (unlikely(!priv->plat->rx_coe)) {
3c20f72f 1361 /* No RX COE for old mac10/100 devices */
bc8acf2c 1362 skb_checksum_none_assert(skb);
47dd7a54
GC		 1363 netif_receive_skb(skb);
1364 } else {
1365 skb->ip_summed = CHECKSUM_UNNECESSARY;
1366 napi_gro_receive(&priv->napi, skb);
1367 }
1368
1369 priv->dev->stats.rx_packets++;
1370 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1371 }
1372 entry = next_entry;
1373 p = p_next; /* use prefetched values */
1374 }
1375
1376 stmmac_rx_refill(priv);
1377
1378 priv->xstats.rx_pkt_n += count;
1379
1380 return count;
1381}
1382
1383/**
1384 * stmmac_poll - stmmac poll method (NAPI)
1385 * @napi : pointer to the napi structure.
1386 * @budget : maximum number of packets that the current CPU can receive from
1387 * all interfaces.
1388 * Description :
1389 * This function implements the the reception process.
1390 * Also it runs the TX completion thread
1391 */
1392static int stmmac_poll(struct napi_struct *napi, int budget)
1393{
1394 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1395 int work_done = 0;
1396
1397 priv->xstats.poll_n++;
1398 stmmac_tx(priv);
1399 work_done = stmmac_rx(priv, budget);
1400
1401 if (work_done < budget) {
1402 napi_complete(napi);
1403 stmmac_enable_irq(priv);
1404 }
1405 return work_done;
1406}
1407
1408/**
1409 * stmmac_tx_timeout
1410 * @dev : Pointer to net device structure
1411 * Description: this function is called when a packet transmission fails to
1412 * complete within a reasonable tmrate. The driver will mark the error in the
1413 * netdev structure and arrange for the device to be reset to a sane state
1414 * in order to transmit a new packet.
1415 */
1416static void stmmac_tx_timeout(struct net_device *dev)
1417{
1418 struct stmmac_priv *priv = netdev_priv(dev);
1419
1420 /* Clear Tx resources and restart transmitting again */
1421 stmmac_tx_err(priv);
47dd7a54
GC		 1422}
1423
1424/* Configuration changes (passed on by ifconfig) */
1425static int stmmac_config(struct net_device *dev, struct ifmap *map)
1426{
1427 if (dev->flags & IFF_UP) /* can't act on a running interface */
1428 return -EBUSY;
1429
1430 /* Don't allow changing the I/O address */
1431 if (map->base_addr != dev->base_addr) {
1432 pr_warning("%s: can't change I/O address\n", dev->name);
1433 return -EOPNOTSUPP;
1434 }
1435
1436 /* Don't allow changing the IRQ */
1437 if (map->irq != dev->irq) {
1438 pr_warning("%s: can't change IRQ number %d\n",
1439 dev->name, dev->irq);
1440 return -EOPNOTSUPP;
1441 }
1442
1443 /* ignore other fields */
1444 return 0;
1445}
1446
1447/**
01789349 1448 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1449 * @dev : pointer to the device structure
1450 * Description:
1451 * This function is a driver entry point which gets called by the kernel
1452 * whenever multicast addresses must be enabled/disabled.
1453 * Return value:
1454 * void.
1455 */
01789349 1456static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1457{
1458 struct stmmac_priv *priv = netdev_priv(dev);
1459
1460 spin_lock(&priv->lock);
db98a0b0 1461 priv->hw->mac->set_filter(dev);
47dd7a54 1462 spin_unlock(&priv->lock);
47dd7a54
GC		 1463}
1464
1465/**
1466 * stmmac_change_mtu - entry point to change MTU size for the device.
1467 * @dev : device pointer.
1468 * @new_mtu : the new MTU size for the device.
1469 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1470 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1471 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1472 * Return value:
1473 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1474 * file on failure.
1475 */
1476static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1477{
1478 struct stmmac_priv *priv = netdev_priv(dev);
1479 int max_mtu;
1480
1481 if (netif_running(dev)) {
1482 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1483 return -EBUSY;
1484 }
1485
48febf7e 1486 if (priv->plat->enh_desc)
47dd7a54
GC		 1487 max_mtu = JUMBO_LEN;
1488 else
45db81e1 1489 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
47dd7a54
GC		 1490
1491 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1492 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1493 return -EINVAL;
1494 }
1495
5e982f3b
MM		 1496 dev->mtu = new_mtu;
1497 netdev_update_features(dev);
1498
1499 return 0;
1500}
1501
c8f44aff
MM		 1502static netdev_features_t stmmac_fix_features(struct net_device *dev,
1503 netdev_features_t features)
5e982f3b
MM		 1504{
1505 struct stmmac_priv *priv = netdev_priv(dev);
1506
38912bdb 1507 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5e982f3b 1508 features &= ~NETIF_F_RXCSUM;
38912bdb
DS		 1509 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1510 features &= ~NETIF_F_IPV6_CSUM;
5e982f3b
MM		 1511 if (!priv->plat->tx_coe)
1512 features &= ~NETIF_F_ALL_CSUM;
1513
ebbb293f
GC		 1514 /* Some GMAC devices have a bugged Jumbo frame support that
1515 * needs to have the Tx COE disabled for oversized frames
1516 * (due to limited buffer sizes). In this case we disable
1517 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1518 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1519 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1520
5e982f3b 1521 return features;
47dd7a54
GC		 1522}
1523
1524static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1525{
1526 struct net_device *dev = (struct net_device *)dev_id;
1527 struct stmmac_priv *priv = netdev_priv(dev);
1528
1529 if (unlikely(!dev)) {
1530 pr_err("%s: invalid dev pointer\n", __func__);
1531 return IRQ_NONE;
1532 }
1533
9dfeb4d9 1534 if (priv->plat->has_gmac)
47dd7a54 1535 /* To handle GMAC own interrupts */
ad01b7d4 1536 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1537
1538 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1539
1540 return IRQ_HANDLED;
1541}
1542
1543#ifdef CONFIG_NET_POLL_CONTROLLER
1544/* Polling receive - used by NETCONSOLE and other diagnostic tools
1545 * to allow network I/O with interrupts disabled. */
1546static void stmmac_poll_controller(struct net_device *dev)
1547{
1548 disable_irq(dev->irq);
1549 stmmac_interrupt(dev->irq, dev);
1550 enable_irq(dev->irq);
1551}
1552#endif
1553
1554/**
1555 * stmmac_ioctl - Entry point for the Ioctl
1556 * @dev: Device pointer.
1557 * @rq: An IOCTL specefic structure, that can contain a pointer to
1558 * a proprietary structure used to pass information to the driver.
1559 * @cmd: IOCTL command
1560 * Description:
1561 * Currently there are no special functionality supported in IOCTL, just the
1562 * phy_mii_ioctl(...) can be invoked.
1563 */
1564static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1565{
1566 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1567 int ret;
47dd7a54
GC		 1568
1569 if (!netif_running(dev))
1570 return -EINVAL;
1571
28b04113
RC		 1572 if (!priv->phydev)
1573 return -EINVAL;
1574
28b04113 1575 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
28b04113 1576
47dd7a54
GC		 1577 return ret;
1578}
1579
7ac29055
GC		 1580#ifdef CONFIG_STMMAC_DEBUG_FS
1581static struct dentry *stmmac_fs_dir;
1582static struct dentry *stmmac_rings_status;
e7434821 1583static struct dentry *stmmac_dma_cap;
7ac29055
GC		 1584
1585static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1586{
1587 struct tmp_s {
1588 u64 a;
1589 unsigned int b;
1590 unsigned int c;
1591 };
1592 int i;
1593 struct net_device *dev = seq->private;
1594 struct stmmac_priv *priv = netdev_priv(dev);
1595
1596 seq_printf(seq, "=======================\n");
1597 seq_printf(seq, " RX descriptor ring\n");
1598 seq_printf(seq, "=======================\n");
1599
1600 for (i = 0; i < priv->dma_rx_size; i++) {
1601 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1602 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1603 i, (unsigned int)(x->a),
1604 (unsigned int)((x->a) >> 32), x->b, x->c);
1605 seq_printf(seq, "\n");
1606 }
1607
1608 seq_printf(seq, "\n");
1609 seq_printf(seq, "=======================\n");
1610 seq_printf(seq, " TX descriptor ring\n");
1611 seq_printf(seq, "=======================\n");
1612
1613 for (i = 0; i < priv->dma_tx_size; i++) {
1614 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1615 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1616 i, (unsigned int)(x->a),
1617 (unsigned int)((x->a) >> 32), x->b, x->c);
1618 seq_printf(seq, "\n");
1619 }
1620
1621 return 0;
1622}
1623
1624static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1625{
1626 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1627}
1628
1629static const struct file_operations stmmac_rings_status_fops = {
1630 .owner = THIS_MODULE,
1631 .open = stmmac_sysfs_ring_open,
1632 .read = seq_read,
1633 .llseek = seq_lseek,
1634 .release = seq_release,
1635};
1636
e7434821
GC		 1637static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1638{
1639 struct net_device *dev = seq->private;
1640 struct stmmac_priv *priv = netdev_priv(dev);
1641
19e30c14 1642 if (!priv->hw_cap_support) {
e7434821
GC		 1643 seq_printf(seq, "DMA HW features not supported\n");
1644 return 0;
1645 }
1646
1647 seq_printf(seq, "==============================\n");
1648 seq_printf(seq, "\tDMA HW features\n");
1649 seq_printf(seq, "==============================\n");
1650
1651 seq_printf(seq, "\t10/100 Mbps %s\n",
1652 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1653 seq_printf(seq, "\t1000 Mbps %s\n",
1654 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1655 seq_printf(seq, "\tHalf duple %s\n",
1656 (priv->dma_cap.half_duplex) ? "Y" : "N");
1657 seq_printf(seq, "\tHash Filter: %s\n",
1658 (priv->dma_cap.hash_filter) ? "Y" : "N");
1659 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1660 (priv->dma_cap.multi_addr) ? "Y" : "N");
1661 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1662 (priv->dma_cap.pcs) ? "Y" : "N");
1663 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1664 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1665 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1666 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1667 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1668 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1669 seq_printf(seq, "\tRMON module: %s\n",
1670 (priv->dma_cap.rmon) ? "Y" : "N");
1671 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1672 (priv->dma_cap.time_stamp) ? "Y" : "N");
1673 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1674 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1675 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1676 (priv->dma_cap.eee) ? "Y" : "N");
1677 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1678 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1679 (priv->dma_cap.tx_coe) ? "Y" : "N");
1680 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1681 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1682 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1683 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1684 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1685 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1686 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1687 priv->dma_cap.number_rx_channel);
1688 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1689 priv->dma_cap.number_tx_channel);
1690 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1691 (priv->dma_cap.enh_desc) ? "Y" : "N");
1692
1693 return 0;
1694}
1695
1696static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1697{
1698 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1699}
1700
1701static const struct file_operations stmmac_dma_cap_fops = {
1702 .owner = THIS_MODULE,
1703 .open = stmmac_sysfs_dma_cap_open,
1704 .read = seq_read,
1705 .llseek = seq_lseek,
1706 .release = seq_release,
1707};
1708
7ac29055
GC		 1709static int stmmac_init_fs(struct net_device *dev)
1710{
1711 /* Create debugfs entries */
1712 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1713
1714 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1715 pr_err("ERROR %s, debugfs create directory failed\n",
1716 STMMAC_RESOURCE_NAME);
1717
1718 return -ENOMEM;
1719 }
1720
1721 /* Entry to report DMA RX/TX rings */
1722 stmmac_rings_status = debugfs_create_file("descriptors_status",
1723 S_IRUGO, stmmac_fs_dir, dev,
1724 &stmmac_rings_status_fops);
1725
1726 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1727 pr_info("ERROR creating stmmac ring debugfs file\n");
1728 debugfs_remove(stmmac_fs_dir);
1729
1730 return -ENOMEM;
1731 }
1732
e7434821
GC		 1733 /* Entry to report the DMA HW features */
1734 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1735 dev, &stmmac_dma_cap_fops);
1736
1737 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1738 pr_info("ERROR creating stmmac MMC debugfs file\n");
1739 debugfs_remove(stmmac_rings_status);
1740 debugfs_remove(stmmac_fs_dir);
1741
1742 return -ENOMEM;
1743 }
1744
7ac29055
GC		 1745 return 0;
1746}
1747
1748static void stmmac_exit_fs(void)
1749{
1750 debugfs_remove(stmmac_rings_status);
e7434821 1751 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 1752 debugfs_remove(stmmac_fs_dir);
1753}
1754#endif /* CONFIG_STMMAC_DEBUG_FS */
1755
47dd7a54
GC		 1756static const struct net_device_ops stmmac_netdev_ops = {
1757 .ndo_open = stmmac_open,
1758 .ndo_start_xmit = stmmac_xmit,
1759 .ndo_stop = stmmac_release,
1760 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1761 .ndo_fix_features = stmmac_fix_features,
01789349 1762 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1763 .ndo_tx_timeout = stmmac_tx_timeout,
1764 .ndo_do_ioctl = stmmac_ioctl,
1765 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1766#ifdef CONFIG_NET_POLL_CONTROLLER
1767 .ndo_poll_controller = stmmac_poll_controller,
1768#endif
1769 .ndo_set_mac_address = eth_mac_addr,
1770};
1771
cf3f047b
GC		 1772/**
1773 * stmmac_hw_init - Init the MAC device
1774 * @priv : pointer to the private device structure.
1775 * Description: this function detects which MAC device
1776 * (GMAC/MAC10-100) has to attached, checks the HW capability
1777 * (if supported) and sets the driver's features (for example
1778 * to use the ring or chaine mode or support the normal/enh
1779 * descriptor structure).
1780 */
1781static int stmmac_hw_init(struct stmmac_priv *priv)
1782{
1783 int ret = 0;
1784 struct mac_device_info *mac;
1785
1786 /* Identify the MAC HW device */
1787 if (priv->plat->has_gmac)
1788 mac = dwmac1000_setup(priv->ioaddr);
1789 else
1790 mac = dwmac100_setup(priv->ioaddr);
1791 if (!mac)
1792 return -ENOMEM;
1793
1794 priv->hw = mac;
1795
1796 /* To use the chained or ring mode */
1797 priv->hw->ring = &ring_mode_ops;
1798
1799 /* Get and dump the chip ID */
1800 stmmac_get_synopsys_id(priv);
1801
1802 /* Get the HW capability (new GMAC newer than 3.50a) */
1803 priv->hw_cap_support = stmmac_get_hw_features(priv);
1804 if (priv->hw_cap_support) {
1805 pr_info(" DMA HW capability register supported");
1806
1807 /* We can override some gmac/dma configuration fields: e.g.
1808 * enh_desc, tx_coe (e.g. that are passed through the
1809 * platform) with the values from the HW capability
1810 * register (if supported).
1811 */
1812 priv->plat->enh_desc = priv->dma_cap.enh_desc;
cf3f047b 1813 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
38912bdb
DS		 1814
1815 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1816
1817 if (priv->dma_cap.rx_coe_type2)
1818 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
1819 else if (priv->dma_cap.rx_coe_type1)
1820 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
1821
cf3f047b
GC		 1822 } else
1823 pr_info(" No HW DMA feature register supported");
1824
1825 /* Select the enhnaced/normal descriptor structures */
1826 stmmac_selec_desc_mode(priv);
1827
38912bdb
DS		 1828 /* Enable the IPC (Checksum Offload) and check if the feature has been
1829 * enabled during the core configuration. */
1830 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
1831 if (!ret) {
1832 pr_warning(" RX IPC Checksum Offload not configured.\n");
1833 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1834 }
1835
1836 if (priv->plat->rx_coe)
1837 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1838 priv->plat->rx_coe);
cf3f047b
GC		 1839 if (priv->plat->tx_coe)
1840 pr_info(" TX Checksum insertion supported\n");
1841
1842 if (priv->plat->pmt) {
1843 pr_info(" Wake-Up On Lan supported\n");
1844 device_set_wakeup_capable(priv->device, 1);
1845 }
1846
1847 return ret;
1848}
1849
47dd7a54 1850/**
bfab27a1
GC		 1851 * stmmac_dvr_probe
1852 * @device: device pointer
1853 * Description: this is the main probe function used to
1854 * call the alloc_etherdev, allocate the priv structure.
47dd7a54 1855 */
bfab27a1 1856struct stmmac_priv *stmmac_dvr_probe(struct device *device,
cf3f047b
GC		 1857 struct plat_stmmacenet_data *plat_dat,
1858 void __iomem *addr)
47dd7a54
GC		 1859{
1860 int ret = 0;
bfab27a1
GC		 1861 struct net_device *ndev = NULL;
1862 struct stmmac_priv *priv;
47dd7a54 1863
bfab27a1 1864 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
41de8d4c 1865 if (!ndev)
bfab27a1 1866 return NULL;
bfab27a1
GC		 1867
1868 SET_NETDEV_DEV(ndev, device);
1869
1870 priv = netdev_priv(ndev);
1871 priv->device = device;
1872 priv->dev = ndev;
47dd7a54 1873
bfab27a1 1874 ether_setup(ndev);
47dd7a54 1875
bfab27a1 1876 stmmac_set_ethtool_ops(ndev);
cf3f047b
GC		 1877 priv->pause = pause;
1878 priv->plat = plat_dat;
1879 priv->ioaddr = addr;
1880 priv->dev->base_addr = (unsigned long)addr;
1881
1882 /* Verify driver arguments */
1883 stmmac_verify_args();
bfab27a1 1884
cf3f047b
GC		 1885 /* Override with kernel parameters if supplied XXX CRS XXX
1886 * this needs to have multiple instances */
1887 if ((phyaddr >= 0) && (phyaddr <= 31))
1888 priv->plat->phy_addr = phyaddr;
1889
1890 /* Init MAC and get the capabilities */
1891 stmmac_hw_init(priv);
1892
1893 ndev->netdev_ops = &stmmac_netdev_ops;
bfab27a1 1894
cf3f047b
GC		 1895 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1896 NETIF_F_RXCSUM;
bfab27a1
GC		 1897 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1898 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
47dd7a54
GC		 1899#ifdef STMMAC_VLAN_TAG_USED
1900 /* Both mac100 and gmac support receive VLAN tag detection */
bfab27a1 1901 ndev->features |= NETIF_F_HW_VLAN_RX;
47dd7a54
GC		 1902#endif
1903 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1904
47dd7a54
GC		 1905 if (flow_ctrl)
1906 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1907
bfab27a1 1908 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
47dd7a54 1909
f8e96161 1910 spin_lock_init(&priv->lock);
a9097a96 1911 spin_lock_init(&priv->tx_lock);
f8e96161 1912
bfab27a1 1913 ret = register_netdev(ndev);
47dd7a54 1914 if (ret) {
cf3f047b 1915 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
bfab27a1 1916 goto error;
47dd7a54
GC		 1917 }
1918
ba1377ff
GC		 1919 if (stmmac_clk_get(priv))
1920 goto error;
1921
cd7201f4
GC		 1922 /* If a specific clk_csr value is passed from the platform
1923 * this means that the CSR Clock Range selection cannot be
1924 * changed at run-time and it is fixed. Viceversa the driver'll try to
1925 * set the MDC clock dynamically according to the csr actual
1926 * clock input.
1927 */
1928 if (!priv->plat->clk_csr)
1929 stmmac_clk_csr_set(priv);
1930 else
1931 priv->clk_csr = priv->plat->clk_csr;
1932
bfab27a1 1933 return priv;
47dd7a54 1934
bfab27a1
GC		 1935error:
1936 netif_napi_del(&priv->napi);
47dd7a54 1937
34a52f36 1938 unregister_netdev(ndev);
34a52f36 1939 free_netdev(ndev);
47dd7a54 1940
bfab27a1 1941 return NULL;
47dd7a54
GC		 1942}
1943
1944/**
1945 * stmmac_dvr_remove
bfab27a1 1946 * @ndev: net device pointer
47dd7a54 1947 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
bfab27a1 1948 * changes the link status, releases the DMA descriptor rings.
47dd7a54 1949 */
bfab27a1 1950int stmmac_dvr_remove(struct net_device *ndev)
47dd7a54 1951{
aec7ff27 1952 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1953
1954 pr_info("%s:\n\tremoving driver", __func__);
1955
ad01b7d4
GC		 1956 priv->hw->dma->stop_rx(priv->ioaddr);
1957 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1958
bfab27a1 1959 stmmac_set_mac(priv->ioaddr, false);
47dd7a54 1960 netif_carrier_off(ndev);
47dd7a54 1961 unregister_netdev(ndev);
47dd7a54
GC		 1962 free_netdev(ndev);
1963
1964 return 0;
1965}
1966
1967#ifdef CONFIG_PM
bfab27a1 1968int stmmac_suspend(struct net_device *ndev)
47dd7a54 1969{
874bd42d 1970 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1971 int dis_ic = 0;
1972
874bd42d 1973 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 1974 return 0;
1975
102463b1
FV		 1976 if (priv->phydev)
1977 phy_stop(priv->phydev);
1978
47dd7a54
GC		 1979 spin_lock(&priv->lock);
1980
874bd42d
GC		 1981 netif_device_detach(ndev);
1982 netif_stop_queue(ndev);
47dd7a54
GC		 1983
1984#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 1985 priv->tm->timer_stop();
1986 if (likely(priv->tm->enable))
1987 dis_ic = 1;
47dd7a54 1988#endif
874bd42d
GC		 1989 napi_disable(&priv->napi);
1990
1991 /* Stop TX/RX DMA */
1992 priv->hw->dma->stop_tx(priv->ioaddr);
1993 priv->hw->dma->stop_rx(priv->ioaddr);
1994 /* Clear the Rx/Tx descriptors */
1995 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1996 dis_ic);
1997 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1998
1999 /* Enable Power down mode by programming the PMT regs */
2000 if (device_may_wakeup(priv->device))
2001 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
ba1377ff 2002 else {
bfab27a1 2003 stmmac_set_mac(priv->ioaddr, false);
ba1377ff
GC		 2004 /* Disable clock in case of PWM is off */
2005 stmmac_clk_disable(priv);
2006 }
47dd7a54
GC		 2007 spin_unlock(&priv->lock);
2008 return 0;
2009}
2010
bfab27a1 2011int stmmac_resume(struct net_device *ndev)
47dd7a54 2012{
874bd42d 2013 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 2014
874bd42d 2015 if (!netif_running(ndev))
47dd7a54
GC		 2016 return 0;
2017
c4433be6
GC		 2018 spin_lock(&priv->lock);
2019
47dd7a54
GC		 2020 /* Power Down bit, into the PM register, is cleared
2021 * automatically as soon as a magic packet or a Wake-up frame
2022 * is received. Anyway, it's better to manually clear
2023 * this bit because it can generate problems while resuming
2024 * from another devices (e.g. serial console). */
874bd42d 2025 if (device_may_wakeup(priv->device))
543876c9 2026 priv->hw->mac->pmt(priv->ioaddr, 0);
ba1377ff
GC		 2027 else
2028 /* enable the clk prevously disabled */
2029 stmmac_clk_enable(priv);
47dd7a54 2030
874bd42d 2031 netif_device_attach(ndev);
47dd7a54
GC		 2032
2033 /* Enable the MAC and DMA */
bfab27a1 2034 stmmac_set_mac(priv->ioaddr, true);
ad01b7d4
GC		 2035 priv->hw->dma->start_tx(priv->ioaddr);
2036 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 2037
2038#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2039 if (likely(priv->tm->enable))
2040 priv->tm->timer_start(tmrate);
47dd7a54
GC		 2041#endif
2042 napi_enable(&priv->napi);
2043
874bd42d 2044 netif_start_queue(ndev);
47dd7a54 2045
47dd7a54 2046 spin_unlock(&priv->lock);
102463b1
FV		 2047
2048 if (priv->phydev)
2049 phy_start(priv->phydev);
2050
47dd7a54
GC		 2051 return 0;
2052}
47dd7a54 2053
bfab27a1 2054int stmmac_freeze(struct net_device *ndev)
874bd42d 2055{
874bd42d
GC		 2056 if (!ndev || !netif_running(ndev))
2057 return 0;
2058
2059 return stmmac_release(ndev);
2060}
2061
bfab27a1 2062int stmmac_restore(struct net_device *ndev)
874bd42d 2063{
874bd42d
GC		 2064 if (!ndev || !netif_running(ndev))
2065 return 0;
2066
2067 return stmmac_open(ndev);
2068}
874bd42d 2069#endif /* CONFIG_PM */
47dd7a54 2070
47dd7a54
GC		 2071#ifndef MODULE
2072static int __init stmmac_cmdline_opt(char *str)
2073{
2074 char *opt;
2075
2076 if (!str || !*str)
2077 return -EINVAL;
2078 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 2079 if (!strncmp(opt, "debug:", 6)) {
2080 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2081 goto err;
2082 } else if (!strncmp(opt, "phyaddr:", 8)) {
2083 if (strict_strtoul(opt + 8, 0,
2084 (unsigned long *)&phyaddr))
2085 goto err;
2086 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2087 if (strict_strtoul(opt + 11, 0,
2088 (unsigned long *)&dma_txsize))
2089 goto err;
2090 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2091 if (strict_strtoul(opt + 11, 0,
2092 (unsigned long *)&dma_rxsize))
2093 goto err;
2094 } else if (!strncmp(opt, "buf_sz:", 7)) {
2095 if (strict_strtoul(opt + 7, 0,
2096 (unsigned long *)&buf_sz))
2097 goto err;
2098 } else if (!strncmp(opt, "tc:", 3)) {
2099 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2100 goto err;
2101 } else if (!strncmp(opt, "watchdog:", 9)) {
2102 if (strict_strtoul(opt + 9, 0,
2103 (unsigned long *)&watchdog))
2104 goto err;
2105 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2106 if (strict_strtoul(opt + 10, 0,
2107 (unsigned long *)&flow_ctrl))
2108 goto err;
2109 } else if (!strncmp(opt, "pause:", 6)) {
2110 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2111 goto err;
47dd7a54 2112#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 2113 } else if (!strncmp(opt, "tmrate:", 7)) {
2114 if (strict_strtoul(opt + 7, 0,
2115 (unsigned long *)&tmrate))
2116 goto err;
47dd7a54 2117#endif
f3240e28 2118 }
47dd7a54
GC		 2119 }
2120 return 0;
f3240e28
GC		 2121
2122err:
2123 pr_err("%s: ERROR broken module parameter conversion", __func__);
2124 return -EINVAL;
47dd7a54
GC		 2125}
2126
2127__setup("stmmaceth=", stmmac_cmdline_opt);
2128#endif
6fc0d0f2
GC		 2129
2130MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2131MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2132MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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