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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
47dd7a54 GC |
31 | #include <linux/kernel.h> |
32 | #include <linux/interrupt.h> | |
47dd7a54 GC |
33 | #include <linux/ip.h> |
34 | #include <linux/tcp.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/if_ether.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/mii.h> | |
01789349 | 40 | #include <linux/if.h> |
47dd7a54 GC |
41 | #include <linux/if_vlan.h> |
42 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
70c71606 | 44 | #include <linux/prefetch.h> |
7ac29055 GC |
45 | #ifdef CONFIG_STMMAC_DEBUG_FS |
46 | #include <linux/debugfs.h> | |
47 | #include <linux/seq_file.h> | |
48 | #endif | |
286a8372 | 49 | #include "stmmac.h" |
47dd7a54 | 50 | |
47dd7a54 GC |
51 | #undef STMMAC_DEBUG |
52 | /*#define STMMAC_DEBUG*/ | |
53 | #ifdef STMMAC_DEBUG | |
54 | #define DBG(nlevel, klevel, fmt, args...) \ | |
55 | ((void)(netif_msg_##nlevel(priv) && \ | |
56 | printk(KERN_##klevel fmt, ## args))) | |
57 | #else | |
58 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
59 | #endif | |
60 | ||
61 | #undef STMMAC_RX_DEBUG | |
62 | /*#define STMMAC_RX_DEBUG*/ | |
63 | #ifdef STMMAC_RX_DEBUG | |
64 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
65 | #else | |
66 | #define RX_DBG(fmt, args...) do { } while (0) | |
67 | #endif | |
68 | ||
69 | #undef STMMAC_XMIT_DEBUG | |
70 | /*#define STMMAC_XMIT_DEBUG*/ | |
71 | #ifdef STMMAC_TX_DEBUG | |
72 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
73 | #else | |
74 | #define TX_DBG(fmt, args...) do { } while (0) | |
75 | #endif | |
76 | ||
77 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
78 | #define JUMBO_LEN 9000 | |
79 | ||
80 | /* Module parameters */ | |
81 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
82 | static int watchdog = TX_TIMEO; | |
83 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
85 | ||
86 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
87 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
88 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
89 | ||
bfab27a1 | 90 | int phyaddr = -1; |
47dd7a54 GC |
91 | module_param(phyaddr, int, S_IRUGO); |
92 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
93 | ||
94 | #define DMA_TX_SIZE 256 | |
95 | static int dma_txsize = DMA_TX_SIZE; | |
96 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
97 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
98 | ||
99 | #define DMA_RX_SIZE 256 | |
100 | static int dma_rxsize = DMA_RX_SIZE; | |
101 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
102 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
103 | ||
104 | static int flow_ctrl = FLOW_OFF; | |
105 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
106 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
107 | ||
108 | static int pause = PAUSE_TIME; | |
109 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
110 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
111 | ||
112 | #define TC_DEFAULT 64 | |
113 | static int tc = TC_DEFAULT; | |
114 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
115 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
116 | ||
47dd7a54 GC |
117 | /* Pay attention to tune this parameter; take care of both |
118 | * hardware capability and network stabitily/performance impact. | |
119 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
120 | #ifdef CONFIG_STMMAC_TIMER | |
121 | #define DEFAULT_PERIODIC_RATE 256 | |
122 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
123 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
124 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
125 | #endif | |
126 | ||
127 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
128 | static int buf_sz = DMA_BUFFER_SIZE; | |
129 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
130 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
131 | ||
47dd7a54 GC |
132 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
133 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
134 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
135 | ||
136 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 | 137 | |
bfab27a1 GC |
138 | #ifdef CONFIG_STMMAC_DEBUG_FS |
139 | static int stmmac_init_fs(struct net_device *dev); | |
140 | static void stmmac_exit_fs(void); | |
141 | #endif | |
142 | ||
47dd7a54 GC |
143 | /** |
144 | * stmmac_verify_args - verify the driver parameters. | |
145 | * Description: it verifies if some wrong parameter is passed to the driver. | |
146 | * Note that wrong parameters are replaced with the default values. | |
147 | */ | |
148 | static void stmmac_verify_args(void) | |
149 | { | |
150 | if (unlikely(watchdog < 0)) | |
151 | watchdog = TX_TIMEO; | |
152 | if (unlikely(dma_rxsize < 0)) | |
153 | dma_rxsize = DMA_RX_SIZE; | |
154 | if (unlikely(dma_txsize < 0)) | |
155 | dma_txsize = DMA_TX_SIZE; | |
156 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
157 | buf_sz = DMA_BUFFER_SIZE; | |
158 | if (unlikely(flow_ctrl > 1)) | |
159 | flow_ctrl = FLOW_AUTO; | |
160 | else if (likely(flow_ctrl < 0)) | |
161 | flow_ctrl = FLOW_OFF; | |
162 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
163 | pause = PAUSE_TIME; | |
47dd7a54 GC |
164 | } |
165 | ||
cd7201f4 GC |
166 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
167 | { | |
168 | #ifdef CONFIG_HAVE_CLK | |
169 | u32 clk_rate; | |
170 | ||
31ea38ee GC |
171 | if (IS_ERR(priv->stmmac_clk)) |
172 | return; | |
173 | ||
cd7201f4 GC |
174 | clk_rate = clk_get_rate(priv->stmmac_clk); |
175 | ||
176 | /* Platform provided default clk_csr would be assumed valid | |
177 | * for all other cases except for the below mentioned ones. */ | |
178 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { | |
179 | if (clk_rate < CSR_F_35M) | |
180 | priv->clk_csr = STMMAC_CSR_20_35M; | |
181 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
182 | priv->clk_csr = STMMAC_CSR_35_60M; | |
183 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
184 | priv->clk_csr = STMMAC_CSR_60_100M; | |
185 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
186 | priv->clk_csr = STMMAC_CSR_100_150M; | |
187 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
188 | priv->clk_csr = STMMAC_CSR_150_250M; | |
189 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) | |
190 | priv->clk_csr = STMMAC_CSR_250_300M; | |
191 | } /* For values higher than the IEEE 802.3 specified frequency | |
192 | * we can not estimate the proper divider as it is not known | |
193 | * the frequency of clk_csr_i. So we do not change the default | |
194 | * divider. */ | |
195 | #endif | |
196 | } | |
197 | ||
47dd7a54 GC |
198 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) |
199 | static void print_pkt(unsigned char *buf, int len) | |
200 | { | |
201 | int j; | |
202 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
203 | for (j = 0; j < len; j++) { | |
204 | if ((j % 16) == 0) | |
205 | pr_info("\n %03x:", j); | |
206 | pr_info(" %02x", buf[j]); | |
207 | } | |
208 | pr_info("\n"); | |
47dd7a54 GC |
209 | } |
210 | #endif | |
211 | ||
212 | /* minimum number of free TX descriptors required to wake up TX process */ | |
213 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
214 | ||
215 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
216 | { | |
217 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
218 | } | |
219 | ||
9dfeb4d9 GC |
220 | /* On some ST platforms, some HW system configuraton registers have to be |
221 | * set according to the link speed negotiated. | |
222 | */ | |
223 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
224 | { | |
225 | struct phy_device *phydev = priv->phydev; | |
226 | ||
227 | if (likely(priv->plat->fix_mac_speed)) | |
228 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
229 | phydev->speed); | |
230 | } | |
231 | ||
47dd7a54 GC |
232 | /** |
233 | * stmmac_adjust_link | |
234 | * @dev: net device structure | |
235 | * Description: it adjusts the link parameters. | |
236 | */ | |
237 | static void stmmac_adjust_link(struct net_device *dev) | |
238 | { | |
239 | struct stmmac_priv *priv = netdev_priv(dev); | |
240 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
241 | unsigned long flags; |
242 | int new_state = 0; | |
243 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
244 | ||
245 | if (phydev == NULL) | |
246 | return; | |
247 | ||
248 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
249 | phydev->addr, phydev->link); | |
250 | ||
251 | spin_lock_irqsave(&priv->lock, flags); | |
252 | if (phydev->link) { | |
ad01b7d4 | 253 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
254 | |
255 | /* Now we make sure that we can be in full duplex mode. | |
256 | * If not, we operate in half-duplex mode. */ | |
257 | if (phydev->duplex != priv->oldduplex) { | |
258 | new_state = 1; | |
259 | if (!(phydev->duplex)) | |
db98a0b0 | 260 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 261 | else |
db98a0b0 | 262 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
263 | priv->oldduplex = phydev->duplex; |
264 | } | |
265 | /* Flow Control operation */ | |
266 | if (phydev->pause) | |
ad01b7d4 | 267 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 268 | fc, pause_time); |
47dd7a54 GC |
269 | |
270 | if (phydev->speed != priv->speed) { | |
271 | new_state = 1; | |
272 | switch (phydev->speed) { | |
273 | case 1000: | |
9dfeb4d9 | 274 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 275 | ctrl &= ~priv->hw->link.port; |
cf3f047b | 276 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
277 | break; |
278 | case 100: | |
279 | case 10: | |
9dfeb4d9 | 280 | if (priv->plat->has_gmac) { |
db98a0b0 | 281 | ctrl |= priv->hw->link.port; |
47dd7a54 | 282 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 283 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 284 | } else { |
db98a0b0 | 285 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
286 | } |
287 | } else { | |
db98a0b0 | 288 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 289 | } |
9dfeb4d9 | 290 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
291 | break; |
292 | default: | |
293 | if (netif_msg_link(priv)) | |
294 | pr_warning("%s: Speed (%d) is not 10" | |
295 | " or 100!\n", dev->name, phydev->speed); | |
296 | break; | |
297 | } | |
298 | ||
299 | priv->speed = phydev->speed; | |
300 | } | |
301 | ||
ad01b7d4 | 302 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
303 | |
304 | if (!priv->oldlink) { | |
305 | new_state = 1; | |
306 | priv->oldlink = 1; | |
307 | } | |
308 | } else if (priv->oldlink) { | |
309 | new_state = 1; | |
310 | priv->oldlink = 0; | |
311 | priv->speed = 0; | |
312 | priv->oldduplex = -1; | |
313 | } | |
314 | ||
315 | if (new_state && netif_msg_link(priv)) | |
316 | phy_print_status(phydev); | |
317 | ||
318 | spin_unlock_irqrestore(&priv->lock, flags); | |
319 | ||
320 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
321 | } | |
322 | ||
323 | /** | |
324 | * stmmac_init_phy - PHY initialization | |
325 | * @dev: net device structure | |
326 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
327 | * to the mac driver. | |
328 | * Return value: | |
329 | * 0 on success | |
330 | */ | |
331 | static int stmmac_init_phy(struct net_device *dev) | |
332 | { | |
333 | struct stmmac_priv *priv = netdev_priv(dev); | |
334 | struct phy_device *phydev; | |
109cdd66 GC |
335 | char phy_id[MII_BUS_ID_SIZE + 3]; |
336 | char bus_id[MII_BUS_ID_SIZE]; | |
79ee1dc3 | 337 | int interface = priv->plat->interface; |
47dd7a54 GC |
338 | priv->oldlink = 0; |
339 | priv->speed = 0; | |
340 | priv->oldduplex = -1; | |
341 | ||
f142af2e SK |
342 | if (priv->plat->phy_bus_name) |
343 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", | |
344 | priv->plat->phy_bus_name, priv->plat->bus_id); | |
345 | else | |
346 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", | |
347 | priv->plat->bus_id); | |
348 | ||
109cdd66 | 349 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 350 | priv->plat->phy_addr); |
47dd7a54 GC |
351 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
352 | ||
79ee1dc3 | 353 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); |
47dd7a54 GC |
354 | |
355 | if (IS_ERR(phydev)) { | |
356 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
357 | return PTR_ERR(phydev); | |
358 | } | |
359 | ||
79ee1dc3 | 360 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 SK |
361 | if ((interface == PHY_INTERFACE_MODE_MII) || |
362 | (interface == PHY_INTERFACE_MODE_RMII)) | |
363 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | | |
364 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 365 | |
47dd7a54 GC |
366 | /* |
367 | * Broken HW is sometimes missing the pull-up resistor on the | |
368 | * MDIO line, which results in reads to non-existent devices returning | |
369 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
370 | * device as well. | |
371 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
372 | */ | |
373 | if (phydev->phy_id == 0) { | |
374 | phy_disconnect(phydev); | |
375 | return -ENODEV; | |
376 | } | |
377 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 378 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
379 | |
380 | priv->phydev = phydev; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
47dd7a54 GC |
385 | /** |
386 | * display_ring | |
387 | * @p: pointer to the ring. | |
388 | * @size: size of the ring. | |
389 | * Description: display all the descriptors within the ring. | |
390 | */ | |
391 | static void display_ring(struct dma_desc *p, int size) | |
392 | { | |
393 | struct tmp_s { | |
394 | u64 a; | |
395 | unsigned int b; | |
396 | unsigned int c; | |
397 | }; | |
398 | int i; | |
399 | for (i = 0; i < size; i++) { | |
400 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
401 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
402 | i, (unsigned int)virt_to_phys(&p[i]), | |
403 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
404 | x->b, x->c); | |
405 | pr_info("\n"); | |
406 | } | |
407 | } | |
408 | ||
286a8372 GC |
409 | static int stmmac_set_bfsize(int mtu, int bufsize) |
410 | { | |
411 | int ret = bufsize; | |
412 | ||
413 | if (mtu >= BUF_SIZE_4KiB) | |
414 | ret = BUF_SIZE_8KiB; | |
415 | else if (mtu >= BUF_SIZE_2KiB) | |
416 | ret = BUF_SIZE_4KiB; | |
417 | else if (mtu >= DMA_BUFFER_SIZE) | |
418 | ret = BUF_SIZE_2KiB; | |
419 | else | |
420 | ret = DMA_BUFFER_SIZE; | |
421 | ||
422 | return ret; | |
423 | } | |
424 | ||
47dd7a54 GC |
425 | /** |
426 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
427 | * @dev: net device structure | |
428 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
429 | * and allocates the socket buffers. It suppors the chained and ring |
430 | * modes. | |
47dd7a54 GC |
431 | */ |
432 | static void init_dma_desc_rings(struct net_device *dev) | |
433 | { | |
434 | int i; | |
435 | struct stmmac_priv *priv = netdev_priv(dev); | |
436 | struct sk_buff *skb; | |
437 | unsigned int txsize = priv->dma_tx_size; | |
438 | unsigned int rxsize = priv->dma_rx_size; | |
286a8372 GC |
439 | unsigned int bfsize; |
440 | int dis_ic = 0; | |
441 | int des3_as_data_buf = 0; | |
47dd7a54 | 442 | |
286a8372 GC |
443 | /* Set the max buffer size according to the DESC mode |
444 | * and the MTU. Note that RING mode allows 16KiB bsize. */ | |
445 | bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); | |
446 | ||
447 | if (bfsize == BUF_SIZE_16KiB) | |
448 | des3_as_data_buf = 1; | |
47dd7a54 | 449 | else |
286a8372 | 450 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 451 | |
73cfe264 GC |
452 | #ifdef CONFIG_STMMAC_TIMER |
453 | /* Disable interrupts on completion for the reception if timer is on */ | |
454 | if (likely(priv->tm->enable)) | |
455 | dis_ic = 1; | |
456 | #endif | |
47dd7a54 GC |
457 | |
458 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
459 | txsize, rxsize, bfsize); | |
460 | ||
461 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
462 | priv->rx_skbuff = | |
463 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
464 | priv->dma_rx = | |
465 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
466 | rxsize * | |
467 | sizeof(struct dma_desc), | |
468 | &priv->dma_rx_phy, | |
469 | GFP_KERNEL); | |
470 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
471 | GFP_KERNEL); | |
472 | priv->dma_tx = | |
473 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
474 | txsize * | |
475 | sizeof(struct dma_desc), | |
476 | &priv->dma_tx_phy, | |
477 | GFP_KERNEL); | |
478 | ||
479 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
480 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
481 | return; | |
482 | } | |
483 | ||
286a8372 | 484 | DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " |
47dd7a54 GC |
485 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", |
486 | dev->name, priv->dma_rx, priv->dma_tx, | |
487 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
488 | ||
489 | /* RX INITIALIZATION */ | |
490 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
491 | "skb\t\tskb data\tdma data\n"); | |
492 | ||
493 | for (i = 0; i < rxsize; i++) { | |
494 | struct dma_desc *p = priv->dma_rx + i; | |
495 | ||
45db81e1 GC |
496 | skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, |
497 | GFP_KERNEL); | |
47dd7a54 GC |
498 | if (unlikely(skb == NULL)) { |
499 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
500 | break; | |
501 | } | |
45db81e1 | 502 | skb_reserve(skb, NET_IP_ALIGN); |
47dd7a54 GC |
503 | priv->rx_skbuff[i] = skb; |
504 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
505 | bfsize, DMA_FROM_DEVICE); | |
506 | ||
507 | p->des2 = priv->rx_skbuff_dma[i]; | |
286a8372 GC |
508 | |
509 | priv->hw->ring->init_desc3(des3_as_data_buf, p); | |
510 | ||
47dd7a54 GC |
511 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], |
512 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
513 | } | |
514 | priv->cur_rx = 0; | |
515 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
516 | priv->dma_buf_sz = bfsize; | |
517 | buf_sz = bfsize; | |
518 | ||
519 | /* TX INITIALIZATION */ | |
520 | for (i = 0; i < txsize; i++) { | |
521 | priv->tx_skbuff[i] = NULL; | |
522 | priv->dma_tx[i].des2 = 0; | |
523 | } | |
286a8372 GC |
524 | |
525 | /* In case of Chained mode this sets the des3 to the next | |
526 | * element in the chain */ | |
527 | priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); | |
528 | priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); | |
529 | ||
47dd7a54 GC |
530 | priv->dirty_tx = 0; |
531 | priv->cur_tx = 0; | |
532 | ||
533 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
534 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
535 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
536 | |
537 | if (netif_msg_hw(priv)) { | |
538 | pr_info("RX descriptor ring:\n"); | |
539 | display_ring(priv->dma_rx, rxsize); | |
540 | pr_info("TX descriptor ring:\n"); | |
541 | display_ring(priv->dma_tx, txsize); | |
542 | } | |
47dd7a54 GC |
543 | } |
544 | ||
545 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
546 | { | |
547 | int i; | |
548 | ||
549 | for (i = 0; i < priv->dma_rx_size; i++) { | |
550 | if (priv->rx_skbuff[i]) { | |
551 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
552 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
553 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
554 | } | |
555 | priv->rx_skbuff[i] = NULL; | |
556 | } | |
47dd7a54 GC |
557 | } |
558 | ||
559 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
560 | { | |
561 | int i; | |
562 | ||
563 | for (i = 0; i < priv->dma_tx_size; i++) { | |
564 | if (priv->tx_skbuff[i] != NULL) { | |
565 | struct dma_desc *p = priv->dma_tx + i; | |
566 | if (p->des2) | |
567 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
568 | priv->hw->desc->get_tx_len(p), |
569 | DMA_TO_DEVICE); | |
47dd7a54 GC |
570 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
571 | priv->tx_skbuff[i] = NULL; | |
572 | } | |
573 | } | |
47dd7a54 GC |
574 | } |
575 | ||
576 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
577 | { | |
578 | /* Release the DMA TX/RX socket buffers */ | |
579 | dma_free_rx_skbufs(priv); | |
580 | dma_free_tx_skbufs(priv); | |
581 | ||
582 | /* Free the region of consistent memory previously allocated for | |
583 | * the DMA */ | |
584 | dma_free_coherent(priv->device, | |
585 | priv->dma_tx_size * sizeof(struct dma_desc), | |
586 | priv->dma_tx, priv->dma_tx_phy); | |
587 | dma_free_coherent(priv->device, | |
588 | priv->dma_rx_size * sizeof(struct dma_desc), | |
589 | priv->dma_rx, priv->dma_rx_phy); | |
590 | kfree(priv->rx_skbuff_dma); | |
591 | kfree(priv->rx_skbuff); | |
592 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
593 | } |
594 | ||
47dd7a54 GC |
595 | /** |
596 | * stmmac_dma_operation_mode - HW DMA operation mode | |
597 | * @priv : pointer to the private device structure. | |
598 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 599 | * or Store-And-Forward capability. |
47dd7a54 GC |
600 | */ |
601 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
602 | { | |
61b8013a SK |
603 | if (likely(priv->plat->force_sf_dma_mode || |
604 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
605 | /* | |
606 | * In case of GMAC, SF mode can be enabled | |
607 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
608 | * 1) TX COE if actually supported |
609 | * 2) There is no bugged Jumbo frame support | |
610 | * that needs to not insert csum in the TDES. | |
611 | */ | |
612 | priv->hw->dma->dma_mode(priv->ioaddr, | |
613 | SF_DMA_MODE, SF_DMA_MODE); | |
614 | tc = SF_DMA_MODE; | |
615 | } else | |
616 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
617 | } |
618 | ||
47dd7a54 GC |
619 | /** |
620 | * stmmac_tx: | |
621 | * @priv: private driver structure | |
622 | * Description: it reclaims resources after transmission completes. | |
623 | */ | |
624 | static void stmmac_tx(struct stmmac_priv *priv) | |
625 | { | |
626 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 | 627 | |
a9097a96 GC |
628 | spin_lock(&priv->tx_lock); |
629 | ||
47dd7a54 GC |
630 | while (priv->dirty_tx != priv->cur_tx) { |
631 | int last; | |
632 | unsigned int entry = priv->dirty_tx % txsize; | |
633 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
634 | struct dma_desc *p = priv->dma_tx + entry; | |
635 | ||
636 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 637 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
638 | break; |
639 | ||
640 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 641 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
642 | if (likely(last)) { |
643 | int tx_error = | |
db98a0b0 GC |
644 | priv->hw->desc->tx_status(&priv->dev->stats, |
645 | &priv->xstats, p, | |
ad01b7d4 | 646 | priv->ioaddr); |
47dd7a54 GC |
647 | if (likely(tx_error == 0)) { |
648 | priv->dev->stats.tx_packets++; | |
649 | priv->xstats.tx_pkt_n++; | |
650 | } else | |
651 | priv->dev->stats.tx_errors++; | |
652 | } | |
653 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
654 | priv->cur_tx, priv->dirty_tx); | |
655 | ||
656 | if (likely(p->des2)) | |
657 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 658 | priv->hw->desc->get_tx_len(p), |
47dd7a54 | 659 | DMA_TO_DEVICE); |
286a8372 | 660 | priv->hw->ring->clean_desc3(p); |
47dd7a54 GC |
661 | |
662 | if (likely(skb != NULL)) { | |
663 | /* | |
664 | * If there's room in the queue (limit it to size) | |
665 | * we add this skb back into the pool, | |
666 | * if it's the right size. | |
667 | */ | |
668 | if ((skb_queue_len(&priv->rx_recycle) < | |
669 | priv->dma_rx_size) && | |
670 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
671 | __skb_queue_head(&priv->rx_recycle, skb); | |
672 | else | |
673 | dev_kfree_skb(skb); | |
674 | ||
675 | priv->tx_skbuff[entry] = NULL; | |
676 | } | |
677 | ||
db98a0b0 | 678 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 GC |
679 | |
680 | entry = (++priv->dirty_tx) % txsize; | |
681 | } | |
682 | if (unlikely(netif_queue_stopped(priv->dev) && | |
683 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
684 | netif_tx_lock(priv->dev); | |
685 | if (netif_queue_stopped(priv->dev) && | |
686 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
687 | TX_DBG("%s: restart transmit\n", __func__); | |
688 | netif_wake_queue(priv->dev); | |
689 | } | |
690 | netif_tx_unlock(priv->dev); | |
691 | } | |
a9097a96 | 692 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
693 | } |
694 | ||
695 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
696 | { | |
73cfe264 GC |
697 | #ifdef CONFIG_STMMAC_TIMER |
698 | if (likely(priv->tm->enable)) | |
699 | priv->tm->timer_start(tmrate); | |
700 | else | |
47dd7a54 | 701 | #endif |
ad01b7d4 | 702 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
703 | } |
704 | ||
705 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
706 | { | |
73cfe264 GC |
707 | #ifdef CONFIG_STMMAC_TIMER |
708 | if (likely(priv->tm->enable)) | |
709 | priv->tm->timer_stop(); | |
710 | else | |
47dd7a54 | 711 | #endif |
ad01b7d4 | 712 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
713 | } |
714 | ||
715 | static int stmmac_has_work(struct stmmac_priv *priv) | |
716 | { | |
717 | unsigned int has_work = 0; | |
718 | int rxret, tx_work = 0; | |
719 | ||
db98a0b0 | 720 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
721 | (priv->cur_rx % priv->dma_rx_size)); |
722 | ||
723 | if (priv->dirty_tx != priv->cur_tx) | |
724 | tx_work = 1; | |
725 | ||
726 | if (likely(!rxret || tx_work)) | |
727 | has_work = 1; | |
728 | ||
729 | return has_work; | |
730 | } | |
731 | ||
732 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
733 | { | |
734 | if (likely(stmmac_has_work(priv))) { | |
735 | stmmac_disable_irq(priv); | |
736 | napi_schedule(&priv->napi); | |
737 | } | |
738 | } | |
739 | ||
740 | #ifdef CONFIG_STMMAC_TIMER | |
741 | void stmmac_schedule(struct net_device *dev) | |
742 | { | |
743 | struct stmmac_priv *priv = netdev_priv(dev); | |
744 | ||
745 | priv->xstats.sched_timer_n++; | |
746 | ||
747 | _stmmac_schedule(priv); | |
47dd7a54 GC |
748 | } |
749 | ||
750 | static void stmmac_no_timer_started(unsigned int x) | |
751 | {; | |
752 | }; | |
753 | ||
754 | static void stmmac_no_timer_stopped(void) | |
755 | {; | |
756 | }; | |
757 | #endif | |
758 | ||
759 | /** | |
760 | * stmmac_tx_err: | |
761 | * @priv: pointer to the private device structure | |
762 | * Description: it cleans the descriptors and restarts the transmission | |
763 | * in case of errors. | |
764 | */ | |
765 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
766 | { | |
767 | netif_stop_queue(priv->dev); | |
768 | ||
ad01b7d4 | 769 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 770 | dma_free_tx_skbufs(priv); |
db98a0b0 | 771 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
772 | priv->dirty_tx = 0; |
773 | priv->cur_tx = 0; | |
ad01b7d4 | 774 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
775 | |
776 | priv->dev->stats.tx_errors++; | |
777 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
778 | } |
779 | ||
47dd7a54 | 780 | |
aec7ff27 GC |
781 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
782 | { | |
aec7ff27 GC |
783 | int status; |
784 | ||
ad01b7d4 | 785 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
786 | if (likely(status == handle_tx_rx)) |
787 | _stmmac_schedule(priv); | |
788 | ||
789 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
790 | /* Try to bump up the dma threshold on this failure */ | |
791 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
792 | tc += 64; | |
ad01b7d4 | 793 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 794 | priv->xstats.threshold = tc; |
47dd7a54 | 795 | } |
aec7ff27 GC |
796 | } else if (unlikely(status == tx_hard_error)) |
797 | stmmac_tx_err(priv); | |
47dd7a54 GC |
798 | } |
799 | ||
1c901a46 GC |
800 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
801 | { | |
802 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
803 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; | |
804 | ||
4f795b25 GC |
805 | /* Mask MMC irq, counters are managed in SW and registers |
806 | * are cleared on each READ eventually. */ | |
1c901a46 | 807 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
808 | |
809 | if (priv->dma_cap.rmon) { | |
810 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
811 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
812 | } else | |
aae54cff | 813 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
814 | } |
815 | ||
f0b9d786 GC |
816 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
817 | { | |
818 | u32 hwid = priv->hw->synopsys_uid; | |
819 | ||
820 | /* Only check valid Synopsys Id because old MAC chips | |
821 | * have no HW registers where get the ID */ | |
822 | if (likely(hwid)) { | |
823 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
824 | u32 synid = (hwid & 0x000000ff); | |
825 | ||
cf3f047b | 826 | pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", |
f0b9d786 GC |
827 | uid, synid); |
828 | ||
829 | return synid; | |
830 | } | |
831 | return 0; | |
832 | } | |
e7434821 | 833 | |
19e30c14 GC |
834 | /** |
835 | * stmmac_selec_desc_mode | |
836 | * @dev : device pointer | |
837 | * Description: select the Enhanced/Alternate or Normal descriptors */ | |
838 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) | |
839 | { | |
840 | if (priv->plat->enh_desc) { | |
841 | pr_info(" Enhanced/Alternate descriptors\n"); | |
842 | priv->hw->desc = &enh_desc_ops; | |
843 | } else { | |
844 | pr_info(" Normal descriptors\n"); | |
845 | priv->hw->desc = &ndesc_ops; | |
846 | } | |
847 | } | |
848 | ||
849 | /** | |
850 | * stmmac_get_hw_features | |
851 | * @priv : private device pointer | |
852 | * Description: | |
853 | * new GMAC chip generations have a new register to indicate the | |
854 | * presence of the optional feature/functions. | |
855 | * This can be also used to override the value passed through the | |
856 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
857 | */ |
858 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
859 | { | |
5e6efe88 | 860 | u32 hw_cap = 0; |
3c20f72f | 861 | |
5e6efe88 GC |
862 | if (priv->hw->dma->get_hw_feature) { |
863 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 864 | |
1db123fb RK |
865 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
866 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
867 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
868 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
869 | priv->dma_cap.multi_addr = | |
870 | (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; | |
871 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; | |
872 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
873 | priv->dma_cap.pmt_remote_wake_up = | |
874 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; | |
875 | priv->dma_cap.pmt_magic_frame = | |
876 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; | |
19e30c14 | 877 | /* MMC */ |
1db123fb | 878 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
e7434821 | 879 | /* IEEE 1588-2002*/ |
1db123fb RK |
880 | priv->dma_cap.time_stamp = |
881 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; | |
e7434821 | 882 | /* IEEE 1588-2008*/ |
1db123fb RK |
883 | priv->dma_cap.atime_stamp = |
884 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; | |
e7434821 | 885 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
886 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
887 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 888 | /* TX and RX csum */ |
1db123fb RK |
889 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
890 | priv->dma_cap.rx_coe_type1 = | |
891 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; | |
892 | priv->dma_cap.rx_coe_type2 = | |
893 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; | |
894 | priv->dma_cap.rxfifo_over_2048 = | |
895 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; | |
e7434821 | 896 | /* TX and RX number of channels */ |
1db123fb RK |
897 | priv->dma_cap.number_rx_channel = |
898 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; | |
899 | priv->dma_cap.number_tx_channel = | |
900 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; | |
e7434821 | 901 | /* Alternate (enhanced) DESC mode*/ |
1db123fb RK |
902 | priv->dma_cap.enh_desc = |
903 | (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
e7434821 | 904 | |
19e30c14 | 905 | } |
e7434821 GC |
906 | |
907 | return hw_cap; | |
908 | } | |
909 | ||
bfab27a1 GC |
910 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
911 | { | |
912 | /* verify if the MAC address is valid, in case of failures it | |
913 | * generates a random MAC address */ | |
914 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { | |
915 | priv->hw->mac->get_umac_addr((void __iomem *) | |
916 | priv->dev->base_addr, | |
917 | priv->dev->dev_addr, 0); | |
918 | if (!is_valid_ether_addr(priv->dev->dev_addr)) | |
f2cedb63 | 919 | eth_hw_addr_random(priv->dev); |
bfab27a1 GC |
920 | } |
921 | pr_warning("%s: device MAC address %pM\n", priv->dev->name, | |
922 | priv->dev->dev_addr); | |
923 | } | |
924 | ||
0f1f88a8 GC |
925 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
926 | { | |
927 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; | |
928 | ||
929 | /* Some DMA parameters can be passed from the platform; | |
930 | * in case of these are not passed we keep a default | |
931 | * (good for all the chips) and init the DMA! */ | |
932 | if (priv->plat->dma_cfg) { | |
933 | pbl = priv->plat->dma_cfg->pbl; | |
934 | fixed_burst = priv->plat->dma_cfg->fixed_burst; | |
935 | burst_len = priv->plat->dma_cfg->burst_len; | |
936 | } | |
937 | ||
938 | return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, | |
939 | burst_len, priv->dma_tx_phy, | |
940 | priv->dma_rx_phy); | |
941 | } | |
942 | ||
47dd7a54 GC |
943 | /** |
944 | * stmmac_open - open entry point of the driver | |
945 | * @dev : pointer to the device structure. | |
946 | * Description: | |
947 | * This function is the open entry point of the driver. | |
948 | * Return value: | |
949 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
950 | * file on failure. | |
951 | */ | |
952 | static int stmmac_open(struct net_device *dev) | |
953 | { | |
954 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
955 | int ret; |
956 | ||
47dd7a54 | 957 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 958 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
4bfcbd7a FV |
959 | if (unlikely(priv->tm == NULL)) |
960 | return -ENOMEM; | |
e404decb | 961 | |
47dd7a54 GC |
962 | priv->tm->freq = tmrate; |
963 | ||
73cfe264 GC |
964 | /* Test if the external timer can be actually used. |
965 | * In case of failure continue without timer. */ | |
47dd7a54 | 966 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 967 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
968 | priv->tm->freq = 0; |
969 | priv->tm->timer_start = stmmac_no_timer_started; | |
970 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
971 | } else |
972 | priv->tm->enable = 1; | |
47dd7a54 | 973 | #endif |
4bfcbd7a FV |
974 | stmmac_clk_enable(priv); |
975 | ||
976 | stmmac_check_ether_addr(priv); | |
977 | ||
f66ffe28 GC |
978 | ret = stmmac_init_phy(dev); |
979 | if (unlikely(ret)) { | |
980 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
981 | goto open_error; | |
982 | } | |
47dd7a54 GC |
983 | |
984 | /* Create and initialize the TX/RX descriptors chains. */ | |
985 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
986 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
987 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
988 | init_dma_desc_rings(dev); | |
989 | ||
990 | /* DMA initialization and SW reset */ | |
0f1f88a8 | 991 | ret = stmmac_init_dma_engine(priv); |
f66ffe28 | 992 | if (ret < 0) { |
47dd7a54 | 993 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 994 | goto open_error; |
47dd7a54 GC |
995 | } |
996 | ||
997 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 998 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
cf3f047b | 999 | |
ca5f12c1 | 1000 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
1001 | if (priv->plat->bus_setup) |
1002 | priv->plat->bus_setup(priv->ioaddr); | |
cf3f047b | 1003 | |
47dd7a54 | 1004 | /* Initialize the MAC Core */ |
ad01b7d4 | 1005 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 1006 | |
f66ffe28 GC |
1007 | /* Request the IRQ lines */ |
1008 | ret = request_irq(dev->irq, stmmac_interrupt, | |
1009 | IRQF_SHARED, dev->name, dev); | |
1010 | if (unlikely(ret < 0)) { | |
1011 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1012 | __func__, dev->irq, ret); | |
1013 | goto open_error; | |
1014 | } | |
1015 | ||
7a13f8f5 FV |
1016 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1017 | if (priv->wol_irq != dev->irq) { | |
1018 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1019 | IRQF_SHARED, dev->name, dev); | |
1020 | if (unlikely(ret < 0)) { | |
1021 | pr_err("%s: ERROR: allocating the ext WoL IRQ %d " | |
1022 | "(error: %d)\n", __func__, priv->wol_irq, ret); | |
1023 | goto open_error_wolirq; | |
1024 | } | |
1025 | } | |
1026 | ||
47dd7a54 | 1027 | /* Enable the MAC Rx/Tx */ |
bfab27a1 | 1028 | stmmac_set_mac(priv->ioaddr, true); |
47dd7a54 GC |
1029 | |
1030 | /* Set the HW DMA mode and the COE */ | |
1031 | stmmac_dma_operation_mode(priv); | |
1032 | ||
1033 | /* Extra statistics */ | |
1034 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1035 | priv->xstats.threshold = tc; | |
1036 | ||
4f795b25 | 1037 | stmmac_mmc_setup(priv); |
1c901a46 | 1038 | |
bfab27a1 GC |
1039 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1040 | ret = stmmac_init_fs(dev); | |
1041 | if (ret < 0) | |
cf3f047b | 1042 | pr_warning("%s: failed debugFS registration\n", __func__); |
bfab27a1 | 1043 | #endif |
47dd7a54 GC |
1044 | /* Start the ball rolling... */ |
1045 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
1046 | priv->hw->dma->start_tx(priv->ioaddr); |
1047 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1048 | |
1049 | #ifdef CONFIG_STMMAC_TIMER | |
1050 | priv->tm->timer_start(tmrate); | |
1051 | #endif | |
cf3f047b | 1052 | |
47dd7a54 GC |
1053 | /* Dump DMA/MAC registers */ |
1054 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
1055 | priv->hw->mac->dump_regs(priv->ioaddr); |
1056 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
1057 | } |
1058 | ||
1059 | if (priv->phydev) | |
1060 | phy_start(priv->phydev); | |
1061 | ||
1062 | napi_enable(&priv->napi); | |
1063 | skb_queue_head_init(&priv->rx_recycle); | |
1064 | netif_start_queue(dev); | |
f66ffe28 | 1065 | |
47dd7a54 | 1066 | return 0; |
f66ffe28 | 1067 | |
7a13f8f5 FV |
1068 | open_error_wolirq: |
1069 | free_irq(dev->irq, dev); | |
1070 | ||
f66ffe28 GC |
1071 | open_error: |
1072 | #ifdef CONFIG_STMMAC_TIMER | |
1073 | kfree(priv->tm); | |
1074 | #endif | |
1075 | if (priv->phydev) | |
1076 | phy_disconnect(priv->phydev); | |
1077 | ||
ba1377ff | 1078 | stmmac_clk_disable(priv); |
4bfcbd7a | 1079 | |
f66ffe28 | 1080 | return ret; |
47dd7a54 GC |
1081 | } |
1082 | ||
1083 | /** | |
1084 | * stmmac_release - close entry point of the driver | |
1085 | * @dev : device pointer. | |
1086 | * Description: | |
1087 | * This is the stop entry point of the driver. | |
1088 | */ | |
1089 | static int stmmac_release(struct net_device *dev) | |
1090 | { | |
1091 | struct stmmac_priv *priv = netdev_priv(dev); | |
1092 | ||
1093 | /* Stop and disconnect the PHY */ | |
1094 | if (priv->phydev) { | |
1095 | phy_stop(priv->phydev); | |
1096 | phy_disconnect(priv->phydev); | |
1097 | priv->phydev = NULL; | |
1098 | } | |
1099 | ||
1100 | netif_stop_queue(dev); | |
1101 | ||
1102 | #ifdef CONFIG_STMMAC_TIMER | |
1103 | /* Stop and release the timer */ | |
1104 | stmmac_close_ext_timer(); | |
1105 | if (priv->tm != NULL) | |
1106 | kfree(priv->tm); | |
1107 | #endif | |
1108 | napi_disable(&priv->napi); | |
1109 | skb_queue_purge(&priv->rx_recycle); | |
1110 | ||
1111 | /* Free the IRQ lines */ | |
1112 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1113 | if (priv->wol_irq != dev->irq) |
1114 | free_irq(priv->wol_irq, dev); | |
47dd7a54 GC |
1115 | |
1116 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1117 | priv->hw->dma->stop_tx(priv->ioaddr); |
1118 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1119 | |
1120 | /* Release and free the Rx/Tx resources */ | |
1121 | free_dma_desc_resources(priv); | |
1122 | ||
19449bfc | 1123 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1124 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1125 | |
1126 | netif_carrier_off(dev); | |
1127 | ||
bfab27a1 GC |
1128 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1129 | stmmac_exit_fs(); | |
1130 | #endif | |
ba1377ff | 1131 | stmmac_clk_disable(priv); |
bfab27a1 | 1132 | |
47dd7a54 GC |
1133 | return 0; |
1134 | } | |
1135 | ||
47dd7a54 GC |
1136 | /** |
1137 | * stmmac_xmit: | |
1138 | * @skb : the socket buffer | |
1139 | * @dev : device pointer | |
1140 | * Description : Tx entry point of the driver. | |
1141 | */ | |
1142 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1143 | { | |
1144 | struct stmmac_priv *priv = netdev_priv(dev); | |
1145 | unsigned int txsize = priv->dma_tx_size; | |
1146 | unsigned int entry; | |
1147 | int i, csum_insertion = 0; | |
1148 | int nfrags = skb_shinfo(skb)->nr_frags; | |
1149 | struct dma_desc *desc, *first; | |
286a8372 | 1150 | unsigned int nopaged_len = skb_headlen(skb); |
47dd7a54 GC |
1151 | |
1152 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1153 | if (!netif_queue_stopped(dev)) { | |
1154 | netif_stop_queue(dev); | |
1155 | /* This is a hard error, log it. */ | |
1156 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
1157 | __func__); | |
1158 | } | |
1159 | return NETDEV_TX_BUSY; | |
1160 | } | |
1161 | ||
a9097a96 GC |
1162 | spin_lock(&priv->tx_lock); |
1163 | ||
47dd7a54 GC |
1164 | entry = priv->cur_tx % txsize; |
1165 | ||
1166 | #ifdef STMMAC_XMIT_DEBUG | |
1167 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1168 | pr_info("stmmac xmit:\n" | |
1169 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1170 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
286a8372 | 1171 | skb, skb->len, nopaged_len, nfrags, skb->ip_summed, |
47dd7a54 GC |
1172 | !skb_is_gso(skb) ? "isn't" : "is"); |
1173 | #endif | |
1174 | ||
5e982f3b | 1175 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1176 | |
1177 | desc = priv->dma_tx + entry; | |
1178 | first = desc; | |
1179 | ||
1180 | #ifdef STMMAC_XMIT_DEBUG | |
1181 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1182 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1183 | "\t\tn_frags: %d, ip_summed: %d\n", | |
286a8372 | 1184 | skb->len, nopaged_len, nfrags, skb->ip_summed); |
47dd7a54 GC |
1185 | #endif |
1186 | priv->tx_skbuff[entry] = skb; | |
286a8372 GC |
1187 | |
1188 | if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { | |
1189 | entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); | |
47dd7a54 GC |
1190 | desc = priv->dma_tx + entry; |
1191 | } else { | |
47dd7a54 GC |
1192 | desc->des2 = dma_map_single(priv->device, skb->data, |
1193 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1194 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1195 | csum_insertion); | |
47dd7a54 GC |
1196 | } |
1197 | ||
1198 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1199 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1200 | int len = skb_frag_size(frag); | |
47dd7a54 GC |
1201 | |
1202 | entry = (++priv->cur_tx) % txsize; | |
1203 | desc = priv->dma_tx + entry; | |
1204 | ||
1205 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
f722380d IC |
1206 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1207 | DMA_TO_DEVICE); | |
47dd7a54 | 1208 | priv->tx_skbuff[entry] = NULL; |
db98a0b0 | 1209 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1210 | wmb(); |
db98a0b0 | 1211 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1212 | } |
1213 | ||
1214 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1215 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1216 | |
47dd7a54 | 1217 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1218 | /* Clean IC while using timer */ |
1219 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1220 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1221 | #endif |
eb0dc4bb SH |
1222 | |
1223 | wmb(); | |
1224 | ||
47dd7a54 | 1225 | /* To avoid raise condition */ |
db98a0b0 | 1226 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1227 | |
1228 | priv->cur_tx++; | |
1229 | ||
1230 | #ifdef STMMAC_XMIT_DEBUG | |
1231 | if (netif_msg_pktdata(priv)) { | |
1232 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1233 | "first=%p, nfrags=%d\n", | |
1234 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1235 | entry, first, nfrags); | |
1236 | display_ring(priv->dma_tx, txsize); | |
1237 | pr_info(">>> frame to be transmitted: "); | |
1238 | print_pkt(skb->data, skb->len); | |
1239 | } | |
1240 | #endif | |
1241 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1242 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1243 | netif_stop_queue(dev); | |
1244 | } | |
1245 | ||
1246 | dev->stats.tx_bytes += skb->len; | |
1247 | ||
3e82ce12 RC |
1248 | skb_tx_timestamp(skb); |
1249 | ||
52f64fae RC |
1250 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1251 | ||
a9097a96 GC |
1252 | spin_unlock(&priv->tx_lock); |
1253 | ||
47dd7a54 GC |
1254 | return NETDEV_TX_OK; |
1255 | } | |
1256 | ||
1257 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1258 | { | |
1259 | unsigned int rxsize = priv->dma_rx_size; | |
1260 | int bfsize = priv->dma_buf_sz; | |
1261 | struct dma_desc *p = priv->dma_rx; | |
1262 | ||
1263 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1264 | unsigned int entry = priv->dirty_rx % rxsize; | |
1265 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1266 | struct sk_buff *skb; | |
1267 | ||
1268 | skb = __skb_dequeue(&priv->rx_recycle); | |
1269 | if (skb == NULL) | |
1270 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1271 | bfsize); | |
1272 | ||
1273 | if (unlikely(skb == NULL)) | |
1274 | break; | |
1275 | ||
1276 | priv->rx_skbuff[entry] = skb; | |
1277 | priv->rx_skbuff_dma[entry] = | |
1278 | dma_map_single(priv->device, skb->data, bfsize, | |
1279 | DMA_FROM_DEVICE); | |
1280 | ||
1281 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
286a8372 GC |
1282 | |
1283 | if (unlikely(priv->plat->has_gmac)) | |
1284 | priv->hw->ring->refill_desc3(bfsize, p + entry); | |
1285 | ||
47dd7a54 GC |
1286 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); |
1287 | } | |
eb0dc4bb | 1288 | wmb(); |
db98a0b0 | 1289 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1290 | } |
47dd7a54 GC |
1291 | } |
1292 | ||
1293 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1294 | { | |
1295 | unsigned int rxsize = priv->dma_rx_size; | |
1296 | unsigned int entry = priv->cur_rx % rxsize; | |
1297 | unsigned int next_entry; | |
1298 | unsigned int count = 0; | |
1299 | struct dma_desc *p = priv->dma_rx + entry; | |
1300 | struct dma_desc *p_next; | |
1301 | ||
1302 | #ifdef STMMAC_RX_DEBUG | |
1303 | if (netif_msg_hw(priv)) { | |
1304 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1305 | display_ring(priv->dma_rx, rxsize); | |
1306 | } | |
1307 | #endif | |
1308 | count = 0; | |
db98a0b0 | 1309 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1310 | int status; |
1311 | ||
1312 | if (count >= limit) | |
1313 | break; | |
1314 | ||
1315 | count++; | |
1316 | ||
1317 | next_entry = (++priv->cur_rx) % rxsize; | |
1318 | p_next = priv->dma_rx + next_entry; | |
1319 | prefetch(p_next); | |
1320 | ||
1321 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1322 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1323 | &priv->xstats, p)); | |
47dd7a54 GC |
1324 | if (unlikely(status == discard_frame)) |
1325 | priv->dev->stats.rx_errors++; | |
1326 | else { | |
1327 | struct sk_buff *skb; | |
3eeb2997 | 1328 | int frame_len; |
47dd7a54 | 1329 | |
38912bdb DS |
1330 | frame_len = priv->hw->desc->get_rx_frame_len(p, |
1331 | priv->plat->rx_coe); | |
3eeb2997 GC |
1332 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
1333 | * Type frames (LLC/LLC-SNAP) */ | |
1334 | if (unlikely(status != llc_snap)) | |
1335 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1336 | #ifdef STMMAC_RX_DEBUG |
1337 | if (frame_len > ETH_FRAME_LEN) | |
1338 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1339 | frame_len, status); | |
1340 | ||
1341 | if (netif_msg_hw(priv)) | |
1342 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1343 | p, entry, p->des2); | |
1344 | #endif | |
1345 | skb = priv->rx_skbuff[entry]; | |
1346 | if (unlikely(!skb)) { | |
1347 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1348 | priv->dev->name); | |
1349 | priv->dev->stats.rx_dropped++; | |
1350 | break; | |
1351 | } | |
1352 | prefetch(skb->data - NET_IP_ALIGN); | |
1353 | priv->rx_skbuff[entry] = NULL; | |
1354 | ||
1355 | skb_put(skb, frame_len); | |
1356 | dma_unmap_single(priv->device, | |
1357 | priv->rx_skbuff_dma[entry], | |
1358 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1359 | #ifdef STMMAC_RX_DEBUG | |
1360 | if (netif_msg_pktdata(priv)) { | |
1361 | pr_info(" frame received (%dbytes)", frame_len); | |
1362 | print_pkt(skb->data, frame_len); | |
1363 | } | |
1364 | #endif | |
1365 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1366 | ||
38912bdb | 1367 | if (unlikely(!priv->plat->rx_coe)) { |
3c20f72f | 1368 | /* No RX COE for old mac10/100 devices */ |
bc8acf2c | 1369 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1370 | netif_receive_skb(skb); |
1371 | } else { | |
1372 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1373 | napi_gro_receive(&priv->napi, skb); | |
1374 | } | |
1375 | ||
1376 | priv->dev->stats.rx_packets++; | |
1377 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1378 | } |
1379 | entry = next_entry; | |
1380 | p = p_next; /* use prefetched values */ | |
1381 | } | |
1382 | ||
1383 | stmmac_rx_refill(priv); | |
1384 | ||
1385 | priv->xstats.rx_pkt_n += count; | |
1386 | ||
1387 | return count; | |
1388 | } | |
1389 | ||
1390 | /** | |
1391 | * stmmac_poll - stmmac poll method (NAPI) | |
1392 | * @napi : pointer to the napi structure. | |
1393 | * @budget : maximum number of packets that the current CPU can receive from | |
1394 | * all interfaces. | |
1395 | * Description : | |
1396 | * This function implements the the reception process. | |
1397 | * Also it runs the TX completion thread | |
1398 | */ | |
1399 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1400 | { | |
1401 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1402 | int work_done = 0; | |
1403 | ||
1404 | priv->xstats.poll_n++; | |
1405 | stmmac_tx(priv); | |
1406 | work_done = stmmac_rx(priv, budget); | |
1407 | ||
1408 | if (work_done < budget) { | |
1409 | napi_complete(napi); | |
1410 | stmmac_enable_irq(priv); | |
1411 | } | |
1412 | return work_done; | |
1413 | } | |
1414 | ||
1415 | /** | |
1416 | * stmmac_tx_timeout | |
1417 | * @dev : Pointer to net device structure | |
1418 | * Description: this function is called when a packet transmission fails to | |
1419 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1420 | * netdev structure and arrange for the device to be reset to a sane state | |
1421 | * in order to transmit a new packet. | |
1422 | */ | |
1423 | static void stmmac_tx_timeout(struct net_device *dev) | |
1424 | { | |
1425 | struct stmmac_priv *priv = netdev_priv(dev); | |
1426 | ||
1427 | /* Clear Tx resources and restart transmitting again */ | |
1428 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1429 | } |
1430 | ||
1431 | /* Configuration changes (passed on by ifconfig) */ | |
1432 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1433 | { | |
1434 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1435 | return -EBUSY; | |
1436 | ||
1437 | /* Don't allow changing the I/O address */ | |
1438 | if (map->base_addr != dev->base_addr) { | |
1439 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1440 | return -EOPNOTSUPP; | |
1441 | } | |
1442 | ||
1443 | /* Don't allow changing the IRQ */ | |
1444 | if (map->irq != dev->irq) { | |
1445 | pr_warning("%s: can't change IRQ number %d\n", | |
1446 | dev->name, dev->irq); | |
1447 | return -EOPNOTSUPP; | |
1448 | } | |
1449 | ||
1450 | /* ignore other fields */ | |
1451 | return 0; | |
1452 | } | |
1453 | ||
1454 | /** | |
01789349 | 1455 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
1456 | * @dev : pointer to the device structure |
1457 | * Description: | |
1458 | * This function is a driver entry point which gets called by the kernel | |
1459 | * whenever multicast addresses must be enabled/disabled. | |
1460 | * Return value: | |
1461 | * void. | |
1462 | */ | |
01789349 | 1463 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
1464 | { |
1465 | struct stmmac_priv *priv = netdev_priv(dev); | |
1466 | ||
1467 | spin_lock(&priv->lock); | |
cffb13f4 | 1468 | priv->hw->mac->set_filter(dev, priv->synopsys_id); |
47dd7a54 | 1469 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1470 | } |
1471 | ||
1472 | /** | |
1473 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1474 | * @dev : device pointer. | |
1475 | * @new_mtu : the new MTU size for the device. | |
1476 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1477 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1478 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1479 | * Return value: | |
1480 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1481 | * file on failure. | |
1482 | */ | |
1483 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1484 | { | |
1485 | struct stmmac_priv *priv = netdev_priv(dev); | |
1486 | int max_mtu; | |
1487 | ||
1488 | if (netif_running(dev)) { | |
1489 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1490 | return -EBUSY; | |
1491 | } | |
1492 | ||
48febf7e | 1493 | if (priv->plat->enh_desc) |
47dd7a54 GC |
1494 | max_mtu = JUMBO_LEN; |
1495 | else | |
45db81e1 | 1496 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 GC |
1497 | |
1498 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1499 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1500 | return -EINVAL; | |
1501 | } | |
1502 | ||
5e982f3b MM |
1503 | dev->mtu = new_mtu; |
1504 | netdev_update_features(dev); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
c8f44aff MM |
1509 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
1510 | netdev_features_t features) | |
5e982f3b MM |
1511 | { |
1512 | struct stmmac_priv *priv = netdev_priv(dev); | |
1513 | ||
38912bdb | 1514 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 1515 | features &= ~NETIF_F_RXCSUM; |
38912bdb DS |
1516 | else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) |
1517 | features &= ~NETIF_F_IPV6_CSUM; | |
5e982f3b MM |
1518 | if (!priv->plat->tx_coe) |
1519 | features &= ~NETIF_F_ALL_CSUM; | |
1520 | ||
ebbb293f GC |
1521 | /* Some GMAC devices have a bugged Jumbo frame support that |
1522 | * needs to have the Tx COE disabled for oversized frames | |
1523 | * (due to limited buffer sizes). In this case we disable | |
1524 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1525 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1526 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1527 | |
5e982f3b | 1528 | return features; |
47dd7a54 GC |
1529 | } |
1530 | ||
1531 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1532 | { | |
1533 | struct net_device *dev = (struct net_device *)dev_id; | |
1534 | struct stmmac_priv *priv = netdev_priv(dev); | |
1535 | ||
1536 | if (unlikely(!dev)) { | |
1537 | pr_err("%s: invalid dev pointer\n", __func__); | |
1538 | return IRQ_NONE; | |
1539 | } | |
1540 | ||
9dfeb4d9 | 1541 | if (priv->plat->has_gmac) |
47dd7a54 | 1542 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1543 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1544 | |
1545 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1546 | |
1547 | return IRQ_HANDLED; | |
1548 | } | |
1549 | ||
1550 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1551 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1552 | * to allow network I/O with interrupts disabled. */ | |
1553 | static void stmmac_poll_controller(struct net_device *dev) | |
1554 | { | |
1555 | disable_irq(dev->irq); | |
1556 | stmmac_interrupt(dev->irq, dev); | |
1557 | enable_irq(dev->irq); | |
1558 | } | |
1559 | #endif | |
1560 | ||
1561 | /** | |
1562 | * stmmac_ioctl - Entry point for the Ioctl | |
1563 | * @dev: Device pointer. | |
1564 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1565 | * a proprietary structure used to pass information to the driver. | |
1566 | * @cmd: IOCTL command | |
1567 | * Description: | |
1568 | * Currently there are no special functionality supported in IOCTL, just the | |
1569 | * phy_mii_ioctl(...) can be invoked. | |
1570 | */ | |
1571 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1572 | { | |
1573 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1574 | int ret; |
47dd7a54 GC |
1575 | |
1576 | if (!netif_running(dev)) | |
1577 | return -EINVAL; | |
1578 | ||
28b04113 RC |
1579 | if (!priv->phydev) |
1580 | return -EINVAL; | |
1581 | ||
28b04113 | 1582 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); |
28b04113 | 1583 | |
47dd7a54 GC |
1584 | return ret; |
1585 | } | |
1586 | ||
7ac29055 GC |
1587 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1588 | static struct dentry *stmmac_fs_dir; | |
1589 | static struct dentry *stmmac_rings_status; | |
e7434821 | 1590 | static struct dentry *stmmac_dma_cap; |
7ac29055 GC |
1591 | |
1592 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) | |
1593 | { | |
1594 | struct tmp_s { | |
1595 | u64 a; | |
1596 | unsigned int b; | |
1597 | unsigned int c; | |
1598 | }; | |
1599 | int i; | |
1600 | struct net_device *dev = seq->private; | |
1601 | struct stmmac_priv *priv = netdev_priv(dev); | |
1602 | ||
1603 | seq_printf(seq, "=======================\n"); | |
1604 | seq_printf(seq, " RX descriptor ring\n"); | |
1605 | seq_printf(seq, "=======================\n"); | |
1606 | ||
1607 | for (i = 0; i < priv->dma_rx_size; i++) { | |
1608 | struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); | |
1609 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1610 | i, (unsigned int)(x->a), | |
1611 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1612 | seq_printf(seq, "\n"); | |
1613 | } | |
1614 | ||
1615 | seq_printf(seq, "\n"); | |
1616 | seq_printf(seq, "=======================\n"); | |
1617 | seq_printf(seq, " TX descriptor ring\n"); | |
1618 | seq_printf(seq, "=======================\n"); | |
1619 | ||
1620 | for (i = 0; i < priv->dma_tx_size; i++) { | |
1621 | struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); | |
1622 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1623 | i, (unsigned int)(x->a), | |
1624 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1625 | seq_printf(seq, "\n"); | |
1626 | } | |
1627 | ||
1628 | return 0; | |
1629 | } | |
1630 | ||
1631 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
1632 | { | |
1633 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
1634 | } | |
1635 | ||
1636 | static const struct file_operations stmmac_rings_status_fops = { | |
1637 | .owner = THIS_MODULE, | |
1638 | .open = stmmac_sysfs_ring_open, | |
1639 | .read = seq_read, | |
1640 | .llseek = seq_lseek, | |
1641 | .release = seq_release, | |
1642 | }; | |
1643 | ||
e7434821 GC |
1644 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
1645 | { | |
1646 | struct net_device *dev = seq->private; | |
1647 | struct stmmac_priv *priv = netdev_priv(dev); | |
1648 | ||
19e30c14 | 1649 | if (!priv->hw_cap_support) { |
e7434821 GC |
1650 | seq_printf(seq, "DMA HW features not supported\n"); |
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | seq_printf(seq, "==============================\n"); | |
1655 | seq_printf(seq, "\tDMA HW features\n"); | |
1656 | seq_printf(seq, "==============================\n"); | |
1657 | ||
1658 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
1659 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
1660 | seq_printf(seq, "\t1000 Mbps %s\n", | |
1661 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
1662 | seq_printf(seq, "\tHalf duple %s\n", | |
1663 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
1664 | seq_printf(seq, "\tHash Filter: %s\n", | |
1665 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
1666 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
1667 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
1668 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
1669 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
1670 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
1671 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
1672 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
1673 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
1674 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
1675 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
1676 | seq_printf(seq, "\tRMON module: %s\n", | |
1677 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
1678 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
1679 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
1680 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
1681 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
1682 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
1683 | (priv->dma_cap.eee) ? "Y" : "N"); | |
1684 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
1685 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
1686 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
1687 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
1688 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
1689 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
1690 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
1691 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
1692 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
1693 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
1694 | priv->dma_cap.number_rx_channel); | |
1695 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
1696 | priv->dma_cap.number_tx_channel); | |
1697 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
1698 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
1699 | ||
1700 | return 0; | |
1701 | } | |
1702 | ||
1703 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
1704 | { | |
1705 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
1706 | } | |
1707 | ||
1708 | static const struct file_operations stmmac_dma_cap_fops = { | |
1709 | .owner = THIS_MODULE, | |
1710 | .open = stmmac_sysfs_dma_cap_open, | |
1711 | .read = seq_read, | |
1712 | .llseek = seq_lseek, | |
1713 | .release = seq_release, | |
1714 | }; | |
1715 | ||
7ac29055 GC |
1716 | static int stmmac_init_fs(struct net_device *dev) |
1717 | { | |
1718 | /* Create debugfs entries */ | |
1719 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
1720 | ||
1721 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
1722 | pr_err("ERROR %s, debugfs create directory failed\n", | |
1723 | STMMAC_RESOURCE_NAME); | |
1724 | ||
1725 | return -ENOMEM; | |
1726 | } | |
1727 | ||
1728 | /* Entry to report DMA RX/TX rings */ | |
1729 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
1730 | S_IRUGO, stmmac_fs_dir, dev, | |
1731 | &stmmac_rings_status_fops); | |
1732 | ||
1733 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
1734 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
1735 | debugfs_remove(stmmac_fs_dir); | |
1736 | ||
1737 | return -ENOMEM; | |
1738 | } | |
1739 | ||
e7434821 GC |
1740 | /* Entry to report the DMA HW features */ |
1741 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
1742 | dev, &stmmac_dma_cap_fops); | |
1743 | ||
1744 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
1745 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
1746 | debugfs_remove(stmmac_rings_status); | |
1747 | debugfs_remove(stmmac_fs_dir); | |
1748 | ||
1749 | return -ENOMEM; | |
1750 | } | |
1751 | ||
7ac29055 GC |
1752 | return 0; |
1753 | } | |
1754 | ||
1755 | static void stmmac_exit_fs(void) | |
1756 | { | |
1757 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 1758 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
1759 | debugfs_remove(stmmac_fs_dir); |
1760 | } | |
1761 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
1762 | ||
47dd7a54 GC |
1763 | static const struct net_device_ops stmmac_netdev_ops = { |
1764 | .ndo_open = stmmac_open, | |
1765 | .ndo_start_xmit = stmmac_xmit, | |
1766 | .ndo_stop = stmmac_release, | |
1767 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1768 | .ndo_fix_features = stmmac_fix_features, |
01789349 | 1769 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
1770 | .ndo_tx_timeout = stmmac_tx_timeout, |
1771 | .ndo_do_ioctl = stmmac_ioctl, | |
1772 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1773 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1774 | .ndo_poll_controller = stmmac_poll_controller, | |
1775 | #endif | |
1776 | .ndo_set_mac_address = eth_mac_addr, | |
1777 | }; | |
1778 | ||
cf3f047b GC |
1779 | /** |
1780 | * stmmac_hw_init - Init the MAC device | |
1781 | * @priv : pointer to the private device structure. | |
1782 | * Description: this function detects which MAC device | |
1783 | * (GMAC/MAC10-100) has to attached, checks the HW capability | |
1784 | * (if supported) and sets the driver's features (for example | |
1785 | * to use the ring or chaine mode or support the normal/enh | |
1786 | * descriptor structure). | |
1787 | */ | |
1788 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
1789 | { | |
1790 | int ret = 0; | |
1791 | struct mac_device_info *mac; | |
1792 | ||
1793 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
1794 | if (priv->plat->has_gmac) { |
1795 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
cf3f047b | 1796 | mac = dwmac1000_setup(priv->ioaddr); |
03f2eecd | 1797 | } else { |
cf3f047b | 1798 | mac = dwmac100_setup(priv->ioaddr); |
03f2eecd | 1799 | } |
cf3f047b GC |
1800 | if (!mac) |
1801 | return -ENOMEM; | |
1802 | ||
1803 | priv->hw = mac; | |
1804 | ||
1805 | /* To use the chained or ring mode */ | |
1806 | priv->hw->ring = &ring_mode_ops; | |
1807 | ||
1808 | /* Get and dump the chip ID */ | |
cffb13f4 | 1809 | priv->synopsys_id = stmmac_get_synopsys_id(priv); |
cf3f047b GC |
1810 | |
1811 | /* Get the HW capability (new GMAC newer than 3.50a) */ | |
1812 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
1813 | if (priv->hw_cap_support) { | |
1814 | pr_info(" DMA HW capability register supported"); | |
1815 | ||
1816 | /* We can override some gmac/dma configuration fields: e.g. | |
1817 | * enh_desc, tx_coe (e.g. that are passed through the | |
1818 | * platform) with the values from the HW capability | |
1819 | * register (if supported). | |
1820 | */ | |
1821 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 1822 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
38912bdb DS |
1823 | |
1824 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
1825 | ||
1826 | if (priv->dma_cap.rx_coe_type2) | |
1827 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
1828 | else if (priv->dma_cap.rx_coe_type1) | |
1829 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
1830 | ||
cf3f047b GC |
1831 | } else |
1832 | pr_info(" No HW DMA feature register supported"); | |
1833 | ||
1834 | /* Select the enhnaced/normal descriptor structures */ | |
1835 | stmmac_selec_desc_mode(priv); | |
1836 | ||
38912bdb DS |
1837 | /* Enable the IPC (Checksum Offload) and check if the feature has been |
1838 | * enabled during the core configuration. */ | |
1839 | ret = priv->hw->mac->rx_ipc(priv->ioaddr); | |
1840 | if (!ret) { | |
1841 | pr_warning(" RX IPC Checksum Offload not configured.\n"); | |
1842 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; | |
1843 | } | |
1844 | ||
1845 | if (priv->plat->rx_coe) | |
1846 | pr_info(" RX Checksum Offload Engine supported (type %d)\n", | |
1847 | priv->plat->rx_coe); | |
cf3f047b GC |
1848 | if (priv->plat->tx_coe) |
1849 | pr_info(" TX Checksum insertion supported\n"); | |
1850 | ||
1851 | if (priv->plat->pmt) { | |
1852 | pr_info(" Wake-Up On Lan supported\n"); | |
1853 | device_set_wakeup_capable(priv->device, 1); | |
1854 | } | |
1855 | ||
1856 | return ret; | |
1857 | } | |
1858 | ||
47dd7a54 | 1859 | /** |
bfab27a1 GC |
1860 | * stmmac_dvr_probe |
1861 | * @device: device pointer | |
1862 | * Description: this is the main probe function used to | |
1863 | * call the alloc_etherdev, allocate the priv structure. | |
47dd7a54 | 1864 | */ |
bfab27a1 | 1865 | struct stmmac_priv *stmmac_dvr_probe(struct device *device, |
cf3f047b GC |
1866 | struct plat_stmmacenet_data *plat_dat, |
1867 | void __iomem *addr) | |
47dd7a54 GC |
1868 | { |
1869 | int ret = 0; | |
bfab27a1 GC |
1870 | struct net_device *ndev = NULL; |
1871 | struct stmmac_priv *priv; | |
47dd7a54 | 1872 | |
bfab27a1 | 1873 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 1874 | if (!ndev) |
bfab27a1 | 1875 | return NULL; |
bfab27a1 GC |
1876 | |
1877 | SET_NETDEV_DEV(ndev, device); | |
1878 | ||
1879 | priv = netdev_priv(ndev); | |
1880 | priv->device = device; | |
1881 | priv->dev = ndev; | |
47dd7a54 | 1882 | |
bfab27a1 | 1883 | ether_setup(ndev); |
47dd7a54 | 1884 | |
bfab27a1 | 1885 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
1886 | priv->pause = pause; |
1887 | priv->plat = plat_dat; | |
1888 | priv->ioaddr = addr; | |
1889 | priv->dev->base_addr = (unsigned long)addr; | |
1890 | ||
1891 | /* Verify driver arguments */ | |
1892 | stmmac_verify_args(); | |
bfab27a1 | 1893 | |
cf3f047b GC |
1894 | /* Override with kernel parameters if supplied XXX CRS XXX |
1895 | * this needs to have multiple instances */ | |
1896 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
1897 | priv->plat->phy_addr = phyaddr; | |
1898 | ||
1899 | /* Init MAC and get the capabilities */ | |
1900 | stmmac_hw_init(priv); | |
1901 | ||
1902 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 1903 | |
cf3f047b GC |
1904 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1905 | NETIF_F_RXCSUM; | |
bfab27a1 GC |
1906 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
1907 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
1908 | #ifdef STMMAC_VLAN_TAG_USED |
1909 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
bfab27a1 | 1910 | ndev->features |= NETIF_F_HW_VLAN_RX; |
47dd7a54 GC |
1911 | #endif |
1912 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1913 | ||
47dd7a54 GC |
1914 | if (flow_ctrl) |
1915 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1916 | ||
bfab27a1 | 1917 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 1918 | |
f8e96161 | 1919 | spin_lock_init(&priv->lock); |
a9097a96 | 1920 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 1921 | |
bfab27a1 | 1922 | ret = register_netdev(ndev); |
47dd7a54 | 1923 | if (ret) { |
cf3f047b | 1924 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
bfab27a1 | 1925 | goto error; |
47dd7a54 GC |
1926 | } |
1927 | ||
ba1377ff | 1928 | if (stmmac_clk_get(priv)) |
31ea38ee | 1929 | pr_warning("%s: warning: cannot get CSR clock\n", __func__); |
ba1377ff | 1930 | |
cd7201f4 GC |
1931 | /* If a specific clk_csr value is passed from the platform |
1932 | * this means that the CSR Clock Range selection cannot be | |
1933 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
1934 | * set the MDC clock dynamically according to the csr actual | |
1935 | * clock input. | |
1936 | */ | |
1937 | if (!priv->plat->clk_csr) | |
1938 | stmmac_clk_csr_set(priv); | |
1939 | else | |
1940 | priv->clk_csr = priv->plat->clk_csr; | |
1941 | ||
4bfcbd7a FV |
1942 | /* MDIO bus Registration */ |
1943 | ret = stmmac_mdio_register(ndev); | |
1944 | if (ret < 0) { | |
1945 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
1946 | __func__, priv->plat->bus_id); | |
1947 | goto error; | |
1948 | } | |
1949 | ||
bfab27a1 | 1950 | return priv; |
47dd7a54 | 1951 | |
bfab27a1 GC |
1952 | error: |
1953 | netif_napi_del(&priv->napi); | |
47dd7a54 | 1954 | |
34a52f36 | 1955 | unregister_netdev(ndev); |
34a52f36 | 1956 | free_netdev(ndev); |
47dd7a54 | 1957 | |
bfab27a1 | 1958 | return NULL; |
47dd7a54 GC |
1959 | } |
1960 | ||
1961 | /** | |
1962 | * stmmac_dvr_remove | |
bfab27a1 | 1963 | * @ndev: net device pointer |
47dd7a54 | 1964 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 1965 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 1966 | */ |
bfab27a1 | 1967 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 1968 | { |
aec7ff27 | 1969 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1970 | |
1971 | pr_info("%s:\n\tremoving driver", __func__); | |
1972 | ||
ad01b7d4 GC |
1973 | priv->hw->dma->stop_rx(priv->ioaddr); |
1974 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1975 | |
bfab27a1 | 1976 | stmmac_set_mac(priv->ioaddr, false); |
4bfcbd7a | 1977 | stmmac_mdio_unregister(ndev); |
47dd7a54 | 1978 | netif_carrier_off(ndev); |
47dd7a54 | 1979 | unregister_netdev(ndev); |
47dd7a54 GC |
1980 | free_netdev(ndev); |
1981 | ||
1982 | return 0; | |
1983 | } | |
1984 | ||
1985 | #ifdef CONFIG_PM | |
bfab27a1 | 1986 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 1987 | { |
874bd42d | 1988 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1989 | int dis_ic = 0; |
1990 | ||
874bd42d | 1991 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
1992 | return 0; |
1993 | ||
102463b1 FV |
1994 | if (priv->phydev) |
1995 | phy_stop(priv->phydev); | |
1996 | ||
47dd7a54 GC |
1997 | spin_lock(&priv->lock); |
1998 | ||
874bd42d GC |
1999 | netif_device_detach(ndev); |
2000 | netif_stop_queue(ndev); | |
47dd7a54 GC |
2001 | |
2002 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2003 | priv->tm->timer_stop(); |
2004 | if (likely(priv->tm->enable)) | |
2005 | dis_ic = 1; | |
47dd7a54 | 2006 | #endif |
874bd42d GC |
2007 | napi_disable(&priv->napi); |
2008 | ||
2009 | /* Stop TX/RX DMA */ | |
2010 | priv->hw->dma->stop_tx(priv->ioaddr); | |
2011 | priv->hw->dma->stop_rx(priv->ioaddr); | |
2012 | /* Clear the Rx/Tx descriptors */ | |
2013 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
2014 | dis_ic); | |
2015 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
2016 | ||
2017 | /* Enable Power down mode by programming the PMT regs */ | |
2018 | if (device_may_wakeup(priv->device)) | |
2019 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
ba1377ff | 2020 | else { |
bfab27a1 | 2021 | stmmac_set_mac(priv->ioaddr, false); |
ba1377ff GC |
2022 | /* Disable clock in case of PWM is off */ |
2023 | stmmac_clk_disable(priv); | |
2024 | } | |
47dd7a54 GC |
2025 | spin_unlock(&priv->lock); |
2026 | return 0; | |
2027 | } | |
2028 | ||
bfab27a1 | 2029 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 2030 | { |
874bd42d | 2031 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 | 2032 | |
874bd42d | 2033 | if (!netif_running(ndev)) |
47dd7a54 GC |
2034 | return 0; |
2035 | ||
c4433be6 GC |
2036 | spin_lock(&priv->lock); |
2037 | ||
47dd7a54 GC |
2038 | /* Power Down bit, into the PM register, is cleared |
2039 | * automatically as soon as a magic packet or a Wake-up frame | |
2040 | * is received. Anyway, it's better to manually clear | |
2041 | * this bit because it can generate problems while resuming | |
2042 | * from another devices (e.g. serial console). */ | |
874bd42d | 2043 | if (device_may_wakeup(priv->device)) |
543876c9 | 2044 | priv->hw->mac->pmt(priv->ioaddr, 0); |
ba1377ff GC |
2045 | else |
2046 | /* enable the clk prevously disabled */ | |
2047 | stmmac_clk_enable(priv); | |
47dd7a54 | 2048 | |
874bd42d | 2049 | netif_device_attach(ndev); |
47dd7a54 GC |
2050 | |
2051 | /* Enable the MAC and DMA */ | |
bfab27a1 | 2052 | stmmac_set_mac(priv->ioaddr, true); |
ad01b7d4 GC |
2053 | priv->hw->dma->start_tx(priv->ioaddr); |
2054 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
2055 | |
2056 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2057 | if (likely(priv->tm->enable)) |
2058 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
2059 | #endif |
2060 | napi_enable(&priv->napi); | |
2061 | ||
874bd42d | 2062 | netif_start_queue(ndev); |
47dd7a54 | 2063 | |
47dd7a54 | 2064 | spin_unlock(&priv->lock); |
102463b1 FV |
2065 | |
2066 | if (priv->phydev) | |
2067 | phy_start(priv->phydev); | |
2068 | ||
47dd7a54 GC |
2069 | return 0; |
2070 | } | |
47dd7a54 | 2071 | |
bfab27a1 | 2072 | int stmmac_freeze(struct net_device *ndev) |
874bd42d | 2073 | { |
874bd42d GC |
2074 | if (!ndev || !netif_running(ndev)) |
2075 | return 0; | |
2076 | ||
2077 | return stmmac_release(ndev); | |
2078 | } | |
2079 | ||
bfab27a1 | 2080 | int stmmac_restore(struct net_device *ndev) |
874bd42d | 2081 | { |
874bd42d GC |
2082 | if (!ndev || !netif_running(ndev)) |
2083 | return 0; | |
2084 | ||
2085 | return stmmac_open(ndev); | |
2086 | } | |
874bd42d | 2087 | #endif /* CONFIG_PM */ |
47dd7a54 | 2088 | |
47dd7a54 GC |
2089 | #ifndef MODULE |
2090 | static int __init stmmac_cmdline_opt(char *str) | |
2091 | { | |
2092 | char *opt; | |
2093 | ||
2094 | if (!str || !*str) | |
2095 | return -EINVAL; | |
2096 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 GC |
2097 | if (!strncmp(opt, "debug:", 6)) { |
2098 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) | |
2099 | goto err; | |
2100 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
2101 | if (strict_strtoul(opt + 8, 0, | |
2102 | (unsigned long *)&phyaddr)) | |
2103 | goto err; | |
2104 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
2105 | if (strict_strtoul(opt + 11, 0, | |
2106 | (unsigned long *)&dma_txsize)) | |
2107 | goto err; | |
2108 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
2109 | if (strict_strtoul(opt + 11, 0, | |
2110 | (unsigned long *)&dma_rxsize)) | |
2111 | goto err; | |
2112 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
2113 | if (strict_strtoul(opt + 7, 0, | |
2114 | (unsigned long *)&buf_sz)) | |
2115 | goto err; | |
2116 | } else if (!strncmp(opt, "tc:", 3)) { | |
2117 | if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) | |
2118 | goto err; | |
2119 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
2120 | if (strict_strtoul(opt + 9, 0, | |
2121 | (unsigned long *)&watchdog)) | |
2122 | goto err; | |
2123 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
2124 | if (strict_strtoul(opt + 10, 0, | |
2125 | (unsigned long *)&flow_ctrl)) | |
2126 | goto err; | |
2127 | } else if (!strncmp(opt, "pause:", 6)) { | |
2128 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) | |
2129 | goto err; | |
47dd7a54 | 2130 | #ifdef CONFIG_STMMAC_TIMER |
f3240e28 GC |
2131 | } else if (!strncmp(opt, "tmrate:", 7)) { |
2132 | if (strict_strtoul(opt + 7, 0, | |
2133 | (unsigned long *)&tmrate)) | |
2134 | goto err; | |
47dd7a54 | 2135 | #endif |
f3240e28 | 2136 | } |
47dd7a54 GC |
2137 | } |
2138 | return 0; | |
f3240e28 GC |
2139 | |
2140 | err: | |
2141 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
2142 | return -EINVAL; | |
47dd7a54 GC |
2143 | } |
2144 | ||
2145 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
2146 | #endif | |
6fc0d0f2 GC |
2147 | |
2148 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); | |
2149 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
2150 | MODULE_LICENSE("GPL"); |