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Merge branch 'linus' into timers/core
[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
6a81c26f 31#include <linux/clk.h>
47dd7a54
GC		 32#include <linux/kernel.h>
33#include <linux/interrupt.h>
47dd7a54
GC		 34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/skbuff.h>
37#include <linux/ethtool.h>
38#include <linux/if_ether.h>
39#include <linux/crc32.h>
40#include <linux/mii.h>
01789349 41#include <linux/if.h>
47dd7a54
GC		 42#include <linux/if_vlan.h>
43#include <linux/dma-mapping.h>
5a0e3ad6 44#include <linux/slab.h>
70c71606 45#include <linux/prefetch.h>
7ac29055
GC		 46#ifdef CONFIG_STMMAC_DEBUG_FS
47#include <linux/debugfs.h>
48#include <linux/seq_file.h>
ceb69499 49#endif /* CONFIG_STMMAC_DEBUG_FS */
891434b1
RK		 50#include <linux/net_tstamp.h>
51#include "stmmac_ptp.h"
286a8372 52#include "stmmac.h"
47dd7a54 53
47dd7a54
GC		 54#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
55#define JUMBO_LEN 9000
56
57/* Module parameters */
32ceabca 58#define TX_TIMEO 5000
47dd7a54
GC		 59static int watchdog = TX_TIMEO;
60module_param(watchdog, int, S_IRUGO | S_IWUSR);
32ceabca 61MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
47dd7a54 62
32ceabca 63static int debug = -1;
47dd7a54 64module_param(debug, int, S_IRUGO | S_IWUSR);
32ceabca 65MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
47dd7a54 66
bfab27a1 67int phyaddr = -1;
47dd7a54
GC		 68module_param(phyaddr, int, S_IRUGO);
69MODULE_PARM_DESC(phyaddr, "Physical device address");
70
71#define DMA_TX_SIZE 256
72static int dma_txsize = DMA_TX_SIZE;
73module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
74MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
75
76#define DMA_RX_SIZE 256
77static int dma_rxsize = DMA_RX_SIZE;
78module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
79MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
80
81static int flow_ctrl = FLOW_OFF;
82module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
83MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
84
85static int pause = PAUSE_TIME;
86module_param(pause, int, S_IRUGO | S_IWUSR);
87MODULE_PARM_DESC(pause, "Flow Control Pause Time");
88
89#define TC_DEFAULT 64
90static int tc = TC_DEFAULT;
91module_param(tc, int, S_IRUGO | S_IWUSR);
92MODULE_PARM_DESC(tc, "DMA threshold control value");
93
47dd7a54
GC		 94#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
95static int buf_sz = DMA_BUFFER_SIZE;
96module_param(buf_sz, int, S_IRUGO | S_IWUSR);
97MODULE_PARM_DESC(buf_sz, "DMA buffer size");
98
47dd7a54
GC		 99static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
100 NETIF_MSG_LINK | NETIF_MSG_IFUP |
101 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
102
d765955d
GC		 103#define STMMAC_DEFAULT_LPI_TIMER 1000
104static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
105module_param(eee_timer, int, S_IRUGO | S_IWUSR);
106MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
f5351ef7 107#define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
d765955d 108
4a7d666a
GC		 109/* By default the driver will use the ring mode to manage tx and rx descriptors
110 * but passing this value so user can force to use the chain instead of the ring
111 */
112static unsigned int chain_mode;
113module_param(chain_mode, int, S_IRUGO);
114MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
115
47dd7a54 116static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54 117
bfab27a1
GC		 118#ifdef CONFIG_STMMAC_DEBUG_FS
119static int stmmac_init_fs(struct net_device *dev);
120static void stmmac_exit_fs(void);
121#endif
122
9125cdd1
GC		 123#define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
124
47dd7a54
GC		 125/**
126 * stmmac_verify_args - verify the driver parameters.
127 * Description: it verifies if some wrong parameter is passed to the driver.
128 * Note that wrong parameters are replaced with the default values.
129 */
130static void stmmac_verify_args(void)
131{
132 if (unlikely(watchdog < 0))
133 watchdog = TX_TIMEO;
134 if (unlikely(dma_rxsize < 0))
135 dma_rxsize = DMA_RX_SIZE;
136 if (unlikely(dma_txsize < 0))
137 dma_txsize = DMA_TX_SIZE;
138 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
139 buf_sz = DMA_BUFFER_SIZE;
140 if (unlikely(flow_ctrl > 1))
141 flow_ctrl = FLOW_AUTO;
142 else if (likely(flow_ctrl < 0))
143 flow_ctrl = FLOW_OFF;
144 if (unlikely((pause < 0) || (pause > 0xffff)))
145 pause = PAUSE_TIME;
d765955d
GC		 146 if (eee_timer < 0)
147 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
47dd7a54
GC		 148}
149
32ceabca
GC		 150/**
151 * stmmac_clk_csr_set - dynamically set the MDC clock
152 * @priv: driver private structure
153 * Description: this is to dynamically set the MDC clock according to the csr
154 * clock input.
155 * Note:
156 * If a specific clk_csr value is passed from the platform
157 * this means that the CSR Clock Range selection cannot be
158 * changed at run-time and it is fixed (as reported in the driver
159 * documentation). Viceversa the driver will try to set the MDC
160 * clock dynamically according to the actual clock input.
161 */
cd7201f4
GC		 162static void stmmac_clk_csr_set(struct stmmac_priv *priv)
163{
cd7201f4
GC		 164 u32 clk_rate;
165
166 clk_rate = clk_get_rate(priv->stmmac_clk);
167
168 /* Platform provided default clk_csr would be assumed valid
ceb69499
GC		 169 * for all other cases except for the below mentioned ones.
170 * For values higher than the IEEE 802.3 specified frequency
171 * we can not estimate the proper divider as it is not known
172 * the frequency of clk_csr_i. So we do not change the default
173 * divider.
174 */
cd7201f4
GC		 175 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
176 if (clk_rate < CSR_F_35M)
177 priv->clk_csr = STMMAC_CSR_20_35M;
178 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
179 priv->clk_csr = STMMAC_CSR_35_60M;
180 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
181 priv->clk_csr = STMMAC_CSR_60_100M;
182 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
183 priv->clk_csr = STMMAC_CSR_100_150M;
184 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
185 priv->clk_csr = STMMAC_CSR_150_250M;
186 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
187 priv->clk_csr = STMMAC_CSR_250_300M;
ceb69499 188 }
cd7201f4
GC		 189}
190
47dd7a54
GC		 191static void print_pkt(unsigned char *buf, int len)
192{
193 int j;
83d7af64 194 pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
47dd7a54
GC		 195 for (j = 0; j < len; j++) {
196 if ((j % 16) == 0)
83d7af64
GC		 197 pr_debug("\n %03x:", j);
198 pr_debug(" %02x", buf[j]);
47dd7a54 199 }
83d7af64 200 pr_debug("\n");
47dd7a54 201}
47dd7a54
GC		 202
203/* minimum number of free TX descriptors required to wake up TX process */
204#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
205
206static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
207{
208 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
209}
210
32ceabca
GC		 211/**
212 * stmmac_hw_fix_mac_speed: callback for speed selection
213 * @priv: driver private structure
214 * Description: on some platforms (e.g. ST), some HW system configuraton
215 * registers have to be set according to the link speed negotiated.
9dfeb4d9
GC		 216 */
217static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
218{
219 struct phy_device *phydev = priv->phydev;
220
221 if (likely(priv->plat->fix_mac_speed))
ceb69499 222 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
9dfeb4d9
GC		 223}
224
32ceabca
GC		 225/**
226 * stmmac_enable_eee_mode: Check and enter in LPI mode
227 * @priv: driver private structure
228 * Description: this function is to verify and enter in LPI mode for EEE.
229 */
d765955d
GC		 230static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
231{
232 /* Check and enter in LPI mode */
233 if ((priv->dirty_tx == priv->cur_tx) &&
234 (priv->tx_path_in_lpi_mode == false))
235 priv->hw->mac->set_eee_mode(priv->ioaddr);
236}
237
32ceabca
GC		 238/**
239 * stmmac_disable_eee_mode: disable/exit from EEE
240 * @priv: driver private structure
241 * Description: this function is to exit and disable EEE in case of
242 * LPI state is true. This is called by the xmit.
243 */
d765955d
GC		 244void stmmac_disable_eee_mode(struct stmmac_priv *priv)
245{
d765955d
GC		 246 priv->hw->mac->reset_eee_mode(priv->ioaddr);
247 del_timer_sync(&priv->eee_ctrl_timer);
248 priv->tx_path_in_lpi_mode = false;
249}
250
251/**
32ceabca 252 * stmmac_eee_ctrl_timer: EEE TX SW timer.
d765955d
GC		 253 * @arg : data hook
254 * Description:
32ceabca 255 * if there is no data transfer and if we are not in LPI state,
d765955d
GC		 256 * then MAC Transmitter can be moved to LPI state.
257 */
258static void stmmac_eee_ctrl_timer(unsigned long arg)
259{
260 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
261
262 stmmac_enable_eee_mode(priv);
f5351ef7 263 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
d765955d
GC		 264}
265
266/**
32ceabca
GC		 267 * stmmac_eee_init: init EEE
268 * @priv: driver private structure
d765955d
GC		 269 * Description:
270 * If the EEE support has been enabled while configuring the driver,
271 * if the GMAC actually supports the EEE (from the HW cap reg) and the
272 * phy can also manage EEE, so enable the LPI state and start the timer
273 * to verify if the tx path can enter in LPI state.
274 */
275bool stmmac_eee_init(struct stmmac_priv *priv)
276{
277 bool ret = false;
278
f5351ef7
GC		 279 /* Using PCS we cannot dial with the phy registers at this stage
280 * so we do not support extra feature like EEE.
281 */
282 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
283 (priv->pcs == STMMAC_PCS_RTBI))
284 goto out;
285
d765955d
GC		 286 /* MAC core supports the EEE feature. */
287 if (priv->dma_cap.eee) {
288 /* Check if the PHY supports EEE */
289 if (phy_init_eee(priv->phydev, 1))
290 goto out;
291
f5351ef7
GC		 292 if (!priv->eee_active) {
293 priv->eee_active = 1;
294 init_timer(&priv->eee_ctrl_timer);
295 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
296 priv->eee_ctrl_timer.data = (unsigned long)priv;
297 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
298 add_timer(&priv->eee_ctrl_timer);
299
300 priv->hw->mac->set_eee_timer(priv->ioaddr,
301 STMMAC_DEFAULT_LIT_LS,
302 priv->tx_lpi_timer);
303 } else
304 /* Set HW EEE according to the speed */
305 priv->hw->mac->set_eee_pls(priv->ioaddr,
306 priv->phydev->link);
d765955d
GC		 307
308 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
309
310 ret = true;
311 }
312out:
313 return ret;
314}
315
32ceabca
GC		 316/* stmmac_get_tx_hwtstamp: get HW TX timestamps
317 * @priv: driver private structure
891434b1
RK		 318 * @entry : descriptor index to be used.
319 * @skb : the socket buffer
320 * Description :
321 * This function will read timestamp from the descriptor & pass it to stack.
322 * and also perform some sanity checks.
323 */
324static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
ceb69499 325 unsigned int entry, struct sk_buff *skb)
891434b1
RK		 326{
327 struct skb_shared_hwtstamps shhwtstamp;
328 u64 ns;
329 void *desc = NULL;
330
331 if (!priv->hwts_tx_en)
332 return;
333
ceb69499 334 /* exit if skb doesn't support hw tstamp */
891434b1
RK		 335 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
336 return;
337
338 if (priv->adv_ts)
339 desc = (priv->dma_etx + entry);
340 else
341 desc = (priv->dma_tx + entry);
342
343 /* check tx tstamp status */
344 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
345 return;
346
347 /* get the valid tstamp */
348 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
349
350 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
351 shhwtstamp.hwtstamp = ns_to_ktime(ns);
352 /* pass tstamp to stack */
353 skb_tstamp_tx(skb, &shhwtstamp);
354
355 return;
356}
357
32ceabca
GC		 358/* stmmac_get_rx_hwtstamp: get HW RX timestamps
359 * @priv: driver private structure
891434b1
RK		 360 * @entry : descriptor index to be used.
361 * @skb : the socket buffer
362 * Description :
363 * This function will read received packet's timestamp from the descriptor
364 * and pass it to stack. It also perform some sanity checks.
365 */
366static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
ceb69499 367 unsigned int entry, struct sk_buff *skb)
891434b1
RK		 368{
369 struct skb_shared_hwtstamps *shhwtstamp = NULL;
370 u64 ns;
371 void *desc = NULL;
372
373 if (!priv->hwts_rx_en)
374 return;
375
376 if (priv->adv_ts)
377 desc = (priv->dma_erx + entry);
378 else
379 desc = (priv->dma_rx + entry);
380
ceb69499 381 /* exit if rx tstamp is not valid */
891434b1
RK		 382 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
383 return;
384
385 /* get valid tstamp */
386 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
387 shhwtstamp = skb_hwtstamps(skb);
388 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
389 shhwtstamp->hwtstamp = ns_to_ktime(ns);
390}
391
392/**
393 * stmmac_hwtstamp_ioctl - control hardware timestamping.
394 * @dev: device pointer.
395 * @ifr: An IOCTL specefic structure, that can contain a pointer to
396 * a proprietary structure used to pass information to the driver.
397 * Description:
398 * This function configures the MAC to enable/disable both outgoing(TX)
399 * and incoming(RX) packets time stamping based on user input.
400 * Return Value:
401 * 0 on success and an appropriate -ve integer on failure.
402 */
403static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
404{
405 struct stmmac_priv *priv = netdev_priv(dev);
406 struct hwtstamp_config config;
407 struct timespec now;
408 u64 temp = 0;
409 u32 ptp_v2 = 0;
410 u32 tstamp_all = 0;
411 u32 ptp_over_ipv4_udp = 0;
412 u32 ptp_over_ipv6_udp = 0;
413 u32 ptp_over_ethernet = 0;
414 u32 snap_type_sel = 0;
415 u32 ts_master_en = 0;
416 u32 ts_event_en = 0;
417 u32 value = 0;
418
419 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
420 netdev_alert(priv->dev, "No support for HW time stamping\n");
421 priv->hwts_tx_en = 0;
422 priv->hwts_rx_en = 0;
423
424 return -EOPNOTSUPP;
425 }
426
427 if (copy_from_user(&config, ifr->ifr_data,
ceb69499 428 sizeof(struct hwtstamp_config)))
891434b1
RK		 429 return -EFAULT;
430
431 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
432 __func__, config.flags, config.tx_type, config.rx_filter);
433
434 /* reserved for future extensions */
435 if (config.flags)
436 return -EINVAL;
437
438 switch (config.tx_type) {
439 case HWTSTAMP_TX_OFF:
440 priv->hwts_tx_en = 0;
441 break;
442 case HWTSTAMP_TX_ON:
443 priv->hwts_tx_en = 1;
444 break;
445 default:
446 return -ERANGE;
447 }
448
449 if (priv->adv_ts) {
450 switch (config.rx_filter) {
891434b1 451 case HWTSTAMP_FILTER_NONE:
ceb69499 452 /* time stamp no incoming packet at all */
891434b1
RK		 453 config.rx_filter = HWTSTAMP_FILTER_NONE;
454 break;
455
891434b1 456 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
ceb69499 457 /* PTP v1, UDP, any kind of event packet */
891434b1
RK		 458 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
459 /* take time stamp for all event messages */
460 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
461
462 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
463 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
464 break;
465
891434b1 466 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
ceb69499 467 /* PTP v1, UDP, Sync packet */
891434b1
RK		 468 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
469 /* take time stamp for SYNC messages only */
470 ts_event_en = PTP_TCR_TSEVNTENA;
471
472 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
473 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
474 break;
475
891434b1 476 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
ceb69499 477 /* PTP v1, UDP, Delay_req packet */
891434b1
RK		 478 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
479 /* take time stamp for Delay_Req messages only */
480 ts_master_en = PTP_TCR_TSMSTRENA;
481 ts_event_en = PTP_TCR_TSEVNTENA;
482
483 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
484 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
485 break;
486
891434b1 487 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
ceb69499 488 /* PTP v2, UDP, any kind of event packet */
891434b1
RK		 489 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
490 ptp_v2 = PTP_TCR_TSVER2ENA;
491 /* take time stamp for all event messages */
492 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
493
494 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
495 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
496 break;
497
891434b1 498 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
ceb69499 499 /* PTP v2, UDP, Sync packet */
891434b1
RK		 500 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
501 ptp_v2 = PTP_TCR_TSVER2ENA;
502 /* take time stamp for SYNC messages only */
503 ts_event_en = PTP_TCR_TSEVNTENA;
504
505 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
506 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
507 break;
508
891434b1 509 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
ceb69499 510 /* PTP v2, UDP, Delay_req packet */
891434b1
RK		 511 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
512 ptp_v2 = PTP_TCR_TSVER2ENA;
513 /* take time stamp for Delay_Req messages only */
514 ts_master_en = PTP_TCR_TSMSTRENA;
515 ts_event_en = PTP_TCR_TSEVNTENA;
516
517 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
518 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
519 break;
520
891434b1 521 case HWTSTAMP_FILTER_PTP_V2_EVENT:
ceb69499 522 /* PTP v2/802.AS1 any layer, any kind of event packet */
891434b1
RK		 523 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
524 ptp_v2 = PTP_TCR_TSVER2ENA;
525 /* take time stamp for all event messages */
526 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
527
528 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
529 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
530 ptp_over_ethernet = PTP_TCR_TSIPENA;
531 break;
532
891434b1 533 case HWTSTAMP_FILTER_PTP_V2_SYNC:
ceb69499 534 /* PTP v2/802.AS1, any layer, Sync packet */
891434b1
RK		 535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
536 ptp_v2 = PTP_TCR_TSVER2ENA;
537 /* take time stamp for SYNC messages only */
538 ts_event_en = PTP_TCR_TSEVNTENA;
539
540 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
541 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
542 ptp_over_ethernet = PTP_TCR_TSIPENA;
543 break;
544
891434b1 545 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
ceb69499 546 /* PTP v2/802.AS1, any layer, Delay_req packet */
891434b1
RK		 547 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
548 ptp_v2 = PTP_TCR_TSVER2ENA;
549 /* take time stamp for Delay_Req messages only */
550 ts_master_en = PTP_TCR_TSMSTRENA;
551 ts_event_en = PTP_TCR_TSEVNTENA;
552
553 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
554 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
555 ptp_over_ethernet = PTP_TCR_TSIPENA;
556 break;
557
891434b1 558 case HWTSTAMP_FILTER_ALL:
ceb69499 559 /* time stamp any incoming packet */
891434b1
RK		 560 config.rx_filter = HWTSTAMP_FILTER_ALL;
561 tstamp_all = PTP_TCR_TSENALL;
562 break;
563
564 default:
565 return -ERANGE;
566 }
567 } else {
568 switch (config.rx_filter) {
569 case HWTSTAMP_FILTER_NONE:
570 config.rx_filter = HWTSTAMP_FILTER_NONE;
571 break;
572 default:
573 /* PTP v1, UDP, any kind of event packet */
574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
575 break;
576 }
577 }
578 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
579
580 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
581 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
582 else {
583 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
ceb69499
GC		 584 tstamp_all | ptp_v2 | ptp_over_ethernet |
585 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
586 ts_master_en | snap_type_sel);
891434b1
RK		 587
588 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
589
590 /* program Sub Second Increment reg */
591 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
592
593 /* calculate default added value:
594 * formula is :
595 * addend = (2^32)/freq_div_ratio;
596 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
597 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
598 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
599 * achive 20ns accuracy.
600 *
601 * 2^x * y == (y << x), hence
602 * 2^32 * 50000000 ==> (50000000 << 32)
603 */
ceb69499 604 temp = (u64) (50000000ULL << 32);
891434b1
RK		 605 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
606 priv->hw->ptp->config_addend(priv->ioaddr,
607 priv->default_addend);
608
609 /* initialize system time */
610 getnstimeofday(&now);
611 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
612 now.tv_nsec);
613 }
614
615 return copy_to_user(ifr->ifr_data, &config,
616 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
617}
618
32ceabca
GC		 619/**
620 * stmmac_init_ptp: init PTP
621 * @priv: driver private structure
622 * Description: this is to verify if the HW supports the PTPv1 or v2.
623 * This is done by looking at the HW cap. register.
624 * Also it registers the ptp driver.
625 */
92ba6888 626static int stmmac_init_ptp(struct stmmac_priv *priv)
891434b1 627{
92ba6888
RK		 628 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
629 return -EOPNOTSUPP;
630
631 if (netif_msg_hw(priv)) {
632 if (priv->dma_cap.time_stamp) {
633 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
634 priv->adv_ts = 0;
635 }
636 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
ceb69499
GC		 637 pr_debug
638 ("IEEE 1588-2008 Advanced Time Stamp supported\n");
92ba6888
RK		 639 priv->adv_ts = 1;
640 }
891434b1
RK		 641 }
642
643 priv->hw->ptp = &stmmac_ptp;
644 priv->hwts_tx_en = 0;
645 priv->hwts_rx_en = 0;
92ba6888
RK		 646
647 return stmmac_ptp_register(priv);
648}
649
650static void stmmac_release_ptp(struct stmmac_priv *priv)
651{
652 stmmac_ptp_unregister(priv);
891434b1
RK		 653}
654
47dd7a54
GC		 655/**
656 * stmmac_adjust_link
657 * @dev: net device structure
658 * Description: it adjusts the link parameters.
659 */
660static void stmmac_adjust_link(struct net_device *dev)
661{
662 struct stmmac_priv *priv = netdev_priv(dev);
663 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 664 unsigned long flags;
665 int new_state = 0;
666 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
667
668 if (phydev == NULL)
669 return;
670
47dd7a54 671 spin_lock_irqsave(&priv->lock, flags);
d765955d 672
47dd7a54 673 if (phydev->link) {
ad01b7d4 674 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 675
676 /* Now we make sure that we can be in full duplex mode.
677 * If not, we operate in half-duplex mode. */
678 if (phydev->duplex != priv->oldduplex) {
679 new_state = 1;
680 if (!(phydev->duplex))
db98a0b0 681 ctrl &= ~priv->hw->link.duplex;
47dd7a54 682 else
db98a0b0 683 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 684 priv->oldduplex = phydev->duplex;
685 }
686 /* Flow Control operation */
687 if (phydev->pause)
ad01b7d4 688 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 689 fc, pause_time);
47dd7a54
GC		 690
691 if (phydev->speed != priv->speed) {
692 new_state = 1;
693 switch (phydev->speed) {
694 case 1000:
9dfeb4d9 695 if (likely(priv->plat->has_gmac))
db98a0b0 696 ctrl &= ~priv->hw->link.port;
ceb69499 697 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 698 break;
699 case 100:
700 case 10:
9dfeb4d9 701 if (priv->plat->has_gmac) {
db98a0b0 702 ctrl |= priv->hw->link.port;
47dd7a54 703 if (phydev->speed == SPEED_100) {
db98a0b0 704 ctrl |= priv->hw->link.speed;
47dd7a54 705 } else {
db98a0b0 706 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 707 }
708 } else {
db98a0b0 709 ctrl &= ~priv->hw->link.port;
47dd7a54 710 }
9dfeb4d9 711 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 712 break;
713 default:
714 if (netif_msg_link(priv))
ceb69499
GC		 715 pr_warn("%s: Speed (%d) not 10/100\n",
716 dev->name, phydev->speed);
47dd7a54
GC		 717 break;
718 }
719
720 priv->speed = phydev->speed;
721 }
722
ad01b7d4 723 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 724
725 if (!priv->oldlink) {
726 new_state = 1;
727 priv->oldlink = 1;
728 }
729 } else if (priv->oldlink) {
730 new_state = 1;
731 priv->oldlink = 0;
732 priv->speed = 0;
733 priv->oldduplex = -1;
734 }
735
736 if (new_state && netif_msg_link(priv))
737 phy_print_status(phydev);
738
f5351ef7
GC		 739 /* At this stage, it could be needed to setup the EEE or adjust some
740 * MAC related HW registers.
741 */
742 priv->eee_enabled = stmmac_eee_init(priv);
d765955d 743
47dd7a54 744 spin_unlock_irqrestore(&priv->lock, flags);
47dd7a54
GC		 745}
746
32ceabca
GC		 747/**
748 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
749 * @priv: driver private structure
750 * Description: this is to verify if the HW supports the PCS.
751 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
752 * configured for the TBI, RTBI, or SGMII PHY interface.
753 */
e58bb43f
GC		 754static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
755{
756 int interface = priv->plat->interface;
757
758 if (priv->dma_cap.pcs) {
0d909dcd
BA		 759 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
760 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
761 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
762 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
e58bb43f
GC		 763 pr_debug("STMMAC: PCS RGMII support enable\n");
764 priv->pcs = STMMAC_PCS_RGMII;
0d909dcd 765 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
e58bb43f
GC		 766 pr_debug("STMMAC: PCS SGMII support enable\n");
767 priv->pcs = STMMAC_PCS_SGMII;
768 }
769 }
770}
771
47dd7a54
GC		 772/**
773 * stmmac_init_phy - PHY initialization
774 * @dev: net device structure
775 * Description: it initializes the driver's PHY state, and attaches the PHY
776 * to the mac driver.
777 * Return value:
778 * 0 on success
779 */
780static int stmmac_init_phy(struct net_device *dev)
781{
782 struct stmmac_priv *priv = netdev_priv(dev);
783 struct phy_device *phydev;
d765955d 784 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
109cdd66 785 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 786 int interface = priv->plat->interface;
47dd7a54
GC		 787 priv->oldlink = 0;
788 priv->speed = 0;
789 priv->oldduplex = -1;
790
f142af2e
SK		 791 if (priv->plat->phy_bus_name)
792 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
ceb69499 793 priv->plat->phy_bus_name, priv->plat->bus_id);
f142af2e
SK		 794 else
795 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
ceb69499 796 priv->plat->bus_id);
f142af2e 797
d765955d 798 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 799 priv->plat->phy_addr);
d765955d 800 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
47dd7a54 801
f9a8f83b 802 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
47dd7a54
GC		 803
804 if (IS_ERR(phydev)) {
805 pr_err("%s: Could not attach to PHY\n", dev->name);
806 return PTR_ERR(phydev);
807 }
808
79ee1dc3 809 /* Stop Advertising 1000BASE Capability if interface is not GMII */
c5b9b4e4
SK		 810 if ((interface == PHY_INTERFACE_MODE_MII) ||
811 (interface == PHY_INTERFACE_MODE_RMII))
812 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
813 SUPPORTED_1000baseT_Full);
79ee1dc3 814
47dd7a54
GC		 815 /*
816 * Broken HW is sometimes missing the pull-up resistor on the
817 * MDIO line, which results in reads to non-existent devices returning
818 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
819 * device as well.
820 * Note: phydev->phy_id is the result of reading the UID PHY registers.
821 */
822 if (phydev->phy_id == 0) {
823 phy_disconnect(phydev);
824 return -ENODEV;
825 }
826 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 827 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 828
829 priv->phydev = phydev;
830
831 return 0;
832}
833
47dd7a54 834/**
32ceabca
GC		 835 * stmmac_display_ring: display ring
836 * @head: pointer to the head of the ring passed.
47dd7a54 837 * @size: size of the ring.
32ceabca 838 * @extend_desc: to verify if extended descriptors are used.
c24602ef 839 * Description: display the control/status and buffer descriptors.
47dd7a54 840 */
c24602ef 841static void stmmac_display_ring(void *head, int size, int extend_desc)
47dd7a54 842{
47dd7a54 843 int i;
ceb69499
GC		 844 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
845 struct dma_desc *p = (struct dma_desc *)head;
c24602ef 846
47dd7a54 847 for (i = 0; i < size; i++) {
c24602ef
GC		 848 u64 x;
849 if (extend_desc) {
850 x = *(u64 *) ep;
851 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 852 i, (unsigned int)virt_to_phys(ep),
853 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 854 ep->basic.des2, ep->basic.des3);
855 ep++;
856 } else {
857 x = *(u64 *) p;
858 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
ceb69499
GC		 859 i, (unsigned int)virt_to_phys(p),
860 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 861 p->des2, p->des3);
862 p++;
863 }
47dd7a54
GC		 864 pr_info("\n");
865 }
866}
867
c24602ef
GC		 868static void stmmac_display_rings(struct stmmac_priv *priv)
869{
870 unsigned int txsize = priv->dma_tx_size;
871 unsigned int rxsize = priv->dma_rx_size;
872
873 if (priv->extend_desc) {
874 pr_info("Extended RX descriptor ring:\n");
ceb69499 875 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
c24602ef 876 pr_info("Extended TX descriptor ring:\n");
ceb69499 877 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
c24602ef
GC		 878 } else {
879 pr_info("RX descriptor ring:\n");
880 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
881 pr_info("TX descriptor ring:\n");
882 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
883 }
884}
885
286a8372
GC		 886static int stmmac_set_bfsize(int mtu, int bufsize)
887{
888 int ret = bufsize;
889
890 if (mtu >= BUF_SIZE_4KiB)
891 ret = BUF_SIZE_8KiB;
892 else if (mtu >= BUF_SIZE_2KiB)
893 ret = BUF_SIZE_4KiB;
894 else if (mtu >= DMA_BUFFER_SIZE)
895 ret = BUF_SIZE_2KiB;
896 else
897 ret = DMA_BUFFER_SIZE;
898
899 return ret;
900}
901
32ceabca
GC		 902/**
903 * stmmac_clear_descriptors: clear descriptors
904 * @priv: driver private structure
905 * Description: this function is called to clear the tx and rx descriptors
906 * in case of both basic and extended descriptors are used.
907 */
c24602ef
GC		 908static void stmmac_clear_descriptors(struct stmmac_priv *priv)
909{
910 int i;
911 unsigned int txsize = priv->dma_tx_size;
912 unsigned int rxsize = priv->dma_rx_size;
913
914 /* Clear the Rx/Tx descriptors */
915 for (i = 0; i < rxsize; i++)
916 if (priv->extend_desc)
917 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
918 priv->use_riwt, priv->mode,
919 (i == rxsize - 1));
920 else
921 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
922 priv->use_riwt, priv->mode,
923 (i == rxsize - 1));
924 for (i = 0; i < txsize; i++)
925 if (priv->extend_desc)
926 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
927 priv->mode,
928 (i == txsize - 1));
929 else
930 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
931 priv->mode,
932 (i == txsize - 1));
933}
934
935static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
936 int i)
937{
938 struct sk_buff *skb;
939
940 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
941 GFP_KERNEL);
56329137 942 if (!skb) {
c24602ef 943 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
56329137 944 return -ENOMEM;
c24602ef
GC		 945 }
946 skb_reserve(skb, NET_IP_ALIGN);
947 priv->rx_skbuff[i] = skb;
948 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
949 priv->dma_buf_sz,
950 DMA_FROM_DEVICE);
56329137
BZ		 951 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
952 pr_err("%s: DMA mapping error\n", __func__);
953 dev_kfree_skb_any(skb);
954 return -EINVAL;
955 }
c24602ef
GC		 956
957 p->des2 = priv->rx_skbuff_dma[i];
958
959 if ((priv->mode == STMMAC_RING_MODE) &&
960 (priv->dma_buf_sz == BUF_SIZE_16KiB))
961 priv->hw->ring->init_desc3(p);
962
963 return 0;
964}
965
56329137
BZ		 966static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
967{
968 if (priv->rx_skbuff[i]) {
969 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
970 priv->dma_buf_sz, DMA_FROM_DEVICE);
971 dev_kfree_skb_any(priv->rx_skbuff[i]);
972 }
973 priv->rx_skbuff[i] = NULL;
974}
975
47dd7a54
GC		 976/**
977 * init_dma_desc_rings - init the RX/TX descriptor rings
978 * @dev: net device structure
979 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 980 * and allocates the socket buffers. It suppors the chained and ring
981 * modes.
47dd7a54 982 */
56329137 983static int init_dma_desc_rings(struct net_device *dev)
47dd7a54
GC		 984{
985 int i;
986 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 987 unsigned int txsize = priv->dma_tx_size;
988 unsigned int rxsize = priv->dma_rx_size;
4a7d666a 989 unsigned int bfsize = 0;
56329137 990 int ret = -ENOMEM;
47dd7a54 991
286a8372 992 /* Set the max buffer size according to the DESC mode
ceb69499
GC		 993 * and the MTU. Note that RING mode allows 16KiB bsize.
994 */
4a7d666a
GC		 995 if (priv->mode == STMMAC_RING_MODE)
996 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
286a8372 997
4a7d666a 998 if (bfsize < BUF_SIZE_16KiB)
286a8372 999 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 1000
83d7af64
GC		 1001 if (netif_msg_probe(priv))
1002 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1003 txsize, rxsize, bfsize);
47dd7a54 1004
c24602ef
GC		 1005 if (priv->extend_desc) {
1006 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1007 sizeof(struct
1008 dma_extended_desc),
1009 &priv->dma_rx_phy,
1010 GFP_KERNEL);
56329137
BZ		 1011 if (!priv->dma_erx)
1012 goto err_dma;
1013
c24602ef
GC		 1014 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1015 sizeof(struct
1016 dma_extended_desc),
1017 &priv->dma_tx_phy,
1018 GFP_KERNEL);
56329137
BZ		 1019 if (!priv->dma_etx) {
1020 dma_free_coherent(priv->device, priv->dma_rx_size *
1021 sizeof(struct dma_extended_desc),
1022 priv->dma_erx, priv->dma_rx_phy);
1023 goto err_dma;
1024 }
c24602ef
GC		 1025 } else {
1026 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1027 sizeof(struct dma_desc),
1028 &priv->dma_rx_phy,
1029 GFP_KERNEL);
56329137
BZ		 1030 if (!priv->dma_rx)
1031 goto err_dma;
1032
c24602ef
GC		 1033 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1034 sizeof(struct dma_desc),
1035 &priv->dma_tx_phy,
1036 GFP_KERNEL);
56329137
BZ		 1037 if (!priv->dma_tx) {
1038 dma_free_coherent(priv->device, priv->dma_rx_size *
1039 sizeof(struct dma_desc),
1040 priv->dma_rx, priv->dma_rx_phy);
1041 goto err_dma;
1042 }
c24602ef
GC		 1043 }
1044
b2adaca9
JP		 1045 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1046 GFP_KERNEL);
56329137
BZ		 1047 if (!priv->rx_skbuff_dma)
1048 goto err_rx_skbuff_dma;
1049
b2adaca9
JP		 1050 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1051 GFP_KERNEL);
56329137
BZ		 1052 if (!priv->rx_skbuff)
1053 goto err_rx_skbuff;
1054
cf32deec 1055 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
ceb69499 1056 GFP_KERNEL);
56329137
BZ		 1057 if (!priv->tx_skbuff_dma)
1058 goto err_tx_skbuff_dma;
1059
b2adaca9
JP		 1060 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1061 GFP_KERNEL);
56329137
BZ		 1062 if (!priv->tx_skbuff)
1063 goto err_tx_skbuff;
1064
83d7af64 1065 if (netif_msg_probe(priv)) {
c24602ef
GC		 1066 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1067 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
47dd7a54 1068
83d7af64
GC		 1069 /* RX INITIALIZATION */
1070 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1071 }
47dd7a54 1072 for (i = 0; i < rxsize; i++) {
c24602ef
GC		 1073 struct dma_desc *p;
1074 if (priv->extend_desc)
1075 p = &((priv->dma_erx + i)->basic);
1076 else
1077 p = priv->dma_rx + i;
47dd7a54 1078
56329137
BZ		 1079 ret = stmmac_init_rx_buffers(priv, p, i);
1080 if (ret)
1081 goto err_init_rx_buffers;
286a8372 1082
83d7af64
GC		 1083 if (netif_msg_probe(priv))
1084 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1085 priv->rx_skbuff[i]->data,
1086 (unsigned int)priv->rx_skbuff_dma[i]);
47dd7a54
GC		 1087 }
1088 priv->cur_rx = 0;
1089 priv->dirty_rx = (unsigned int)(i - rxsize);
1090 priv->dma_buf_sz = bfsize;
1091 buf_sz = bfsize;
1092
c24602ef
GC		 1093 /* Setup the chained descriptor addresses */
1094 if (priv->mode == STMMAC_CHAIN_MODE) {
1095 if (priv->extend_desc) {
1096 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1097 rxsize, 1);
1098 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1099 txsize, 1);
1100 } else {
1101 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1102 rxsize, 0);
1103 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1104 txsize, 0);
1105 }
1106 }
1107
47dd7a54
GC		 1108 /* TX INITIALIZATION */
1109 for (i = 0; i < txsize; i++) {
c24602ef
GC		 1110 struct dma_desc *p;
1111 if (priv->extend_desc)
1112 p = &((priv->dma_etx + i)->basic);
1113 else
1114 p = priv->dma_tx + i;
1115 p->des2 = 0;
cf32deec 1116 priv->tx_skbuff_dma[i] = 0;
47dd7a54 1117 priv->tx_skbuff[i] = NULL;
47dd7a54 1118 }
286a8372 1119
47dd7a54
GC		 1120 priv->dirty_tx = 0;
1121 priv->cur_tx = 0;
1122
c24602ef 1123 stmmac_clear_descriptors(priv);
47dd7a54 1124
c24602ef
GC		 1125 if (netif_msg_hw(priv))
1126 stmmac_display_rings(priv);
56329137
BZ		 1127
1128 return 0;
1129err_init_rx_buffers:
1130 while (--i >= 0)
1131 stmmac_free_rx_buffers(priv, i);
1132 kfree(priv->tx_skbuff);
1133err_tx_skbuff:
1134 kfree(priv->tx_skbuff_dma);
1135err_tx_skbuff_dma:
1136 kfree(priv->rx_skbuff);
1137err_rx_skbuff:
1138 kfree(priv->rx_skbuff_dma);
1139err_rx_skbuff_dma:
1140 if (priv->extend_desc) {
1141 dma_free_coherent(priv->device, priv->dma_tx_size *
1142 sizeof(struct dma_extended_desc),
1143 priv->dma_etx, priv->dma_tx_phy);
1144 dma_free_coherent(priv->device, priv->dma_rx_size *
1145 sizeof(struct dma_extended_desc),
1146 priv->dma_erx, priv->dma_rx_phy);
1147 } else {
1148 dma_free_coherent(priv->device,
1149 priv->dma_tx_size * sizeof(struct dma_desc),
1150 priv->dma_tx, priv->dma_tx_phy);
1151 dma_free_coherent(priv->device,
1152 priv->dma_rx_size * sizeof(struct dma_desc),
1153 priv->dma_rx, priv->dma_rx_phy);
1154 }
1155err_dma:
1156 return ret;
47dd7a54
GC		 1157}
1158
1159static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1160{
1161 int i;
1162
56329137
BZ		 1163 for (i = 0; i < priv->dma_rx_size; i++)
1164 stmmac_free_rx_buffers(priv, i);
47dd7a54
GC		 1165}
1166
1167static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1168{
1169 int i;
1170
1171 for (i = 0; i < priv->dma_tx_size; i++) {
1172 if (priv->tx_skbuff[i] != NULL) {
c24602ef
GC		 1173 struct dma_desc *p;
1174 if (priv->extend_desc)
1175 p = &((priv->dma_etx + i)->basic);
1176 else
1177 p = priv->dma_tx + i;
1178
cf32deec
RK		 1179 if (priv->tx_skbuff_dma[i])
1180 dma_unmap_single(priv->device,
1181 priv->tx_skbuff_dma[i],
db98a0b0
GC		 1182 priv->hw->desc->get_tx_len(p),
1183 DMA_TO_DEVICE);
47dd7a54
GC		 1184 dev_kfree_skb_any(priv->tx_skbuff[i]);
1185 priv->tx_skbuff[i] = NULL;
cf32deec 1186 priv->tx_skbuff_dma[i] = 0;
47dd7a54
GC		 1187 }
1188 }
47dd7a54
GC		 1189}
1190
1191static void free_dma_desc_resources(struct stmmac_priv *priv)
1192{
1193 /* Release the DMA TX/RX socket buffers */
1194 dma_free_rx_skbufs(priv);
1195 dma_free_tx_skbufs(priv);
1196
ceb69499 1197 /* Free DMA regions of consistent memory previously allocated */
c24602ef
GC		 1198 if (!priv->extend_desc) {
1199 dma_free_coherent(priv->device,
1200 priv->dma_tx_size * sizeof(struct dma_desc),
1201 priv->dma_tx, priv->dma_tx_phy);
1202 dma_free_coherent(priv->device,
1203 priv->dma_rx_size * sizeof(struct dma_desc),
1204 priv->dma_rx, priv->dma_rx_phy);
1205 } else {
1206 dma_free_coherent(priv->device, priv->dma_tx_size *
1207 sizeof(struct dma_extended_desc),
1208 priv->dma_etx, priv->dma_tx_phy);
1209 dma_free_coherent(priv->device, priv->dma_rx_size *
1210 sizeof(struct dma_extended_desc),
1211 priv->dma_erx, priv->dma_rx_phy);
1212 }
47dd7a54
GC		 1213 kfree(priv->rx_skbuff_dma);
1214 kfree(priv->rx_skbuff);
cf32deec 1215 kfree(priv->tx_skbuff_dma);
47dd7a54 1216 kfree(priv->tx_skbuff);
47dd7a54
GC		 1217}
1218
47dd7a54
GC		 1219/**
1220 * stmmac_dma_operation_mode - HW DMA operation mode
32ceabca 1221 * @priv: driver private structure
47dd7a54 1222 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 1223 * or Store-And-Forward capability.
47dd7a54
GC		 1224 */
1225static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1226{
61b8013a 1227 if (likely(priv->plat->force_sf_dma_mode ||
ceb69499 1228 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
61b8013a
SK		 1229 /*
1230 * In case of GMAC, SF mode can be enabled
1231 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 1232 * 1) TX COE if actually supported
1233 * 2) There is no bugged Jumbo frame support
1234 * that needs to not insert csum in the TDES.
1235 */
ceb69499 1236 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
ebbb293f
GC		 1237 tc = SF_DMA_MODE;
1238 } else
1239 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 1240}
1241
47dd7a54 1242/**
9125cdd1 1243 * stmmac_tx_clean:
32ceabca 1244 * @priv: driver private structure
47dd7a54
GC		 1245 * Description: it reclaims resources after transmission completes.
1246 */
9125cdd1 1247static void stmmac_tx_clean(struct stmmac_priv *priv)
47dd7a54
GC		 1248{
1249 unsigned int txsize = priv->dma_tx_size;
47dd7a54 1250
a9097a96
GC		 1251 spin_lock(&priv->tx_lock);
1252
9125cdd1
GC		 1253 priv->xstats.tx_clean++;
1254
47dd7a54
GC		 1255 while (priv->dirty_tx != priv->cur_tx) {
1256 int last;
1257 unsigned int entry = priv->dirty_tx % txsize;
1258 struct sk_buff *skb = priv->tx_skbuff[entry];
c24602ef
GC		 1259 struct dma_desc *p;
1260
1261 if (priv->extend_desc)
ceb69499 1262 p = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1263 else
1264 p = priv->dma_tx + entry;
47dd7a54
GC		 1265
1266 /* Check if the descriptor is owned by the DMA. */
db98a0b0 1267 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 1268 break;
1269
c24602ef 1270 /* Verify tx error by looking at the last segment. */
db98a0b0 1271 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 1272 if (likely(last)) {
1273 int tx_error =
ceb69499
GC		 1274 priv->hw->desc->tx_status(&priv->dev->stats,
1275 &priv->xstats, p,
1276 priv->ioaddr);
47dd7a54
GC		 1277 if (likely(tx_error == 0)) {
1278 priv->dev->stats.tx_packets++;
1279 priv->xstats.tx_pkt_n++;
1280 } else
1281 priv->dev->stats.tx_errors++;
891434b1
RK		 1282
1283 stmmac_get_tx_hwtstamp(priv, entry, skb);
47dd7a54 1284 }
83d7af64
GC		 1285 if (netif_msg_tx_done(priv))
1286 pr_debug("%s: curr %d, dirty %d\n", __func__,
1287 priv->cur_tx, priv->dirty_tx);
47dd7a54 1288
cf32deec
RK		 1289 if (likely(priv->tx_skbuff_dma[entry])) {
1290 dma_unmap_single(priv->device,
1291 priv->tx_skbuff_dma[entry],
db98a0b0 1292 priv->hw->desc->get_tx_len(p),
47dd7a54 1293 DMA_TO_DEVICE);
cf32deec
RK		 1294 priv->tx_skbuff_dma[entry] = 0;
1295 }
891434b1 1296 priv->hw->ring->clean_desc3(priv, p);
47dd7a54
GC		 1297
1298 if (likely(skb != NULL)) {
acb600de 1299 dev_kfree_skb(skb);
47dd7a54
GC		 1300 priv->tx_skbuff[entry] = NULL;
1301 }
1302
4a7d666a 1303 priv->hw->desc->release_tx_desc(p, priv->mode);
47dd7a54 1304
13497f58 1305 priv->dirty_tx++;
47dd7a54
GC		 1306 }
1307 if (unlikely(netif_queue_stopped(priv->dev) &&
1308 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1309 netif_tx_lock(priv->dev);
1310 if (netif_queue_stopped(priv->dev) &&
ceb69499 1311 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
83d7af64
GC		 1312 if (netif_msg_tx_done(priv))
1313 pr_debug("%s: restart transmit\n", __func__);
47dd7a54
GC		 1314 netif_wake_queue(priv->dev);
1315 }
1316 netif_tx_unlock(priv->dev);
1317 }
d765955d
GC		 1318
1319 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1320 stmmac_enable_eee_mode(priv);
f5351ef7 1321 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
d765955d 1322 }
a9097a96 1323 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 1324}
1325
9125cdd1 1326static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
47dd7a54 1327{
7284a3f1 1328 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 1329}
1330
9125cdd1 1331static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
47dd7a54 1332{
7284a3f1 1333 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 1334}
1335
47dd7a54 1336/**
32ceabca
GC		 1337 * stmmac_tx_err: irq tx error mng function
1338 * @priv: driver private structure
47dd7a54
GC		 1339 * Description: it cleans the descriptors and restarts the transmission
1340 * in case of errors.
1341 */
1342static void stmmac_tx_err(struct stmmac_priv *priv)
1343{
c24602ef
GC		 1344 int i;
1345 int txsize = priv->dma_tx_size;
47dd7a54
GC		 1346 netif_stop_queue(priv->dev);
1347
ad01b7d4 1348 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1349 dma_free_tx_skbufs(priv);
c24602ef
GC		 1350 for (i = 0; i < txsize; i++)
1351 if (priv->extend_desc)
1352 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1353 priv->mode,
1354 (i == txsize - 1));
1355 else
1356 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1357 priv->mode,
1358 (i == txsize - 1));
47dd7a54
GC		 1359 priv->dirty_tx = 0;
1360 priv->cur_tx = 0;
ad01b7d4 1361 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 1362
1363 priv->dev->stats.tx_errors++;
1364 netif_wake_queue(priv->dev);
47dd7a54
GC		 1365}
1366
32ceabca
GC		 1367/**
1368 * stmmac_dma_interrupt: DMA ISR
1369 * @priv: driver private structure
1370 * Description: this is the DMA ISR. It is called by the main ISR.
1371 * It calls the dwmac dma routine to understand which type of interrupt
1372 * happened. In case of there is a Normal interrupt and either TX or RX
1373 * interrupt happened so the NAPI is scheduled.
1374 */
aec7ff27
GC		 1375static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1376{
aec7ff27
GC		 1377 int status;
1378
ad01b7d4 1379 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
9125cdd1
GC		 1380 if (likely((status & handle_rx)) || (status & handle_tx)) {
1381 if (likely(napi_schedule_prep(&priv->napi))) {
1382 stmmac_disable_dma_irq(priv);
1383 __napi_schedule(&priv->napi);
1384 }
1385 }
1386 if (unlikely(status & tx_hard_error_bump_tc)) {
aec7ff27
GC		 1387 /* Try to bump up the dma threshold on this failure */
1388 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1389 tc += 64;
ad01b7d4 1390 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 1391 priv->xstats.threshold = tc;
47dd7a54 1392 }
aec7ff27
GC		 1393 } else if (unlikely(status == tx_hard_error))
1394 stmmac_tx_err(priv);
47dd7a54
GC		 1395}
1396
32ceabca
GC		 1397/**
1398 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1399 * @priv: driver private structure
1400 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1401 */
1c901a46
GC		 1402static void stmmac_mmc_setup(struct stmmac_priv *priv)
1403{
1404 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
ceb69499 1405 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1c901a46 1406
1c901a46 1407 dwmac_mmc_intr_all_mask(priv->ioaddr);
4f795b25
GC		 1408
1409 if (priv->dma_cap.rmon) {
1410 dwmac_mmc_ctrl(priv->ioaddr, mode);
1411 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1412 } else
aae54cff 1413 pr_info(" No MAC Management Counters available\n");
1c901a46
GC		 1414}
1415
f0b9d786
GC		 1416static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1417{
1418 u32 hwid = priv->hw->synopsys_uid;
1419
ceb69499 1420 /* Check Synopsys Id (not available on old chips) */
f0b9d786
GC		 1421 if (likely(hwid)) {
1422 u32 uid = ((hwid & 0x0000ff00) >> 8);
1423 u32 synid = (hwid & 0x000000ff);
1424
cf3f047b 1425 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
f0b9d786
GC		 1426 uid, synid);
1427
1428 return synid;
1429 }
1430 return 0;
1431}
e7434821 1432
19e30c14 1433/**
32ceabca
GC		 1434 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1435 * @priv: driver private structure
1436 * Description: select the Enhanced/Alternate or Normal descriptors.
1437 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1438 * supported by the HW cap. register.
ff3dd78c 1439 */
19e30c14
GC		 1440static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1441{
1442 if (priv->plat->enh_desc) {
1443 pr_info(" Enhanced/Alternate descriptors\n");
c24602ef
GC		 1444
1445 /* GMAC older than 3.50 has no extended descriptors */
1446 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1447 pr_info("\tEnabled extended descriptors\n");
1448 priv->extend_desc = 1;
1449 } else
1450 pr_warn("Extended descriptors not supported\n");
1451
19e30c14
GC		 1452 priv->hw->desc = &enh_desc_ops;
1453 } else {
1454 pr_info(" Normal descriptors\n");
1455 priv->hw->desc = &ndesc_ops;
1456 }
1457}
1458
1459/**
32ceabca
GC		 1460 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1461 * @priv: driver private structure
19e30c14
GC		 1462 * Description:
1463 * new GMAC chip generations have a new register to indicate the
1464 * presence of the optional feature/functions.
1465 * This can be also used to override the value passed through the
1466 * platform and necessary for old MAC10/100 and GMAC chips.
e7434821
GC		 1467 */
1468static int stmmac_get_hw_features(struct stmmac_priv *priv)
1469{
5e6efe88 1470 u32 hw_cap = 0;
3c20f72f 1471
5e6efe88
GC		 1472 if (priv->hw->dma->get_hw_feature) {
1473 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
e7434821 1474
1db123fb
RK		 1475 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1476 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1477 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1478 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
ceb69499 1479 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1db123fb
RK		 1480 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1481 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1482 priv->dma_cap.pmt_remote_wake_up =
ceb69499 1483 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1db123fb 1484 priv->dma_cap.pmt_magic_frame =
ceb69499 1485 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
19e30c14 1486 /* MMC */
1db123fb 1487 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
ceb69499 1488 /* IEEE 1588-2002 */
1db123fb 1489 priv->dma_cap.time_stamp =
ceb69499
GC		 1490 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1491 /* IEEE 1588-2008 */
1db123fb 1492 priv->dma_cap.atime_stamp =
ceb69499 1493 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 1494 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 1495 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1496 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 1497 /* TX and RX csum */
1db123fb
RK		 1498 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1499 priv->dma_cap.rx_coe_type1 =
ceb69499 1500 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1db123fb 1501 priv->dma_cap.rx_coe_type2 =
ceb69499 1502 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1db123fb 1503 priv->dma_cap.rxfifo_over_2048 =
ceb69499 1504 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 1505 /* TX and RX number of channels */
1db123fb 1506 priv->dma_cap.number_rx_channel =
ceb69499 1507 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1db123fb 1508 priv->dma_cap.number_tx_channel =
ceb69499
GC		 1509 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1510 /* Alternate (enhanced) DESC mode */
1511 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
19e30c14 1512 }
e7434821
GC		 1513
1514 return hw_cap;
1515}
1516
32ceabca
GC		 1517/**
1518 * stmmac_check_ether_addr: check if the MAC addr is valid
1519 * @priv: driver private structure
1520 * Description:
1521 * it is to verify if the MAC address is valid, in case of failures it
1522 * generates a random MAC address
1523 */
bfab27a1
GC		 1524static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1525{
bfab27a1
GC		 1526 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1527 priv->hw->mac->get_umac_addr((void __iomem *)
1528 priv->dev->base_addr,
1529 priv->dev->dev_addr, 0);
ceb69499 1530 if (!is_valid_ether_addr(priv->dev->dev_addr))
f2cedb63 1531 eth_hw_addr_random(priv->dev);
bfab27a1 1532 }
ceb69499
GC		 1533 pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1534 priv->dev->dev_addr);
bfab27a1
GC		 1535}
1536
32ceabca
GC		 1537/**
1538 * stmmac_init_dma_engine: DMA init.
1539 * @priv: driver private structure
1540 * Description:
1541 * It inits the DMA invoking the specific MAC/GMAC callback.
1542 * Some DMA parameters can be passed from the platform;
1543 * in case of these are not passed a default is kept for the MAC or GMAC.
1544 */
0f1f88a8
GC		 1545static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1546{
1547 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
b9cde0a8 1548 int mixed_burst = 0;
c24602ef 1549 int atds = 0;
0f1f88a8 1550
0f1f88a8
GC		 1551 if (priv->plat->dma_cfg) {
1552 pbl = priv->plat->dma_cfg->pbl;
1553 fixed_burst = priv->plat->dma_cfg->fixed_burst;
b9cde0a8 1554 mixed_burst = priv->plat->dma_cfg->mixed_burst;
0f1f88a8
GC		 1555 burst_len = priv->plat->dma_cfg->burst_len;
1556 }
1557
c24602ef
GC		 1558 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1559 atds = 1;
1560
b9cde0a8 1561 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
0f1f88a8 1562 burst_len, priv->dma_tx_phy,
c24602ef 1563 priv->dma_rx_phy, atds);
0f1f88a8
GC		 1564}
1565
9125cdd1 1566/**
32ceabca 1567 * stmmac_tx_timer: mitigation sw timer for tx.
9125cdd1
GC		 1568 * @data: data pointer
1569 * Description:
1570 * This is the timer handler to directly invoke the stmmac_tx_clean.
1571 */
1572static void stmmac_tx_timer(unsigned long data)
1573{
1574 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1575
1576 stmmac_tx_clean(priv);
1577}
1578
1579/**
32ceabca
GC		 1580 * stmmac_init_tx_coalesce: init tx mitigation options.
1581 * @priv: driver private structure
9125cdd1
GC		 1582 * Description:
1583 * This inits the transmit coalesce parameters: i.e. timer rate,
1584 * timer handler and default threshold used for enabling the
1585 * interrupt on completion bit.
1586 */
1587static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1588{
1589 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1590 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1591 init_timer(&priv->txtimer);
1592 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1593 priv->txtimer.data = (unsigned long)priv;
1594 priv->txtimer.function = stmmac_tx_timer;
1595 add_timer(&priv->txtimer);
1596}
1597
47dd7a54
GC		 1598/**
1599 * stmmac_open - open entry point of the driver
1600 * @dev : pointer to the device structure.
1601 * Description:
1602 * This function is the open entry point of the driver.
1603 * Return value:
1604 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1605 * file on failure.
1606 */
1607static int stmmac_open(struct net_device *dev)
1608{
1609 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1610 int ret;
1611
a630844d 1612 clk_prepare_enable(priv->stmmac_clk);
4bfcbd7a
FV		 1613
1614 stmmac_check_ether_addr(priv);
1615
4d8f0825
BA		 1616 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1617 priv->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 1618 ret = stmmac_init_phy(dev);
1619 if (ret) {
1620 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1621 __func__, ret);
c9324d18 1622 goto phy_error;
e58bb43f 1623 }
f66ffe28 1624 }
47dd7a54
GC		 1625
1626 /* Create and initialize the TX/RX descriptors chains. */
1627 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1628 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1629 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
56329137
BZ		 1630
1631 ret = init_dma_desc_rings(dev);
1632 if (ret < 0) {
1633 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1634 goto dma_desc_error;
1635 }
47dd7a54
GC		 1636
1637 /* DMA initialization and SW reset */
0f1f88a8 1638 ret = stmmac_init_dma_engine(priv);
f66ffe28 1639 if (ret < 0) {
56329137 1640 pr_err("%s: DMA engine initialization failed\n", __func__);
c9324d18 1641 goto init_error;
47dd7a54
GC		 1642 }
1643
1644 /* Copy the MAC addr into the HW */
ad01b7d4 1645 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
cf3f047b 1646
ca5f12c1 1647 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 1648 if (priv->plat->bus_setup)
1649 priv->plat->bus_setup(priv->ioaddr);
cf3f047b 1650
47dd7a54 1651 /* Initialize the MAC Core */
ad01b7d4 1652 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 1653
f66ffe28
GC		 1654 /* Request the IRQ lines */
1655 ret = request_irq(dev->irq, stmmac_interrupt,
ceb69499 1656 IRQF_SHARED, dev->name, dev);
f66ffe28
GC		 1657 if (unlikely(ret < 0)) {
1658 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1659 __func__, dev->irq, ret);
c9324d18 1660 goto init_error;
f66ffe28
GC		 1661 }
1662
7a13f8f5
FV		 1663 /* Request the Wake IRQ in case of another line is used for WoL */
1664 if (priv->wol_irq != dev->irq) {
1665 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1666 IRQF_SHARED, dev->name, dev);
1667 if (unlikely(ret < 0)) {
ceb69499
GC		 1668 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1669 __func__, priv->wol_irq, ret);
c9324d18 1670 goto wolirq_error;
7a13f8f5
FV		 1671 }
1672 }
1673
d765955d
GC		 1674 /* Request the IRQ lines */
1675 if (priv->lpi_irq != -ENXIO) {
1676 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1677 dev->name, dev);
1678 if (unlikely(ret < 0)) {
1679 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1680 __func__, priv->lpi_irq, ret);
c9324d18 1681 goto lpiirq_error;
d765955d
GC		 1682 }
1683 }
1684
47dd7a54 1685 /* Enable the MAC Rx/Tx */
bfab27a1 1686 stmmac_set_mac(priv->ioaddr, true);
47dd7a54
GC		 1687
1688 /* Set the HW DMA mode and the COE */
1689 stmmac_dma_operation_mode(priv);
1690
1691 /* Extra statistics */
1692 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1693 priv->xstats.threshold = tc;
1694
4f795b25 1695 stmmac_mmc_setup(priv);
1c901a46 1696
92ba6888
RK		 1697 ret = stmmac_init_ptp(priv);
1698 if (ret)
1699 pr_warn("%s: failed PTP initialisation\n", __func__);
891434b1 1700
bfab27a1
GC		 1701#ifdef CONFIG_STMMAC_DEBUG_FS
1702 ret = stmmac_init_fs(dev);
1703 if (ret < 0)
ceb69499 1704 pr_warn("%s: failed debugFS registration\n", __func__);
bfab27a1 1705#endif
47dd7a54 1706 /* Start the ball rolling... */
83d7af64 1707 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 1708 priv->hw->dma->start_tx(priv->ioaddr);
1709 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54 1710
47dd7a54
GC		 1711 /* Dump DMA/MAC registers */
1712 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 1713 priv->hw->mac->dump_regs(priv->ioaddr);
1714 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 1715 }
1716
1717 if (priv->phydev)
1718 phy_start(priv->phydev);
1719
f5351ef7 1720 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
e58bb43f 1721
f5351ef7 1722 priv->eee_enabled = stmmac_eee_init(priv);
d765955d 1723
9125cdd1
GC		 1724 stmmac_init_tx_coalesce(priv);
1725
62a2ab93
GC		 1726 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1727 priv->rx_riwt = MAX_DMA_RIWT;
1728 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1729 }
1730
e58bb43f
GC		 1731 if (priv->pcs && priv->hw->mac->ctrl_ane)
1732 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1733
47dd7a54 1734 napi_enable(&priv->napi);
47dd7a54 1735 netif_start_queue(dev);
f66ffe28 1736
47dd7a54 1737 return 0;
f66ffe28 1738
c9324d18 1739lpiirq_error:
d765955d
GC		 1740 if (priv->wol_irq != dev->irq)
1741 free_irq(priv->wol_irq, dev);
c9324d18 1742wolirq_error:
7a13f8f5
FV		 1743 free_irq(dev->irq, dev);
1744
c9324d18
GC		 1745init_error:
1746 free_dma_desc_resources(priv);
56329137 1747dma_desc_error:
f66ffe28
GC		 1748 if (priv->phydev)
1749 phy_disconnect(priv->phydev);
c9324d18 1750phy_error:
a630844d 1751 clk_disable_unprepare(priv->stmmac_clk);
4bfcbd7a 1752
f66ffe28 1753 return ret;
47dd7a54
GC		 1754}
1755
1756/**
1757 * stmmac_release - close entry point of the driver
1758 * @dev : device pointer.
1759 * Description:
1760 * This is the stop entry point of the driver.
1761 */
1762static int stmmac_release(struct net_device *dev)
1763{
1764 struct stmmac_priv *priv = netdev_priv(dev);
1765
d765955d
GC		 1766 if (priv->eee_enabled)
1767 del_timer_sync(&priv->eee_ctrl_timer);
1768
47dd7a54
GC		 1769 /* Stop and disconnect the PHY */
1770 if (priv->phydev) {
1771 phy_stop(priv->phydev);
1772 phy_disconnect(priv->phydev);
1773 priv->phydev = NULL;
1774 }
1775
1776 netif_stop_queue(dev);
1777
47dd7a54 1778 napi_disable(&priv->napi);
47dd7a54 1779
9125cdd1
GC		 1780 del_timer_sync(&priv->txtimer);
1781
47dd7a54
GC		 1782 /* Free the IRQ lines */
1783 free_irq(dev->irq, dev);
7a13f8f5
FV		 1784 if (priv->wol_irq != dev->irq)
1785 free_irq(priv->wol_irq, dev);
d765955d
GC		 1786 if (priv->lpi_irq != -ENXIO)
1787 free_irq(priv->lpi_irq, dev);
47dd7a54
GC		 1788
1789 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1790 priv->hw->dma->stop_tx(priv->ioaddr);
1791 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1792
1793 /* Release and free the Rx/Tx resources */
1794 free_dma_desc_resources(priv);
1795
19449bfc 1796 /* Disable the MAC Rx/Tx */
bfab27a1 1797 stmmac_set_mac(priv->ioaddr, false);
47dd7a54
GC		 1798
1799 netif_carrier_off(dev);
1800
bfab27a1
GC		 1801#ifdef CONFIG_STMMAC_DEBUG_FS
1802 stmmac_exit_fs();
1803#endif
a630844d 1804 clk_disable_unprepare(priv->stmmac_clk);
bfab27a1 1805
92ba6888
RK		 1806 stmmac_release_ptp(priv);
1807
47dd7a54
GC		 1808 return 0;
1809}
1810
47dd7a54 1811/**
32ceabca 1812 * stmmac_xmit: Tx entry point of the driver
47dd7a54
GC		 1813 * @skb : the socket buffer
1814 * @dev : device pointer
32ceabca
GC		 1815 * Description : this is the tx entry point of the driver.
1816 * It programs the chain or the ring and supports oversized frames
1817 * and SG feature.
47dd7a54
GC		 1818 */
1819static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1820{
1821 struct stmmac_priv *priv = netdev_priv(dev);
1822 unsigned int txsize = priv->dma_tx_size;
1823 unsigned int entry;
4a7d666a 1824 int i, csum_insertion = 0, is_jumbo = 0;
47dd7a54
GC		 1825 int nfrags = skb_shinfo(skb)->nr_frags;
1826 struct dma_desc *desc, *first;
286a8372 1827 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1828
1829 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1830 if (!netif_queue_stopped(dev)) {
1831 netif_stop_queue(dev);
1832 /* This is a hard error, log it. */
ceb69499 1833 pr_err("%s: Tx Ring full when queue awake\n", __func__);
47dd7a54
GC		 1834 }
1835 return NETDEV_TX_BUSY;
1836 }
1837
a9097a96
GC		 1838 spin_lock(&priv->tx_lock);
1839
d765955d
GC		 1840 if (priv->tx_path_in_lpi_mode)
1841 stmmac_disable_eee_mode(priv);
1842
47dd7a54
GC		 1843 entry = priv->cur_tx % txsize;
1844
5e982f3b 1845 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54 1846
c24602ef 1847 if (priv->extend_desc)
ceb69499 1848 desc = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1849 else
1850 desc = priv->dma_tx + entry;
1851
47dd7a54
GC		 1852 first = desc;
1853
47dd7a54 1854 priv->tx_skbuff[entry] = skb;
286a8372 1855
4a7d666a
GC		 1856 /* To program the descriptors according to the size of the frame */
1857 if (priv->mode == STMMAC_RING_MODE) {
1858 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1859 priv->plat->enh_desc);
1860 if (unlikely(is_jumbo))
1861 entry = priv->hw->ring->jumbo_frm(priv, skb,
1862 csum_insertion);
47dd7a54 1863 } else {
4a7d666a 1864 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
ceb69499 1865 priv->plat->enh_desc);
4a7d666a
GC		 1866 if (unlikely(is_jumbo))
1867 entry = priv->hw->chain->jumbo_frm(priv, skb,
1868 csum_insertion);
1869 }
1870 if (likely(!is_jumbo)) {
47dd7a54 1871 desc->des2 = dma_map_single(priv->device, skb->data,
ceb69499 1872 nopaged_len, DMA_TO_DEVICE);
cf32deec 1873 priv->tx_skbuff_dma[entry] = desc->des2;
db98a0b0 1874 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
4a7d666a
GC		 1875 csum_insertion, priv->mode);
1876 } else
c24602ef 1877 desc = first;
47dd7a54
GC		 1878
1879 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1880 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1881 int len = skb_frag_size(frag);
47dd7a54
GC		 1882
1883 entry = (++priv->cur_tx) % txsize;
c24602ef 1884 if (priv->extend_desc)
ceb69499 1885 desc = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1886 else
1887 desc = priv->dma_tx + entry;
47dd7a54 1888
f722380d
IC		 1889 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1890 DMA_TO_DEVICE);
cf32deec 1891 priv->tx_skbuff_dma[entry] = desc->des2;
47dd7a54 1892 priv->tx_skbuff[entry] = NULL;
4a7d666a
GC		 1893 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1894 priv->mode);
eb0dc4bb 1895 wmb();
db98a0b0 1896 priv->hw->desc->set_tx_owner(desc);
8e839891 1897 wmb();
47dd7a54
GC		 1898 }
1899
9125cdd1 1900 /* Finalize the latest segment. */
db98a0b0 1901 priv->hw->desc->close_tx_desc(desc);
73cfe264 1902
eb0dc4bb 1903 wmb();
9125cdd1
GC		 1904 /* According to the coalesce parameter the IC bit for the latest
1905 * segment could be reset and the timer re-started to invoke the
1906 * stmmac_tx function. This approach takes care about the fragments.
1907 */
1908 priv->tx_count_frames += nfrags + 1;
1909 if (priv->tx_coal_frames > priv->tx_count_frames) {
1910 priv->hw->desc->clear_tx_ic(desc);
1911 priv->xstats.tx_reset_ic_bit++;
9125cdd1
GC		 1912 mod_timer(&priv->txtimer,
1913 STMMAC_COAL_TIMER(priv->tx_coal_timer));
1914 } else
1915 priv->tx_count_frames = 0;
eb0dc4bb 1916
47dd7a54 1917 /* To avoid raise condition */
db98a0b0 1918 priv->hw->desc->set_tx_owner(first);
8e839891 1919 wmb();
47dd7a54
GC		 1920
1921 priv->cur_tx++;
1922
47dd7a54 1923 if (netif_msg_pktdata(priv)) {
83d7af64 1924 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
ceb69499
GC		 1925 __func__, (priv->cur_tx % txsize),
1926 (priv->dirty_tx % txsize), entry, first, nfrags);
83d7af64 1927
c24602ef
GC		 1928 if (priv->extend_desc)
1929 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1930 else
1931 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1932
83d7af64 1933 pr_debug(">>> frame to be transmitted: ");
47dd7a54
GC		 1934 print_pkt(skb->data, skb->len);
1935 }
47dd7a54 1936 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
83d7af64
GC		 1937 if (netif_msg_hw(priv))
1938 pr_debug("%s: stop transmitted packets\n", __func__);
47dd7a54
GC		 1939 netif_stop_queue(dev);
1940 }
1941
1942 dev->stats.tx_bytes += skb->len;
1943
891434b1
RK		 1944 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1945 priv->hwts_tx_en)) {
1946 /* declare that device is doing timestamping */
1947 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1948 priv->hw->desc->enable_tx_timestamp(first);
1949 }
1950
1951 if (!priv->hwts_tx_en)
1952 skb_tx_timestamp(skb);
3e82ce12 1953
52f64fae
RC		 1954 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1955
a9097a96
GC		 1956 spin_unlock(&priv->tx_lock);
1957
47dd7a54
GC		 1958 return NETDEV_TX_OK;
1959}
1960
32ceabca
GC		 1961/**
1962 * stmmac_rx_refill: refill used skb preallocated buffers
1963 * @priv: driver private structure
1964 * Description : this is to reallocate the skb for the reception process
1965 * that is based on zero-copy.
1966 */
47dd7a54
GC		 1967static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1968{
1969 unsigned int rxsize = priv->dma_rx_size;
1970 int bfsize = priv->dma_buf_sz;
47dd7a54
GC		 1971
1972 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1973 unsigned int entry = priv->dirty_rx % rxsize;
c24602ef
GC		 1974 struct dma_desc *p;
1975
1976 if (priv->extend_desc)
ceb69499 1977 p = (struct dma_desc *)(priv->dma_erx + entry);
c24602ef
GC		 1978 else
1979 p = priv->dma_rx + entry;
1980
47dd7a54
GC		 1981 if (likely(priv->rx_skbuff[entry] == NULL)) {
1982 struct sk_buff *skb;
1983
acb600de 1984 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
47dd7a54
GC		 1985
1986 if (unlikely(skb == NULL))
1987 break;
1988
1989 priv->rx_skbuff[entry] = skb;
1990 priv->rx_skbuff_dma[entry] =
1991 dma_map_single(priv->device, skb->data, bfsize,
1992 DMA_FROM_DEVICE);
1993
c24602ef 1994 p->des2 = priv->rx_skbuff_dma[entry];
286a8372 1995
891434b1 1996 priv->hw->ring->refill_desc3(priv, p);
286a8372 1997
83d7af64
GC		 1998 if (netif_msg_rx_status(priv))
1999 pr_debug("\trefill entry #%d\n", entry);
47dd7a54 2000 }
eb0dc4bb 2001 wmb();
c24602ef 2002 priv->hw->desc->set_rx_owner(p);
8e839891 2003 wmb();
47dd7a54 2004 }
47dd7a54
GC		 2005}
2006
32ceabca
GC		 2007/**
2008 * stmmac_rx_refill: refill used skb preallocated buffers
2009 * @priv: driver private structure
2010 * @limit: napi bugget.
2011 * Description : this the function called by the napi poll method.
2012 * It gets all the frames inside the ring.
2013 */
47dd7a54
GC		 2014static int stmmac_rx(struct stmmac_priv *priv, int limit)
2015{
2016 unsigned int rxsize = priv->dma_rx_size;
2017 unsigned int entry = priv->cur_rx % rxsize;
2018 unsigned int next_entry;
2019 unsigned int count = 0;
ceb69499 2020 int coe = priv->plat->rx_coe;
47dd7a54 2021
83d7af64
GC		 2022 if (netif_msg_rx_status(priv)) {
2023 pr_debug("%s: descriptor ring:\n", __func__);
c24602ef 2024 if (priv->extend_desc)
ceb69499 2025 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
c24602ef
GC		 2026 else
2027 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
47dd7a54 2028 }
c24602ef 2029 while (count < limit) {
47dd7a54 2030 int status;
9401bb5c 2031 struct dma_desc *p;
47dd7a54 2032
c24602ef 2033 if (priv->extend_desc)
ceb69499 2034 p = (struct dma_desc *)(priv->dma_erx + entry);
c24602ef 2035 else
ceb69499 2036 p = priv->dma_rx + entry;
c24602ef
GC		 2037
2038 if (priv->hw->desc->get_rx_owner(p))
47dd7a54
GC		 2039 break;
2040
2041 count++;
2042
2043 next_entry = (++priv->cur_rx) % rxsize;
c24602ef 2044 if (priv->extend_desc)
9401bb5c 2045 prefetch(priv->dma_erx + next_entry);
c24602ef 2046 else
9401bb5c 2047 prefetch(priv->dma_rx + next_entry);
47dd7a54
GC		 2048
2049 /* read the status of the incoming frame */
c24602ef
GC		 2050 status = priv->hw->desc->rx_status(&priv->dev->stats,
2051 &priv->xstats, p);
2052 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2053 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2054 &priv->xstats,
2055 priv->dma_erx +
2056 entry);
891434b1 2057 if (unlikely(status == discard_frame)) {
47dd7a54 2058 priv->dev->stats.rx_errors++;
891434b1
RK		 2059 if (priv->hwts_rx_en && !priv->extend_desc) {
2060 /* DESC2 & DESC3 will be overwitten by device
2061 * with timestamp value, hence reinitialize
2062 * them in stmmac_rx_refill() function so that
2063 * device can reuse it.
2064 */
2065 priv->rx_skbuff[entry] = NULL;
2066 dma_unmap_single(priv->device,
ceb69499
GC		 2067 priv->rx_skbuff_dma[entry],
2068 priv->dma_buf_sz,
2069 DMA_FROM_DEVICE);
891434b1
RK		 2070 }
2071 } else {
47dd7a54 2072 struct sk_buff *skb;
3eeb2997 2073 int frame_len;
47dd7a54 2074
ceb69499
GC		 2075 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2076
3eeb2997 2077 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
ceb69499
GC		 2078 * Type frames (LLC/LLC-SNAP)
2079 */
3eeb2997
GC		 2080 if (unlikely(status != llc_snap))
2081 frame_len -= ETH_FCS_LEN;
47dd7a54 2082
83d7af64 2083 if (netif_msg_rx_status(priv)) {
47dd7a54 2084 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
ceb69499 2085 p, entry, p->des2);
83d7af64
GC		 2086 if (frame_len > ETH_FRAME_LEN)
2087 pr_debug("\tframe size %d, COE: %d\n",
2088 frame_len, status);
2089 }
47dd7a54
GC		 2090 skb = priv->rx_skbuff[entry];
2091 if (unlikely(!skb)) {
2092 pr_err("%s: Inconsistent Rx descriptor chain\n",
ceb69499 2093 priv->dev->name);
47dd7a54
GC		 2094 priv->dev->stats.rx_dropped++;
2095 break;
2096 }
2097 prefetch(skb->data - NET_IP_ALIGN);
2098 priv->rx_skbuff[entry] = NULL;
2099
891434b1
RK		 2100 stmmac_get_rx_hwtstamp(priv, entry, skb);
2101
47dd7a54
GC		 2102 skb_put(skb, frame_len);
2103 dma_unmap_single(priv->device,
2104 priv->rx_skbuff_dma[entry],
2105 priv->dma_buf_sz, DMA_FROM_DEVICE);
83d7af64 2106
47dd7a54 2107 if (netif_msg_pktdata(priv)) {
83d7af64 2108 pr_debug("frame received (%dbytes)", frame_len);
47dd7a54
GC		 2109 print_pkt(skb->data, frame_len);
2110 }
83d7af64 2111
47dd7a54
GC		 2112 skb->protocol = eth_type_trans(skb, priv->dev);
2113
ceb69499 2114 if (unlikely(!coe))
bc8acf2c 2115 skb_checksum_none_assert(skb);
62a2ab93 2116 else
47dd7a54 2117 skb->ip_summed = CHECKSUM_UNNECESSARY;
62a2ab93
GC		 2118
2119 napi_gro_receive(&priv->napi, skb);
47dd7a54
GC		 2120
2121 priv->dev->stats.rx_packets++;
2122 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 2123 }
2124 entry = next_entry;
47dd7a54
GC		 2125 }
2126
2127 stmmac_rx_refill(priv);
2128
2129 priv->xstats.rx_pkt_n += count;
2130
2131 return count;
2132}
2133
2134/**
2135 * stmmac_poll - stmmac poll method (NAPI)
2136 * @napi : pointer to the napi structure.
2137 * @budget : maximum number of packets that the current CPU can receive from
2138 * all interfaces.
2139 * Description :
9125cdd1 2140 * To look at the incoming frames and clear the tx resources.
47dd7a54
GC		 2141 */
2142static int stmmac_poll(struct napi_struct *napi, int budget)
2143{
2144 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2145 int work_done = 0;
2146
9125cdd1
GC		 2147 priv->xstats.napi_poll++;
2148 stmmac_tx_clean(priv);
47dd7a54 2149
9125cdd1 2150 work_done = stmmac_rx(priv, budget);
47dd7a54
GC		 2151 if (work_done < budget) {
2152 napi_complete(napi);
9125cdd1 2153 stmmac_enable_dma_irq(priv);
47dd7a54
GC		 2154 }
2155 return work_done;
2156}
2157
2158/**
2159 * stmmac_tx_timeout
2160 * @dev : Pointer to net device structure
2161 * Description: this function is called when a packet transmission fails to
7284a3f1 2162 * complete within a reasonable time. The driver will mark the error in the
47dd7a54
GC		 2163 * netdev structure and arrange for the device to be reset to a sane state
2164 * in order to transmit a new packet.
2165 */
2166static void stmmac_tx_timeout(struct net_device *dev)
2167{
2168 struct stmmac_priv *priv = netdev_priv(dev);
2169
2170 /* Clear Tx resources and restart transmitting again */
2171 stmmac_tx_err(priv);
47dd7a54
GC		 2172}
2173
2174/* Configuration changes (passed on by ifconfig) */
2175static int stmmac_config(struct net_device *dev, struct ifmap *map)
2176{
2177 if (dev->flags & IFF_UP) /* can't act on a running interface */
2178 return -EBUSY;
2179
2180 /* Don't allow changing the I/O address */
2181 if (map->base_addr != dev->base_addr) {
ceb69499 2182 pr_warn("%s: can't change I/O address\n", dev->name);
47dd7a54
GC		 2183 return -EOPNOTSUPP;
2184 }
2185
2186 /* Don't allow changing the IRQ */
2187 if (map->irq != dev->irq) {
ceb69499 2188 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
47dd7a54
GC		 2189 return -EOPNOTSUPP;
2190 }
2191
47dd7a54
GC		 2192 return 0;
2193}
2194
2195/**
01789349 2196 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 2197 * @dev : pointer to the device structure
2198 * Description:
2199 * This function is a driver entry point which gets called by the kernel
2200 * whenever multicast addresses must be enabled/disabled.
2201 * Return value:
2202 * void.
2203 */
01789349 2204static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 2205{
2206 struct stmmac_priv *priv = netdev_priv(dev);
2207
2208 spin_lock(&priv->lock);
cffb13f4 2209 priv->hw->mac->set_filter(dev, priv->synopsys_id);
47dd7a54 2210 spin_unlock(&priv->lock);
47dd7a54
GC		 2211}
2212
2213/**
2214 * stmmac_change_mtu - entry point to change MTU size for the device.
2215 * @dev : device pointer.
2216 * @new_mtu : the new MTU size for the device.
2217 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2218 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2219 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2220 * Return value:
2221 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2222 * file on failure.
2223 */
2224static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2225{
2226 struct stmmac_priv *priv = netdev_priv(dev);
2227 int max_mtu;
2228
2229 if (netif_running(dev)) {
2230 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2231 return -EBUSY;
2232 }
2233
48febf7e 2234 if (priv->plat->enh_desc)
47dd7a54
GC		 2235 max_mtu = JUMBO_LEN;
2236 else
45db81e1 2237 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
47dd7a54
GC		 2238
2239 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2240 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2241 return -EINVAL;
2242 }
2243
5e982f3b
MM		 2244 dev->mtu = new_mtu;
2245 netdev_update_features(dev);
2246
2247 return 0;
2248}
2249
c8f44aff 2250static netdev_features_t stmmac_fix_features(struct net_device *dev,
ceb69499 2251 netdev_features_t features)
5e982f3b
MM		 2252{
2253 struct stmmac_priv *priv = netdev_priv(dev);
2254
38912bdb 2255 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5e982f3b 2256 features &= ~NETIF_F_RXCSUM;
38912bdb
DS		 2257 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2258 features &= ~NETIF_F_IPV6_CSUM;
5e982f3b
MM		 2259 if (!priv->plat->tx_coe)
2260 features &= ~NETIF_F_ALL_CSUM;
2261
ebbb293f
GC		 2262 /* Some GMAC devices have a bugged Jumbo frame support that
2263 * needs to have the Tx COE disabled for oversized frames
2264 * (due to limited buffer sizes). In this case we disable
ceb69499
GC		 2265 * the TX csum insertionin the TDES and not use SF.
2266 */
5e982f3b
MM		 2267 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2268 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 2269
5e982f3b 2270 return features;
47dd7a54
GC		 2271}
2272
32ceabca
GC		 2273/**
2274 * stmmac_interrupt - main ISR
2275 * @irq: interrupt number.
2276 * @dev_id: to pass the net device pointer.
2277 * Description: this is the main driver interrupt service routine.
2278 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2279 * interrupts.
2280 */
47dd7a54
GC		 2281static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2282{
2283 struct net_device *dev = (struct net_device *)dev_id;
2284 struct stmmac_priv *priv = netdev_priv(dev);
2285
2286 if (unlikely(!dev)) {
2287 pr_err("%s: invalid dev pointer\n", __func__);
2288 return IRQ_NONE;
2289 }
2290
d765955d
GC		 2291 /* To handle GMAC own interrupts */
2292 if (priv->plat->has_gmac) {
2293 int status = priv->hw->mac->host_irq_status((void __iomem *)
0982a0f6
GC		 2294 dev->base_addr,
2295 &priv->xstats);
d765955d 2296 if (unlikely(status)) {
d765955d 2297 /* For LPI we need to save the tx status */
0982a0f6 2298 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
d765955d 2299 priv->tx_path_in_lpi_mode = true;
0982a0f6 2300 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
d765955d 2301 priv->tx_path_in_lpi_mode = false;
d765955d
GC		 2302 }
2303 }
aec7ff27 2304
d765955d 2305 /* To handle DMA interrupts */
aec7ff27 2306 stmmac_dma_interrupt(priv);
47dd7a54
GC		 2307
2308 return IRQ_HANDLED;
2309}
2310
2311#ifdef CONFIG_NET_POLL_CONTROLLER
2312/* Polling receive - used by NETCONSOLE and other diagnostic tools
ceb69499
GC		 2313 * to allow network I/O with interrupts disabled.
2314 */
47dd7a54
GC		 2315static void stmmac_poll_controller(struct net_device *dev)
2316{
2317 disable_irq(dev->irq);
2318 stmmac_interrupt(dev->irq, dev);
2319 enable_irq(dev->irq);
2320}
2321#endif
2322
2323/**
2324 * stmmac_ioctl - Entry point for the Ioctl
2325 * @dev: Device pointer.
2326 * @rq: An IOCTL specefic structure, that can contain a pointer to
2327 * a proprietary structure used to pass information to the driver.
2328 * @cmd: IOCTL command
2329 * Description:
32ceabca 2330 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
47dd7a54
GC		 2331 */
2332static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2333{
2334 struct stmmac_priv *priv = netdev_priv(dev);
891434b1 2335 int ret = -EOPNOTSUPP;
47dd7a54
GC		 2336
2337 if (!netif_running(dev))
2338 return -EINVAL;
2339
891434b1
RK		 2340 switch (cmd) {
2341 case SIOCGMIIPHY:
2342 case SIOCGMIIREG:
2343 case SIOCSMIIREG:
2344 if (!priv->phydev)
2345 return -EINVAL;
2346 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2347 break;
2348 case SIOCSHWTSTAMP:
2349 ret = stmmac_hwtstamp_ioctl(dev, rq);
2350 break;
2351 default:
2352 break;
2353 }
28b04113 2354
47dd7a54
GC		 2355 return ret;
2356}
2357
7ac29055
GC		 2358#ifdef CONFIG_STMMAC_DEBUG_FS
2359static struct dentry *stmmac_fs_dir;
2360static struct dentry *stmmac_rings_status;
e7434821 2361static struct dentry *stmmac_dma_cap;
7ac29055 2362
c24602ef 2363static void sysfs_display_ring(void *head, int size, int extend_desc,
ceb69499 2364 struct seq_file *seq)
7ac29055 2365{
7ac29055 2366 int i;
ceb69499
GC		 2367 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2368 struct dma_desc *p = (struct dma_desc *)head;
7ac29055 2369
c24602ef
GC		 2370 for (i = 0; i < size; i++) {
2371 u64 x;
2372 if (extend_desc) {
2373 x = *(u64 *) ep;
2374 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 2375 i, (unsigned int)virt_to_phys(ep),
2376 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 2377 ep->basic.des2, ep->basic.des3);
2378 ep++;
2379 } else {
2380 x = *(u64 *) p;
2381 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 2382 i, (unsigned int)virt_to_phys(ep),
2383 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 2384 p->des2, p->des3);
2385 p++;
2386 }
7ac29055
GC		 2387 seq_printf(seq, "\n");
2388 }
c24602ef 2389}
7ac29055 2390
c24602ef
GC		 2391static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2392{
2393 struct net_device *dev = seq->private;
2394 struct stmmac_priv *priv = netdev_priv(dev);
2395 unsigned int txsize = priv->dma_tx_size;
2396 unsigned int rxsize = priv->dma_rx_size;
7ac29055 2397
c24602ef
GC		 2398 if (priv->extend_desc) {
2399 seq_printf(seq, "Extended RX descriptor ring:\n");
ceb69499 2400 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
c24602ef 2401 seq_printf(seq, "Extended TX descriptor ring:\n");
ceb69499 2402 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
c24602ef
GC		 2403 } else {
2404 seq_printf(seq, "RX descriptor ring:\n");
2405 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2406 seq_printf(seq, "TX descriptor ring:\n");
2407 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
7ac29055
GC		 2408 }
2409
2410 return 0;
2411}
2412
2413static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2414{
2415 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2416}
2417
2418static const struct file_operations stmmac_rings_status_fops = {
2419 .owner = THIS_MODULE,
2420 .open = stmmac_sysfs_ring_open,
2421 .read = seq_read,
2422 .llseek = seq_lseek,
74863948 2423 .release = single_release,
7ac29055
GC		 2424};
2425
e7434821
GC		 2426static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2427{
2428 struct net_device *dev = seq->private;
2429 struct stmmac_priv *priv = netdev_priv(dev);
2430
19e30c14 2431 if (!priv->hw_cap_support) {
e7434821
GC		 2432 seq_printf(seq, "DMA HW features not supported\n");
2433 return 0;
2434 }
2435
2436 seq_printf(seq, "==============================\n");
2437 seq_printf(seq, "\tDMA HW features\n");
2438 seq_printf(seq, "==============================\n");
2439
2440 seq_printf(seq, "\t10/100 Mbps %s\n",
2441 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2442 seq_printf(seq, "\t1000 Mbps %s\n",
2443 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2444 seq_printf(seq, "\tHalf duple %s\n",
2445 (priv->dma_cap.half_duplex) ? "Y" : "N");
2446 seq_printf(seq, "\tHash Filter: %s\n",
2447 (priv->dma_cap.hash_filter) ? "Y" : "N");
2448 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2449 (priv->dma_cap.multi_addr) ? "Y" : "N");
2450 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2451 (priv->dma_cap.pcs) ? "Y" : "N");
2452 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2453 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2454 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2455 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2456 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2457 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2458 seq_printf(seq, "\tRMON module: %s\n",
2459 (priv->dma_cap.rmon) ? "Y" : "N");
2460 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2461 (priv->dma_cap.time_stamp) ? "Y" : "N");
2462 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2463 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2464 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2465 (priv->dma_cap.eee) ? "Y" : "N");
2466 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2467 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2468 (priv->dma_cap.tx_coe) ? "Y" : "N");
2469 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2470 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2471 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2472 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2473 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2474 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2475 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2476 priv->dma_cap.number_rx_channel);
2477 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2478 priv->dma_cap.number_tx_channel);
2479 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2480 (priv->dma_cap.enh_desc) ? "Y" : "N");
2481
2482 return 0;
2483}
2484
2485static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2486{
2487 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2488}
2489
2490static const struct file_operations stmmac_dma_cap_fops = {
2491 .owner = THIS_MODULE,
2492 .open = stmmac_sysfs_dma_cap_open,
2493 .read = seq_read,
2494 .llseek = seq_lseek,
74863948 2495 .release = single_release,
e7434821
GC		 2496};
2497
7ac29055
GC		 2498static int stmmac_init_fs(struct net_device *dev)
2499{
2500 /* Create debugfs entries */
2501 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2502
2503 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2504 pr_err("ERROR %s, debugfs create directory failed\n",
2505 STMMAC_RESOURCE_NAME);
2506
2507 return -ENOMEM;
2508 }
2509
2510 /* Entry to report DMA RX/TX rings */
2511 stmmac_rings_status = debugfs_create_file("descriptors_status",
ceb69499
GC		 2512 S_IRUGO, stmmac_fs_dir, dev,
2513 &stmmac_rings_status_fops);
7ac29055
GC		 2514
2515 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2516 pr_info("ERROR creating stmmac ring debugfs file\n");
2517 debugfs_remove(stmmac_fs_dir);
2518
2519 return -ENOMEM;
2520 }
2521
e7434821
GC		 2522 /* Entry to report the DMA HW features */
2523 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2524 dev, &stmmac_dma_cap_fops);
2525
2526 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2527 pr_info("ERROR creating stmmac MMC debugfs file\n");
2528 debugfs_remove(stmmac_rings_status);
2529 debugfs_remove(stmmac_fs_dir);
2530
2531 return -ENOMEM;
2532 }
2533
7ac29055
GC		 2534 return 0;
2535}
2536
2537static void stmmac_exit_fs(void)
2538{
2539 debugfs_remove(stmmac_rings_status);
e7434821 2540 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 2541 debugfs_remove(stmmac_fs_dir);
2542}
2543#endif /* CONFIG_STMMAC_DEBUG_FS */
2544
47dd7a54
GC		 2545static const struct net_device_ops stmmac_netdev_ops = {
2546 .ndo_open = stmmac_open,
2547 .ndo_start_xmit = stmmac_xmit,
2548 .ndo_stop = stmmac_release,
2549 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 2550 .ndo_fix_features = stmmac_fix_features,
01789349 2551 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 2552 .ndo_tx_timeout = stmmac_tx_timeout,
2553 .ndo_do_ioctl = stmmac_ioctl,
2554 .ndo_set_config = stmmac_config,
47dd7a54
GC		 2555#ifdef CONFIG_NET_POLL_CONTROLLER
2556 .ndo_poll_controller = stmmac_poll_controller,
2557#endif
2558 .ndo_set_mac_address = eth_mac_addr,
2559};
2560
cf3f047b
GC		 2561/**
2562 * stmmac_hw_init - Init the MAC device
32ceabca 2563 * @priv: driver private structure
cf3f047b
GC		 2564 * Description: this function detects which MAC device
2565 * (GMAC/MAC10-100) has to attached, checks the HW capability
2566 * (if supported) and sets the driver's features (for example
2567 * to use the ring or chaine mode or support the normal/enh
2568 * descriptor structure).
2569 */
2570static int stmmac_hw_init(struct stmmac_priv *priv)
2571{
c24602ef 2572 int ret;
cf3f047b
GC		 2573 struct mac_device_info *mac;
2574
2575 /* Identify the MAC HW device */
03f2eecd
MKB		 2576 if (priv->plat->has_gmac) {
2577 priv->dev->priv_flags |= IFF_UNICAST_FLT;
cf3f047b 2578 mac = dwmac1000_setup(priv->ioaddr);
03f2eecd 2579 } else {
cf3f047b 2580 mac = dwmac100_setup(priv->ioaddr);
03f2eecd 2581 }
cf3f047b
GC		 2582 if (!mac)
2583 return -ENOMEM;
2584
2585 priv->hw = mac;
2586
cf3f047b 2587 /* Get and dump the chip ID */
cffb13f4 2588 priv->synopsys_id = stmmac_get_synopsys_id(priv);
cf3f047b 2589
4a7d666a 2590 /* To use the chained or ring mode */
ceb69499 2591 if (chain_mode) {
4a7d666a
GC		 2592 priv->hw->chain = &chain_mode_ops;
2593 pr_info(" Chain mode enabled\n");
2594 priv->mode = STMMAC_CHAIN_MODE;
2595 } else {
2596 priv->hw->ring = &ring_mode_ops;
2597 pr_info(" Ring mode enabled\n");
2598 priv->mode = STMMAC_RING_MODE;
2599 }
2600
cf3f047b
GC		 2601 /* Get the HW capability (new GMAC newer than 3.50a) */
2602 priv->hw_cap_support = stmmac_get_hw_features(priv);
2603 if (priv->hw_cap_support) {
2604 pr_info(" DMA HW capability register supported");
2605
2606 /* We can override some gmac/dma configuration fields: e.g.
2607 * enh_desc, tx_coe (e.g. that are passed through the
2608 * platform) with the values from the HW capability
2609 * register (if supported).
2610 */
2611 priv->plat->enh_desc = priv->dma_cap.enh_desc;
cf3f047b 2612 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
38912bdb
DS		 2613
2614 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2615
2616 if (priv->dma_cap.rx_coe_type2)
2617 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2618 else if (priv->dma_cap.rx_coe_type1)
2619 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2620
cf3f047b
GC		 2621 } else
2622 pr_info(" No HW DMA feature register supported");
2623
61369d02
BA		 2624 /* To use alternate (extended) or normal descriptor structures */
2625 stmmac_selec_desc_mode(priv);
2626
38912bdb
DS		 2627 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2628 if (!ret) {
ceb69499 2629 pr_warn(" RX IPC Checksum Offload not configured.\n");
38912bdb
DS		 2630 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2631 }
2632
2633 if (priv->plat->rx_coe)
2634 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2635 priv->plat->rx_coe);
cf3f047b
GC		 2636 if (priv->plat->tx_coe)
2637 pr_info(" TX Checksum insertion supported\n");
2638
2639 if (priv->plat->pmt) {
2640 pr_info(" Wake-Up On Lan supported\n");
2641 device_set_wakeup_capable(priv->device, 1);
2642 }
2643
c24602ef 2644 return 0;
cf3f047b
GC		 2645}
2646
47dd7a54 2647/**
bfab27a1
GC		 2648 * stmmac_dvr_probe
2649 * @device: device pointer
ff3dd78c
GC		 2650 * @plat_dat: platform data pointer
2651 * @addr: iobase memory address
bfab27a1
GC		 2652 * Description: this is the main probe function used to
2653 * call the alloc_etherdev, allocate the priv structure.
47dd7a54 2654 */
bfab27a1 2655struct stmmac_priv *stmmac_dvr_probe(struct device *device,
cf3f047b
GC		 2656 struct plat_stmmacenet_data *plat_dat,
2657 void __iomem *addr)
47dd7a54
GC		 2658{
2659 int ret = 0;
bfab27a1
GC		 2660 struct net_device *ndev = NULL;
2661 struct stmmac_priv *priv;
47dd7a54 2662
bfab27a1 2663 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
41de8d4c 2664 if (!ndev)
bfab27a1 2665 return NULL;
bfab27a1
GC		 2666
2667 SET_NETDEV_DEV(ndev, device);
2668
2669 priv = netdev_priv(ndev);
2670 priv->device = device;
2671 priv->dev = ndev;
47dd7a54 2672
bfab27a1 2673 ether_setup(ndev);
47dd7a54 2674
bfab27a1 2675 stmmac_set_ethtool_ops(ndev);
cf3f047b
GC		 2676 priv->pause = pause;
2677 priv->plat = plat_dat;
2678 priv->ioaddr = addr;
2679 priv->dev->base_addr = (unsigned long)addr;
2680
2681 /* Verify driver arguments */
2682 stmmac_verify_args();
bfab27a1 2683
cf3f047b 2684 /* Override with kernel parameters if supplied XXX CRS XXX
ceb69499
GC		 2685 * this needs to have multiple instances
2686 */
cf3f047b
GC		 2687 if ((phyaddr >= 0) && (phyaddr <= 31))
2688 priv->plat->phy_addr = phyaddr;
2689
2690 /* Init MAC and get the capabilities */
c24602ef
GC		 2691 ret = stmmac_hw_init(priv);
2692 if (ret)
2693 goto error_free_netdev;
cf3f047b
GC		 2694
2695 ndev->netdev_ops = &stmmac_netdev_ops;
bfab27a1 2696
cf3f047b
GC		 2697 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2698 NETIF_F_RXCSUM;
bfab27a1
GC		 2699 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2700 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
47dd7a54
GC		 2701#ifdef STMMAC_VLAN_TAG_USED
2702 /* Both mac100 and gmac support receive VLAN tag detection */
f646968f 2703 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
47dd7a54
GC		 2704#endif
2705 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2706
47dd7a54
GC		 2707 if (flow_ctrl)
2708 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2709
62a2ab93
GC		 2710 /* Rx Watchdog is available in the COREs newer than the 3.40.
2711 * In some case, for example on bugged HW this feature
2712 * has to be disable and this can be done by passing the
2713 * riwt_off field from the platform.
2714 */
2715 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2716 priv->use_riwt = 1;
2717 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2718 }
2719
bfab27a1 2720 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
47dd7a54 2721
f8e96161 2722 spin_lock_init(&priv->lock);
a9097a96 2723 spin_lock_init(&priv->tx_lock);
f8e96161 2724
bfab27a1 2725 ret = register_netdev(ndev);
47dd7a54 2726 if (ret) {
cf3f047b 2727 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
6a81c26f 2728 goto error_netdev_register;
47dd7a54
GC		 2729 }
2730
ae4d8cf2 2731 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
6a81c26f 2732 if (IS_ERR(priv->stmmac_clk)) {
ceb69499 2733 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
6a81c26f
VK		 2734 goto error_clk_get;
2735 }
ba1377ff 2736
cd7201f4
GC		 2737 /* If a specific clk_csr value is passed from the platform
2738 * this means that the CSR Clock Range selection cannot be
2739 * changed at run-time and it is fixed. Viceversa the driver'll try to
2740 * set the MDC clock dynamically according to the csr actual
2741 * clock input.
2742 */
2743 if (!priv->plat->clk_csr)
2744 stmmac_clk_csr_set(priv);
2745 else
2746 priv->clk_csr = priv->plat->clk_csr;
2747
e58bb43f
GC		 2748 stmmac_check_pcs_mode(priv);
2749
4d8f0825
BA		 2750 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2751 priv->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 2752 /* MDIO bus Registration */
2753 ret = stmmac_mdio_register(ndev);
2754 if (ret < 0) {
2755 pr_debug("%s: MDIO bus (id: %d) registration failed",
2756 __func__, priv->plat->bus_id);
2757 goto error_mdio_register;
2758 }
4bfcbd7a
FV		 2759 }
2760
bfab27a1 2761 return priv;
47dd7a54 2762
6a81c26f
VK		 2763error_mdio_register:
2764 clk_put(priv->stmmac_clk);
2765error_clk_get:
34a52f36 2766 unregister_netdev(ndev);
6a81c26f
VK		 2767error_netdev_register:
2768 netif_napi_del(&priv->napi);
c24602ef 2769error_free_netdev:
34a52f36 2770 free_netdev(ndev);
47dd7a54 2771
bfab27a1 2772 return NULL;
47dd7a54
GC		 2773}
2774
2775/**
2776 * stmmac_dvr_remove
bfab27a1 2777 * @ndev: net device pointer
47dd7a54 2778 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
bfab27a1 2779 * changes the link status, releases the DMA descriptor rings.
47dd7a54 2780 */
bfab27a1 2781int stmmac_dvr_remove(struct net_device *ndev)
47dd7a54 2782{
aec7ff27 2783 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 2784
2785 pr_info("%s:\n\tremoving driver", __func__);
2786
ad01b7d4
GC		 2787 priv->hw->dma->stop_rx(priv->ioaddr);
2788 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 2789
bfab27a1 2790 stmmac_set_mac(priv->ioaddr, false);
4d8f0825
BA		 2791 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2792 priv->pcs != STMMAC_PCS_RTBI)
e58bb43f 2793 stmmac_mdio_unregister(ndev);
47dd7a54 2794 netif_carrier_off(ndev);
47dd7a54 2795 unregister_netdev(ndev);
47dd7a54
GC		 2796 free_netdev(ndev);
2797
2798 return 0;
2799}
2800
2801#ifdef CONFIG_PM
bfab27a1 2802int stmmac_suspend(struct net_device *ndev)
47dd7a54 2803{
874bd42d 2804 struct stmmac_priv *priv = netdev_priv(ndev);
f8c5a875 2805 unsigned long flags;
47dd7a54 2806
874bd42d 2807 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 2808 return 0;
2809
102463b1
FV		 2810 if (priv->phydev)
2811 phy_stop(priv->phydev);
2812
f8c5a875 2813 spin_lock_irqsave(&priv->lock, flags);
47dd7a54 2814
874bd42d
GC		 2815 netif_device_detach(ndev);
2816 netif_stop_queue(ndev);
47dd7a54 2817
874bd42d
GC		 2818 napi_disable(&priv->napi);
2819
2820 /* Stop TX/RX DMA */
2821 priv->hw->dma->stop_tx(priv->ioaddr);
2822 priv->hw->dma->stop_rx(priv->ioaddr);
c24602ef
GC		 2823
2824 stmmac_clear_descriptors(priv);
874bd42d
GC		 2825
2826 /* Enable Power down mode by programming the PMT regs */
2827 if (device_may_wakeup(priv->device))
2828 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
ba1377ff 2829 else {
bfab27a1 2830 stmmac_set_mac(priv->ioaddr, false);
ba1377ff 2831 /* Disable clock in case of PWM is off */
a630844d 2832 clk_disable_unprepare(priv->stmmac_clk);
ba1377ff 2833 }
f8c5a875 2834 spin_unlock_irqrestore(&priv->lock, flags);
47dd7a54
GC		 2835 return 0;
2836}
2837
bfab27a1 2838int stmmac_resume(struct net_device *ndev)
47dd7a54 2839{
874bd42d 2840 struct stmmac_priv *priv = netdev_priv(ndev);
f8c5a875 2841 unsigned long flags;
47dd7a54 2842
874bd42d 2843 if (!netif_running(ndev))
47dd7a54
GC		 2844 return 0;
2845
f8c5a875 2846 spin_lock_irqsave(&priv->lock, flags);
c4433be6 2847
47dd7a54
GC		 2848 /* Power Down bit, into the PM register, is cleared
2849 * automatically as soon as a magic packet or a Wake-up frame
2850 * is received. Anyway, it's better to manually clear
2851 * this bit because it can generate problems while resuming
ceb69499
GC		 2852 * from another devices (e.g. serial console).
2853 */
874bd42d 2854 if (device_may_wakeup(priv->device))
543876c9 2855 priv->hw->mac->pmt(priv->ioaddr, 0);
ba1377ff
GC		 2856 else
2857 /* enable the clk prevously disabled */
a630844d 2858 clk_prepare_enable(priv->stmmac_clk);
47dd7a54 2859
874bd42d 2860 netif_device_attach(ndev);
47dd7a54
GC		 2861
2862 /* Enable the MAC and DMA */
bfab27a1 2863 stmmac_set_mac(priv->ioaddr, true);
ad01b7d4
GC		 2864 priv->hw->dma->start_tx(priv->ioaddr);
2865 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54 2866
47dd7a54
GC		 2867 napi_enable(&priv->napi);
2868
874bd42d 2869 netif_start_queue(ndev);
47dd7a54 2870
f8c5a875 2871 spin_unlock_irqrestore(&priv->lock, flags);
102463b1
FV		 2872
2873 if (priv->phydev)
2874 phy_start(priv->phydev);
2875
47dd7a54
GC		 2876 return 0;
2877}
47dd7a54 2878
bfab27a1 2879int stmmac_freeze(struct net_device *ndev)
874bd42d 2880{
874bd42d
GC		 2881 if (!ndev || !netif_running(ndev))
2882 return 0;
2883
2884 return stmmac_release(ndev);
2885}
2886
bfab27a1 2887int stmmac_restore(struct net_device *ndev)
874bd42d 2888{
874bd42d
GC		 2889 if (!ndev || !netif_running(ndev))
2890 return 0;
2891
2892 return stmmac_open(ndev);
2893}
874bd42d 2894#endif /* CONFIG_PM */
47dd7a54 2895
33d5e332
GC		 2896/* Driver can be configured w/ and w/ both PCI and Platf drivers
2897 * depending on the configuration selected.
2898 */
ba27ec66
GC		 2899static int __init stmmac_init(void)
2900{
493682b8 2901 int ret;
ba27ec66 2902
493682b8
KK		 2903 ret = stmmac_register_platform();
2904 if (ret)
2905 goto err;
2906 ret = stmmac_register_pci();
2907 if (ret)
2908 goto err_pci;
33d5e332 2909 return 0;
493682b8
KK		 2910err_pci:
2911 stmmac_unregister_platform();
2912err:
2913 pr_err("stmmac: driver registration failed\n");
2914 return ret;
ba27ec66
GC		 2915}
2916
2917static void __exit stmmac_exit(void)
2918{
33d5e332
GC		 2919 stmmac_unregister_platform();
2920 stmmac_unregister_pci();
ba27ec66
GC		 2921}
2922
2923module_init(stmmac_init);
2924module_exit(stmmac_exit);
2925
47dd7a54
GC		 2926#ifndef MODULE
2927static int __init stmmac_cmdline_opt(char *str)
2928{
2929 char *opt;
2930
2931 if (!str || !*str)
2932 return -EINVAL;
2933 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28 2934 if (!strncmp(opt, "debug:", 6)) {
ea2ab871 2935 if (kstrtoint(opt + 6, 0, &debug))
f3240e28
GC		 2936 goto err;
2937 } else if (!strncmp(opt, "phyaddr:", 8)) {
ea2ab871 2938 if (kstrtoint(opt + 8, 0, &phyaddr))
f3240e28
GC		 2939 goto err;
2940 } else if (!strncmp(opt, "dma_txsize:", 11)) {
ea2ab871 2941 if (kstrtoint(opt + 11, 0, &dma_txsize))
f3240e28
GC		 2942 goto err;
2943 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
ea2ab871 2944 if (kstrtoint(opt + 11, 0, &dma_rxsize))
f3240e28
GC		 2945 goto err;
2946 } else if (!strncmp(opt, "buf_sz:", 7)) {
ea2ab871 2947 if (kstrtoint(opt + 7, 0, &buf_sz))
f3240e28
GC		 2948 goto err;
2949 } else if (!strncmp(opt, "tc:", 3)) {
ea2ab871 2950 if (kstrtoint(opt + 3, 0, &tc))
f3240e28
GC		 2951 goto err;
2952 } else if (!strncmp(opt, "watchdog:", 9)) {
ea2ab871 2953 if (kstrtoint(opt + 9, 0, &watchdog))
f3240e28
GC		 2954 goto err;
2955 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
ea2ab871 2956 if (kstrtoint(opt + 10, 0, &flow_ctrl))
f3240e28
GC		 2957 goto err;
2958 } else if (!strncmp(opt, "pause:", 6)) {
ea2ab871 2959 if (kstrtoint(opt + 6, 0, &pause))
f3240e28 2960 goto err;
506f669c 2961 } else if (!strncmp(opt, "eee_timer:", 10)) {
d765955d
GC		 2962 if (kstrtoint(opt + 10, 0, &eee_timer))
2963 goto err;
4a7d666a
GC		 2964 } else if (!strncmp(opt, "chain_mode:", 11)) {
2965 if (kstrtoint(opt + 11, 0, &chain_mode))
2966 goto err;
f3240e28 2967 }
47dd7a54
GC		 2968 }
2969 return 0;
f3240e28
GC		 2970
2971err:
2972 pr_err("%s: ERROR broken module parameter conversion", __func__);
2973 return -EINVAL;
47dd7a54
GC		 2974}
2975
2976__setup("stmmaceth=", stmmac_cmdline_opt);
ceb69499 2977#endif /* MODULE */
6fc0d0f2
GC		 2978
2979MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2980MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2981MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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