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net: introduce IFF_UNICAST_FLT private flag
[deliverable/linux.git] / drivers / net / ethernet / sun / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
a6b7a407 10#include <linux/interrupt.h>
a3138df9
DM		 11#include <linux/pci.h>
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/ethtool.h>
15#include <linux/etherdevice.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/bitops.h>
19#include <linux/mii.h>
01789349 20#include <linux/if.h>
a3138df9
DM		 21#include <linux/if_ether.h>
22#include <linux/if_vlan.h>
23#include <linux/ip.h>
24#include <linux/in.h>
25#include <linux/ipv6.h>
26#include <linux/log2.h>
27#include <linux/jiffies.h>
28#include <linux/crc32.h>
ccffad25 29#include <linux/list.h>
5a0e3ad6 30#include <linux/slab.h>
a3138df9
DM		 31
32#include <linux/io.h>
a3138df9 33#include <linux/of_device.h>
a3138df9
DM		 34
35#include "niu.h"
36
37#define DRV_MODULE_NAME "niu"
3cfa856d
DM		 38#define DRV_MODULE_VERSION "1.1"
39#define DRV_MODULE_RELDATE "Apr 22, 2010"
a3138df9
DM		 40
41static char version[] __devinitdata =
42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
43
44MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
45MODULE_DESCRIPTION("NIU ethernet driver");
46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
a3138df9
DM		 49#ifndef readq
50static u64 readq(void __iomem *reg)
51{
e23a59e1 52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 53}
54
55static void writeq(u64 val, void __iomem *reg)
56{
57 writel(val & 0xffffffff, reg);
58 writel(val >> 32, reg + 0x4UL);
59}
60#endif
61
a3aa1884 62static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
64 {}
65};
66
67MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
68
69#define NIU_TX_TIMEOUT (5 * HZ)
70
71#define nr64(reg) readq(np->regs + (reg))
72#define nw64(reg, val) writeq((val), np->regs + (reg))
73
74#define nr64_mac(reg) readq(np->mac_regs + (reg))
75#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
76
77#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
78#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
79
80#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
81#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
82
83#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
84#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
85
86#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
87
88static int niu_debug;
89static int debug = -1;
90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "NIU debug level");
92
a3138df9
DM		 93#define niu_lock_parent(np, flags) \
94 spin_lock_irqsave(&np->parent->lock, flags)
95#define niu_unlock_parent(np, flags) \
96 spin_unlock_irqrestore(&np->parent->lock, flags)
97
5fbd7e24
MW		 98static int serdes_init_10g_serdes(struct niu *np);
99
a3138df9
DM		 100static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
101 u64 bits, int limit, int delay)
102{
103 while (--limit >= 0) {
104 u64 val = nr64_mac(reg);
105
106 if (!(val & bits))
107 break;
108 udelay(delay);
109 }
110 if (limit < 0)
111 return -ENODEV;
112 return 0;
113}
114
115static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
116 u64 bits, int limit, int delay,
117 const char *reg_name)
118{
119 int err;
120
121 nw64_mac(reg, bits);
122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
123 if (err)
f10a1f2e
JP		 124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
125 (unsigned long long)bits, reg_name,
126 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 127 return err;
128}
129
130#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
131({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
133})
134
135static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
136 u64 bits, int limit, int delay)
137{
138 while (--limit >= 0) {
139 u64 val = nr64_ipp(reg);
140
141 if (!(val & bits))
142 break;
143 udelay(delay);
144 }
145 if (limit < 0)
146 return -ENODEV;
147 return 0;
148}
149
150static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
151 u64 bits, int limit, int delay,
152 const char *reg_name)
153{
154 int err;
155 u64 val;
156
157 val = nr64_ipp(reg);
158 val |= bits;
159 nw64_ipp(reg, val);
160
161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
162 if (err)
f10a1f2e
JP		 163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
164 (unsigned long long)bits, reg_name,
165 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 166 return err;
167}
168
169#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
170({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
172})
173
174static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
175 u64 bits, int limit, int delay)
176{
177 while (--limit >= 0) {
178 u64 val = nr64(reg);
179
180 if (!(val & bits))
181 break;
182 udelay(delay);
183 }
184 if (limit < 0)
185 return -ENODEV;
186 return 0;
187}
188
189#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
190({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
192})
193
194static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay,
196 const char *reg_name)
197{
198 int err;
199
200 nw64(reg, bits);
201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
202 if (err)
f10a1f2e
JP		 203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
204 (unsigned long long)bits, reg_name,
205 (unsigned long long)nr64(reg));
a3138df9
DM		 206 return err;
207}
208
209#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
210({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
212})
213
214static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
215{
216 u64 val = (u64) lp->timer;
217
218 if (on)
219 val |= LDG_IMGMT_ARM;
220
221 nw64(LDG_IMGMT(lp->ldg_num), val);
222}
223
224static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
225{
226 unsigned long mask_reg, bits;
227 u64 val;
228
229 if (ldn < 0 || ldn > LDN_MAX)
230 return -EINVAL;
231
232 if (ldn < 64) {
233 mask_reg = LD_IM0(ldn);
234 bits = LD_IM0_MASK;
235 } else {
236 mask_reg = LD_IM1(ldn - 64);
237 bits = LD_IM1_MASK;
238 }
239
240 val = nr64(mask_reg);
241 if (on)
242 val &= ~bits;
243 else
244 val |= bits;
245 nw64(mask_reg, val);
246
247 return 0;
248}
249
250static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
251{
252 struct niu_parent *parent = np->parent;
253 int i;
254
255 for (i = 0; i <= LDN_MAX; i++) {
256 int err;
257
258 if (parent->ldg_map[i] != lp->ldg_num)
259 continue;
260
261 err = niu_ldn_irq_enable(np, i, on);
262 if (err)
263 return err;
264 }
265 return 0;
266}
267
268static int niu_enable_interrupts(struct niu *np, int on)
269{
270 int i;
271
272 for (i = 0; i < np->num_ldg; i++) {
273 struct niu_ldg *lp = &np->ldg[i];
274 int err;
275
276 err = niu_enable_ldn_in_ldg(np, lp, on);
277 if (err)
278 return err;
279 }
280 for (i = 0; i < np->num_ldg; i++)
281 niu_ldg_rearm(np, &np->ldg[i], on);
282
283 return 0;
284}
285
286static u32 phy_encode(u32 type, int port)
287{
807540ba 288 return type << (port * 2);
a3138df9
DM		 289}
290
291static u32 phy_decode(u32 val, int port)
292{
293 return (val >> (port * 2)) & PORT_TYPE_MASK;
294}
295
296static int mdio_wait(struct niu *np)
297{
298 int limit = 1000;
299 u64 val;
300
301 while (--limit > 0) {
302 val = nr64(MIF_FRAME_OUTPUT);
303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
304 return val & MIF_FRAME_OUTPUT_DATA;
305
306 udelay(10);
307 }
308
309 return -ENODEV;
310}
311
312static int mdio_read(struct niu *np, int port, int dev, int reg)
313{
314 int err;
315
316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
317 err = mdio_wait(np);
318 if (err < 0)
319 return err;
320
321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
322 return mdio_wait(np);
323}
324
325static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
326{
327 int err;
328
329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
330 err = mdio_wait(np);
331 if (err < 0)
332 return err;
333
334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
335 err = mdio_wait(np);
336 if (err < 0)
337 return err;
338
339 return 0;
340}
341
342static int mii_read(struct niu *np, int port, int reg)
343{
344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
345 return mdio_wait(np);
346}
347
348static int mii_write(struct niu *np, int port, int reg, int data)
349{
350 int err;
351
352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
353 err = mdio_wait(np);
354 if (err < 0)
355 return err;
356
357 return 0;
358}
359
360static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
361{
362 int err;
363
364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
365 ESR2_TI_PLL_TX_CFG_L(channel),
366 val & 0xffff);
367 if (!err)
368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
369 ESR2_TI_PLL_TX_CFG_H(channel),
370 val >> 16);
371 return err;
372}
373
374static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
375{
376 int err;
377
378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
379 ESR2_TI_PLL_RX_CFG_L(channel),
380 val & 0xffff);
381 if (!err)
382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
383 ESR2_TI_PLL_RX_CFG_H(channel),
384 val >> 16);
385 return err;
386}
387
388/* Mode is always 10G fiber. */
e3e081e1 389static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 390{
391 struct niu_link_config *lp = &np->link_config;
392 u32 tx_cfg, rx_cfg;
393 unsigned long i;
394
395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
398 PLL_RX_CFG_EQ_LP_ADAPTIVE);
399
400 if (lp->loopback_mode == LOOPBACK_PHY) {
401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
402
403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
405
406 tx_cfg |= PLL_TX_CFG_ENTEST;
407 rx_cfg |= PLL_RX_CFG_ENTEST;
408 }
409
410 /* Initialize all 4 lanes of the SERDES. */
411 for (i = 0; i < 4; i++) {
412 int err = esr2_set_tx_cfg(np, i, tx_cfg);
413 if (err)
414 return err;
415 }
416
417 for (i = 0; i < 4; i++) {
418 int err = esr2_set_rx_cfg(np, i, rx_cfg);
419 if (err)
420 return err;
421 }
422
423 return 0;
424}
425
e3e081e1
SB		 426static int serdes_init_niu_1g_serdes(struct niu *np)
427{
428 struct niu_link_config *lp = &np->link_config;
429 u16 pll_cfg, pll_sts;
430 int max_retry = 100;
51e0f058 431 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 432 u32 tx_cfg, rx_cfg;
433 unsigned long i;
434 int err;
435
436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
437 PLL_TX_CFG_RATE_HALF);
438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
440 PLL_RX_CFG_RATE_HALF);
441
442 if (np->port == 0)
443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
444
445 if (lp->loopback_mode == LOOPBACK_PHY) {
446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
447
448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
449 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
450
451 tx_cfg |= PLL_TX_CFG_ENTEST;
452 rx_cfg |= PLL_RX_CFG_ENTEST;
453 }
454
455 /* Initialize PLL for 1G */
456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
457
458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
459 ESR2_TI_PLL_CFG_L, pll_cfg);
460 if (err) {
f10a1f2e
JP		 461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
462 np->port, __func__);
e3e081e1
SB		 463 return err;
464 }
465
466 pll_sts = PLL_CFG_ENPLL;
467
468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_STS_L, pll_sts);
470 if (err) {
f10a1f2e
JP		 471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
472 np->port, __func__);
e3e081e1
SB		 473 return err;
474 }
475
476 udelay(200);
477
478 /* Initialize all 4 lanes of the SERDES. */
479 for (i = 0; i < 4; i++) {
480 err = esr2_set_tx_cfg(np, i, tx_cfg);
481 if (err)
482 return err;
483 }
484
485 for (i = 0; i < 4; i++) {
486 err = esr2_set_rx_cfg(np, i, rx_cfg);
487 if (err)
488 return err;
489 }
490
491 switch (np->port) {
492 case 0:
493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
494 mask = val;
495 break;
496
497 case 1:
498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
499 mask = val;
500 break;
501
502 default:
503 return -EINVAL;
504 }
505
506 while (max_retry--) {
507 sig = nr64(ESR_INT_SIGNALS);
508 if ((sig & mask) == val)
509 break;
510
511 mdelay(500);
512 }
513
514 if ((sig & mask) != val) {
f10a1f2e
JP		 515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
516 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 517 return -ENODEV;
518 }
519
520 return 0;
521}
522
523static int serdes_init_niu_10g_serdes(struct niu *np)
524{
525 struct niu_link_config *lp = &np->link_config;
526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
527 int max_retry = 100;
51e0f058 528 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 529 unsigned long i;
530 int err;
531
532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
535 PLL_RX_CFG_EQ_LP_ADAPTIVE);
536
537 if (lp->loopback_mode == LOOPBACK_PHY) {
538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
539
540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
541 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
542
543 tx_cfg |= PLL_TX_CFG_ENTEST;
544 rx_cfg |= PLL_RX_CFG_ENTEST;
545 }
546
547 /* Initialize PLL for 10G */
548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
549
550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
552 if (err) {
f10a1f2e
JP		 553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
554 np->port, __func__);
e3e081e1
SB		 555 return err;
556 }
557
558 pll_sts = PLL_CFG_ENPLL;
559
560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
562 if (err) {
f10a1f2e
JP		 563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
564 np->port, __func__);
e3e081e1
SB		 565 return err;
566 }
567
568 udelay(200);
569
570 /* Initialize all 4 lanes of the SERDES. */
571 for (i = 0; i < 4; i++) {
572 err = esr2_set_tx_cfg(np, i, tx_cfg);
573 if (err)
574 return err;
575 }
576
577 for (i = 0; i < 4; i++) {
578 err = esr2_set_rx_cfg(np, i, rx_cfg);
579 if (err)
580 return err;
581 }
582
583 /* check if serdes is ready */
584
585 switch (np->port) {
586 case 0:
587 mask = ESR_INT_SIGNALS_P0_BITS;
588 val = (ESR_INT_SRDY0_P0 |
589 ESR_INT_DET0_P0 |
590 ESR_INT_XSRDY_P0 |
591 ESR_INT_XDP_P0_CH3 |
592 ESR_INT_XDP_P0_CH2 |
593 ESR_INT_XDP_P0_CH1 |
594 ESR_INT_XDP_P0_CH0);
595 break;
596
597 case 1:
598 mask = ESR_INT_SIGNALS_P1_BITS;
599 val = (ESR_INT_SRDY0_P1 |
600 ESR_INT_DET0_P1 |
601 ESR_INT_XSRDY_P1 |
602 ESR_INT_XDP_P1_CH3 |
603 ESR_INT_XDP_P1_CH2 |
604 ESR_INT_XDP_P1_CH1 |
605 ESR_INT_XDP_P1_CH0);
606 break;
607
608 default:
609 return -EINVAL;
610 }
611
612 while (max_retry--) {
613 sig = nr64(ESR_INT_SIGNALS);
614 if ((sig & mask) == val)
615 break;
616
617 mdelay(500);
618 }
619
620 if ((sig & mask) != val) {
f10a1f2e
JP		 621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
622 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 623
624 /* 10G failed, try initializing at 1G */
625 err = serdes_init_niu_1g_serdes(np);
626 if (!err) {
627 np->flags &= ~NIU_FLAGS_10G;
628 np->mac_xcvr = MAC_XCVR_PCS;
629 } else {
f10a1f2e
JP		 630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
631 np->port);
e3e081e1
SB		 632 return -ENODEV;
633 }
634 }
635 return 0;
636}
637
a3138df9
DM		 638static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
639{
640 int err;
641
642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
643 if (err >= 0) {
644 *val = (err & 0xffff);
645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
646 ESR_RXTX_CTRL_H(chan));
647 if (err >= 0)
648 *val |= ((err & 0xffff) << 16);
649 err = 0;
650 }
651 return err;
652}
653
654static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
655{
656 int err;
657
658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
659 ESR_GLUE_CTRL0_L(chan));
660 if (err >= 0) {
661 *val = (err & 0xffff);
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
663 ESR_GLUE_CTRL0_H(chan));
664 if (err >= 0) {
665 *val |= ((err & 0xffff) << 16);
666 err = 0;
667 }
668 }
669 return err;
670}
671
672static int esr_read_reset(struct niu *np, u32 *val)
673{
674 int err;
675
676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
677 ESR_RXTX_RESET_CTRL_L);
678 if (err >= 0) {
679 *val = (err & 0xffff);
680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
681 ESR_RXTX_RESET_CTRL_H);
682 if (err >= 0) {
683 *val |= ((err & 0xffff) << 16);
684 err = 0;
685 }
686 }
687 return err;
688}
689
690static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
691{
692 int err;
693
694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
695 ESR_RXTX_CTRL_L(chan), val & 0xffff);
696 if (!err)
697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
698 ESR_RXTX_CTRL_H(chan), (val >> 16));
699 return err;
700}
701
702static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
703{
704 int err;
705
706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
707 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
708 if (!err)
709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
710 ESR_GLUE_CTRL0_H(chan), (val >> 16));
711 return err;
712}
713
714static int esr_reset(struct niu *np)
715{
f166400b 716 u32 uninitialized_var(reset);
a3138df9
DM		 717 int err;
718
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_RESET_CTRL_L, 0x0000);
721 if (err)
722 return err;
723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 ESR_RXTX_RESET_CTRL_H, 0xffff);
725 if (err)
726 return err;
727 udelay(200);
728
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
730 ESR_RXTX_RESET_CTRL_L, 0xffff);
731 if (err)
732 return err;
733 udelay(200);
734
735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 ESR_RXTX_RESET_CTRL_H, 0x0000);
737 if (err)
738 return err;
739 udelay(200);
740
741 err = esr_read_reset(np, &reset);
742 if (err)
743 return err;
744 if (reset != 0) {
f10a1f2e
JP		 745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
746 np->port, reset);
a3138df9
DM		 747 return -ENODEV;
748 }
749
750 return 0;
751}
752
753static int serdes_init_10g(struct niu *np)
754{
755 struct niu_link_config *lp = &np->link_config;
756 unsigned long ctrl_reg, test_cfg_reg, i;
757 u64 ctrl_val, test_cfg_val, sig, mask, val;
758 int err;
759
760 switch (np->port) {
761 case 0:
762 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
763 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
764 break;
765 case 1:
766 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
767 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
768 break;
769
770 default:
771 return -EINVAL;
772 }
773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
774 ENET_SERDES_CTRL_SDET_1 |
775 ENET_SERDES_CTRL_SDET_2 |
776 ENET_SERDES_CTRL_SDET_3 |
777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
785 test_cfg_val = 0;
786
787 if (lp->loopback_mode == LOOPBACK_PHY) {
788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_0_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_1_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_2_SHIFT) |
794 (ENET_TEST_MD_PAD_LOOPBACK <<
795 ENET_SERDES_TEST_MD_3_SHIFT));
796 }
797
798 nw64(ctrl_reg, ctrl_val);
799 nw64(test_cfg_reg, test_cfg_val);
800
801 /* Initialize all 4 lanes of the SERDES. */
802 for (i = 0; i < 4; i++) {
803 u32 rxtx_ctrl, glue0;
804
805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
806 if (err)
807 return err;
808 err = esr_read_glue0(np, i, &glue0);
809 if (err)
810 return err;
811
812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
815
816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
817 ESR_GLUE_CTRL0_THCNT |
818 ESR_GLUE_CTRL0_BLTIME);
819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
822 (BLTIME_300_CYCLES <<
823 ESR_GLUE_CTRL0_BLTIME_SHIFT));
824
825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
826 if (err)
827 return err;
828 err = esr_write_glue0(np, i, glue0);
829 if (err)
830 return err;
831 }
832
833 err = esr_reset(np);
834 if (err)
835 return err;
836
837 sig = nr64(ESR_INT_SIGNALS);
838 switch (np->port) {
839 case 0:
840 mask = ESR_INT_SIGNALS_P0_BITS;
841 val = (ESR_INT_SRDY0_P0 |
842 ESR_INT_DET0_P0 |
843 ESR_INT_XSRDY_P0 |
844 ESR_INT_XDP_P0_CH3 |
845 ESR_INT_XDP_P0_CH2 |
846 ESR_INT_XDP_P0_CH1 |
847 ESR_INT_XDP_P0_CH0);
848 break;
849
850 case 1:
851 mask = ESR_INT_SIGNALS_P1_BITS;
852 val = (ESR_INT_SRDY0_P1 |
853 ESR_INT_DET0_P1 |
854 ESR_INT_XSRDY_P1 |
855 ESR_INT_XDP_P1_CH3 |
856 ESR_INT_XDP_P1_CH2 |
857 ESR_INT_XDP_P1_CH1 |
858 ESR_INT_XDP_P1_CH0);
859 break;
860
861 default:
862 return -EINVAL;
863 }
864
865 if ((sig & mask) != val) {
a5d6ab56
MW		 866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
868 return 0;
869 }
f10a1f2e
JP		 870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
871 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 872 return -ENODEV;
873 }
a5d6ab56
MW		 874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 876 return 0;
877}
878
879static int serdes_init_1g(struct niu *np)
880{
881 u64 val;
882
883 val = nr64(ENET_SERDES_1_PLL_CFG);
884 val &= ~ENET_SERDES_PLL_FBDIV2;
885 switch (np->port) {
886 case 0:
887 val |= ENET_SERDES_PLL_HRATE0;
888 break;
889 case 1:
890 val |= ENET_SERDES_PLL_HRATE1;
891 break;
892 case 2:
893 val |= ENET_SERDES_PLL_HRATE2;
894 break;
895 case 3:
896 val |= ENET_SERDES_PLL_HRATE3;
897 break;
898 default:
899 return -EINVAL;
900 }
901 nw64(ENET_SERDES_1_PLL_CFG, val);
902
903 return 0;
904}
905
5fbd7e24
MW		 906static int serdes_init_1g_serdes(struct niu *np)
907{
908 struct niu_link_config *lp = &np->link_config;
909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
910 u64 ctrl_val, test_cfg_val, sig, mask, val;
911 int err;
912 u64 reset_val, val_rd;
913
914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
916 ENET_SERDES_PLL_FBDIV0;
917 switch (np->port) {
918 case 0:
919 reset_val = ENET_SERDES_RESET_0;
920 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
921 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
922 pll_cfg = ENET_SERDES_0_PLL_CFG;
923 break;
924 case 1:
925 reset_val = ENET_SERDES_RESET_1;
926 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
927 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
928 pll_cfg = ENET_SERDES_1_PLL_CFG;
929 break;
930
931 default:
932 return -EINVAL;
933 }
934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
935 ENET_SERDES_CTRL_SDET_1 |
936 ENET_SERDES_CTRL_SDET_2 |
937 ENET_SERDES_CTRL_SDET_3 |
938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
946 test_cfg_val = 0;
947
948 if (lp->loopback_mode == LOOPBACK_PHY) {
949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_0_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_1_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_2_SHIFT) |
955 (ENET_TEST_MD_PAD_LOOPBACK <<
956 ENET_SERDES_TEST_MD_3_SHIFT));
957 }
958
959 nw64(ENET_SERDES_RESET, reset_val);
960 mdelay(20);
961 val_rd = nr64(ENET_SERDES_RESET);
962 val_rd &= ~reset_val;
963 nw64(pll_cfg, val);
964 nw64(ctrl_reg, ctrl_val);
965 nw64(test_cfg_reg, test_cfg_val);
966 nw64(ENET_SERDES_RESET, val_rd);
967 mdelay(2000);
968
969 /* Initialize all 4 lanes of the SERDES. */
970 for (i = 0; i < 4; i++) {
971 u32 rxtx_ctrl, glue0;
972
973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
974 if (err)
975 return err;
976 err = esr_read_glue0(np, i, &glue0);
977 if (err)
978 return err;
979
980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
983
984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
985 ESR_GLUE_CTRL0_THCNT |
986 ESR_GLUE_CTRL0_BLTIME);
987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
990 (BLTIME_300_CYCLES <<
991 ESR_GLUE_CTRL0_BLTIME_SHIFT));
992
993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
994 if (err)
995 return err;
996 err = esr_write_glue0(np, i, glue0);
997 if (err)
998 return err;
999 }
1000
1001
1002 sig = nr64(ESR_INT_SIGNALS);
1003 switch (np->port) {
1004 case 0:
1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1006 mask = val;
1007 break;
1008
1009 case 1:
1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1011 mask = val;
1012 break;
1013
1014 default:
1015 return -EINVAL;
1016 }
1017
1018 if ((sig & mask) != val) {
f10a1f2e
JP		 1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1021 return -ENODEV;
1022 }
1023
1024 return 0;
1025}
1026
1027static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028{
1029 struct niu_link_config *lp = &np->link_config;
1030 int link_up;
1031 u64 val;
1032 u16 current_speed;
1033 unsigned long flags;
1034 u8 current_duplex;
1035
1036 link_up = 0;
1037 current_speed = SPEED_INVALID;
1038 current_duplex = DUPLEX_INVALID;
1039
1040 spin_lock_irqsave(&np->lock, flags);
1041
1042 val = nr64_pcs(PCS_MII_STAT);
1043
1044 if (val & PCS_MII_STAT_LINK_STATUS) {
1045 link_up = 1;
1046 current_speed = SPEED_1000;
1047 current_duplex = DUPLEX_FULL;
1048 }
1049
1050 lp->active_speed = current_speed;
1051 lp->active_duplex = current_duplex;
1052 spin_unlock_irqrestore(&np->lock, flags);
1053
1054 *link_up_p = link_up;
1055 return 0;
1056}
1057
5fbd7e24
MW		 1058static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059{
1060 unsigned long flags;
1061 struct niu_link_config *lp = &np->link_config;
1062 int link_up = 0;
1063 int link_ok = 1;
1064 u64 val, val2;
1065 u16 current_speed;
1066 u8 current_duplex;
1067
1068 if (!(np->flags & NIU_FLAGS_10G))
1069 return link_status_1g_serdes(np, link_up_p);
1070
1071 current_speed = SPEED_INVALID;
1072 current_duplex = DUPLEX_INVALID;
1073 spin_lock_irqsave(&np->lock, flags);
1074
1075 val = nr64_xpcs(XPCS_STATUS(0));
1076 val2 = nr64_mac(XMAC_INTER2);
1077 if (val2 & 0x01000000)
1078 link_ok = 0;
1079
1080 if ((val & 0x1000ULL) && link_ok) {
1081 link_up = 1;
1082 current_speed = SPEED_10000;
1083 current_duplex = DUPLEX_FULL;
1084 }
1085 lp->active_speed = current_speed;
1086 lp->active_duplex = current_duplex;
1087 spin_unlock_irqrestore(&np->lock, flags);
1088 *link_up_p = link_up;
1089 return 0;
1090}
1091
38bb045d
CB		 1092static int link_status_mii(struct niu *np, int *link_up_p)
1093{
1094 struct niu_link_config *lp = &np->link_config;
1095 int err;
1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097 int supported, advertising, active_speed, active_duplex;
1098
1099 err = mii_read(np, np->phy_addr, MII_BMCR);
1100 if (unlikely(err < 0))
1101 return err;
1102 bmcr = err;
1103
1104 err = mii_read(np, np->phy_addr, MII_BMSR);
1105 if (unlikely(err < 0))
1106 return err;
1107 bmsr = err;
1108
1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110 if (unlikely(err < 0))
1111 return err;
1112 advert = err;
1113
1114 err = mii_read(np, np->phy_addr, MII_LPA);
1115 if (unlikely(err < 0))
1116 return err;
1117 lpa = err;
1118
1119 if (likely(bmsr & BMSR_ESTATEN)) {
1120 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121 if (unlikely(err < 0))
1122 return err;
1123 estatus = err;
1124
1125 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126 if (unlikely(err < 0))
1127 return err;
1128 ctrl1000 = err;
1129
1130 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131 if (unlikely(err < 0))
1132 return err;
1133 stat1000 = err;
1134 } else
1135 estatus = ctrl1000 = stat1000 = 0;
1136
1137 supported = 0;
1138 if (bmsr & BMSR_ANEGCAPABLE)
1139 supported |= SUPPORTED_Autoneg;
1140 if (bmsr & BMSR_10HALF)
1141 supported |= SUPPORTED_10baseT_Half;
1142 if (bmsr & BMSR_10FULL)
1143 supported |= SUPPORTED_10baseT_Full;
1144 if (bmsr & BMSR_100HALF)
1145 supported |= SUPPORTED_100baseT_Half;
1146 if (bmsr & BMSR_100FULL)
1147 supported |= SUPPORTED_100baseT_Full;
1148 if (estatus & ESTATUS_1000_THALF)
1149 supported |= SUPPORTED_1000baseT_Half;
1150 if (estatus & ESTATUS_1000_TFULL)
1151 supported |= SUPPORTED_1000baseT_Full;
1152 lp->supported = supported;
1153
1154 advertising = 0;
1155 if (advert & ADVERTISE_10HALF)
1156 advertising |= ADVERTISED_10baseT_Half;
1157 if (advert & ADVERTISE_10FULL)
1158 advertising |= ADVERTISED_10baseT_Full;
1159 if (advert & ADVERTISE_100HALF)
1160 advertising |= ADVERTISED_100baseT_Half;
1161 if (advert & ADVERTISE_100FULL)
1162 advertising |= ADVERTISED_100baseT_Full;
1163 if (ctrl1000 & ADVERTISE_1000HALF)
1164 advertising |= ADVERTISED_1000baseT_Half;
1165 if (ctrl1000 & ADVERTISE_1000FULL)
1166 advertising |= ADVERTISED_1000baseT_Full;
1167
1168 if (bmcr & BMCR_ANENABLE) {
1169 int neg, neg1000;
1170
1171 lp->active_autoneg = 1;
1172 advertising |= ADVERTISED_Autoneg;
1173
1174 neg = advert & lpa;
1175 neg1000 = (ctrl1000 << 2) & stat1000;
1176
1177 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1178 active_speed = SPEED_1000;
1179 else if (neg & LPA_100)
1180 active_speed = SPEED_100;
1181 else if (neg & (LPA_10HALF | LPA_10FULL))
1182 active_speed = SPEED_10;
1183 else
1184 active_speed = SPEED_INVALID;
1185
1186 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1187 active_duplex = DUPLEX_FULL;
1188 else if (active_speed != SPEED_INVALID)
1189 active_duplex = DUPLEX_HALF;
1190 else
1191 active_duplex = DUPLEX_INVALID;
1192 } else {
1193 lp->active_autoneg = 0;
1194
1195 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1196 active_speed = SPEED_1000;
1197 else if (bmcr & BMCR_SPEED100)
1198 active_speed = SPEED_100;
1199 else
1200 active_speed = SPEED_10;
1201
1202 if (bmcr & BMCR_FULLDPLX)
1203 active_duplex = DUPLEX_FULL;
1204 else
1205 active_duplex = DUPLEX_HALF;
1206 }
1207
1208 lp->active_advertising = advertising;
1209 lp->active_speed = active_speed;
1210 lp->active_duplex = active_duplex;
1211 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1212
1213 return 0;
1214}
1215
5fbd7e24
MW		 1216static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1217{
1218 struct niu_link_config *lp = &np->link_config;
1219 u16 current_speed, bmsr;
1220 unsigned long flags;
1221 u8 current_duplex;
1222 int err, link_up;
1223
1224 link_up = 0;
1225 current_speed = SPEED_INVALID;
1226 current_duplex = DUPLEX_INVALID;
1227
1228 spin_lock_irqsave(&np->lock, flags);
1229
1230 err = -EINVAL;
1231
1232 err = mii_read(np, np->phy_addr, MII_BMSR);
1233 if (err < 0)
1234 goto out;
1235
1236 bmsr = err;
1237 if (bmsr & BMSR_LSTATUS) {
f344c25d 1238 u16 adv, lpa;
5fbd7e24
MW		 1239
1240 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1241 if (err < 0)
1242 goto out;
1243 adv = err;
1244
1245 err = mii_read(np, np->phy_addr, MII_LPA);
1246 if (err < 0)
1247 goto out;
1248 lpa = err;
1249
5fbd7e24
MW		 1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251 if (err < 0)
1252 goto out;
5fbd7e24
MW		 1253 link_up = 1;
1254 current_speed = SPEED_1000;
1255 current_duplex = DUPLEX_FULL;
1256
1257 }
1258 lp->active_speed = current_speed;
1259 lp->active_duplex = current_duplex;
1260 err = 0;
1261
1262out:
1263 spin_unlock_irqrestore(&np->lock, flags);
1264
1265 *link_up_p = link_up;
1266 return err;
1267}
1268
38bb045d
CB		 1269static int link_status_1g(struct niu *np, int *link_up_p)
1270{
1271 struct niu_link_config *lp = &np->link_config;
1272 unsigned long flags;
1273 int err;
1274
1275 spin_lock_irqsave(&np->lock, flags);
1276
1277 err = link_status_mii(np, link_up_p);
1278 lp->supported |= SUPPORTED_TP;
1279 lp->active_advertising |= ADVERTISED_TP;
1280
1281 spin_unlock_irqrestore(&np->lock, flags);
1282 return err;
1283}
1284
a3138df9
DM		 1285static int bcm8704_reset(struct niu *np)
1286{
1287 int err, limit;
1288
1289 err = mdio_read(np, np->phy_addr,
1290 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1291 if (err < 0 || err == 0xffff)
a3138df9
DM		 1292 return err;
1293 err |= BMCR_RESET;
1294 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1295 MII_BMCR, err);
1296 if (err)
1297 return err;
1298
1299 limit = 1000;
1300 while (--limit >= 0) {
1301 err = mdio_read(np, np->phy_addr,
1302 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1303 if (err < 0)
1304 return err;
1305 if (!(err & BMCR_RESET))
1306 break;
1307 }
1308 if (limit < 0) {
f10a1f2e
JP		 1309 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1310 np->port, (err & 0xffff));
a3138df9
DM		 1311 return -ENODEV;
1312 }
1313 return 0;
1314}
1315
1316/* When written, certain PHY registers need to be read back twice
1317 * in order for the bits to settle properly.
1318 */
1319static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1320{
1321 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1322 if (err < 0)
1323 return err;
1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1325 if (err < 0)
1326 return err;
1327 return 0;
1328}
1329
a5d6ab56
MW		 1330static int bcm8706_init_user_dev3(struct niu *np)
1331{
1332 int err;
1333
1334
1335 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1336 BCM8704_USER_OPT_DIGITAL_CTRL);
1337 if (err < 0)
1338 return err;
1339 err &= ~USER_ODIG_CTRL_GPIOS;
1340 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1341 err |= USER_ODIG_CTRL_RESV2;
1342 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1343 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1344 if (err)
1345 return err;
1346
1347 mdelay(1000);
1348
1349 return 0;
1350}
1351
a3138df9
DM		 1352static int bcm8704_init_user_dev3(struct niu *np)
1353{
1354 int err;
1355
1356 err = mdio_write(np, np->phy_addr,
1357 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1358 (USER_CONTROL_OPTXRST_LVL |
1359 USER_CONTROL_OPBIASFLT_LVL |
1360 USER_CONTROL_OBTMPFLT_LVL |
1361 USER_CONTROL_OPPRFLT_LVL |
1362 USER_CONTROL_OPTXFLT_LVL |
1363 USER_CONTROL_OPRXLOS_LVL |
1364 USER_CONTROL_OPRXFLT_LVL |
1365 USER_CONTROL_OPTXON_LVL |
1366 (0x3f << USER_CONTROL_RES1_SHIFT)));
1367 if (err)
1368 return err;
1369
1370 err = mdio_write(np, np->phy_addr,
1371 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1372 (USER_PMD_TX_CTL_XFP_CLKEN |
1373 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1374 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1375 USER_PMD_TX_CTL_TSCK_LPWREN));
1376 if (err)
1377 return err;
1378
1379 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1380 if (err)
1381 return err;
1382 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1383 if (err)
1384 return err;
1385
1386 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1387 BCM8704_USER_OPT_DIGITAL_CTRL);
1388 if (err < 0)
1389 return err;
1390 err &= ~USER_ODIG_CTRL_GPIOS;
1391 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1392 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1393 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1394 if (err)
1395 return err;
1396
1397 mdelay(1000);
1398
1399 return 0;
1400}
1401
b0de8e40
ML		 1402static int mrvl88x2011_act_led(struct niu *np, int val)
1403{
1404 int err;
1405
1406 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1407 MRVL88X2011_LED_8_TO_11_CTL);
1408 if (err < 0)
1409 return err;
1410
1411 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1412 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1413
1414 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1415 MRVL88X2011_LED_8_TO_11_CTL, err);
1416}
1417
1418static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1419{
1420 int err;
1421
1422 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1423 MRVL88X2011_LED_BLINK_CTL);
1424 if (err >= 0) {
1425 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1426 err |= (rate << 4);
1427
1428 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1429 MRVL88X2011_LED_BLINK_CTL, err);
1430 }
1431
1432 return err;
1433}
1434
1435static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1436{
1437 int err;
1438
1439 /* Set LED functions */
1440 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1441 if (err)
1442 return err;
1443
1444 /* led activity */
1445 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1446 if (err)
1447 return err;
1448
1449 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1450 MRVL88X2011_GENERAL_CTL);
1451 if (err < 0)
1452 return err;
1453
1454 err |= MRVL88X2011_ENA_XFPREFCLK;
1455
1456 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1457 MRVL88X2011_GENERAL_CTL, err);
1458 if (err < 0)
1459 return err;
1460
1461 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1462 MRVL88X2011_PMA_PMD_CTL_1);
1463 if (err < 0)
1464 return err;
1465
1466 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1467 err |= MRVL88X2011_LOOPBACK;
1468 else
1469 err &= ~MRVL88X2011_LOOPBACK;
1470
1471 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1472 MRVL88X2011_PMA_PMD_CTL_1, err);
1473 if (err < 0)
1474 return err;
1475
1476 /* Enable PMD */
1477 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1478 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1479}
1480
a5d6ab56
MW		 1481
1482static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1483{
a3138df9 1484 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1485 int err = 0;
a3138df9
DM		 1486
1487#if 1
1488 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1489 MII_STAT1000);
1490 if (err < 0)
1491 return err;
f10a1f2e 1492 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1493
1494 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1495 if (err < 0)
1496 return err;
f10a1f2e 1497 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1498
1499 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1500 MII_NWAYTEST);
1501 if (err < 0)
1502 return err;
f10a1f2e 1503 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1504#endif
1505
1506 /* XXX dig this out it might not be so useful XXX */
1507 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1508 BCM8704_USER_ANALOG_STATUS0);
1509 if (err < 0)
1510 return err;
1511 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1512 BCM8704_USER_ANALOG_STATUS0);
1513 if (err < 0)
1514 return err;
1515 analog_stat0 = err;
1516
1517 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1518 BCM8704_USER_TX_ALARM_STATUS);
1519 if (err < 0)
1520 return err;
1521 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1522 BCM8704_USER_TX_ALARM_STATUS);
1523 if (err < 0)
1524 return err;
1525 tx_alarm_status = err;
1526
1527 if (analog_stat0 != 0x03fc) {
1528 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1529 pr_info("Port %u cable not connected or bad cable\n",
1530 np->port);
a3138df9 1531 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1532 pr_info("Port %u optical module is bad or missing\n",
1533 np->port);
a3138df9
DM		 1534 }
1535 }
1536
1537 return 0;
1538}
1539
a5d6ab56
MW		 1540static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1541{
1542 struct niu_link_config *lp = &np->link_config;
1543 int err;
1544
1545 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1546 MII_BMCR);
1547 if (err < 0)
1548 return err;
1549
1550 err &= ~BMCR_LOOPBACK;
1551
1552 if (lp->loopback_mode == LOOPBACK_MAC)
1553 err |= BMCR_LOOPBACK;
1554
1555 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1556 MII_BMCR, err);
1557 if (err)
1558 return err;
1559
1560 return 0;
1561}
1562
1563static int xcvr_init_10g_bcm8706(struct niu *np)
1564{
1565 int err = 0;
1566 u64 val;
1567
1568 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1569 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1570 return err;
1571
1572 val = nr64_mac(XMAC_CONFIG);
1573 val &= ~XMAC_CONFIG_LED_POLARITY;
1574 val |= XMAC_CONFIG_FORCE_LED_ON;
1575 nw64_mac(XMAC_CONFIG, val);
1576
1577 val = nr64(MIF_CONFIG);
1578 val |= MIF_CONFIG_INDIRECT_MODE;
1579 nw64(MIF_CONFIG, val);
1580
1581 err = bcm8704_reset(np);
1582 if (err)
1583 return err;
1584
1585 err = xcvr_10g_set_lb_bcm870x(np);
1586 if (err)
1587 return err;
1588
1589 err = bcm8706_init_user_dev3(np);
1590 if (err)
1591 return err;
1592
1593 err = xcvr_diag_bcm870x(np);
1594 if (err)
1595 return err;
1596
1597 return 0;
1598}
1599
1600static int xcvr_init_10g_bcm8704(struct niu *np)
1601{
1602 int err;
1603
1604 err = bcm8704_reset(np);
1605 if (err)
1606 return err;
1607
1608 err = bcm8704_init_user_dev3(np);
1609 if (err)
1610 return err;
1611
1612 err = xcvr_10g_set_lb_bcm870x(np);
1613 if (err)
1614 return err;
1615
1616 err = xcvr_diag_bcm870x(np);
1617 if (err)
1618 return err;
1619
1620 return 0;
1621}
1622
b0de8e40
ML		 1623static int xcvr_init_10g(struct niu *np)
1624{
1625 int phy_id, err;
1626 u64 val;
1627
1628 val = nr64_mac(XMAC_CONFIG);
1629 val &= ~XMAC_CONFIG_LED_POLARITY;
1630 val |= XMAC_CONFIG_FORCE_LED_ON;
1631 nw64_mac(XMAC_CONFIG, val);
1632
1633 /* XXX shared resource, lock parent XXX */
1634 val = nr64(MIF_CONFIG);
1635 val |= MIF_CONFIG_INDIRECT_MODE;
1636 nw64(MIF_CONFIG, val);
1637
1638 phy_id = phy_decode(np->parent->port_phy, np->port);
1639 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1640
1641 /* handle different phy types */
1642 switch (phy_id & NIU_PHY_ID_MASK) {
1643 case NIU_PHY_ID_MRVL88X2011:
1644 err = xcvr_init_10g_mrvl88x2011(np);
1645 break;
1646
1647 default: /* bcom 8704 */
1648 err = xcvr_init_10g_bcm8704(np);
1649 break;
1650 }
1651
f344c25d 1652 return err;
b0de8e40
ML		 1653}
1654
a3138df9
DM		 1655static int mii_reset(struct niu *np)
1656{
1657 int limit, err;
1658
1659 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1660 if (err)
1661 return err;
1662
1663 limit = 1000;
1664 while (--limit >= 0) {
1665 udelay(500);
1666 err = mii_read(np, np->phy_addr, MII_BMCR);
1667 if (err < 0)
1668 return err;
1669 if (!(err & BMCR_RESET))
1670 break;
1671 }
1672 if (limit < 0) {
f10a1f2e
JP		 1673 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1674 np->port, err);
a3138df9
DM		 1675 return -ENODEV;
1676 }
1677
1678 return 0;
1679}
1680
5fbd7e24
MW		 1681static int xcvr_init_1g_rgmii(struct niu *np)
1682{
1683 int err;
1684 u64 val;
1685 u16 bmcr, bmsr, estat;
1686
1687 val = nr64(MIF_CONFIG);
1688 val &= ~MIF_CONFIG_INDIRECT_MODE;
1689 nw64(MIF_CONFIG, val);
1690
1691 err = mii_reset(np);
1692 if (err)
1693 return err;
1694
1695 err = mii_read(np, np->phy_addr, MII_BMSR);
1696 if (err < 0)
1697 return err;
1698 bmsr = err;
1699
1700 estat = 0;
1701 if (bmsr & BMSR_ESTATEN) {
1702 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1703 if (err < 0)
1704 return err;
1705 estat = err;
1706 }
1707
1708 bmcr = 0;
1709 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1710 if (err)
1711 return err;
1712
1713 if (bmsr & BMSR_ESTATEN) {
1714 u16 ctrl1000 = 0;
1715
1716 if (estat & ESTATUS_1000_TFULL)
1717 ctrl1000 |= ADVERTISE_1000FULL;
1718 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1719 if (err)
1720 return err;
1721 }
1722
1723 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1724
1725 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1726 if (err)
1727 return err;
1728
1729 err = mii_read(np, np->phy_addr, MII_BMCR);
1730 if (err < 0)
1731 return err;
1732 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1733
1734 err = mii_read(np, np->phy_addr, MII_BMSR);
1735 if (err < 0)
1736 return err;
1737
1738 return 0;
1739}
1740
a3138df9
DM		 1741static int mii_init_common(struct niu *np)
1742{
1743 struct niu_link_config *lp = &np->link_config;
1744 u16 bmcr, bmsr, adv, estat;
1745 int err;
1746
1747 err = mii_reset(np);
1748 if (err)
1749 return err;
1750
1751 err = mii_read(np, np->phy_addr, MII_BMSR);
1752 if (err < 0)
1753 return err;
1754 bmsr = err;
1755
1756 estat = 0;
1757 if (bmsr & BMSR_ESTATEN) {
1758 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1759 if (err < 0)
1760 return err;
1761 estat = err;
1762 }
1763
1764 bmcr = 0;
1765 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1766 if (err)
1767 return err;
1768
1769 if (lp->loopback_mode == LOOPBACK_MAC) {
1770 bmcr |= BMCR_LOOPBACK;
1771 if (lp->active_speed == SPEED_1000)
1772 bmcr |= BMCR_SPEED1000;
1773 if (lp->active_duplex == DUPLEX_FULL)
1774 bmcr |= BMCR_FULLDPLX;
1775 }
1776
1777 if (lp->loopback_mode == LOOPBACK_PHY) {
1778 u16 aux;
1779
1780 aux = (BCM5464R_AUX_CTL_EXT_LB |
1781 BCM5464R_AUX_CTL_WRITE_1);
1782 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1783 if (err)
1784 return err;
1785 }
1786
38bb045d
CB		 1787 if (lp->autoneg) {
1788 u16 ctrl1000;
1789
1790 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1791 if ((bmsr & BMSR_10HALF) &&
1792 (lp->advertising & ADVERTISED_10baseT_Half))
1793 adv |= ADVERTISE_10HALF;
1794 if ((bmsr & BMSR_10FULL) &&
1795 (lp->advertising & ADVERTISED_10baseT_Full))
1796 adv |= ADVERTISE_10FULL;
1797 if ((bmsr & BMSR_100HALF) &&
1798 (lp->advertising & ADVERTISED_100baseT_Half))
1799 adv |= ADVERTISE_100HALF;
1800 if ((bmsr & BMSR_100FULL) &&
1801 (lp->advertising & ADVERTISED_100baseT_Full))
1802 adv |= ADVERTISE_100FULL;
1803 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1804 if (err)
1805 return err;
38bb045d
CB		 1806
1807 if (likely(bmsr & BMSR_ESTATEN)) {
1808 ctrl1000 = 0;
1809 if ((estat & ESTATUS_1000_THALF) &&
1810 (lp->advertising & ADVERTISED_1000baseT_Half))
1811 ctrl1000 |= ADVERTISE_1000HALF;
1812 if ((estat & ESTATUS_1000_TFULL) &&
1813 (lp->advertising & ADVERTISED_1000baseT_Full))
1814 ctrl1000 |= ADVERTISE_1000FULL;
1815 err = mii_write(np, np->phy_addr,
1816 MII_CTRL1000, ctrl1000);
1817 if (err)
1818 return err;
1819 }
1820
1821 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1822 } else {
1823 /* !lp->autoneg */
1824 int fulldpx;
1825
1826 if (lp->duplex == DUPLEX_FULL) {
1827 bmcr |= BMCR_FULLDPLX;
1828 fulldpx = 1;
1829 } else if (lp->duplex == DUPLEX_HALF)
1830 fulldpx = 0;
1831 else
1832 return -EINVAL;
1833
1834 if (lp->speed == SPEED_1000) {
1835 /* if X-full requested while not supported, or
1836 X-half requested while not supported... */
1837 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1838 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1839 return -EINVAL;
1840 bmcr |= BMCR_SPEED1000;
1841 } else if (lp->speed == SPEED_100) {
1842 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1843 (!fulldpx && !(bmsr & BMSR_100HALF)))
1844 return -EINVAL;
1845 bmcr |= BMCR_SPEED100;
1846 } else if (lp->speed == SPEED_10) {
1847 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1848 (!fulldpx && !(bmsr & BMSR_10HALF)))
1849 return -EINVAL;
1850 } else
1851 return -EINVAL;
a3138df9 1852 }
a3138df9
DM		 1853
1854 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1855 if (err)
1856 return err;
1857
38bb045d 1858#if 0
a3138df9
DM		 1859 err = mii_read(np, np->phy_addr, MII_BMCR);
1860 if (err < 0)
1861 return err;
38bb045d
CB		 1862 bmcr = err;
1863
a3138df9
DM		 1864 err = mii_read(np, np->phy_addr, MII_BMSR);
1865 if (err < 0)
1866 return err;
38bb045d
CB		 1867 bmsr = err;
1868
f10a1f2e 1869 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1870 np->port, bmcr, bmsr);
1871#endif
1872
1873 return 0;
1874}
1875
1876static int xcvr_init_1g(struct niu *np)
1877{
1878 u64 val;
1879
1880 /* XXX shared resource, lock parent XXX */
1881 val = nr64(MIF_CONFIG);
1882 val &= ~MIF_CONFIG_INDIRECT_MODE;
1883 nw64(MIF_CONFIG, val);
1884
1885 return mii_init_common(np);
1886}
1887
1888static int niu_xcvr_init(struct niu *np)
1889{
1890 const struct niu_phy_ops *ops = np->phy_ops;
1891 int err;
1892
1893 err = 0;
1894 if (ops->xcvr_init)
1895 err = ops->xcvr_init(np);
1896
1897 return err;
1898}
1899
1900static int niu_serdes_init(struct niu *np)
1901{
1902 const struct niu_phy_ops *ops = np->phy_ops;
1903 int err;
1904
1905 err = 0;
1906 if (ops->serdes_init)
1907 err = ops->serdes_init(np);
1908
1909 return err;
1910}
1911
1912static void niu_init_xif(struct niu *);
0c3b091b 1913static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1914
1915static int niu_link_status_common(struct niu *np, int link_up)
1916{
1917 struct niu_link_config *lp = &np->link_config;
1918 struct net_device *dev = np->dev;
1919 unsigned long flags;
1920
1921 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1922 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1923 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1924 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1925 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1926 "10Mbit/sec",
1927 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1928
1929 spin_lock_irqsave(&np->lock, flags);
1930 niu_init_xif(np);
0c3b091b 1931 niu_handle_led(np, 1);
a3138df9
DM		 1932 spin_unlock_irqrestore(&np->lock, flags);
1933
1934 netif_carrier_on(dev);
1935 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1936 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1937 spin_lock_irqsave(&np->lock, flags);
1938 niu_handle_led(np, 0);
1939 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1940 netif_carrier_off(dev);
1941 }
1942
1943 return 0;
1944}
1945
b0de8e40 1946static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1947{
b0de8e40 1948 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1949
1950 link_up = 0;
1951
b0de8e40
ML		 1952 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1953 MRVL88X2011_10G_PMD_STATUS_2);
1954 if (err < 0)
1955 goto out;
a3138df9 1956
b0de8e40
ML		 1957 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1958 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1959 MRVL88X2011_PMA_PMD_STATUS_1);
1960 if (err < 0)
1961 goto out;
1962
1963 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1964
1965 /* Check PMC Register : 3.0001.2 == 1: read twice */
1966 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1967 MRVL88X2011_PMA_PMD_STATUS_1);
1968 if (err < 0)
1969 goto out;
1970
1971 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1972 MRVL88X2011_PMA_PMD_STATUS_1);
1973 if (err < 0)
1974 goto out;
1975
1976 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1977
1978 /* Check XGXS Register : 4.0018.[0-3,12] */
1979 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1980 MRVL88X2011_10G_XGXS_LANE_STAT);
1981 if (err < 0)
a3138df9
DM		 1982 goto out;
1983
b0de8e40
ML		 1984 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1985 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1986 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1987 0x800))
1988 link_up = (pma_status && pcs_status) ? 1 : 0;
1989
1990 np->link_config.active_speed = SPEED_10000;
1991 np->link_config.active_duplex = DUPLEX_FULL;
1992 err = 0;
1993out:
1994 mrvl88x2011_act_led(np, (link_up ?
1995 MRVL88X2011_LED_CTL_PCS_ACT :
1996 MRVL88X2011_LED_CTL_OFF));
1997
1998 *link_up_p = link_up;
1999 return err;
2000}
2001
a5d6ab56
MW		 2002static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2003{
2004 int err, link_up;
2005 link_up = 0;
2006
2007 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2008 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2009 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2010 goto out;
2011 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2012 err = 0;
2013 goto out;
2014 }
2015
2016 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2017 BCM8704_PCS_10G_R_STATUS);
2018 if (err < 0)
2019 goto out;
2020
2021 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2022 err = 0;
2023 goto out;
2024 }
2025
2026 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2027 BCM8704_PHYXS_XGXS_LANE_STAT);
2028 if (err < 0)
2029 goto out;
2030 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2031 PHYXS_XGXS_LANE_STAT_MAGIC |
2032 PHYXS_XGXS_LANE_STAT_PATTEST |
2033 PHYXS_XGXS_LANE_STAT_LANE3 |
2034 PHYXS_XGXS_LANE_STAT_LANE2 |
2035 PHYXS_XGXS_LANE_STAT_LANE1 |
2036 PHYXS_XGXS_LANE_STAT_LANE0)) {
2037 err = 0;
2038 np->link_config.active_speed = SPEED_INVALID;
2039 np->link_config.active_duplex = DUPLEX_INVALID;
2040 goto out;
2041 }
2042
2043 link_up = 1;
2044 np->link_config.active_speed = SPEED_10000;
2045 np->link_config.active_duplex = DUPLEX_FULL;
2046 err = 0;
2047
2048out:
2049 *link_up_p = link_up;
a5d6ab56
MW		 2050 return err;
2051}
2052
b0de8e40
ML		 2053static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2054{
2055 int err, link_up;
2056
2057 link_up = 0;
2058
a3138df9
DM		 2059 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2060 BCM8704_PMD_RCV_SIGDET);
2061 if (err < 0)
2062 goto out;
2063 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2064 err = 0;
2065 goto out;
2066 }
2067
2068 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2069 BCM8704_PCS_10G_R_STATUS);
2070 if (err < 0)
2071 goto out;
2072 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2073 err = 0;
2074 goto out;
2075 }
2076
2077 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2078 BCM8704_PHYXS_XGXS_LANE_STAT);
2079 if (err < 0)
2080 goto out;
2081
2082 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2083 PHYXS_XGXS_LANE_STAT_MAGIC |
2084 PHYXS_XGXS_LANE_STAT_LANE3 |
2085 PHYXS_XGXS_LANE_STAT_LANE2 |
2086 PHYXS_XGXS_LANE_STAT_LANE1 |
2087 PHYXS_XGXS_LANE_STAT_LANE0)) {
2088 err = 0;
2089 goto out;
2090 }
2091
2092 link_up = 1;
2093 np->link_config.active_speed = SPEED_10000;
2094 np->link_config.active_duplex = DUPLEX_FULL;
2095 err = 0;
2096
2097out:
b0de8e40
ML		 2098 *link_up_p = link_up;
2099 return err;
2100}
2101
2102static int link_status_10g(struct niu *np, int *link_up_p)
2103{
2104 unsigned long flags;
2105 int err = -EINVAL;
2106
2107 spin_lock_irqsave(&np->lock, flags);
2108
2109 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2110 int phy_id;
2111
2112 phy_id = phy_decode(np->parent->port_phy, np->port);
2113 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2114
2115 /* handle different phy types */
2116 switch (phy_id & NIU_PHY_ID_MASK) {
2117 case NIU_PHY_ID_MRVL88X2011:
2118 err = link_status_10g_mrvl(np, link_up_p);
2119 break;
2120
2121 default: /* bcom 8704 */
2122 err = link_status_10g_bcom(np, link_up_p);
2123 break;
2124 }
2125 }
2126
a3138df9
DM		 2127 spin_unlock_irqrestore(&np->lock, flags);
2128
a3138df9
DM		 2129 return err;
2130}
2131
a5d6ab56
MW		 2132static int niu_10g_phy_present(struct niu *np)
2133{
2134 u64 sig, mask, val;
2135
2136 sig = nr64(ESR_INT_SIGNALS);
2137 switch (np->port) {
2138 case 0:
2139 mask = ESR_INT_SIGNALS_P0_BITS;
2140 val = (ESR_INT_SRDY0_P0 |
2141 ESR_INT_DET0_P0 |
2142 ESR_INT_XSRDY_P0 |
2143 ESR_INT_XDP_P0_CH3 |
2144 ESR_INT_XDP_P0_CH2 |
2145 ESR_INT_XDP_P0_CH1 |
2146 ESR_INT_XDP_P0_CH0);
2147 break;
2148
2149 case 1:
2150 mask = ESR_INT_SIGNALS_P1_BITS;
2151 val = (ESR_INT_SRDY0_P1 |
2152 ESR_INT_DET0_P1 |
2153 ESR_INT_XSRDY_P1 |
2154 ESR_INT_XDP_P1_CH3 |
2155 ESR_INT_XDP_P1_CH2 |
2156 ESR_INT_XDP_P1_CH1 |
2157 ESR_INT_XDP_P1_CH0);
2158 break;
2159
2160 default:
2161 return 0;
2162 }
2163
2164 if ((sig & mask) != val)
2165 return 0;
2166 return 1;
2167}
2168
2169static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2170{
2171 unsigned long flags;
2172 int err = 0;
2173 int phy_present;
2174 int phy_present_prev;
2175
2176 spin_lock_irqsave(&np->lock, flags);
2177
2178 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2179 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2180 1 : 0;
2181 phy_present = niu_10g_phy_present(np);
2182 if (phy_present != phy_present_prev) {
2183 /* state change */
2184 if (phy_present) {
9c5cd670 2185 /* A NEM was just plugged in */
a5d6ab56
MW		 2186 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2187 if (np->phy_ops->xcvr_init)
2188 err = np->phy_ops->xcvr_init(np);
2189 if (err) {
9c5cd670
TC		 2190 err = mdio_read(np, np->phy_addr,
2191 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2192 if (err == 0xffff) {
2193 /* No mdio, back-to-back XAUI */
2194 goto out;
2195 }
a5d6ab56
MW		 2196 /* debounce */
2197 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2198 }
2199 } else {
2200 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2201 *link_up_p = 0;
f10a1f2e
JP		 2202 netif_warn(np, link, np->dev,
2203 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2204 }
2205 }
9c5cd670
TC		 2206out:
2207 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2208 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2209 if (err == 0xffff) {
2210 /* No mdio, back-to-back XAUI: it is C10NEM */
2211 *link_up_p = 1;
2212 np->link_config.active_speed = SPEED_10000;
2213 np->link_config.active_duplex = DUPLEX_FULL;
2214 }
2215 }
a5d6ab56
MW		 2216 }
2217
2218 spin_unlock_irqrestore(&np->lock, flags);
2219
9c5cd670 2220 return 0;
a5d6ab56
MW		 2221}
2222
a3138df9
DM		 2223static int niu_link_status(struct niu *np, int *link_up_p)
2224{
2225 const struct niu_phy_ops *ops = np->phy_ops;
2226 int err;
2227
2228 err = 0;
2229 if (ops->link_status)
2230 err = ops->link_status(np, link_up_p);
2231
2232 return err;
2233}
2234
2235static void niu_timer(unsigned long __opaque)
2236{
2237 struct niu *np = (struct niu *) __opaque;
2238 unsigned long off;
2239 int err, link_up;
2240
2241 err = niu_link_status(np, &link_up);
2242 if (!err)
2243 niu_link_status_common(np, link_up);
2244
2245 if (netif_carrier_ok(np->dev))
2246 off = 5 * HZ;
2247 else
2248 off = 1 * HZ;
2249 np->timer.expires = jiffies + off;
2250
2251 add_timer(&np->timer);
2252}
2253
5fbd7e24
MW		 2254static const struct niu_phy_ops phy_ops_10g_serdes = {
2255 .serdes_init = serdes_init_10g_serdes,
2256 .link_status = link_status_10g_serdes,
2257};
2258
e3e081e1
SB		 2259static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2260 .serdes_init = serdes_init_niu_10g_serdes,
2261 .link_status = link_status_10g_serdes,
2262};
2263
2264static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2265 .serdes_init = serdes_init_niu_1g_serdes,
2266 .link_status = link_status_1g_serdes,
2267};
2268
5fbd7e24
MW		 2269static const struct niu_phy_ops phy_ops_1g_rgmii = {
2270 .xcvr_init = xcvr_init_1g_rgmii,
2271 .link_status = link_status_1g_rgmii,
2272};
2273
a3138df9 2274static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2275 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2276 .xcvr_init = xcvr_init_10g,
2277 .link_status = link_status_10g,
2278};
2279
2280static const struct niu_phy_ops phy_ops_10g_fiber = {
2281 .serdes_init = serdes_init_10g,
2282 .xcvr_init = xcvr_init_10g,
2283 .link_status = link_status_10g,
2284};
2285
a5d6ab56
MW		 2286static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2287 .serdes_init = serdes_init_10g,
2288 .xcvr_init = xcvr_init_10g_bcm8706,
2289 .link_status = link_status_10g_hotplug,
2290};
2291
9c5cd670
TC		 2292static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2293 .serdes_init = serdes_init_niu_10g_fiber,
2294 .xcvr_init = xcvr_init_10g_bcm8706,
2295 .link_status = link_status_10g_hotplug,
2296};
2297
a3138df9
DM		 2298static const struct niu_phy_ops phy_ops_10g_copper = {
2299 .serdes_init = serdes_init_10g,
2300 .link_status = link_status_10g, /* XXX */
2301};
2302
2303static const struct niu_phy_ops phy_ops_1g_fiber = {
2304 .serdes_init = serdes_init_1g,
2305 .xcvr_init = xcvr_init_1g,
2306 .link_status = link_status_1g,
2307};
2308
2309static const struct niu_phy_ops phy_ops_1g_copper = {
2310 .xcvr_init = xcvr_init_1g,
2311 .link_status = link_status_1g,
2312};
2313
2314struct niu_phy_template {
2315 const struct niu_phy_ops *ops;
2316 u32 phy_addr_base;
2317};
2318
e3e081e1 2319static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2320 .ops = &phy_ops_10g_fiber_niu,
2321 .phy_addr_base = 16,
2322};
2323
e3e081e1
SB		 2324static const struct niu_phy_template phy_template_niu_10g_serdes = {
2325 .ops = &phy_ops_10g_serdes_niu,
2326 .phy_addr_base = 0,
2327};
2328
2329static const struct niu_phy_template phy_template_niu_1g_serdes = {
2330 .ops = &phy_ops_1g_serdes_niu,
2331 .phy_addr_base = 0,
2332};
2333
a3138df9
DM		 2334static const struct niu_phy_template phy_template_10g_fiber = {
2335 .ops = &phy_ops_10g_fiber,
2336 .phy_addr_base = 8,
2337};
2338
a5d6ab56
MW		 2339static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2340 .ops = &phy_ops_10g_fiber_hotplug,
2341 .phy_addr_base = 8,
2342};
2343
9c5cd670
TC		 2344static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2345 .ops = &phy_ops_niu_10g_hotplug,
2346 .phy_addr_base = 8,
2347};
2348
a3138df9
DM		 2349static const struct niu_phy_template phy_template_10g_copper = {
2350 .ops = &phy_ops_10g_copper,
2351 .phy_addr_base = 10,
2352};
2353
2354static const struct niu_phy_template phy_template_1g_fiber = {
2355 .ops = &phy_ops_1g_fiber,
2356 .phy_addr_base = 0,
2357};
2358
2359static const struct niu_phy_template phy_template_1g_copper = {
2360 .ops = &phy_ops_1g_copper,
2361 .phy_addr_base = 0,
2362};
2363
5fbd7e24
MW		 2364static const struct niu_phy_template phy_template_1g_rgmii = {
2365 .ops = &phy_ops_1g_rgmii,
2366 .phy_addr_base = 0,
2367};
2368
2369static const struct niu_phy_template phy_template_10g_serdes = {
2370 .ops = &phy_ops_10g_serdes,
2371 .phy_addr_base = 0,
2372};
2373
2374static int niu_atca_port_num[4] = {
2375 0, 0, 11, 10
2376};
2377
2378static int serdes_init_10g_serdes(struct niu *np)
2379{
2380 struct niu_link_config *lp = &np->link_config;
2381 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2382 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2383
2384 switch (np->port) {
2385 case 0:
5fbd7e24
MW		 2386 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2387 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2388 pll_cfg = ENET_SERDES_0_PLL_CFG;
2389 break;
2390 case 1:
5fbd7e24
MW		 2391 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2392 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2393 pll_cfg = ENET_SERDES_1_PLL_CFG;
2394 break;
2395
2396 default:
2397 return -EINVAL;
2398 }
2399 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2400 ENET_SERDES_CTRL_SDET_1 |
2401 ENET_SERDES_CTRL_SDET_2 |
2402 ENET_SERDES_CTRL_SDET_3 |
2403 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2404 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2405 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2406 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2407 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2408 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2409 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2410 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2411 test_cfg_val = 0;
2412
2413 if (lp->loopback_mode == LOOPBACK_PHY) {
2414 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2415 ENET_SERDES_TEST_MD_0_SHIFT) |
2416 (ENET_TEST_MD_PAD_LOOPBACK <<
2417 ENET_SERDES_TEST_MD_1_SHIFT) |
2418 (ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_2_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_3_SHIFT));
2422 }
2423
2424 esr_reset(np);
2425 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2426 nw64(ctrl_reg, ctrl_val);
2427 nw64(test_cfg_reg, test_cfg_val);
2428
2429 /* Initialize all 4 lanes of the SERDES. */
2430 for (i = 0; i < 4; i++) {
2431 u32 rxtx_ctrl, glue0;
7c34eb89 2432 int err;
5fbd7e24
MW		 2433
2434 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2435 if (err)
2436 return err;
2437 err = esr_read_glue0(np, i, &glue0);
2438 if (err)
2439 return err;
2440
2441 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2442 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2443 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2444
2445 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2446 ESR_GLUE_CTRL0_THCNT |
2447 ESR_GLUE_CTRL0_BLTIME);
2448 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2449 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2450 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2451 (BLTIME_300_CYCLES <<
2452 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2453
2454 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2455 if (err)
2456 return err;
2457 err = esr_write_glue0(np, i, glue0);
2458 if (err)
2459 return err;
2460 }
2461
2462
2463 sig = nr64(ESR_INT_SIGNALS);
2464 switch (np->port) {
2465 case 0:
2466 mask = ESR_INT_SIGNALS_P0_BITS;
2467 val = (ESR_INT_SRDY0_P0 |
2468 ESR_INT_DET0_P0 |
2469 ESR_INT_XSRDY_P0 |
2470 ESR_INT_XDP_P0_CH3 |
2471 ESR_INT_XDP_P0_CH2 |
2472 ESR_INT_XDP_P0_CH1 |
2473 ESR_INT_XDP_P0_CH0);
2474 break;
2475
2476 case 1:
2477 mask = ESR_INT_SIGNALS_P1_BITS;
2478 val = (ESR_INT_SRDY0_P1 |
2479 ESR_INT_DET0_P1 |
2480 ESR_INT_XSRDY_P1 |
2481 ESR_INT_XDP_P1_CH3 |
2482 ESR_INT_XDP_P1_CH2 |
2483 ESR_INT_XDP_P1_CH1 |
2484 ESR_INT_XDP_P1_CH0);
2485 break;
2486
2487 default:
2488 return -EINVAL;
2489 }
2490
2491 if ((sig & mask) != val) {
2492 int err;
2493 err = serdes_init_1g_serdes(np);
2494 if (!err) {
2495 np->flags &= ~NIU_FLAGS_10G;
2496 np->mac_xcvr = MAC_XCVR_PCS;
2497 } else {
f10a1f2e
JP		 2498 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2499 np->port);
5fbd7e24
MW		 2500 return -ENODEV;
2501 }
2502 }
2503
2504 return 0;
2505}
2506
a3138df9
DM		 2507static int niu_determine_phy_disposition(struct niu *np)
2508{
2509 struct niu_parent *parent = np->parent;
2510 u8 plat_type = parent->plat_type;
2511 const struct niu_phy_template *tp;
2512 u32 phy_addr_off = 0;
2513
2514 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2515 switch (np->flags &
2516 (NIU_FLAGS_10G |
2517 NIU_FLAGS_FIBER |
2518 NIU_FLAGS_XCVR_SERDES)) {
2519 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2520 /* 10G Serdes */
2521 tp = &phy_template_niu_10g_serdes;
2522 break;
2523 case NIU_FLAGS_XCVR_SERDES:
2524 /* 1G Serdes */
2525 tp = &phy_template_niu_1g_serdes;
2526 break;
2527 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2528 /* 10G Fiber */
2529 default:
9c5cd670
TC		 2530 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2531 tp = &phy_template_niu_10g_hotplug;
2532 if (np->port == 0)
2533 phy_addr_off = 8;
2534 if (np->port == 1)
2535 phy_addr_off = 12;
2536 } else {
2537 tp = &phy_template_niu_10g_fiber;
2538 phy_addr_off += np->port;
2539 }
e3e081e1
SB		 2540 break;
2541 }
a3138df9 2542 } else {
5fbd7e24
MW		 2543 switch (np->flags &
2544 (NIU_FLAGS_10G |
2545 NIU_FLAGS_FIBER |
2546 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2547 case 0:
2548 /* 1G copper */
2549 tp = &phy_template_1g_copper;
2550 if (plat_type == PLAT_TYPE_VF_P0)
2551 phy_addr_off = 10;
2552 else if (plat_type == PLAT_TYPE_VF_P1)
2553 phy_addr_off = 26;
2554
2555 phy_addr_off += (np->port ^ 0x3);
2556 break;
2557
2558 case NIU_FLAGS_10G:
2559 /* 10G copper */
e0d8496a 2560 tp = &phy_template_10g_copper;
a3138df9
DM		 2561 break;
2562
2563 case NIU_FLAGS_FIBER:
2564 /* 1G fiber */
2565 tp = &phy_template_1g_fiber;
2566 break;
2567
2568 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2569 /* 10G fiber */
2570 tp = &phy_template_10g_fiber;
2571 if (plat_type == PLAT_TYPE_VF_P0 ||
2572 plat_type == PLAT_TYPE_VF_P1)
2573 phy_addr_off = 8;
2574 phy_addr_off += np->port;
a5d6ab56
MW		 2575 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2576 tp = &phy_template_10g_fiber_hotplug;
2577 if (np->port == 0)
2578 phy_addr_off = 8;
2579 if (np->port == 1)
2580 phy_addr_off = 12;
2581 }
a3138df9
DM		 2582 break;
2583
5fbd7e24
MW		 2584 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2585 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2586 case NIU_FLAGS_XCVR_SERDES:
2587 switch(np->port) {
2588 case 0:
2589 case 1:
2590 tp = &phy_template_10g_serdes;
2591 break;
2592 case 2:
2593 case 3:
2594 tp = &phy_template_1g_rgmii;
2595 break;
2596 default:
2597 return -EINVAL;
2598 break;
2599 }
2600 phy_addr_off = niu_atca_port_num[np->port];
2601 break;
2602
a3138df9
DM		 2603 default:
2604 return -EINVAL;
2605 }
2606 }
2607
2608 np->phy_ops = tp->ops;
2609 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2610
2611 return 0;
2612}
2613
2614static int niu_init_link(struct niu *np)
2615{
2616 struct niu_parent *parent = np->parent;
2617 int err, ignore;
2618
2619 if (parent->plat_type == PLAT_TYPE_NIU) {
2620 err = niu_xcvr_init(np);
2621 if (err)
2622 return err;
2623 msleep(200);
2624 }
2625 err = niu_serdes_init(np);
9c5cd670 2626 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2627 return err;
2628 msleep(200);
2629 err = niu_xcvr_init(np);
9c5cd670 2630 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2631 niu_link_status(np, &ignore);
2632 return 0;
2633}
2634
2635static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2636{
2637 u16 reg0 = addr[4] << 8 | addr[5];
2638 u16 reg1 = addr[2] << 8 | addr[3];
2639 u16 reg2 = addr[0] << 8 | addr[1];
2640
2641 if (np->flags & NIU_FLAGS_XMAC) {
2642 nw64_mac(XMAC_ADDR0, reg0);
2643 nw64_mac(XMAC_ADDR1, reg1);
2644 nw64_mac(XMAC_ADDR2, reg2);
2645 } else {
2646 nw64_mac(BMAC_ADDR0, reg0);
2647 nw64_mac(BMAC_ADDR1, reg1);
2648 nw64_mac(BMAC_ADDR2, reg2);
2649 }
2650}
2651
2652static int niu_num_alt_addr(struct niu *np)
2653{
2654 if (np->flags & NIU_FLAGS_XMAC)
2655 return XMAC_NUM_ALT_ADDR;
2656 else
2657 return BMAC_NUM_ALT_ADDR;
2658}
2659
2660static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2661{
2662 u16 reg0 = addr[4] << 8 | addr[5];
2663 u16 reg1 = addr[2] << 8 | addr[3];
2664 u16 reg2 = addr[0] << 8 | addr[1];
2665
2666 if (index >= niu_num_alt_addr(np))
2667 return -EINVAL;
2668
2669 if (np->flags & NIU_FLAGS_XMAC) {
2670 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2671 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2672 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2673 } else {
2674 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2677 }
2678
2679 return 0;
2680}
2681
2682static int niu_enable_alt_mac(struct niu *np, int index, int on)
2683{
2684 unsigned long reg;
2685 u64 val, mask;
2686
2687 if (index >= niu_num_alt_addr(np))
2688 return -EINVAL;
2689
fa907895 2690 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2691 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2692 mask = 1 << index;
2693 } else {
a3138df9 2694 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2695 mask = 1 << (index + 1);
2696 }
a3138df9
DM		 2697
2698 val = nr64_mac(reg);
2699 if (on)
2700 val |= mask;
2701 else
2702 val &= ~mask;
2703 nw64_mac(reg, val);
2704
2705 return 0;
2706}
2707
2708static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2709 int num, int mac_pref)
2710{
2711 u64 val = nr64_mac(reg);
2712 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2713 val |= num;
2714 if (mac_pref)
2715 val |= HOST_INFO_MPR;
2716 nw64_mac(reg, val);
2717}
2718
2719static int __set_rdc_table_num(struct niu *np,
2720 int xmac_index, int bmac_index,
2721 int rdc_table_num, int mac_pref)
2722{
2723 unsigned long reg;
2724
2725 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2726 return -EINVAL;
2727 if (np->flags & NIU_FLAGS_XMAC)
2728 reg = XMAC_HOST_INFO(xmac_index);
2729 else
2730 reg = BMAC_HOST_INFO(bmac_index);
2731 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2732 return 0;
2733}
2734
2735static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2736 int mac_pref)
2737{
2738 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2739}
2740
2741static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2742 int mac_pref)
2743{
2744 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2745}
2746
2747static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2748 int table_num, int mac_pref)
2749{
2750 if (idx >= niu_num_alt_addr(np))
2751 return -EINVAL;
2752 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2753}
2754
2755static u64 vlan_entry_set_parity(u64 reg_val)
2756{
2757 u64 port01_mask;
2758 u64 port23_mask;
2759
2760 port01_mask = 0x00ff;
2761 port23_mask = 0xff00;
2762
2763 if (hweight64(reg_val & port01_mask) & 1)
2764 reg_val |= ENET_VLAN_TBL_PARITY0;
2765 else
2766 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2767
2768 if (hweight64(reg_val & port23_mask) & 1)
2769 reg_val |= ENET_VLAN_TBL_PARITY1;
2770 else
2771 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2772
2773 return reg_val;
2774}
2775
2776static void vlan_tbl_write(struct niu *np, unsigned long index,
2777 int port, int vpr, int rdc_table)
2778{
2779 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2780
2781 reg_val &= ~((ENET_VLAN_TBL_VPR |
2782 ENET_VLAN_TBL_VLANRDCTBLN) <<
2783 ENET_VLAN_TBL_SHIFT(port));
2784 if (vpr)
2785 reg_val |= (ENET_VLAN_TBL_VPR <<
2786 ENET_VLAN_TBL_SHIFT(port));
2787 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2788
2789 reg_val = vlan_entry_set_parity(reg_val);
2790
2791 nw64(ENET_VLAN_TBL(index), reg_val);
2792}
2793
2794static void vlan_tbl_clear(struct niu *np)
2795{
2796 int i;
2797
2798 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2799 nw64(ENET_VLAN_TBL(i), 0);
2800}
2801
2802static int tcam_wait_bit(struct niu *np, u64 bit)
2803{
2804 int limit = 1000;
2805
2806 while (--limit > 0) {
2807 if (nr64(TCAM_CTL) & bit)
2808 break;
2809 udelay(1);
2810 }
d2a928e4 2811 if (limit <= 0)
a3138df9
DM		 2812 return -ENODEV;
2813
2814 return 0;
2815}
2816
2817static int tcam_flush(struct niu *np, int index)
2818{
2819 nw64(TCAM_KEY_0, 0x00);
2820 nw64(TCAM_KEY_MASK_0, 0xff);
2821 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2822
2823 return tcam_wait_bit(np, TCAM_CTL_STAT);
2824}
2825
2826#if 0
2827static int tcam_read(struct niu *np, int index,
2828 u64 *key, u64 *mask)
2829{
2830 int err;
2831
2832 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2833 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2834 if (!err) {
2835 key[0] = nr64(TCAM_KEY_0);
2836 key[1] = nr64(TCAM_KEY_1);
2837 key[2] = nr64(TCAM_KEY_2);
2838 key[3] = nr64(TCAM_KEY_3);
2839 mask[0] = nr64(TCAM_KEY_MASK_0);
2840 mask[1] = nr64(TCAM_KEY_MASK_1);
2841 mask[2] = nr64(TCAM_KEY_MASK_2);
2842 mask[3] = nr64(TCAM_KEY_MASK_3);
2843 }
2844 return err;
2845}
2846#endif
2847
2848static int tcam_write(struct niu *np, int index,
2849 u64 *key, u64 *mask)
2850{
2851 nw64(TCAM_KEY_0, key[0]);
2852 nw64(TCAM_KEY_1, key[1]);
2853 nw64(TCAM_KEY_2, key[2]);
2854 nw64(TCAM_KEY_3, key[3]);
2855 nw64(TCAM_KEY_MASK_0, mask[0]);
2856 nw64(TCAM_KEY_MASK_1, mask[1]);
2857 nw64(TCAM_KEY_MASK_2, mask[2]);
2858 nw64(TCAM_KEY_MASK_3, mask[3]);
2859 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2860
2861 return tcam_wait_bit(np, TCAM_CTL_STAT);
2862}
2863
2864#if 0
2865static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2866{
2867 int err;
2868
2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2870 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2871 if (!err)
2872 *data = nr64(TCAM_KEY_1);
2873
2874 return err;
2875}
2876#endif
2877
2878static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2879{
2880 nw64(TCAM_KEY_1, assoc_data);
2881 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2882
2883 return tcam_wait_bit(np, TCAM_CTL_STAT);
2884}
2885
2886static void tcam_enable(struct niu *np, int on)
2887{
2888 u64 val = nr64(FFLP_CFG_1);
2889
2890 if (on)
2891 val &= ~FFLP_CFG_1_TCAM_DIS;
2892 else
2893 val |= FFLP_CFG_1_TCAM_DIS;
2894 nw64(FFLP_CFG_1, val);
2895}
2896
2897static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2898{
2899 u64 val = nr64(FFLP_CFG_1);
2900
2901 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2902 FFLP_CFG_1_CAMLAT |
2903 FFLP_CFG_1_CAMRATIO);
2904 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2905 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2906 nw64(FFLP_CFG_1, val);
2907
2908 val = nr64(FFLP_CFG_1);
2909 val |= FFLP_CFG_1_FFLPINITDONE;
2910 nw64(FFLP_CFG_1, val);
2911}
2912
2913static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2914 int on)
2915{
2916 unsigned long reg;
2917 u64 val;
2918
2919 if (class < CLASS_CODE_ETHERTYPE1 ||
2920 class > CLASS_CODE_ETHERTYPE2)
2921 return -EINVAL;
2922
2923 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2924 val = nr64(reg);
2925 if (on)
2926 val |= L2_CLS_VLD;
2927 else
2928 val &= ~L2_CLS_VLD;
2929 nw64(reg, val);
2930
2931 return 0;
2932}
2933
2934#if 0
2935static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2936 u64 ether_type)
2937{
2938 unsigned long reg;
2939 u64 val;
2940
2941 if (class < CLASS_CODE_ETHERTYPE1 ||
2942 class > CLASS_CODE_ETHERTYPE2 ||
2943 (ether_type & ~(u64)0xffff) != 0)
2944 return -EINVAL;
2945
2946 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2947 val = nr64(reg);
2948 val &= ~L2_CLS_ETYPE;
2949 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2950 nw64(reg, val);
2951
2952 return 0;
2953}
2954#endif
2955
2956static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2957 int on)
2958{
2959 unsigned long reg;
2960 u64 val;
2961
2962 if (class < CLASS_CODE_USER_PROG1 ||
2963 class > CLASS_CODE_USER_PROG4)
2964 return -EINVAL;
2965
2966 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2967 val = nr64(reg);
2968 if (on)
2969 val |= L3_CLS_VALID;
2970 else
2971 val &= ~L3_CLS_VALID;
2972 nw64(reg, val);
2973
2974 return 0;
2975}
2976
a3138df9
DM		 2977static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2978 int ipv6, u64 protocol_id,
2979 u64 tos_mask, u64 tos_val)
2980{
2981 unsigned long reg;
2982 u64 val;
2983
2984 if (class < CLASS_CODE_USER_PROG1 ||
2985 class > CLASS_CODE_USER_PROG4 ||
2986 (protocol_id & ~(u64)0xff) != 0 ||
2987 (tos_mask & ~(u64)0xff) != 0 ||
2988 (tos_val & ~(u64)0xff) != 0)
2989 return -EINVAL;
2990
2991 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2992 val = nr64(reg);
2993 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2994 L3_CLS_TOSMASK | L3_CLS_TOS);
2995 if (ipv6)
2996 val |= L3_CLS_IPVER;
2997 val |= (protocol_id << L3_CLS_PID_SHIFT);
2998 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2999 val |= (tos_val << L3_CLS_TOS_SHIFT);
3000 nw64(reg, val);
3001
3002 return 0;
3003}
a3138df9
DM		 3004
3005static int tcam_early_init(struct niu *np)
3006{
3007 unsigned long i;
3008 int err;
3009
3010 tcam_enable(np, 0);
3011 tcam_set_lat_and_ratio(np,
3012 DEFAULT_TCAM_LATENCY,
3013 DEFAULT_TCAM_ACCESS_RATIO);
3014 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3015 err = tcam_user_eth_class_enable(np, i, 0);
3016 if (err)
3017 return err;
3018 }
3019 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3020 err = tcam_user_ip_class_enable(np, i, 0);
3021 if (err)
3022 return err;
3023 }
3024
3025 return 0;
3026}
3027
3028static int tcam_flush_all(struct niu *np)
3029{
3030 unsigned long i;
3031
3032 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3033 int err = tcam_flush(np, i);
3034 if (err)
3035 return err;
3036 }
3037 return 0;
3038}
3039
3040static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3041{
807540ba 3042 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
a3138df9
DM		 3043}
3044
3045#if 0
3046static int hash_read(struct niu *np, unsigned long partition,
3047 unsigned long index, unsigned long num_entries,
3048 u64 *data)
3049{
3050 u64 val = hash_addr_regval(index, num_entries);
3051 unsigned long i;
3052
3053 if (partition >= FCRAM_NUM_PARTITIONS ||
3054 index + num_entries > FCRAM_SIZE)
3055 return -EINVAL;
3056
3057 nw64(HASH_TBL_ADDR(partition), val);
3058 for (i = 0; i < num_entries; i++)
3059 data[i] = nr64(HASH_TBL_DATA(partition));
3060
3061 return 0;
3062}
3063#endif
3064
3065static int hash_write(struct niu *np, unsigned long partition,
3066 unsigned long index, unsigned long num_entries,
3067 u64 *data)
3068{
3069 u64 val = hash_addr_regval(index, num_entries);
3070 unsigned long i;
3071
3072 if (partition >= FCRAM_NUM_PARTITIONS ||
3073 index + (num_entries * 8) > FCRAM_SIZE)
3074 return -EINVAL;
3075
3076 nw64(HASH_TBL_ADDR(partition), val);
3077 for (i = 0; i < num_entries; i++)
3078 nw64(HASH_TBL_DATA(partition), data[i]);
3079
3080 return 0;
3081}
3082
3083static void fflp_reset(struct niu *np)
3084{
3085 u64 val;
3086
3087 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3088 udelay(10);
3089 nw64(FFLP_CFG_1, 0);
3090
3091 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3092 nw64(FFLP_CFG_1, val);
3093}
3094
3095static void fflp_set_timings(struct niu *np)
3096{
3097 u64 val = nr64(FFLP_CFG_1);
3098
3099 val &= ~FFLP_CFG_1_FFLPINITDONE;
3100 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3101 nw64(FFLP_CFG_1, val);
3102
3103 val = nr64(FFLP_CFG_1);
3104 val |= FFLP_CFG_1_FFLPINITDONE;
3105 nw64(FFLP_CFG_1, val);
3106
3107 val = nr64(FCRAM_REF_TMR);
3108 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3109 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3110 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3111 nw64(FCRAM_REF_TMR, val);
3112}
3113
3114static int fflp_set_partition(struct niu *np, u64 partition,
3115 u64 mask, u64 base, int enable)
3116{
3117 unsigned long reg;
3118 u64 val;
3119
3120 if (partition >= FCRAM_NUM_PARTITIONS ||
3121 (mask & ~(u64)0x1f) != 0 ||
3122 (base & ~(u64)0x1f) != 0)
3123 return -EINVAL;
3124
3125 reg = FLW_PRT_SEL(partition);
3126
3127 val = nr64(reg);
3128 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3129 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3130 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3131 if (enable)
3132 val |= FLW_PRT_SEL_EXT;
3133 nw64(reg, val);
3134
3135 return 0;
3136}
3137
3138static int fflp_disable_all_partitions(struct niu *np)
3139{
3140 unsigned long i;
3141
3142 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3143 int err = fflp_set_partition(np, 0, 0, 0, 0);
3144 if (err)
3145 return err;
3146 }
3147 return 0;
3148}
3149
3150static void fflp_llcsnap_enable(struct niu *np, int on)
3151{
3152 u64 val = nr64(FFLP_CFG_1);
3153
3154 if (on)
3155 val |= FFLP_CFG_1_LLCSNAP;
3156 else
3157 val &= ~FFLP_CFG_1_LLCSNAP;
3158 nw64(FFLP_CFG_1, val);
3159}
3160
3161static void fflp_errors_enable(struct niu *np, int on)
3162{
3163 u64 val = nr64(FFLP_CFG_1);
3164
3165 if (on)
3166 val &= ~FFLP_CFG_1_ERRORDIS;
3167 else
3168 val |= FFLP_CFG_1_ERRORDIS;
3169 nw64(FFLP_CFG_1, val);
3170}
3171
3172static int fflp_hash_clear(struct niu *np)
3173{
3174 struct fcram_hash_ipv4 ent;
3175 unsigned long i;
3176
3177 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3178 memset(&ent, 0, sizeof(ent));
3179 ent.header = HASH_HEADER_EXT;
3180
3181 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3182 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3183 if (err)
3184 return err;
3185 }
3186 return 0;
3187}
3188
3189static int fflp_early_init(struct niu *np)
3190{
3191 struct niu_parent *parent;
3192 unsigned long flags;
3193 int err;
3194
3195 niu_lock_parent(np, flags);
3196
3197 parent = np->parent;
3198 err = 0;
3199 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3200 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3201 fflp_reset(np);
3202 fflp_set_timings(np);
3203 err = fflp_disable_all_partitions(np);
3204 if (err) {
f10a1f2e
JP		 3205 netif_printk(np, probe, KERN_DEBUG, np->dev,
3206 "fflp_disable_all_partitions failed, err=%d\n",
3207 err);
a3138df9
DM		 3208 goto out;
3209 }
3210 }
3211
3212 err = tcam_early_init(np);
3213 if (err) {
f10a1f2e
JP		 3214 netif_printk(np, probe, KERN_DEBUG, np->dev,
3215 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3216 goto out;
3217 }
3218 fflp_llcsnap_enable(np, 1);
3219 fflp_errors_enable(np, 0);
3220 nw64(H1POLY, 0);
3221 nw64(H2POLY, 0);
3222
3223 err = tcam_flush_all(np);
3224 if (err) {
f10a1f2e
JP		 3225 netif_printk(np, probe, KERN_DEBUG, np->dev,
3226 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3227 goto out;
3228 }
3229 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3230 err = fflp_hash_clear(np);
3231 if (err) {
f10a1f2e
JP		 3232 netif_printk(np, probe, KERN_DEBUG, np->dev,
3233 "fflp_hash_clear failed, err=%d\n",
3234 err);
a3138df9
DM		 3235 goto out;
3236 }
3237 }
3238
3239 vlan_tbl_clear(np);
3240
a3138df9
DM		 3241 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3242 }
3243out:
3244 niu_unlock_parent(np, flags);
3245 return err;
3246}
3247
3248static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3249{
3250 if (class_code < CLASS_CODE_USER_PROG1 ||
3251 class_code > CLASS_CODE_SCTP_IPV6)
3252 return -EINVAL;
3253
3254 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3255 return 0;
3256}
3257
3258static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3259{
3260 if (class_code < CLASS_CODE_USER_PROG1 ||
3261 class_code > CLASS_CODE_SCTP_IPV6)
3262 return -EINVAL;
3263
3264 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3265 return 0;
3266}
3267
2d96cf8c
SB		 3268/* Entries for the ports are interleaved in the TCAM */
3269static u16 tcam_get_index(struct niu *np, u16 idx)
3270{
3271 /* One entry reserved for IP fragment rule */
3272 if (idx >= (np->clas.tcam_sz - 1))
3273 idx = 0;
807540ba 3274 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
2d96cf8c
SB		 3275}
3276
3277static u16 tcam_get_size(struct niu *np)
3278{
3279 /* One entry reserved for IP fragment rule */
3280 return np->clas.tcam_sz - 1;
3281}
3282
3283static u16 tcam_get_valid_entry_cnt(struct niu *np)
3284{
3285 /* One entry reserved for IP fragment rule */
3286 return np->clas.tcam_valid_entries - 1;
3287}
3288
a3138df9
DM		 3289static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3290 u32 offset, u32 size)
3291{
3292 int i = skb_shinfo(skb)->nr_frags;
3293 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3294
3295 frag->page = page;
3296 frag->page_offset = offset;
3297 frag->size = size;
3298
3299 skb->len += size;
3300 skb->data_len += size;
3301 skb->truesize += size;
3302
3303 skb_shinfo(skb)->nr_frags = i + 1;
3304}
3305
3306static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3307{
3308 a >>= PAGE_SHIFT;
3309 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3310
807540ba 3311 return a & (MAX_RBR_RING_SIZE - 1);
a3138df9
DM		 3312}
3313
3314static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3315 struct page ***link)
3316{
3317 unsigned int h = niu_hash_rxaddr(rp, addr);
3318 struct page *p, **pp;
3319
3320 addr &= PAGE_MASK;
3321 pp = &rp->rxhash[h];
3322 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3323 if (p->index == addr) {
3324 *link = pp;
a0387169 3325 goto found;
a3138df9
DM		 3326 }
3327 }
a0387169 3328 BUG();
a3138df9 3329
a0387169 3330found:
a3138df9
DM		 3331 return p;
3332}
3333
3334static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3335{
3336 unsigned int h = niu_hash_rxaddr(rp, base);
3337
3338 page->index = base;
3339 page->mapping = (struct address_space *) rp->rxhash[h];
3340 rp->rxhash[h] = page;
3341}
3342
3343static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3344 gfp_t mask, int start_index)
3345{
3346 struct page *page;
3347 u64 addr;
3348 int i;
3349
3350 page = alloc_page(mask);
3351 if (!page)
3352 return -ENOMEM;
3353
3354 addr = np->ops->map_page(np->device, page, 0,
3355 PAGE_SIZE, DMA_FROM_DEVICE);
3356
3357 niu_hash_page(rp, page, addr);
3358 if (rp->rbr_blocks_per_page > 1)
3359 atomic_add(rp->rbr_blocks_per_page - 1,
3360 &compound_head(page)->_count);
3361
3362 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3363 __le32 *rbr = &rp->rbr[start_index + i];
3364
3365 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3366 addr += rp->rbr_block_size;
3367 }
3368
3369 return 0;
3370}
3371
3372static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3373{
3374 int index = rp->rbr_index;
3375
3376 rp->rbr_pending++;
3377 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3378 int err = niu_rbr_add_page(np, rp, mask, index);
3379
3380 if (unlikely(err)) {
3381 rp->rbr_pending--;
3382 return;
3383 }
3384
3385 rp->rbr_index += rp->rbr_blocks_per_page;
3386 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3387 if (rp->rbr_index == rp->rbr_table_size)
3388 rp->rbr_index = 0;
3389
3390 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3391 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3392 rp->rbr_pending = 0;
3393 }
3394 }
3395}
3396
3397static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3398{
3399 unsigned int index = rp->rcr_index;
3400 int num_rcr = 0;
3401
3402 rp->rx_dropped++;
3403 while (1) {
3404 struct page *page, **link;
3405 u64 addr, val;
3406 u32 rcr_size;
3407
3408 num_rcr++;
3409
3410 val = le64_to_cpup(&rp->rcr[index]);
3411 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3412 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3413 page = niu_find_rxpage(rp, addr, &link);
3414
3415 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3416 RCR_ENTRY_PKTBUFSZ_SHIFT];
3417 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3418 *link = (struct page *) page->mapping;
3419 np->ops->unmap_page(np->device, page->index,
3420 PAGE_SIZE, DMA_FROM_DEVICE);
3421 page->index = 0;
3422 page->mapping = NULL;
3423 __free_page(page);
3424 rp->rbr_refill_pending++;
3425 }
3426
3427 index = NEXT_RCR(rp, index);
3428 if (!(val & RCR_ENTRY_MULTI))
3429 break;
3430
3431 }
3432 rp->rcr_index = index;
3433
3434 return num_rcr;
3435}
3436
4099e012
DM		 3437static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3438 struct rx_ring_info *rp)
a3138df9
DM		 3439{
3440 unsigned int index = rp->rcr_index;
3cfa856d 3441 struct rx_pkt_hdr1 *rh;
a3138df9
DM		 3442 struct sk_buff *skb;
3443 int len, num_rcr;
3444
3445 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3446 if (unlikely(!skb))
3447 return niu_rx_pkt_ignore(np, rp);
3448
3449 num_rcr = 0;
3450 while (1) {
3451 struct page *page, **link;
3452 u32 rcr_size, append_size;
3453 u64 addr, val, off;
3454
3455 num_rcr++;
3456
3457 val = le64_to_cpup(&rp->rcr[index]);
3458
3459 len = (val & RCR_ENTRY_L2_LEN) >>
3460 RCR_ENTRY_L2_LEN_SHIFT;
3461 len -= ETH_FCS_LEN;
3462
3463 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3464 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3465 page = niu_find_rxpage(rp, addr, &link);
3466
3467 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3468 RCR_ENTRY_PKTBUFSZ_SHIFT];
3469
3470 off = addr & ~PAGE_MASK;
3471 append_size = rcr_size;
3472 if (num_rcr == 1) {
3473 int ptype;
3474
a3138df9
DM		 3475 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3476 if ((ptype == RCR_PKT_TYPE_TCP ||
3477 ptype == RCR_PKT_TYPE_UDP) &&
3478 !(val & (RCR_ENTRY_NOPORT |
3479 RCR_ENTRY_ERROR)))
3480 skb->ip_summed = CHECKSUM_UNNECESSARY;
3481 else
bc8acf2c 3482 skb_checksum_none_assert(skb);
3cfa856d 3483 } else if (!(val & RCR_ENTRY_MULTI))
a3138df9
DM		 3484 append_size = len - skb->len;
3485
3486 niu_rx_skb_append(skb, page, off, append_size);
3487 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3488 *link = (struct page *) page->mapping;
3489 np->ops->unmap_page(np->device, page->index,
3490 PAGE_SIZE, DMA_FROM_DEVICE);
3491 page->index = 0;
3492 page->mapping = NULL;
3493 rp->rbr_refill_pending++;
3494 } else
3495 get_page(page);
3496
3497 index = NEXT_RCR(rp, index);
3498 if (!(val & RCR_ENTRY_MULTI))
3499 break;
3500
3501 }
3502 rp->rcr_index = index;
3503
3cfa856d
DM		 3504 len += sizeof(*rh);
3505 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3506 __pskb_pull_tail(skb, len);
3507
3508 rh = (struct rx_pkt_hdr1 *) skb->data;
3509 if (np->dev->features & NETIF_F_RXHASH)
3510 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3511 (u32)rh->hashval2_1 << 16 |
3512 (u32)rh->hashval1_1 << 8 |
3513 (u32)rh->hashval1_2 << 0);
3514 skb_pull(skb, sizeof(*rh));
a3138df9
DM		 3515
3516 rp->rx_packets++;
3517 rp->rx_bytes += skb->len;
3518
3519 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3520 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3521 napi_gro_receive(napi, skb);
a3138df9
DM		 3522
3523 return num_rcr;
3524}
3525
3526static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3527{
3528 int blocks_per_page = rp->rbr_blocks_per_page;
3529 int err, index = rp->rbr_index;
3530
3531 err = 0;
3532 while (index < (rp->rbr_table_size - blocks_per_page)) {
3533 err = niu_rbr_add_page(np, rp, mask, index);
3534 if (err)
3535 break;
3536
3537 index += blocks_per_page;
3538 }
3539
3540 rp->rbr_index = index;
3541 return err;
3542}
3543
3544static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3545{
3546 int i;
3547
3548 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3549 struct page *page;
3550
3551 page = rp->rxhash[i];
3552 while (page) {
3553 struct page *next = (struct page *) page->mapping;
3554 u64 base = page->index;
3555
3556 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3557 DMA_FROM_DEVICE);
3558 page->index = 0;
3559 page->mapping = NULL;
3560
3561 __free_page(page);
3562
3563 page = next;
3564 }
3565 }
3566
3567 for (i = 0; i < rp->rbr_table_size; i++)
3568 rp->rbr[i] = cpu_to_le32(0);
3569 rp->rbr_index = 0;
3570}
3571
3572static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3573{
3574 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3575 struct sk_buff *skb = tb->skb;
3576 struct tx_pkt_hdr *tp;
3577 u64 tx_flags;
3578 int i, len;
3579
3580 tp = (struct tx_pkt_hdr *) skb->data;
3581 tx_flags = le64_to_cpup(&tp->flags);
3582
3583 rp->tx_packets++;
3584 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3585 ((tx_flags & TXHDR_PAD) / 2));
3586
3587 len = skb_headlen(skb);
3588 np->ops->unmap_single(np->device, tb->mapping,
3589 len, DMA_TO_DEVICE);
3590
3591 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3592 rp->mark_pending--;
3593
3594 tb->skb = NULL;
3595 do {
3596 idx = NEXT_TX(rp, idx);
3597 len -= MAX_TX_DESC_LEN;
3598 } while (len > 0);
3599
3600 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3601 tb = &rp->tx_buffs[idx];
3602 BUG_ON(tb->skb != NULL);
3603 np->ops->unmap_page(np->device, tb->mapping,
3604 skb_shinfo(skb)->frags[i].size,
3605 DMA_TO_DEVICE);
3606 idx = NEXT_TX(rp, idx);
3607 }
3608
3609 dev_kfree_skb(skb);
3610
3611 return idx;
3612}
3613
3614#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3615
3616static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3617{
b4c21639 3618 struct netdev_queue *txq;
a3138df9 3619 u16 pkt_cnt, tmp;
b4c21639 3620 int cons, index;
a3138df9
DM		 3621 u64 cs;
3622
b4c21639
DM		 3623 index = (rp - np->tx_rings);
3624 txq = netdev_get_tx_queue(np->dev, index);
3625
a3138df9
DM		 3626 cs = rp->tx_cs;
3627 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3628 goto out;
3629
3630 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3631 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3632 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3633
3634 rp->last_pkt_cnt = tmp;
3635
3636 cons = rp->cons;
3637
f10a1f2e
JP		 3638 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3639 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3640
3641 while (pkt_cnt--)
3642 cons = release_tx_packet(np, rp, cons);
3643
3644 rp->cons = cons;
3645 smp_mb();
3646
3647out:
b4c21639 3648 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3649 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3650 __netif_tx_lock(txq, smp_processor_id());
3651 if (netif_tx_queue_stopped(txq) &&
a3138df9 3652 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3653 netif_tx_wake_queue(txq);
3654 __netif_tx_unlock(txq);
a3138df9
DM		 3655 }
3656}
3657
b8a606b8
JDB		 3658static inline void niu_sync_rx_discard_stats(struct niu *np,
3659 struct rx_ring_info *rp,
3660 const int limit)
3661{
3662 /* This elaborate scheme is needed for reading the RX discard
3663 * counters, as they are only 16-bit and can overflow quickly,
3664 * and because the overflow indication bit is not usable as
3665 * the counter value does not wrap, but remains at max value
3666 * 0xFFFF.
3667 *
3668 * In theory and in practice counters can be lost in between
3669 * reading nr64() and clearing the counter nw64(). For this
3670 * reason, the number of counter clearings nw64() is
3671 * limited/reduced though the limit parameter.
3672 */
3673 int rx_channel = rp->rx_channel;
3674 u32 misc, wred;
3675
3676 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3677 * following discard events: IPP (Input Port Process),
3678 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3679 * Block Ring) prefetch buffer is empty.
3680 */
3681 misc = nr64(RXMISC(rx_channel));
3682 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3683 nw64(RXMISC(rx_channel), 0);
3684 rp->rx_errors += misc & RXMISC_COUNT;
3685
3686 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3687 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3688 rx_channel);
d231776f 3689
f10a1f2e
JP		 3690 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3691 "rx-%d: MISC drop=%u over=%u\n",
3692 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3693 }
3694
3695 /* WRED (Weighted Random Early Discard) by hardware */
3696 wred = nr64(RED_DIS_CNT(rx_channel));
3697 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3698 nw64(RED_DIS_CNT(rx_channel), 0);
3699 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3700
3701 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3702 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3703
f10a1f2e
JP		 3704 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3705 "rx-%d: WRED drop=%u over=%u\n",
3706 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3707 }
3708}
3709
4099e012
DM		 3710static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3711 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3712{
3713 int qlen, rcr_done = 0, work_done = 0;
3714 struct rxdma_mailbox *mbox = rp->mbox;
3715 u64 stat;
3716
3717#if 1
3718 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3719 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3720#else
3721 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3722 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3723#endif
3724 mbox->rx_dma_ctl_stat = 0;
3725 mbox->rcrstat_a = 0;
3726
f10a1f2e
JP		 3727 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3728 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3729 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3730
3731 rcr_done = work_done = 0;
3732 qlen = min(qlen, budget);
3733 while (work_done < qlen) {
4099e012 3734 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3735 work_done++;
3736 }
3737
3738 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3739 unsigned int i;
3740
3741 for (i = 0; i < rp->rbr_refill_pending; i++)
3742 niu_rbr_refill(np, rp, GFP_ATOMIC);
3743 rp->rbr_refill_pending = 0;
3744 }
3745
3746 stat = (RX_DMA_CTL_STAT_MEX |
3747 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3748 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3749
3750 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3751
e98def1f
JDB		 3752 /* Only sync discards stats when qlen indicate potential for drops */
3753 if (qlen > 10)
3754 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3755
a3138df9
DM		 3756 return work_done;
3757}
3758
3759static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3760{
3761 u64 v0 = lp->v0;
3762 u32 tx_vec = (v0 >> 32);
3763 u32 rx_vec = (v0 & 0xffffffff);
3764 int i, work_done = 0;
3765
f10a1f2e
JP		 3766 netif_printk(np, intr, KERN_DEBUG, np->dev,
3767 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3768
3769 for (i = 0; i < np->num_tx_rings; i++) {
3770 struct tx_ring_info *rp = &np->tx_rings[i];
3771 if (tx_vec & (1 << rp->tx_channel))
3772 niu_tx_work(np, rp);
3773 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3774 }
3775
3776 for (i = 0; i < np->num_rx_rings; i++) {
3777 struct rx_ring_info *rp = &np->rx_rings[i];
3778
3779 if (rx_vec & (1 << rp->rx_channel)) {
3780 int this_work_done;
3781
4099e012 3782 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3783 budget);
3784
3785 budget -= this_work_done;
3786 work_done += this_work_done;
3787 }
3788 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3789 }
3790
3791 return work_done;
3792}
3793
3794static int niu_poll(struct napi_struct *napi, int budget)
3795{
3796 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3797 struct niu *np = lp->np;
3798 int work_done;
3799
3800 work_done = niu_poll_core(np, lp, budget);
3801
3802 if (work_done < budget) {
288379f0 3803 napi_complete(napi);
a3138df9
DM		 3804 niu_ldg_rearm(np, lp, 1);
3805 }
3806 return work_done;
3807}
3808
3809static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3810 u64 stat)
3811{
f10a1f2e 3812 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3813
3814 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3815 pr_cont("RBR_TMOUT ");
a3138df9 3816 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3817 pr_cont("RSP_CNT ");
a3138df9 3818 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3819 pr_cont("BYTE_EN_BUS ");
a3138df9 3820 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3821 pr_cont("RSP_DAT ");
a3138df9 3822 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3823 pr_cont("RCR_ACK ");
a3138df9 3824 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3825 pr_cont("RCR_SHA_PAR ");
a3138df9 3826 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3827 pr_cont("RBR_PRE_PAR ");
a3138df9 3828 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3829 pr_cont("CONFIG ");
a3138df9 3830 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3831 pr_cont("RCRINCON ");
a3138df9 3832 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3833 pr_cont("RCRFULL ");
a3138df9 3834 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3835 pr_cont("RBRFULL ");
a3138df9 3836 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3837 pr_cont("RBRLOGPAGE ");
a3138df9 3838 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3839 pr_cont("CFIGLOGPAGE ");
a3138df9 3840 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3841 pr_cont("DC_FIDO ");
a3138df9 3842
f10a1f2e 3843 pr_cont(")\n");
a3138df9
DM		 3844}
3845
3846static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3847{
3848 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3849 int err = 0;
3850
a3138df9
DM		 3851
3852 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3853 RX_DMA_CTL_STAT_PORT_FATAL))
3854 err = -EINVAL;
3855
406f353c 3856 if (err) {
f10a1f2e
JP		 3857 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3858 rp->rx_channel,
3859 (unsigned long long) stat);
406f353c
MW		 3860
3861 niu_log_rxchan_errors(np, rp, stat);
3862 }
3863
a3138df9
DM		 3864 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3865 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3866
3867 return err;
3868}
3869
3870static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3871 u64 cs)
3872{
f10a1f2e 3873 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3874
3875 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3876 pr_cont("MBOX ");
a3138df9 3877 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3878 pr_cont("PKT_SIZE ");
a3138df9 3879 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3880 pr_cont("TX_RING_OFLOW ");
a3138df9 3881 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3882 pr_cont("PREF_BUF_PAR ");
a3138df9 3883 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3884 pr_cont("NACK_PREF ");
a3138df9 3885 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3886 pr_cont("NACK_PKT_RD ");
a3138df9 3887 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3888 pr_cont("CONF_PART ");
a3138df9 3889 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3890 pr_cont("PKT_PTR ");
a3138df9 3891
f10a1f2e 3892 pr_cont(")\n");
a3138df9
DM		 3893}
3894
3895static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3896{
3897 u64 cs, logh, logl;
3898
3899 cs = nr64(TX_CS(rp->tx_channel));
3900 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3901 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3902
f10a1f2e
JP		 3903 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3904 rp->tx_channel,
3905 (unsigned long long)cs,
3906 (unsigned long long)logh,
3907 (unsigned long long)logl);
a3138df9
DM		 3908
3909 niu_log_txchan_errors(np, rp, cs);
3910
3911 return -ENODEV;
3912}
3913
3914static int niu_mif_interrupt(struct niu *np)
3915{
3916 u64 mif_status = nr64(MIF_STATUS);
3917 int phy_mdint = 0;
3918
3919 if (np->flags & NIU_FLAGS_XMAC) {
3920 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3921
3922 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3923 phy_mdint = 1;
3924 }
3925
f10a1f2e
JP		 3926 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3927 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3928
3929 return -ENODEV;
3930}
3931
3932static void niu_xmac_interrupt(struct niu *np)
3933{
3934 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3935 u64 val;
3936
3937 val = nr64_mac(XTXMAC_STATUS);
3938 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3939 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3940 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3941 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3942 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3943 mp->tx_fifo_errors++;
3944 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3945 mp->tx_overflow_errors++;
3946 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3947 mp->tx_max_pkt_size_errors++;
3948 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3949 mp->tx_underflow_errors++;
3950
3951 val = nr64_mac(XRXMAC_STATUS);
3952 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3953 mp->rx_local_faults++;
3954 if (val & XRXMAC_STATUS_RFLT_DET)
3955 mp->rx_remote_faults++;
3956 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3957 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3958 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3959 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3960 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3961 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3962 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3963 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3964 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3965 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3967 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3968 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3969 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3970 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3971 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3972 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3973 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3974 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3975 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3976 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3977 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3978 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3979 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3980 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3981 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3982 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3983 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3984 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3985 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3986 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3987 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3988 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3989 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3990 if (val & XRXMAC_STATUS_RXUFLOW)
3991 mp->rx_underflows++;
3992 if (val & XRXMAC_STATUS_RXOFLOW)
3993 mp->rx_overflows++;
3994
3995 val = nr64_mac(XMAC_FC_STAT);
3996 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3997 mp->pause_off_state++;
3998 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3999 mp->pause_on_state++;
4000 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4001 mp->pause_received++;
4002}
4003
4004static void niu_bmac_interrupt(struct niu *np)
4005{
4006 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4007 u64 val;
4008
4009 val = nr64_mac(BTXMAC_STATUS);
4010 if (val & BTXMAC_STATUS_UNDERRUN)
4011 mp->tx_underflow_errors++;
4012 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4013 mp->tx_max_pkt_size_errors++;
4014 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4015 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4016 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4017 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4018
4019 val = nr64_mac(BRXMAC_STATUS);
4020 if (val & BRXMAC_STATUS_OVERFLOW)
4021 mp->rx_overflows++;
4022 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4023 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4024 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4025 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4026 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4027 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4028 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4029 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4030
4031 val = nr64_mac(BMAC_CTRL_STATUS);
4032 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4033 mp->pause_off_state++;
4034 if (val & BMAC_CTRL_STATUS_PAUSE)
4035 mp->pause_on_state++;
4036 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4037 mp->pause_received++;
4038}
4039
4040static int niu_mac_interrupt(struct niu *np)
4041{
4042 if (np->flags & NIU_FLAGS_XMAC)
4043 niu_xmac_interrupt(np);
4044 else
4045 niu_bmac_interrupt(np);
4046
4047 return 0;
4048}
4049
4050static void niu_log_device_error(struct niu *np, u64 stat)
4051{
f10a1f2e 4052 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4053
4054 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4055 pr_cont("META2 ");
a3138df9 4056 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4057 pr_cont("META1 ");
a3138df9 4058 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4059 pr_cont("PEU ");
a3138df9 4060 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4061 pr_cont("TXC ");
a3138df9 4062 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4063 pr_cont("RDMC ");
a3138df9 4064 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4065 pr_cont("TDMC ");
a3138df9 4066 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4067 pr_cont("ZCP ");
a3138df9 4068 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4069 pr_cont("FFLP ");
a3138df9 4070 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4071 pr_cont("IPP ");
a3138df9 4072 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4073 pr_cont("MAC ");
a3138df9 4074 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4075 pr_cont("SMX ");
a3138df9 4076
f10a1f2e 4077 pr_cont(")\n");
a3138df9
DM		 4078}
4079
4080static int niu_device_error(struct niu *np)
4081{
4082 u64 stat = nr64(SYS_ERR_STAT);
4083
f10a1f2e
JP		 4084 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4085 (unsigned long long)stat);
a3138df9
DM		 4086
4087 niu_log_device_error(np, stat);
4088
4089 return -ENODEV;
4090}
4091
406f353c
MW		 4092static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4093 u64 v0, u64 v1, u64 v2)
a3138df9 4094{
406f353c 4095
a3138df9
DM		 4096 int i, err = 0;
4097
406f353c
MW		 4098 lp->v0 = v0;
4099 lp->v1 = v1;
4100 lp->v2 = v2;
4101
a3138df9
DM		 4102 if (v1 & 0x00000000ffffffffULL) {
4103 u32 rx_vec = (v1 & 0xffffffff);
4104
4105 for (i = 0; i < np->num_rx_rings; i++) {
4106 struct rx_ring_info *rp = &np->rx_rings[i];
4107
4108 if (rx_vec & (1 << rp->rx_channel)) {
4109 int r = niu_rx_error(np, rp);
406f353c 4110 if (r) {
a3138df9 4111 err = r;
406f353c
MW		 4112 } else {
4113 if (!v0)
4114 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4115 RX_DMA_CTL_STAT_MEX);
4116 }
a3138df9
DM		 4117 }
4118 }
4119 }
4120 if (v1 & 0x7fffffff00000000ULL) {
4121 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4122
4123 for (i = 0; i < np->num_tx_rings; i++) {
4124 struct tx_ring_info *rp = &np->tx_rings[i];
4125
4126 if (tx_vec & (1 << rp->tx_channel)) {
4127 int r = niu_tx_error(np, rp);
4128 if (r)
4129 err = r;
4130 }
4131 }
4132 }
4133 if ((v0 | v1) & 0x8000000000000000ULL) {
4134 int r = niu_mif_interrupt(np);
4135 if (r)
4136 err = r;
4137 }
4138 if (v2) {
4139 if (v2 & 0x01ef) {
4140 int r = niu_mac_interrupt(np);
4141 if (r)
4142 err = r;
4143 }
4144 if (v2 & 0x0210) {
4145 int r = niu_device_error(np);
4146 if (r)
4147 err = r;
4148 }
4149 }
4150
4151 if (err)
4152 niu_enable_interrupts(np, 0);
4153
406f353c 4154 return err;
a3138df9
DM		 4155}
4156
4157static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4158 int ldn)
4159{
4160 struct rxdma_mailbox *mbox = rp->mbox;
4161 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4162
4163 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4164 RX_DMA_CTL_STAT_RCRTO);
4165 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4166
f10a1f2e
JP		 4167 netif_printk(np, intr, KERN_DEBUG, np->dev,
4168 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4169}
4170
4171static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4172 int ldn)
4173{
4174 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4175
f10a1f2e
JP		 4176 netif_printk(np, intr, KERN_DEBUG, np->dev,
4177 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4178}
4179
4180static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4181{
4182 struct niu_parent *parent = np->parent;
4183 u32 rx_vec, tx_vec;
4184 int i;
4185
4186 tx_vec = (v0 >> 32);
4187 rx_vec = (v0 & 0xffffffff);
4188
4189 for (i = 0; i < np->num_rx_rings; i++) {
4190 struct rx_ring_info *rp = &np->rx_rings[i];
4191 int ldn = LDN_RXDMA(rp->rx_channel);
4192
4193 if (parent->ldg_map[ldn] != ldg)
4194 continue;
4195
4196 nw64(LD_IM0(ldn), LD_IM0_MASK);
4197 if (rx_vec & (1 << rp->rx_channel))
4198 niu_rxchan_intr(np, rp, ldn);
4199 }
4200
4201 for (i = 0; i < np->num_tx_rings; i++) {
4202 struct tx_ring_info *rp = &np->tx_rings[i];
4203 int ldn = LDN_TXDMA(rp->tx_channel);
4204
4205 if (parent->ldg_map[ldn] != ldg)
4206 continue;
4207
4208 nw64(LD_IM0(ldn), LD_IM0_MASK);
4209 if (tx_vec & (1 << rp->tx_channel))
4210 niu_txchan_intr(np, rp, ldn);
4211 }
4212}
4213
4214static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4215 u64 v0, u64 v1, u64 v2)
4216{
288379f0 4217 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4218 lp->v0 = v0;
4219 lp->v1 = v1;
4220 lp->v2 = v2;
4221 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4222 __napi_schedule(&lp->napi);
a3138df9
DM		 4223 }
4224}
4225
4226static irqreturn_t niu_interrupt(int irq, void *dev_id)
4227{
4228 struct niu_ldg *lp = dev_id;
4229 struct niu *np = lp->np;
4230 int ldg = lp->ldg_num;
4231 unsigned long flags;
4232 u64 v0, v1, v2;
4233
4234 if (netif_msg_intr(np))
f10a1f2e
JP		 4235 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4236 __func__, lp, ldg);
a3138df9
DM		 4237
4238 spin_lock_irqsave(&np->lock, flags);
4239
4240 v0 = nr64(LDSV0(ldg));
4241 v1 = nr64(LDSV1(ldg));
4242 v2 = nr64(LDSV2(ldg));
4243
4244 if (netif_msg_intr(np))
02b1bae5 4245 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4246 (unsigned long long) v0,
4247 (unsigned long long) v1,
4248 (unsigned long long) v2);
4249
4250 if (unlikely(!v0 && !v1 && !v2)) {
4251 spin_unlock_irqrestore(&np->lock, flags);
4252 return IRQ_NONE;
4253 }
4254
4255 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4256 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4257 if (err)
4258 goto out;
4259 }
4260 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4261 niu_schedule_napi(np, lp, v0, v1, v2);
4262 else
4263 niu_ldg_rearm(np, lp, 1);
4264out:
4265 spin_unlock_irqrestore(&np->lock, flags);
4266
4267 return IRQ_HANDLED;
4268}
4269
4270static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4271{
4272 if (rp->mbox) {
4273 np->ops->free_coherent(np->device,
4274 sizeof(struct rxdma_mailbox),
4275 rp->mbox, rp->mbox_dma);
4276 rp->mbox = NULL;
4277 }
4278 if (rp->rcr) {
4279 np->ops->free_coherent(np->device,
4280 MAX_RCR_RING_SIZE * sizeof(__le64),
4281 rp->rcr, rp->rcr_dma);
4282 rp->rcr = NULL;
4283 rp->rcr_table_size = 0;
4284 rp->rcr_index = 0;
4285 }
4286 if (rp->rbr) {
4287 niu_rbr_free(np, rp);
4288
4289 np->ops->free_coherent(np->device,
4290 MAX_RBR_RING_SIZE * sizeof(__le32),
4291 rp->rbr, rp->rbr_dma);
4292 rp->rbr = NULL;
4293 rp->rbr_table_size = 0;
4294 rp->rbr_index = 0;
4295 }
4296 kfree(rp->rxhash);
4297 rp->rxhash = NULL;
4298}
4299
4300static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4301{
4302 if (rp->mbox) {
4303 np->ops->free_coherent(np->device,
4304 sizeof(struct txdma_mailbox),
4305 rp->mbox, rp->mbox_dma);
4306 rp->mbox = NULL;
4307 }
4308 if (rp->descr) {
4309 int i;
4310
4311 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4312 if (rp->tx_buffs[i].skb)
4313 (void) release_tx_packet(np, rp, i);
4314 }
4315
4316 np->ops->free_coherent(np->device,
4317 MAX_TX_RING_SIZE * sizeof(__le64),
4318 rp->descr, rp->descr_dma);
4319 rp->descr = NULL;
4320 rp->pending = 0;
4321 rp->prod = 0;
4322 rp->cons = 0;
4323 rp->wrap_bit = 0;
4324 }
4325}
4326
4327static void niu_free_channels(struct niu *np)
4328{
4329 int i;
4330
4331 if (np->rx_rings) {
4332 for (i = 0; i < np->num_rx_rings; i++) {
4333 struct rx_ring_info *rp = &np->rx_rings[i];
4334
4335 niu_free_rx_ring_info(np, rp);
4336 }
4337 kfree(np->rx_rings);
4338 np->rx_rings = NULL;
4339 np->num_rx_rings = 0;
4340 }
4341
4342 if (np->tx_rings) {
4343 for (i = 0; i < np->num_tx_rings; i++) {
4344 struct tx_ring_info *rp = &np->tx_rings[i];
4345
4346 niu_free_tx_ring_info(np, rp);
4347 }
4348 kfree(np->tx_rings);
4349 np->tx_rings = NULL;
4350 np->num_tx_rings = 0;
4351 }
4352}
4353
4354static int niu_alloc_rx_ring_info(struct niu *np,
4355 struct rx_ring_info *rp)
4356{
4357 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4358
4359 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4360 GFP_KERNEL);
4361 if (!rp->rxhash)
4362 return -ENOMEM;
4363
4364 rp->mbox = np->ops->alloc_coherent(np->device,
4365 sizeof(struct rxdma_mailbox),
4366 &rp->mbox_dma, GFP_KERNEL);
4367 if (!rp->mbox)
4368 return -ENOMEM;
4369 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4370 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4371 rp->mbox);
a3138df9
DM		 4372 return -EINVAL;
4373 }
4374
4375 rp->rcr = np->ops->alloc_coherent(np->device,
4376 MAX_RCR_RING_SIZE * sizeof(__le64),
4377 &rp->rcr_dma, GFP_KERNEL);
4378 if (!rp->rcr)
4379 return -ENOMEM;
4380 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4381 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4382 rp->rcr);
a3138df9
DM		 4383 return -EINVAL;
4384 }
4385 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4386 rp->rcr_index = 0;
4387
4388 rp->rbr = np->ops->alloc_coherent(np->device,
4389 MAX_RBR_RING_SIZE * sizeof(__le32),
4390 &rp->rbr_dma, GFP_KERNEL);
4391 if (!rp->rbr)
4392 return -ENOMEM;
4393 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4394 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4395 rp->rbr);
a3138df9
DM		 4396 return -EINVAL;
4397 }
4398 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4399 rp->rbr_index = 0;
4400 rp->rbr_pending = 0;
4401
4402 return 0;
4403}
4404
4405static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4406{
4407 int mtu = np->dev->mtu;
4408
4409 /* These values are recommended by the HW designers for fair
4410 * utilization of DRR amongst the rings.
4411 */
4412 rp->max_burst = mtu + 32;
4413 if (rp->max_burst > 4096)
4414 rp->max_burst = 4096;
4415}
4416
4417static int niu_alloc_tx_ring_info(struct niu *np,
4418 struct tx_ring_info *rp)
4419{
4420 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4421
4422 rp->mbox = np->ops->alloc_coherent(np->device,
4423 sizeof(struct txdma_mailbox),
4424 &rp->mbox_dma, GFP_KERNEL);
4425 if (!rp->mbox)
4426 return -ENOMEM;
4427 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4428 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4429 rp->mbox);
a3138df9
DM		 4430 return -EINVAL;
4431 }
4432
4433 rp->descr = np->ops->alloc_coherent(np->device,
4434 MAX_TX_RING_SIZE * sizeof(__le64),
4435 &rp->descr_dma, GFP_KERNEL);
4436 if (!rp->descr)
4437 return -ENOMEM;
4438 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4439 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4440 rp->descr);
a3138df9
DM		 4441 return -EINVAL;
4442 }
4443
4444 rp->pending = MAX_TX_RING_SIZE;
4445 rp->prod = 0;
4446 rp->cons = 0;
4447 rp->wrap_bit = 0;
4448
4449 /* XXX make these configurable... XXX */
4450 rp->mark_freq = rp->pending / 4;
4451
4452 niu_set_max_burst(np, rp);
4453
4454 return 0;
4455}
4456
4457static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4458{
81429973 4459 u16 bss;
a3138df9 4460
81429973 4461 bss = min(PAGE_SHIFT, 15);
a3138df9 4462
81429973
OJ		 4463 rp->rbr_block_size = 1 << bss;
4464 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4465
4466 rp->rbr_sizes[0] = 256;
4467 rp->rbr_sizes[1] = 1024;
4468 if (np->dev->mtu > ETH_DATA_LEN) {
4469 switch (PAGE_SIZE) {
4470 case 4 * 1024:
4471 rp->rbr_sizes[2] = 4096;
4472 break;
4473
4474 default:
4475 rp->rbr_sizes[2] = 8192;
4476 break;
4477 }
4478 } else {
4479 rp->rbr_sizes[2] = 2048;
4480 }
4481 rp->rbr_sizes[3] = rp->rbr_block_size;
4482}
4483
4484static int niu_alloc_channels(struct niu *np)
4485{
4486 struct niu_parent *parent = np->parent;
4487 int first_rx_channel, first_tx_channel;
9690c636
DM		 4488 int num_rx_rings, num_tx_rings;
4489 struct rx_ring_info *rx_rings;
4490 struct tx_ring_info *tx_rings;
a3138df9
DM		 4491 int i, port, err;
4492
4493 port = np->port;
4494 first_rx_channel = first_tx_channel = 0;
4495 for (i = 0; i < port; i++) {
4496 first_rx_channel += parent->rxchan_per_port[i];
4497 first_tx_channel += parent->txchan_per_port[i];
4498 }
4499
9690c636
DM		 4500 num_rx_rings = parent->rxchan_per_port[port];
4501 num_tx_rings = parent->txchan_per_port[port];
a3138df9 4502
9690c636
DM		 4503 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4504 GFP_KERNEL);
a3138df9 4505 err = -ENOMEM;
9690c636 4506 if (!rx_rings)
a3138df9
DM		 4507 goto out_err;
4508
9690c636
DM		 4509 np->num_rx_rings = num_rx_rings;
4510 smp_wmb();
4511 np->rx_rings = rx_rings;
4512
4513 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4514
a3138df9
DM		 4515 for (i = 0; i < np->num_rx_rings; i++) {
4516 struct rx_ring_info *rp = &np->rx_rings[i];
4517
4518 rp->np = np;
4519 rp->rx_channel = first_rx_channel + i;
4520
4521 err = niu_alloc_rx_ring_info(np, rp);
4522 if (err)
4523 goto out_err;
4524
4525 niu_size_rbr(np, rp);
4526
4527 /* XXX better defaults, configurable, etc... XXX */
4528 rp->nonsyn_window = 64;
4529 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4530 rp->syn_window = 64;
4531 rp->syn_threshold = rp->rcr_table_size - 64;
4532 rp->rcr_pkt_threshold = 16;
4533 rp->rcr_timeout = 8;
4534 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4535 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4536 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4537
4538 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4539 if (err)
4540 return err;
4541 }
4542
9690c636
DM		 4543 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4544 GFP_KERNEL);
a3138df9 4545 err = -ENOMEM;
9690c636 4546 if (!tx_rings)
a3138df9
DM		 4547 goto out_err;
4548
9690c636
DM		 4549 np->num_tx_rings = num_tx_rings;
4550 smp_wmb();
4551 np->tx_rings = tx_rings;
4552
4553 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4554
a3138df9
DM		 4555 for (i = 0; i < np->num_tx_rings; i++) {
4556 struct tx_ring_info *rp = &np->tx_rings[i];
4557
4558 rp->np = np;
4559 rp->tx_channel = first_tx_channel + i;
4560
4561 err = niu_alloc_tx_ring_info(np, rp);
4562 if (err)
4563 goto out_err;
4564 }
4565
4566 return 0;
4567
4568out_err:
4569 niu_free_channels(np);
4570 return err;
4571}
4572
4573static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4574{
4575 int limit = 1000;
4576
4577 while (--limit > 0) {
4578 u64 val = nr64(TX_CS(channel));
4579 if (val & TX_CS_SNG_STATE)
4580 return 0;
4581 }
4582 return -ENODEV;
4583}
4584
4585static int niu_tx_channel_stop(struct niu *np, int channel)
4586{
4587 u64 val = nr64(TX_CS(channel));
4588
4589 val |= TX_CS_STOP_N_GO;
4590 nw64(TX_CS(channel), val);
4591
4592 return niu_tx_cs_sng_poll(np, channel);
4593}
4594
4595static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4596{
4597 int limit = 1000;
4598
4599 while (--limit > 0) {
4600 u64 val = nr64(TX_CS(channel));
4601 if (!(val & TX_CS_RST))
4602 return 0;
4603 }
4604 return -ENODEV;
4605}
4606
4607static int niu_tx_channel_reset(struct niu *np, int channel)
4608{
4609 u64 val = nr64(TX_CS(channel));
4610 int err;
4611
4612 val |= TX_CS_RST;
4613 nw64(TX_CS(channel), val);
4614
4615 err = niu_tx_cs_reset_poll(np, channel);
4616 if (!err)
4617 nw64(TX_RING_KICK(channel), 0);
4618
4619 return err;
4620}
4621
4622static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4623{
4624 u64 val;
4625
4626 nw64(TX_LOG_MASK1(channel), 0);
4627 nw64(TX_LOG_VAL1(channel), 0);
4628 nw64(TX_LOG_MASK2(channel), 0);
4629 nw64(TX_LOG_VAL2(channel), 0);
4630 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4631 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4632 nw64(TX_LOG_PAGE_HDL(channel), 0);
4633
4634 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4635 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4636 nw64(TX_LOG_PAGE_VLD(channel), val);
4637
4638 /* XXX TXDMA 32bit mode? XXX */
4639
4640 return 0;
4641}
4642
4643static void niu_txc_enable_port(struct niu *np, int on)
4644{
4645 unsigned long flags;
4646 u64 val, mask;
4647
4648 niu_lock_parent(np, flags);
4649 val = nr64(TXC_CONTROL);
4650 mask = (u64)1 << np->port;
4651 if (on) {
4652 val |= TXC_CONTROL_ENABLE | mask;
4653 } else {
4654 val &= ~mask;
4655 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4656 val &= ~TXC_CONTROL_ENABLE;
4657 }
4658 nw64(TXC_CONTROL, val);
4659 niu_unlock_parent(np, flags);
4660}
4661
4662static void niu_txc_set_imask(struct niu *np, u64 imask)
4663{
4664 unsigned long flags;
4665 u64 val;
4666
4667 niu_lock_parent(np, flags);
4668 val = nr64(TXC_INT_MASK);
4669 val &= ~TXC_INT_MASK_VAL(np->port);
4670 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4671 niu_unlock_parent(np, flags);
4672}
4673
4674static void niu_txc_port_dma_enable(struct niu *np, int on)
4675{
4676 u64 val = 0;
4677
4678 if (on) {
4679 int i;
4680
4681 for (i = 0; i < np->num_tx_rings; i++)
4682 val |= (1 << np->tx_rings[i].tx_channel);
4683 }
4684 nw64(TXC_PORT_DMA(np->port), val);
4685}
4686
4687static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4688{
4689 int err, channel = rp->tx_channel;
4690 u64 val, ring_len;
4691
4692 err = niu_tx_channel_stop(np, channel);
4693 if (err)
4694 return err;
4695
4696 err = niu_tx_channel_reset(np, channel);
4697 if (err)
4698 return err;
4699
4700 err = niu_tx_channel_lpage_init(np, channel);
4701 if (err)
4702 return err;
4703
4704 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4705 nw64(TX_ENT_MSK(channel), 0);
4706
4707 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4708 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4709 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4710 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4711 return -EINVAL;
4712 }
4713
4714 /* The length field in TX_RNG_CFIG is measured in 64-byte
4715 * blocks. rp->pending is the number of TX descriptors in
4716 * our ring, 8 bytes each, thus we divide by 8 bytes more
4717 * to get the proper value the chip wants.
4718 */
4719 ring_len = (rp->pending / 8);
4720
4721 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4722 rp->descr_dma);
4723 nw64(TX_RNG_CFIG(channel), val);
4724
4725 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4726 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4727 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4728 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4729 return -EINVAL;
4730 }
4731 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4732 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4733
4734 nw64(TX_CS(channel), 0);
4735
4736 rp->last_pkt_cnt = 0;
4737
4738 return 0;
4739}
4740
4741static void niu_init_rdc_groups(struct niu *np)
4742{
4743 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4744 int i, first_table_num = tp->first_table_num;
4745
4746 for (i = 0; i < tp->num_tables; i++) {
4747 struct rdc_table *tbl = &tp->tables[i];
4748 int this_table = first_table_num + i;
4749 int slot;
4750
4751 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4752 nw64(RDC_TBL(this_table, slot),
4753 tbl->rxdma_channel[slot]);
4754 }
4755
4756 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4757}
4758
4759static void niu_init_drr_weight(struct niu *np)
4760{
4761 int type = phy_decode(np->parent->port_phy, np->port);
4762 u64 val;
4763
4764 switch (type) {
4765 case PORT_TYPE_10G:
4766 val = PT_DRR_WEIGHT_DEFAULT_10G;
4767 break;
4768
4769 case PORT_TYPE_1G:
4770 default:
4771 val = PT_DRR_WEIGHT_DEFAULT_1G;
4772 break;
4773 }
4774 nw64(PT_DRR_WT(np->port), val);
4775}
4776
4777static int niu_init_hostinfo(struct niu *np)
4778{
4779 struct niu_parent *parent = np->parent;
4780 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4781 int i, err, num_alt = niu_num_alt_addr(np);
4782 int first_rdc_table = tp->first_table_num;
4783
4784 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4785 if (err)
4786 return err;
4787
4788 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4789 if (err)
4790 return err;
4791
4792 for (i = 0; i < num_alt; i++) {
4793 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4794 if (err)
4795 return err;
4796 }
4797
4798 return 0;
4799}
4800
4801static int niu_rx_channel_reset(struct niu *np, int channel)
4802{
4803 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4804 RXDMA_CFIG1_RST, 1000, 10,
4805 "RXDMA_CFIG1");
4806}
4807
4808static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4809{
4810 u64 val;
4811
4812 nw64(RX_LOG_MASK1(channel), 0);
4813 nw64(RX_LOG_VAL1(channel), 0);
4814 nw64(RX_LOG_MASK2(channel), 0);
4815 nw64(RX_LOG_VAL2(channel), 0);
4816 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4817 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4818 nw64(RX_LOG_PAGE_HDL(channel), 0);
4819
4820 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4821 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4822 nw64(RX_LOG_PAGE_VLD(channel), val);
4823
4824 return 0;
4825}
4826
4827static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4828{
4829 u64 val;
4830
4831 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4832 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4833 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4834 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4835 nw64(RDC_RED_PARA(rp->rx_channel), val);
4836}
4837
4838static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4839{
4840 u64 val = 0;
4841
efb6c736 4842 *ret = 0;
a3138df9
DM		 4843 switch (rp->rbr_block_size) {
4844 case 4 * 1024:
4845 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4846 break;
4847 case 8 * 1024:
4848 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4849 break;
4850 case 16 * 1024:
4851 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4852 break;
4853 case 32 * 1024:
4854 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4855 break;
4856 default:
4857 return -EINVAL;
4858 }
4859 val |= RBR_CFIG_B_VLD2;
4860 switch (rp->rbr_sizes[2]) {
4861 case 2 * 1024:
4862 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4863 break;
4864 case 4 * 1024:
4865 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4866 break;
4867 case 8 * 1024:
4868 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4869 break;
4870 case 16 * 1024:
4871 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4872 break;
4873
4874 default:
4875 return -EINVAL;
4876 }
4877 val |= RBR_CFIG_B_VLD1;
4878 switch (rp->rbr_sizes[1]) {
4879 case 1 * 1024:
4880 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4881 break;
4882 case 2 * 1024:
4883 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4884 break;
4885 case 4 * 1024:
4886 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4887 break;
4888 case 8 * 1024:
4889 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4890 break;
4891
4892 default:
4893 return -EINVAL;
4894 }
4895 val |= RBR_CFIG_B_VLD0;
4896 switch (rp->rbr_sizes[0]) {
4897 case 256:
4898 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4899 break;
4900 case 512:
4901 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4902 break;
4903 case 1 * 1024:
4904 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4905 break;
4906 case 2 * 1024:
4907 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4908 break;
4909
4910 default:
4911 return -EINVAL;
4912 }
4913
4914 *ret = val;
4915 return 0;
4916}
4917
4918static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4919{
4920 u64 val = nr64(RXDMA_CFIG1(channel));
4921 int limit;
4922
4923 if (on)
4924 val |= RXDMA_CFIG1_EN;
4925 else
4926 val &= ~RXDMA_CFIG1_EN;
4927 nw64(RXDMA_CFIG1(channel), val);
4928
4929 limit = 1000;
4930 while (--limit > 0) {
4931 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4932 break;
4933 udelay(10);
4934 }
4935 if (limit <= 0)
4936 return -ENODEV;
4937 return 0;
4938}
4939
4940static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4941{
4942 int err, channel = rp->rx_channel;
4943 u64 val;
4944
4945 err = niu_rx_channel_reset(np, channel);
4946 if (err)
4947 return err;
4948
4949 err = niu_rx_channel_lpage_init(np, channel);
4950 if (err)
4951 return err;
4952
4953 niu_rx_channel_wred_init(np, rp);
4954
4955 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4956 nw64(RX_DMA_CTL_STAT(channel),
4957 (RX_DMA_CTL_STAT_MEX |
4958 RX_DMA_CTL_STAT_RCRTHRES |
4959 RX_DMA_CTL_STAT_RCRTO |
4960 RX_DMA_CTL_STAT_RBR_EMPTY));
4961 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3cfa856d
DM		 4962 nw64(RXDMA_CFIG2(channel),
4963 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4964 RXDMA_CFIG2_FULL_HDR));
a3138df9
DM		 4965 nw64(RBR_CFIG_A(channel),
4966 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4967 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4968 err = niu_compute_rbr_cfig_b(rp, &val);
4969 if (err)
4970 return err;
4971 nw64(RBR_CFIG_B(channel), val);
4972 nw64(RCRCFIG_A(channel),
4973 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4974 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4975 nw64(RCRCFIG_B(channel),
4976 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4977 RCRCFIG_B_ENTOUT |
4978 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4979
4980 err = niu_enable_rx_channel(np, channel, 1);
4981 if (err)
4982 return err;
4983
4984 nw64(RBR_KICK(channel), rp->rbr_index);
4985
4986 val = nr64(RX_DMA_CTL_STAT(channel));
4987 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4988 nw64(RX_DMA_CTL_STAT(channel), val);
4989
4990 return 0;
4991}
4992
4993static int niu_init_rx_channels(struct niu *np)
4994{
4995 unsigned long flags;
4996 u64 seed = jiffies_64;
4997 int err, i;
4998
4999 niu_lock_parent(np, flags);
5000 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
5001 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5002 niu_unlock_parent(np, flags);
5003
5004 /* XXX RXDMA 32bit mode? XXX */
5005
5006 niu_init_rdc_groups(np);
5007 niu_init_drr_weight(np);
5008
5009 err = niu_init_hostinfo(np);
5010 if (err)
5011 return err;
5012
5013 for (i = 0; i < np->num_rx_rings; i++) {
5014 struct rx_ring_info *rp = &np->rx_rings[i];
5015
5016 err = niu_init_one_rx_channel(np, rp);
5017 if (err)
5018 return err;
5019 }
5020
5021 return 0;
5022}
5023
5024static int niu_set_ip_frag_rule(struct niu *np)
5025{
5026 struct niu_parent *parent = np->parent;
5027 struct niu_classifier *cp = &np->clas;
5028 struct niu_tcam_entry *tp;
5029 int index, err;
5030
2d96cf8c 5031 index = cp->tcam_top;
a3138df9
DM		 5032 tp = &parent->tcam[index];
5033
5034 /* Note that the noport bit is the same in both ipv4 and
5035 * ipv6 format TCAM entries.
5036 */
5037 memset(tp, 0, sizeof(*tp));
5038 tp->key[1] = TCAM_V4KEY1_NOPORT;
5039 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5040 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5041 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5042 err = tcam_write(np, index, tp->key, tp->key_mask);
5043 if (err)
5044 return err;
5045 err = tcam_assoc_write(np, index, tp->assoc_data);
5046 if (err)
5047 return err;
2d96cf8c
SB		 5048 tp->valid = 1;
5049 cp->tcam_valid_entries++;
a3138df9
DM		 5050
5051 return 0;
5052}
5053
5054static int niu_init_classifier_hw(struct niu *np)
5055{
5056 struct niu_parent *parent = np->parent;
5057 struct niu_classifier *cp = &np->clas;
5058 int i, err;
5059
5060 nw64(H1POLY, cp->h1_init);
5061 nw64(H2POLY, cp->h2_init);
5062
5063 err = niu_init_hostinfo(np);
5064 if (err)
5065 return err;
5066
5067 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5068 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5069
5070 vlan_tbl_write(np, i, np->port,
5071 vp->vlan_pref, vp->rdc_num);
5072 }
5073
5074 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5075 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5076
5077 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5078 ap->rdc_num, ap->mac_pref);
5079 if (err)
5080 return err;
5081 }
5082
5083 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5084 int index = i - CLASS_CODE_USER_PROG1;
5085
5086 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5087 if (err)
5088 return err;
5089 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5090 if (err)
5091 return err;
5092 }
5093
5094 err = niu_set_ip_frag_rule(np);
5095 if (err)
5096 return err;
5097
5098 tcam_enable(np, 1);
5099
5100 return 0;
5101}
5102
5103static int niu_zcp_write(struct niu *np, int index, u64 *data)
5104{
5105 nw64(ZCP_RAM_DATA0, data[0]);
5106 nw64(ZCP_RAM_DATA1, data[1]);
5107 nw64(ZCP_RAM_DATA2, data[2]);
5108 nw64(ZCP_RAM_DATA3, data[3]);
5109 nw64(ZCP_RAM_DATA4, data[4]);
5110 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5111 nw64(ZCP_RAM_ACC,
5112 (ZCP_RAM_ACC_WRITE |
5113 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5114 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5115
5116 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5117 1000, 100);
5118}
5119
5120static int niu_zcp_read(struct niu *np, int index, u64 *data)
5121{
5122 int err;
5123
5124 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5125 1000, 100);
5126 if (err) {
f10a1f2e
JP		 5127 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5128 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5129 return err;
5130 }
5131
5132 nw64(ZCP_RAM_ACC,
5133 (ZCP_RAM_ACC_READ |
5134 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5135 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5136
5137 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5138 1000, 100);
5139 if (err) {
f10a1f2e
JP		 5140 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5141 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5142 return err;
5143 }
5144
5145 data[0] = nr64(ZCP_RAM_DATA0);
5146 data[1] = nr64(ZCP_RAM_DATA1);
5147 data[2] = nr64(ZCP_RAM_DATA2);
5148 data[3] = nr64(ZCP_RAM_DATA3);
5149 data[4] = nr64(ZCP_RAM_DATA4);
5150
5151 return 0;
5152}
5153
5154static void niu_zcp_cfifo_reset(struct niu *np)
5155{
5156 u64 val = nr64(RESET_CFIFO);
5157
5158 val |= RESET_CFIFO_RST(np->port);
5159 nw64(RESET_CFIFO, val);
5160 udelay(10);
5161
5162 val &= ~RESET_CFIFO_RST(np->port);
5163 nw64(RESET_CFIFO, val);
5164}
5165
5166static int niu_init_zcp(struct niu *np)
5167{
5168 u64 data[5], rbuf[5];
5169 int i, max, err;
5170
5171 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5172 if (np->port == 0 || np->port == 1)
5173 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5174 else
5175 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5176 } else
5177 max = NIU_CFIFO_ENTRIES;
5178
5179 data[0] = 0;
5180 data[1] = 0;
5181 data[2] = 0;
5182 data[3] = 0;
5183 data[4] = 0;
5184
5185 for (i = 0; i < max; i++) {
5186 err = niu_zcp_write(np, i, data);
5187 if (err)
5188 return err;
5189 err = niu_zcp_read(np, i, rbuf);
5190 if (err)
5191 return err;
5192 }
5193
5194 niu_zcp_cfifo_reset(np);
5195 nw64(CFIFO_ECC(np->port), 0);
5196 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5197 (void) nr64(ZCP_INT_STAT);
5198 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5199
5200 return 0;
5201}
5202
5203static void niu_ipp_write(struct niu *np, int index, u64 *data)
5204{
5205 u64 val = nr64_ipp(IPP_CFIG);
5206
5207 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5208 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5209 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5210 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5211 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5212 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5213 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5214 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5215}
5216
5217static void niu_ipp_read(struct niu *np, int index, u64 *data)
5218{
5219 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5220 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5221 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5222 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5223 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5224 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5225}
5226
5227static int niu_ipp_reset(struct niu *np)
5228{
5229 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5230 1000, 100, "IPP_CFIG");
5231}
5232
5233static int niu_init_ipp(struct niu *np)
5234{
5235 u64 data[5], rbuf[5], val;
5236 int i, max, err;
5237
5238 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5239 if (np->port == 0 || np->port == 1)
5240 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5241 else
5242 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5243 } else
5244 max = NIU_DFIFO_ENTRIES;
5245
5246 data[0] = 0;
5247 data[1] = 0;
5248 data[2] = 0;
5249 data[3] = 0;
5250 data[4] = 0;
5251
5252 for (i = 0; i < max; i++) {
5253 niu_ipp_write(np, i, data);
5254 niu_ipp_read(np, i, rbuf);
5255 }
5256
5257 (void) nr64_ipp(IPP_INT_STAT);
5258 (void) nr64_ipp(IPP_INT_STAT);
5259
5260 err = niu_ipp_reset(np);
5261 if (err)
5262 return err;
5263
5264 (void) nr64_ipp(IPP_PKT_DIS);
5265 (void) nr64_ipp(IPP_BAD_CS_CNT);
5266 (void) nr64_ipp(IPP_ECC);
5267
5268 (void) nr64_ipp(IPP_INT_STAT);
5269
5270 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5271
5272 val = nr64_ipp(IPP_CFIG);
5273 val &= ~IPP_CFIG_IP_MAX_PKT;
5274 val |= (IPP_CFIG_IPP_ENABLE |
5275 IPP_CFIG_DFIFO_ECC_EN |
5276 IPP_CFIG_DROP_BAD_CRC |
5277 IPP_CFIG_CKSUM_EN |
5278 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5279 nw64_ipp(IPP_CFIG, val);
5280
5281 return 0;
5282}
5283
0c3b091b 5284static void niu_handle_led(struct niu *np, int status)
a3138df9 5285{
a3138df9 5286 u64 val;
a3138df9
DM		 5287 val = nr64_mac(XMAC_CONFIG);
5288
5289 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5290 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5291 if (status) {
a3138df9
DM		 5292 val |= XMAC_CONFIG_LED_POLARITY;
5293 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5294 } else {
5295 val |= XMAC_CONFIG_FORCE_LED_ON;
5296 val &= ~XMAC_CONFIG_LED_POLARITY;
5297 }
5298 }
5299
0c3b091b
ML		 5300 nw64_mac(XMAC_CONFIG, val);
5301}
5302
5303static void niu_init_xif_xmac(struct niu *np)
5304{
5305 struct niu_link_config *lp = &np->link_config;
5306 u64 val;
5307
5fbd7e24
MW		 5308 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5309 val = nr64(MIF_CONFIG);
5310 val |= MIF_CONFIG_ATCA_GE;
5311 nw64(MIF_CONFIG, val);
5312 }
5313
0c3b091b 5314 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5315 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5316
5317 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5318
5319 if (lp->loopback_mode == LOOPBACK_MAC) {
5320 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5321 val |= XMAC_CONFIG_LOOPBACK;
5322 } else {
5323 val &= ~XMAC_CONFIG_LOOPBACK;
5324 }
5325
5326 if (np->flags & NIU_FLAGS_10G) {
5327 val &= ~XMAC_CONFIG_LFS_DISABLE;
5328 } else {
5329 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5330 if (!(np->flags & NIU_FLAGS_FIBER) &&
5331 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5332 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5333 else
5334 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5335 }
5336
5337 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5338
5339 if (lp->active_speed == SPEED_100)
5340 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5341 else
5342 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5343
5344 nw64_mac(XMAC_CONFIG, val);
5345
5346 val = nr64_mac(XMAC_CONFIG);
5347 val &= ~XMAC_CONFIG_MODE_MASK;
5348 if (np->flags & NIU_FLAGS_10G) {
5349 val |= XMAC_CONFIG_MODE_XGMII;
5350 } else {
38bb045d 5351 if (lp->active_speed == SPEED_1000)
a3138df9 5352 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5353 else
5354 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5355 }
5356
5357 nw64_mac(XMAC_CONFIG, val);
5358}
5359
5360static void niu_init_xif_bmac(struct niu *np)
5361{
5362 struct niu_link_config *lp = &np->link_config;
5363 u64 val;
5364
5365 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5366
5367 if (lp->loopback_mode == LOOPBACK_MAC)
5368 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5369 else
5370 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5371
5372 if (lp->active_speed == SPEED_1000)
5373 val |= BMAC_XIF_CONFIG_GMII_MODE;
5374 else
5375 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5376
5377 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5378 BMAC_XIF_CONFIG_LED_POLARITY);
5379
5380 if (!(np->flags & NIU_FLAGS_10G) &&
5381 !(np->flags & NIU_FLAGS_FIBER) &&
5382 lp->active_speed == SPEED_100)
5383 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5384 else
5385 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5386
5387 nw64_mac(BMAC_XIF_CONFIG, val);
5388}
5389
5390static void niu_init_xif(struct niu *np)
5391{
5392 if (np->flags & NIU_FLAGS_XMAC)
5393 niu_init_xif_xmac(np);
5394 else
5395 niu_init_xif_bmac(np);
5396}
5397
5398static void niu_pcs_mii_reset(struct niu *np)
5399{
5fbd7e24 5400 int limit = 1000;
a3138df9
DM		 5401 u64 val = nr64_pcs(PCS_MII_CTL);
5402 val |= PCS_MII_CTL_RST;
5403 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5404 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5405 udelay(100);
5406 val = nr64_pcs(PCS_MII_CTL);
5407 }
a3138df9
DM		 5408}
5409
5410static void niu_xpcs_reset(struct niu *np)
5411{
5fbd7e24 5412 int limit = 1000;
a3138df9
DM		 5413 u64 val = nr64_xpcs(XPCS_CONTROL1);
5414 val |= XPCS_CONTROL1_RESET;
5415 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5416 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5417 udelay(100);
5418 val = nr64_xpcs(XPCS_CONTROL1);
5419 }
a3138df9
DM		 5420}
5421
5422static int niu_init_pcs(struct niu *np)
5423{
5424 struct niu_link_config *lp = &np->link_config;
5425 u64 val;
5426
5fbd7e24
MW		 5427 switch (np->flags & (NIU_FLAGS_10G |
5428 NIU_FLAGS_FIBER |
5429 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5430 case NIU_FLAGS_FIBER:
5431 /* 1G fiber */
5432 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5433 nw64_pcs(PCS_DPATH_MODE, 0);
5434 niu_pcs_mii_reset(np);
5435 break;
5436
5437 case NIU_FLAGS_10G:
5438 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5439 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5440 /* 10G SERDES */
a3138df9
DM		 5441 if (!(np->flags & NIU_FLAGS_XMAC))
5442 return -EINVAL;
5443
5444 /* 10G copper or fiber */
5445 val = nr64_mac(XMAC_CONFIG);
5446 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5447 nw64_mac(XMAC_CONFIG, val);
5448
5449 niu_xpcs_reset(np);
5450
5451 val = nr64_xpcs(XPCS_CONTROL1);
5452 if (lp->loopback_mode == LOOPBACK_PHY)
5453 val |= XPCS_CONTROL1_LOOPBACK;
5454 else
5455 val &= ~XPCS_CONTROL1_LOOPBACK;
5456 nw64_xpcs(XPCS_CONTROL1, val);
5457
5458 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5459 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5460 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5461 break;
5462
5fbd7e24
MW		 5463
5464 case NIU_FLAGS_XCVR_SERDES:
5465 /* 1G SERDES */
5466 niu_pcs_mii_reset(np);
5467 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5468 nw64_pcs(PCS_DPATH_MODE, 0);
5469 break;
5470
a3138df9
DM		 5471 case 0:
5472 /* 1G copper */
5fbd7e24
MW		 5473 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5474 /* 1G RGMII FIBER */
a3138df9
DM		 5475 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5476 niu_pcs_mii_reset(np);
5477 break;
5478
5479 default:
5480 return -EINVAL;
5481 }
5482
5483 return 0;
5484}
5485
5486static int niu_reset_tx_xmac(struct niu *np)
5487{
5488 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5489 (XTXMAC_SW_RST_REG_RS |
5490 XTXMAC_SW_RST_SOFT_RST),
5491 1000, 100, "XTXMAC_SW_RST");
5492}
5493
5494static int niu_reset_tx_bmac(struct niu *np)
5495{
5496 int limit;
5497
5498 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5499 limit = 1000;
5500 while (--limit >= 0) {
5501 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5502 break;
5503 udelay(100);
5504 }
5505 if (limit < 0) {
f10a1f2e 5506 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5507 np->port,
5508 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5509 return -ENODEV;
5510 }
5511
5512 return 0;
5513}
5514
5515static int niu_reset_tx_mac(struct niu *np)
5516{
5517 if (np->flags & NIU_FLAGS_XMAC)
5518 return niu_reset_tx_xmac(np);
5519 else
5520 return niu_reset_tx_bmac(np);
5521}
5522
5523static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5524{
5525 u64 val;
5526
5527 val = nr64_mac(XMAC_MIN);
5528 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5529 XMAC_MIN_RX_MIN_PKT_SIZE);
5530 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5531 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5532 nw64_mac(XMAC_MIN, val);
5533
5534 nw64_mac(XMAC_MAX, max);
5535
5536 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5537
5538 val = nr64_mac(XMAC_IPG);
5539 if (np->flags & NIU_FLAGS_10G) {
5540 val &= ~XMAC_IPG_IPG_XGMII;
5541 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5542 } else {
5543 val &= ~XMAC_IPG_IPG_MII_GMII;
5544 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5545 }
5546 nw64_mac(XMAC_IPG, val);
5547
5548 val = nr64_mac(XMAC_CONFIG);
5549 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5550 XMAC_CONFIG_STRETCH_MODE |
5551 XMAC_CONFIG_VAR_MIN_IPG_EN |
5552 XMAC_CONFIG_TX_ENABLE);
5553 nw64_mac(XMAC_CONFIG, val);
5554
5555 nw64_mac(TXMAC_FRM_CNT, 0);
5556 nw64_mac(TXMAC_BYTE_CNT, 0);
5557}
5558
5559static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5560{
5561 u64 val;
5562
5563 nw64_mac(BMAC_MIN_FRAME, min);
5564 nw64_mac(BMAC_MAX_FRAME, max);
5565
5566 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5567 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5568 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5569
5570 val = nr64_mac(BTXMAC_CONFIG);
5571 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5572 BTXMAC_CONFIG_ENABLE);
5573 nw64_mac(BTXMAC_CONFIG, val);
5574}
5575
5576static void niu_init_tx_mac(struct niu *np)
5577{
5578 u64 min, max;
5579
5580 min = 64;
5581 if (np->dev->mtu > ETH_DATA_LEN)
5582 max = 9216;
5583 else
5584 max = 1522;
5585
5586 /* The XMAC_MIN register only accepts values for TX min which
5587 * have the low 3 bits cleared.
5588 */
8c87df45 5589 BUG_ON(min & 0x7);
a3138df9
DM		 5590
5591 if (np->flags & NIU_FLAGS_XMAC)
5592 niu_init_tx_xmac(np, min, max);
5593 else
5594 niu_init_tx_bmac(np, min, max);
5595}
5596
5597static int niu_reset_rx_xmac(struct niu *np)
5598{
5599 int limit;
5600
5601 nw64_mac(XRXMAC_SW_RST,
5602 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5603 limit = 1000;
5604 while (--limit >= 0) {
5605 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5606 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5607 break;
a3138df9
DM		 5608 udelay(100);
5609 }
5610 if (limit < 0) {
f10a1f2e 5611 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5612 np->port,
5613 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5614 return -ENODEV;
5615 }
5616
5617 return 0;
5618}
5619
5620static int niu_reset_rx_bmac(struct niu *np)
5621{
5622 int limit;
5623
5624 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5625 limit = 1000;
5626 while (--limit >= 0) {
5627 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5628 break;
5629 udelay(100);
5630 }
5631 if (limit < 0) {
f10a1f2e 5632 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5633 np->port,
5634 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5635 return -ENODEV;
5636 }
5637
5638 return 0;
5639}
5640
5641static int niu_reset_rx_mac(struct niu *np)
5642{
5643 if (np->flags & NIU_FLAGS_XMAC)
5644 return niu_reset_rx_xmac(np);
5645 else
5646 return niu_reset_rx_bmac(np);
5647}
5648
5649static void niu_init_rx_xmac(struct niu *np)
5650{
5651 struct niu_parent *parent = np->parent;
5652 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5653 int first_rdc_table = tp->first_table_num;
5654 unsigned long i;
5655 u64 val;
5656
5657 nw64_mac(XMAC_ADD_FILT0, 0);
5658 nw64_mac(XMAC_ADD_FILT1, 0);
5659 nw64_mac(XMAC_ADD_FILT2, 0);
5660 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5661 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5662 for (i = 0; i < MAC_NUM_HASH; i++)
5663 nw64_mac(XMAC_HASH_TBL(i), 0);
5664 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5665 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5666 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5667
5668 val = nr64_mac(XMAC_CONFIG);
5669 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5670 XMAC_CONFIG_PROMISCUOUS |
5671 XMAC_CONFIG_PROMISC_GROUP |
5672 XMAC_CONFIG_ERR_CHK_DIS |
5673 XMAC_CONFIG_RX_CRC_CHK_DIS |
5674 XMAC_CONFIG_RESERVED_MULTICAST |
5675 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5676 XMAC_CONFIG_ADDR_FILTER_EN |
5677 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5678 XMAC_CONFIG_STRIP_CRC |
5679 XMAC_CONFIG_PASS_FLOW_CTRL |
5680 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5681 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5682 nw64_mac(XMAC_CONFIG, val);
5683
5684 nw64_mac(RXMAC_BT_CNT, 0);
5685 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5686 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5687 nw64_mac(RXMAC_FRAG_CNT, 0);
5688 nw64_mac(RXMAC_HIST_CNT1, 0);
5689 nw64_mac(RXMAC_HIST_CNT2, 0);
5690 nw64_mac(RXMAC_HIST_CNT3, 0);
5691 nw64_mac(RXMAC_HIST_CNT4, 0);
5692 nw64_mac(RXMAC_HIST_CNT5, 0);
5693 nw64_mac(RXMAC_HIST_CNT6, 0);
5694 nw64_mac(RXMAC_HIST_CNT7, 0);
5695 nw64_mac(RXMAC_MPSZER_CNT, 0);
5696 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5697 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5698 nw64_mac(LINK_FAULT_CNT, 0);
5699}
5700
5701static void niu_init_rx_bmac(struct niu *np)
5702{
5703 struct niu_parent *parent = np->parent;
5704 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5705 int first_rdc_table = tp->first_table_num;
5706 unsigned long i;
5707 u64 val;
5708
5709 nw64_mac(BMAC_ADD_FILT0, 0);
5710 nw64_mac(BMAC_ADD_FILT1, 0);
5711 nw64_mac(BMAC_ADD_FILT2, 0);
5712 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5713 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5714 for (i = 0; i < MAC_NUM_HASH; i++)
5715 nw64_mac(BMAC_HASH_TBL(i), 0);
5716 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5717 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5718 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5719
5720 val = nr64_mac(BRXMAC_CONFIG);
5721 val &= ~(BRXMAC_CONFIG_ENABLE |
5722 BRXMAC_CONFIG_STRIP_PAD |
5723 BRXMAC_CONFIG_STRIP_FCS |
5724 BRXMAC_CONFIG_PROMISC |
5725 BRXMAC_CONFIG_PROMISC_GRP |
5726 BRXMAC_CONFIG_ADDR_FILT_EN |
5727 BRXMAC_CONFIG_DISCARD_DIS);
5728 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5729 nw64_mac(BRXMAC_CONFIG, val);
5730
5731 val = nr64_mac(BMAC_ADDR_CMPEN);
5732 val |= BMAC_ADDR_CMPEN_EN0;
5733 nw64_mac(BMAC_ADDR_CMPEN, val);
5734}
5735
5736static void niu_init_rx_mac(struct niu *np)
5737{
5738 niu_set_primary_mac(np, np->dev->dev_addr);
5739
5740 if (np->flags & NIU_FLAGS_XMAC)
5741 niu_init_rx_xmac(np);
5742 else
5743 niu_init_rx_bmac(np);
5744}
5745
5746static void niu_enable_tx_xmac(struct niu *np, int on)
5747{
5748 u64 val = nr64_mac(XMAC_CONFIG);
5749
5750 if (on)
5751 val |= XMAC_CONFIG_TX_ENABLE;
5752 else
5753 val &= ~XMAC_CONFIG_TX_ENABLE;
5754 nw64_mac(XMAC_CONFIG, val);
5755}
5756
5757static void niu_enable_tx_bmac(struct niu *np, int on)
5758{
5759 u64 val = nr64_mac(BTXMAC_CONFIG);
5760
5761 if (on)
5762 val |= BTXMAC_CONFIG_ENABLE;
5763 else
5764 val &= ~BTXMAC_CONFIG_ENABLE;
5765 nw64_mac(BTXMAC_CONFIG, val);
5766}
5767
5768static void niu_enable_tx_mac(struct niu *np, int on)
5769{
5770 if (np->flags & NIU_FLAGS_XMAC)
5771 niu_enable_tx_xmac(np, on);
5772 else
5773 niu_enable_tx_bmac(np, on);
5774}
5775
5776static void niu_enable_rx_xmac(struct niu *np, int on)
5777{
5778 u64 val = nr64_mac(XMAC_CONFIG);
5779
5780 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5781 XMAC_CONFIG_PROMISCUOUS);
5782
5783 if (np->flags & NIU_FLAGS_MCAST)
5784 val |= XMAC_CONFIG_HASH_FILTER_EN;
5785 if (np->flags & NIU_FLAGS_PROMISC)
5786 val |= XMAC_CONFIG_PROMISCUOUS;
5787
5788 if (on)
5789 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5790 else
5791 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5792 nw64_mac(XMAC_CONFIG, val);
5793}
5794
5795static void niu_enable_rx_bmac(struct niu *np, int on)
5796{
5797 u64 val = nr64_mac(BRXMAC_CONFIG);
5798
5799 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5800 BRXMAC_CONFIG_PROMISC);
5801
5802 if (np->flags & NIU_FLAGS_MCAST)
5803 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5804 if (np->flags & NIU_FLAGS_PROMISC)
5805 val |= BRXMAC_CONFIG_PROMISC;
5806
5807 if (on)
5808 val |= BRXMAC_CONFIG_ENABLE;
5809 else
5810 val &= ~BRXMAC_CONFIG_ENABLE;
5811 nw64_mac(BRXMAC_CONFIG, val);
5812}
5813
5814static void niu_enable_rx_mac(struct niu *np, int on)
5815{
5816 if (np->flags & NIU_FLAGS_XMAC)
5817 niu_enable_rx_xmac(np, on);
5818 else
5819 niu_enable_rx_bmac(np, on);
5820}
5821
5822static int niu_init_mac(struct niu *np)
5823{
5824 int err;
5825
5826 niu_init_xif(np);
5827 err = niu_init_pcs(np);
5828 if (err)
5829 return err;
5830
5831 err = niu_reset_tx_mac(np);
5832 if (err)
5833 return err;
5834 niu_init_tx_mac(np);
5835 err = niu_reset_rx_mac(np);
5836 if (err)
5837 return err;
5838 niu_init_rx_mac(np);
5839
5840 /* This looks hookey but the RX MAC reset we just did will
5841 * undo some of the state we setup in niu_init_tx_mac() so we
5842 * have to call it again. In particular, the RX MAC reset will
5843 * set the XMAC_MAX register back to it's default value.
5844 */
5845 niu_init_tx_mac(np);
5846 niu_enable_tx_mac(np, 1);
5847
5848 niu_enable_rx_mac(np, 1);
5849
5850 return 0;
5851}
5852
5853static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5854{
5855 (void) niu_tx_channel_stop(np, rp->tx_channel);
5856}
5857
5858static void niu_stop_tx_channels(struct niu *np)
5859{
5860 int i;
5861
5862 for (i = 0; i < np->num_tx_rings; i++) {
5863 struct tx_ring_info *rp = &np->tx_rings[i];
5864
5865 niu_stop_one_tx_channel(np, rp);
5866 }
5867}
5868
5869static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5870{
5871 (void) niu_tx_channel_reset(np, rp->tx_channel);
5872}
5873
5874static void niu_reset_tx_channels(struct niu *np)
5875{
5876 int i;
5877
5878 for (i = 0; i < np->num_tx_rings; i++) {
5879 struct tx_ring_info *rp = &np->tx_rings[i];
5880
5881 niu_reset_one_tx_channel(np, rp);
5882 }
5883}
5884
5885static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5886{
5887 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5888}
5889
5890static void niu_stop_rx_channels(struct niu *np)
5891{
5892 int i;
5893
5894 for (i = 0; i < np->num_rx_rings; i++) {
5895 struct rx_ring_info *rp = &np->rx_rings[i];
5896
5897 niu_stop_one_rx_channel(np, rp);
5898 }
5899}
5900
5901static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5902{
5903 int channel = rp->rx_channel;
5904
5905 (void) niu_rx_channel_reset(np, channel);
5906 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5907 nw64(RX_DMA_CTL_STAT(channel), 0);
5908 (void) niu_enable_rx_channel(np, channel, 0);
5909}
5910
5911static void niu_reset_rx_channels(struct niu *np)
5912{
5913 int i;
5914
5915 for (i = 0; i < np->num_rx_rings; i++) {
5916 struct rx_ring_info *rp = &np->rx_rings[i];
5917
5918 niu_reset_one_rx_channel(np, rp);
5919 }
5920}
5921
5922static void niu_disable_ipp(struct niu *np)
5923{
5924 u64 rd, wr, val;
5925 int limit;
5926
5927 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5928 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5929 limit = 100;
5930 while (--limit >= 0 && (rd != wr)) {
5931 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5932 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5933 }
5934 if (limit < 0 &&
5935 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5936 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5937 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5938 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5939 }
5940
5941 val = nr64_ipp(IPP_CFIG);
5942 val &= ~(IPP_CFIG_IPP_ENABLE |
5943 IPP_CFIG_DFIFO_ECC_EN |
5944 IPP_CFIG_DROP_BAD_CRC |
5945 IPP_CFIG_CKSUM_EN);
5946 nw64_ipp(IPP_CFIG, val);
5947
5948 (void) niu_ipp_reset(np);
5949}
5950
5951static int niu_init_hw(struct niu *np)
5952{
5953 int i, err;
5954
f10a1f2e 5955 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5956 niu_txc_enable_port(np, 1);
5957 niu_txc_port_dma_enable(np, 1);
5958 niu_txc_set_imask(np, 0);
5959
f10a1f2e 5960 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5961 for (i = 0; i < np->num_tx_rings; i++) {
5962 struct tx_ring_info *rp = &np->tx_rings[i];
5963
5964 err = niu_init_one_tx_channel(np, rp);
5965 if (err)
5966 return err;
5967 }
5968
f10a1f2e 5969 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5970 err = niu_init_rx_channels(np);
5971 if (err)
5972 goto out_uninit_tx_channels;
5973
f10a1f2e 5974 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5975 err = niu_init_classifier_hw(np);
5976 if (err)
5977 goto out_uninit_rx_channels;
5978
f10a1f2e 5979 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5980 err = niu_init_zcp(np);
5981 if (err)
5982 goto out_uninit_rx_channels;
5983
f10a1f2e 5984 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5985 err = niu_init_ipp(np);
5986 if (err)
5987 goto out_uninit_rx_channels;
5988
f10a1f2e 5989 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5990 err = niu_init_mac(np);
5991 if (err)
5992 goto out_uninit_ipp;
5993
5994 return 0;
5995
5996out_uninit_ipp:
f10a1f2e 5997 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5998 niu_disable_ipp(np);
5999
6000out_uninit_rx_channels:
f10a1f2e 6001 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 6002 niu_stop_rx_channels(np);
6003 niu_reset_rx_channels(np);
6004
6005out_uninit_tx_channels:
f10a1f2e 6006 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 6007 niu_stop_tx_channels(np);
6008 niu_reset_tx_channels(np);
6009
6010 return err;
6011}
6012
6013static void niu_stop_hw(struct niu *np)
6014{
f10a1f2e 6015 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6016 niu_enable_interrupts(np, 0);
6017
f10a1f2e 6018 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6019 niu_enable_rx_mac(np, 0);
6020
f10a1f2e 6021 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6022 niu_disable_ipp(np);
6023
f10a1f2e 6024 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6025 niu_stop_tx_channels(np);
6026
f10a1f2e 6027 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6028 niu_stop_rx_channels(np);
6029
f10a1f2e 6030 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6031 niu_reset_tx_channels(np);
6032
f10a1f2e 6033 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6034 niu_reset_rx_channels(np);
6035}
6036
70340d72
RO		 6037static void niu_set_irq_name(struct niu *np)
6038{
6039 int port = np->port;
6040 int i, j = 1;
6041
6042 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6043
6044 if (port == 0) {
6045 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6046 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6047 j = 3;
6048 }
6049
6050 for (i = 0; i < np->num_ldg - j; i++) {
6051 if (i < np->num_rx_rings)
6052 sprintf(np->irq_name[i+j], "%s-rx-%d",
6053 np->dev->name, i);
6054 else if (i < np->num_tx_rings + np->num_rx_rings)
6055 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6056 i - np->num_rx_rings);
6057 }
6058}
6059
a3138df9
DM		 6060static int niu_request_irq(struct niu *np)
6061{
6062 int i, j, err;
6063
70340d72
RO		 6064 niu_set_irq_name(np);
6065
a3138df9
DM		 6066 err = 0;
6067 for (i = 0; i < np->num_ldg; i++) {
6068 struct niu_ldg *lp = &np->ldg[i];
6069
ab392d2d 6070 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
70340d72 6071 np->irq_name[i], lp);
a3138df9
DM		 6072 if (err)
6073 goto out_free_irqs;
6074
6075 }
6076
6077 return 0;
6078
6079out_free_irqs:
6080 for (j = 0; j < i; j++) {
6081 struct niu_ldg *lp = &np->ldg[j];
6082
6083 free_irq(lp->irq, lp);
6084 }
6085 return err;
6086}
6087
6088static void niu_free_irq(struct niu *np)
6089{
6090 int i;
6091
6092 for (i = 0; i < np->num_ldg; i++) {
6093 struct niu_ldg *lp = &np->ldg[i];
6094
6095 free_irq(lp->irq, lp);
6096 }
6097}
6098
6099static void niu_enable_napi(struct niu *np)
6100{
6101 int i;
6102
6103 for (i = 0; i < np->num_ldg; i++)
6104 napi_enable(&np->ldg[i].napi);
6105}
6106
6107static void niu_disable_napi(struct niu *np)
6108{
6109 int i;
6110
6111 for (i = 0; i < np->num_ldg; i++)
6112 napi_disable(&np->ldg[i].napi);
6113}
6114
6115static int niu_open(struct net_device *dev)
6116{
6117 struct niu *np = netdev_priv(dev);
6118 int err;
6119
6120 netif_carrier_off(dev);
6121
6122 err = niu_alloc_channels(np);
6123 if (err)
6124 goto out_err;
6125
6126 err = niu_enable_interrupts(np, 0);
6127 if (err)
6128 goto out_free_channels;
6129
6130 err = niu_request_irq(np);
6131 if (err)
6132 goto out_free_channels;
6133
6134 niu_enable_napi(np);
6135
6136 spin_lock_irq(&np->lock);
6137
6138 err = niu_init_hw(np);
6139 if (!err) {
6140 init_timer(&np->timer);
6141 np->timer.expires = jiffies + HZ;
6142 np->timer.data = (unsigned long) np;
6143 np->timer.function = niu_timer;
6144
6145 err = niu_enable_interrupts(np, 1);
6146 if (err)
6147 niu_stop_hw(np);
6148 }
6149
6150 spin_unlock_irq(&np->lock);
6151
6152 if (err) {
6153 niu_disable_napi(np);
6154 goto out_free_irq;
6155 }
6156
b4c21639 6157 netif_tx_start_all_queues(dev);
a3138df9
DM		 6158
6159 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6160 netif_carrier_on(dev);
6161
6162 add_timer(&np->timer);
6163
6164 return 0;
6165
6166out_free_irq:
6167 niu_free_irq(np);
6168
6169out_free_channels:
6170 niu_free_channels(np);
6171
6172out_err:
6173 return err;
6174}
6175
6176static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6177{
6178 cancel_work_sync(&np->reset_task);
6179
6180 niu_disable_napi(np);
b4c21639 6181 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6182
6183 del_timer_sync(&np->timer);
6184
6185 spin_lock_irq(&np->lock);
6186
6187 niu_stop_hw(np);
6188
6189 spin_unlock_irq(&np->lock);
6190}
6191
6192static int niu_close(struct net_device *dev)
6193{
6194 struct niu *np = netdev_priv(dev);
6195
6196 niu_full_shutdown(np, dev);
6197
6198 niu_free_irq(np);
6199
6200 niu_free_channels(np);
6201
0c3b091b
ML		 6202 niu_handle_led(np, 0);
6203
a3138df9
DM		 6204 return 0;
6205}
6206
6207static void niu_sync_xmac_stats(struct niu *np)
6208{
6209 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6210
6211 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6212 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6213
6214 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6215 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6216 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6217 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6218 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6219 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6220 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6221 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6222 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6223 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6224 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6225 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6226 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6227 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6228 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6229 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6230}
6231
6232static void niu_sync_bmac_stats(struct niu *np)
6233{
6234 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6235
6236 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6237 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6238
6239 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6240 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6241 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6242 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6243}
6244
6245static void niu_sync_mac_stats(struct niu *np)
6246{
6247 if (np->flags & NIU_FLAGS_XMAC)
6248 niu_sync_xmac_stats(np);
6249 else
6250 niu_sync_bmac_stats(np);
6251}
6252
1a7a1032 6253static void niu_get_rx_stats(struct niu *np,
6254 struct rtnl_link_stats64 *stats)
a3138df9 6255{
1a7a1032 6256 u64 pkts, dropped, errors, bytes;
9690c636 6257 struct rx_ring_info *rx_rings;
a3138df9
DM		 6258 int i;
6259
6260 pkts = dropped = errors = bytes = 0;
9690c636
DM		 6261
6262 rx_rings = ACCESS_ONCE(np->rx_rings);
6263 if (!rx_rings)
6264 goto no_rings;
6265
a3138df9 6266 for (i = 0; i < np->num_rx_rings; i++) {
9690c636 6267 struct rx_ring_info *rp = &rx_rings[i];
a3138df9 6268
b8a606b8
JDB		 6269 niu_sync_rx_discard_stats(np, rp, 0);
6270
a3138df9
DM		 6271 pkts += rp->rx_packets;
6272 bytes += rp->rx_bytes;
6273 dropped += rp->rx_dropped;
6274 errors += rp->rx_errors;
6275 }
9690c636
DM		 6276
6277no_rings:
1a7a1032 6278 stats->rx_packets = pkts;
6279 stats->rx_bytes = bytes;
6280 stats->rx_dropped = dropped;
6281 stats->rx_errors = errors;
a3138df9
DM		 6282}
6283
1a7a1032 6284static void niu_get_tx_stats(struct niu *np,
6285 struct rtnl_link_stats64 *stats)
a3138df9 6286{
1a7a1032 6287 u64 pkts, errors, bytes;
9690c636 6288 struct tx_ring_info *tx_rings;
a3138df9
DM		 6289 int i;
6290
6291 pkts = errors = bytes = 0;
9690c636
DM		 6292
6293 tx_rings = ACCESS_ONCE(np->tx_rings);
6294 if (!tx_rings)
6295 goto no_rings;
6296
a3138df9 6297 for (i = 0; i < np->num_tx_rings; i++) {
9690c636 6298 struct tx_ring_info *rp = &tx_rings[i];
a3138df9
DM		 6299
6300 pkts += rp->tx_packets;
6301 bytes += rp->tx_bytes;
6302 errors += rp->tx_errors;
6303 }
9690c636
DM		 6304
6305no_rings:
1a7a1032 6306 stats->tx_packets = pkts;
6307 stats->tx_bytes = bytes;
6308 stats->tx_errors = errors;
a3138df9
DM		 6309}
6310
1a7a1032 6311static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev,
6312 struct rtnl_link_stats64 *stats)
a3138df9
DM		 6313{
6314 struct niu *np = netdev_priv(dev);
6315
9690c636 6316 if (netif_running(dev)) {
1a7a1032 6317 niu_get_rx_stats(np, stats);
6318 niu_get_tx_stats(np, stats);
9690c636 6319 }
1a7a1032 6320
6321 return stats;
a3138df9
DM		 6322}
6323
6324static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6325{
6326 int i;
6327
6328 for (i = 0; i < 16; i++)
6329 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6330}
6331
6332static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6333{
6334 int i;
6335
6336 for (i = 0; i < 16; i++)
6337 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6338}
6339
6340static void niu_load_hash(struct niu *np, u16 *hash)
6341{
6342 if (np->flags & NIU_FLAGS_XMAC)
6343 niu_load_hash_xmac(np, hash);
6344 else
6345 niu_load_hash_bmac(np, hash);
6346}
6347
6348static void niu_set_rx_mode(struct net_device *dev)
6349{
6350 struct niu *np = netdev_priv(dev);
6351 int i, alt_cnt, err;
ccffad25 6352 struct netdev_hw_addr *ha;
a3138df9
DM		 6353 unsigned long flags;
6354 u16 hash[16] = { 0, };
6355
6356 spin_lock_irqsave(&np->lock, flags);
6357 niu_enable_rx_mac(np, 0);
6358
6359 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6360 if (dev->flags & IFF_PROMISC)
6361 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6362 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6363 np->flags |= NIU_FLAGS_MCAST;
6364
32e7bfc4 6365 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6366 if (alt_cnt > niu_num_alt_addr(np)) {
6367 alt_cnt = 0;
6368 np->flags |= NIU_FLAGS_PROMISC;
6369 }
6370
6371 if (alt_cnt) {
6372 int index = 0;
6373
32e7bfc4 6374 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6375 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6376 if (err)
f10a1f2e
JP		 6377 netdev_warn(dev, "Error %d adding alt mac %d\n",
6378 err, index);
a3138df9
DM		 6379 err = niu_enable_alt_mac(np, index, 1);
6380 if (err)
f10a1f2e
JP		 6381 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6382 err, index);
a3138df9
DM		 6383
6384 index++;
6385 }
6386 } else {
3b5bcede
MW		 6387 int alt_start;
6388 if (np->flags & NIU_FLAGS_XMAC)
6389 alt_start = 0;
6390 else
6391 alt_start = 1;
6392 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6393 err = niu_enable_alt_mac(np, i, 0);
6394 if (err)
f10a1f2e
JP		 6395 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6396 err, i);
a3138df9
DM		 6397 }
6398 }
6399 if (dev->flags & IFF_ALLMULTI) {
6400 for (i = 0; i < 16; i++)
6401 hash[i] = 0xffff;
4cd24eaf 6402 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6403 netdev_for_each_mc_addr(ha, dev) {
6404 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6405
6406 crc >>= 24;
6407 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6408 }
6409 }
6410
6411 if (np->flags & NIU_FLAGS_MCAST)
6412 niu_load_hash(np, hash);
6413
6414 niu_enable_rx_mac(np, 1);
6415 spin_unlock_irqrestore(&np->lock, flags);
6416}
6417
6418static int niu_set_mac_addr(struct net_device *dev, void *p)
6419{
6420 struct niu *np = netdev_priv(dev);
6421 struct sockaddr *addr = p;
6422 unsigned long flags;
6423
6424 if (!is_valid_ether_addr(addr->sa_data))
6425 return -EINVAL;
6426
6427 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6428
6429 if (!netif_running(dev))
6430 return 0;
6431
6432 spin_lock_irqsave(&np->lock, flags);
6433 niu_enable_rx_mac(np, 0);
6434 niu_set_primary_mac(np, dev->dev_addr);
6435 niu_enable_rx_mac(np, 1);
6436 spin_unlock_irqrestore(&np->lock, flags);
6437
6438 return 0;
6439}
6440
6441static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6442{
6443 return -EOPNOTSUPP;
6444}
6445
6446static void niu_netif_stop(struct niu *np)
6447{
6448 np->dev->trans_start = jiffies; /* prevent tx timeout */
6449
6450 niu_disable_napi(np);
6451
6452 netif_tx_disable(np->dev);
6453}
6454
6455static void niu_netif_start(struct niu *np)
6456{
6457 /* NOTE: unconditional netif_wake_queue is only appropriate
6458 * so long as all callers are assured to have free tx slots
6459 * (such as after niu_init_hw).
6460 */
b4c21639 6461 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6462
6463 niu_enable_napi(np);
6464
6465 niu_enable_interrupts(np, 1);
6466}
6467
cff502a3
SB		 6468static void niu_reset_buffers(struct niu *np)
6469{
6470 int i, j, k, err;
6471
6472 if (np->rx_rings) {
6473 for (i = 0; i < np->num_rx_rings; i++) {
6474 struct rx_ring_info *rp = &np->rx_rings[i];
6475
6476 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6477 struct page *page;
6478
6479 page = rp->rxhash[j];
6480 while (page) {
6481 struct page *next =
6482 (struct page *) page->mapping;
6483 u64 base = page->index;
6484 base = base >> RBR_DESCR_ADDR_SHIFT;
6485 rp->rbr[k++] = cpu_to_le32(base);
6486 page = next;
6487 }
6488 }
6489 for (; k < MAX_RBR_RING_SIZE; k++) {
6490 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6491 if (unlikely(err))
6492 break;
6493 }
6494
6495 rp->rbr_index = rp->rbr_table_size - 1;
6496 rp->rcr_index = 0;
6497 rp->rbr_pending = 0;
6498 rp->rbr_refill_pending = 0;
6499 }
6500 }
6501 if (np->tx_rings) {
6502 for (i = 0; i < np->num_tx_rings; i++) {
6503 struct tx_ring_info *rp = &np->tx_rings[i];
6504
6505 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6506 if (rp->tx_buffs[j].skb)
6507 (void) release_tx_packet(np, rp, j);
6508 }
6509
6510 rp->pending = MAX_TX_RING_SIZE;
6511 rp->prod = 0;
6512 rp->cons = 0;
6513 rp->wrap_bit = 0;
6514 }
6515 }
6516}
6517
a3138df9
DM		 6518static void niu_reset_task(struct work_struct *work)
6519{
6520 struct niu *np = container_of(work, struct niu, reset_task);
6521 unsigned long flags;
6522 int err;
6523
6524 spin_lock_irqsave(&np->lock, flags);
6525 if (!netif_running(np->dev)) {
6526 spin_unlock_irqrestore(&np->lock, flags);
6527 return;
6528 }
6529
6530 spin_unlock_irqrestore(&np->lock, flags);
6531
6532 del_timer_sync(&np->timer);
6533
6534 niu_netif_stop(np);
6535
6536 spin_lock_irqsave(&np->lock, flags);
6537
6538 niu_stop_hw(np);
6539
cff502a3
SB		 6540 spin_unlock_irqrestore(&np->lock, flags);
6541
6542 niu_reset_buffers(np);
6543
6544 spin_lock_irqsave(&np->lock, flags);
6545
a3138df9
DM		 6546 err = niu_init_hw(np);
6547 if (!err) {
6548 np->timer.expires = jiffies + HZ;
6549 add_timer(&np->timer);
6550 niu_netif_start(np);
6551 }
6552
6553 spin_unlock_irqrestore(&np->lock, flags);
6554}
6555
6556static void niu_tx_timeout(struct net_device *dev)
6557{
6558 struct niu *np = netdev_priv(dev);
6559
f10a1f2e 6560 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6561 dev->name);
6562
6563 schedule_work(&np->reset_task);
6564}
6565
6566static void niu_set_txd(struct tx_ring_info *rp, int index,
6567 u64 mapping, u64 len, u64 mark,
6568 u64 n_frags)
6569{
6570 __le64 *desc = &rp->descr[index];
6571
6572 *desc = cpu_to_le64(mark |
6573 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6574 (len << TX_DESC_TR_LEN_SHIFT) |
6575 (mapping & TX_DESC_SAD));
6576}
6577
6578static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6579 u64 pad_bytes, u64 len)
6580{
6581 u16 eth_proto, eth_proto_inner;
6582 u64 csum_bits, l3off, ihl, ret;
6583 u8 ip_proto;
6584 int ipv6;
6585
6586 eth_proto = be16_to_cpu(ehdr->h_proto);
6587 eth_proto_inner = eth_proto;
6588 if (eth_proto == ETH_P_8021Q) {
6589 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6590 __be16 val = vp->h_vlan_encapsulated_proto;
6591
6592 eth_proto_inner = be16_to_cpu(val);
6593 }
6594
6595 ipv6 = ihl = 0;
6596 switch (skb->protocol) {
09640e63 6597 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6598 ip_proto = ip_hdr(skb)->protocol;
6599 ihl = ip_hdr(skb)->ihl;
6600 break;
09640e63 6601 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6602 ip_proto = ipv6_hdr(skb)->nexthdr;
6603 ihl = (40 >> 2);
6604 ipv6 = 1;
6605 break;
6606 default:
6607 ip_proto = ihl = 0;
6608 break;
6609 }
6610
6611 csum_bits = TXHDR_CSUM_NONE;
6612 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6613 u64 start, stuff;
6614
6615 csum_bits = (ip_proto == IPPROTO_TCP ?
6616 TXHDR_CSUM_TCP :
6617 (ip_proto == IPPROTO_UDP ?
6618 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6619
0d0b1672 6620 start = skb_checksum_start_offset(skb) -
a3138df9
DM		 6621 (pad_bytes + sizeof(struct tx_pkt_hdr));
6622 stuff = start + skb->csum_offset;
6623
6624 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6625 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6626 }
6627
6628 l3off = skb_network_offset(skb) -
6629 (pad_bytes + sizeof(struct tx_pkt_hdr));
6630
6631 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6632 (len << TXHDR_LEN_SHIFT) |
6633 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6634 (ihl << TXHDR_IHL_SHIFT) |
6635 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6636 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6637 (ipv6 ? TXHDR_IP_VER : 0) |
6638 csum_bits);
6639
6640 return ret;
6641}
6642
61357325
SH		 6643static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6644 struct net_device *dev)
a3138df9
DM		 6645{
6646 struct niu *np = netdev_priv(dev);
6647 unsigned long align, headroom;
b4c21639 6648 struct netdev_queue *txq;
a3138df9
DM		 6649 struct tx_ring_info *rp;
6650 struct tx_pkt_hdr *tp;
6651 unsigned int len, nfg;
6652 struct ethhdr *ehdr;
6653 int prod, i, tlen;
6654 u64 mapping, mrk;
6655
b4c21639
DM		 6656 i = skb_get_queue_mapping(skb);
6657 rp = &np->tx_rings[i];
6658 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6659
6660 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6661 netif_tx_stop_queue(txq);
f10a1f2e 6662 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6663 rp->tx_errors++;
6664 return NETDEV_TX_BUSY;
6665 }
6666
6667 if (skb->len < ETH_ZLEN) {
6668 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6669
6670 if (skb_pad(skb, pad_bytes))
6671 goto out;
6672 skb_put(skb, pad_bytes);
6673 }
6674
6675 len = sizeof(struct tx_pkt_hdr) + 15;
6676 if (skb_headroom(skb) < len) {
6677 struct sk_buff *skb_new;
6678
6679 skb_new = skb_realloc_headroom(skb, len);
6680 if (!skb_new) {
6681 rp->tx_errors++;
6682 goto out_drop;
6683 }
6684 kfree_skb(skb);
6685 skb = skb_new;
3ebebccf
DM		 6686 } else
6687 skb_orphan(skb);
a3138df9
DM		 6688
6689 align = ((unsigned long) skb->data & (16 - 1));
6690 headroom = align + sizeof(struct tx_pkt_hdr);
6691
6692 ehdr = (struct ethhdr *) skb->data;
6693 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6694
6695 len = skb->len - sizeof(struct tx_pkt_hdr);
6696 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6697 tp->resv = 0;
6698
6699 len = skb_headlen(skb);
6700 mapping = np->ops->map_single(np->device, skb->data,
6701 len, DMA_TO_DEVICE);
6702
6703 prod = rp->prod;
6704
6705 rp->tx_buffs[prod].skb = skb;
6706 rp->tx_buffs[prod].mapping = mapping;
6707
6708 mrk = TX_DESC_SOP;
6709 if (++rp->mark_counter == rp->mark_freq) {
6710 rp->mark_counter = 0;
6711 mrk |= TX_DESC_MARK;
6712 rp->mark_pending++;
6713 }
6714
6715 tlen = len;
6716 nfg = skb_shinfo(skb)->nr_frags;
6717 while (tlen > 0) {
6718 tlen -= MAX_TX_DESC_LEN;
6719 nfg++;
6720 }
6721
6722 while (len > 0) {
6723 unsigned int this_len = len;
6724
6725 if (this_len > MAX_TX_DESC_LEN)
6726 this_len = MAX_TX_DESC_LEN;
6727
6728 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6729 mrk = nfg = 0;
6730
6731 prod = NEXT_TX(rp, prod);
6732 mapping += this_len;
6733 len -= this_len;
6734 }
6735
6736 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6737 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6738
6739 len = frag->size;
6740 mapping = np->ops->map_page(np->device, frag->page,
6741 frag->page_offset, len,
6742 DMA_TO_DEVICE);
6743
6744 rp->tx_buffs[prod].skb = NULL;
6745 rp->tx_buffs[prod].mapping = mapping;
6746
6747 niu_set_txd(rp, prod, mapping, len, 0, 0);
6748
6749 prod = NEXT_TX(rp, prod);
6750 }
6751
6752 if (prod < rp->prod)
6753 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6754 rp->prod = prod;
6755
6756 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6757
6758 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6759 netif_tx_stop_queue(txq);
a3138df9 6760 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6761 netif_tx_wake_queue(txq);
a3138df9
DM		 6762 }
6763
a3138df9
DM		 6764out:
6765 return NETDEV_TX_OK;
6766
6767out_drop:
6768 rp->tx_errors++;
6769 kfree_skb(skb);
6770 goto out;
6771}
6772
6773static int niu_change_mtu(struct net_device *dev, int new_mtu)
6774{
6775 struct niu *np = netdev_priv(dev);
6776 int err, orig_jumbo, new_jumbo;
6777
6778 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6779 return -EINVAL;
6780
6781 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6782 new_jumbo = (new_mtu > ETH_DATA_LEN);
6783
6784 dev->mtu = new_mtu;
6785
6786 if (!netif_running(dev) ||
6787 (orig_jumbo == new_jumbo))
6788 return 0;
6789
6790 niu_full_shutdown(np, dev);
6791
6792 niu_free_channels(np);
6793
6794 niu_enable_napi(np);
6795
6796 err = niu_alloc_channels(np);
6797 if (err)
6798 return err;
6799
6800 spin_lock_irq(&np->lock);
6801
6802 err = niu_init_hw(np);
6803 if (!err) {
6804 init_timer(&np->timer);
6805 np->timer.expires = jiffies + HZ;
6806 np->timer.data = (unsigned long) np;
6807 np->timer.function = niu_timer;
6808
6809 err = niu_enable_interrupts(np, 1);
6810 if (err)
6811 niu_stop_hw(np);
6812 }
6813
6814 spin_unlock_irq(&np->lock);
6815
6816 if (!err) {
b4c21639 6817 netif_tx_start_all_queues(dev);
a3138df9
DM		 6818 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6819 netif_carrier_on(dev);
6820
6821 add_timer(&np->timer);
6822 }
6823
6824 return err;
6825}
6826
6827static void niu_get_drvinfo(struct net_device *dev,
6828 struct ethtool_drvinfo *info)
6829{
6830 struct niu *np = netdev_priv(dev);
6831 struct niu_vpd *vpd = &np->vpd;
6832
6833 strcpy(info->driver, DRV_MODULE_NAME);
6834 strcpy(info->version, DRV_MODULE_VERSION);
6835 sprintf(info->fw_version, "%d.%d",
6836 vpd->fcode_major, vpd->fcode_minor);
6837 if (np->parent->plat_type != PLAT_TYPE_NIU)
6838 strcpy(info->bus_info, pci_name(np->pdev));
6839}
6840
6841static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6842{
6843 struct niu *np = netdev_priv(dev);
6844 struct niu_link_config *lp;
6845
6846 lp = &np->link_config;
6847
6848 memset(cmd, 0, sizeof(*cmd));
6849 cmd->phy_address = np->phy_addr;
6850 cmd->supported = lp->supported;
38bb045d
CB		 6851 cmd->advertising = lp->active_advertising;
6852 cmd->autoneg = lp->active_autoneg;
70739497 6853 ethtool_cmd_speed_set(cmd, lp->active_speed);
a3138df9 6854 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6855 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6856 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6857 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6858
6859 return 0;
6860}
6861
6862static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6863{
38bb045d
CB		 6864 struct niu *np = netdev_priv(dev);
6865 struct niu_link_config *lp = &np->link_config;
6866
6867 lp->advertising = cmd->advertising;
25db0338 6868 lp->speed = ethtool_cmd_speed(cmd);
38bb045d
CB		 6869 lp->duplex = cmd->duplex;
6870 lp->autoneg = cmd->autoneg;
6871 return niu_init_link(np);
a3138df9
DM		 6872}
6873
6874static u32 niu_get_msglevel(struct net_device *dev)
6875{
6876 struct niu *np = netdev_priv(dev);
6877 return np->msg_enable;
6878}
6879
6880static void niu_set_msglevel(struct net_device *dev, u32 value)
6881{
6882 struct niu *np = netdev_priv(dev);
6883 np->msg_enable = value;
6884}
6885
38bb045d
CB		 6886static int niu_nway_reset(struct net_device *dev)
6887{
6888 struct niu *np = netdev_priv(dev);
6889
6890 if (np->link_config.autoneg)
6891 return niu_init_link(np);
6892
6893 return 0;
6894}
6895
a3138df9
DM		 6896static int niu_get_eeprom_len(struct net_device *dev)
6897{
6898 struct niu *np = netdev_priv(dev);
6899
6900 return np->eeprom_len;
6901}
6902
6903static int niu_get_eeprom(struct net_device *dev,
6904 struct ethtool_eeprom *eeprom, u8 *data)
6905{
6906 struct niu *np = netdev_priv(dev);
6907 u32 offset, len, val;
6908
6909 offset = eeprom->offset;
6910 len = eeprom->len;
6911
6912 if (offset + len < offset)
6913 return -EINVAL;
6914 if (offset >= np->eeprom_len)
6915 return -EINVAL;
6916 if (offset + len > np->eeprom_len)
6917 len = eeprom->len = np->eeprom_len - offset;
6918
6919 if (offset & 3) {
6920 u32 b_offset, b_count;
6921
6922 b_offset = offset & 3;
6923 b_count = 4 - b_offset;
6924 if (b_count > len)
6925 b_count = len;
6926
6927 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6928 memcpy(data, ((char *)&val) + b_offset, b_count);
6929 data += b_count;
6930 len -= b_count;
6931 offset += b_count;
6932 }
6933 while (len >= 4) {
6934 val = nr64(ESPC_NCR(offset / 4));
6935 memcpy(data, &val, 4);
6936 data += 4;
6937 len -= 4;
6938 offset += 4;
6939 }
6940 if (len) {
6941 val = nr64(ESPC_NCR(offset / 4));
6942 memcpy(data, &val, len);
6943 }
6944 return 0;
6945}
6946
2d96cf8c
SB		 6947static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6948{
6949 switch (flow_type) {
6950 case TCP_V4_FLOW:
6951 case TCP_V6_FLOW:
6952 *pid = IPPROTO_TCP;
6953 break;
6954 case UDP_V4_FLOW:
6955 case UDP_V6_FLOW:
6956 *pid = IPPROTO_UDP;
6957 break;
6958 case SCTP_V4_FLOW:
6959 case SCTP_V6_FLOW:
6960 *pid = IPPROTO_SCTP;
6961 break;
6962 case AH_V4_FLOW:
6963 case AH_V6_FLOW:
6964 *pid = IPPROTO_AH;
6965 break;
6966 case ESP_V4_FLOW:
6967 case ESP_V6_FLOW:
6968 *pid = IPPROTO_ESP;
6969 break;
6970 default:
6971 *pid = 0;
6972 break;
6973 }
6974}
6975
6976static int niu_class_to_ethflow(u64 class, int *flow_type)
6977{
6978 switch (class) {
6979 case CLASS_CODE_TCP_IPV4:
6980 *flow_type = TCP_V4_FLOW;
6981 break;
6982 case CLASS_CODE_UDP_IPV4:
6983 *flow_type = UDP_V4_FLOW;
6984 break;
6985 case CLASS_CODE_AH_ESP_IPV4:
6986 *flow_type = AH_V4_FLOW;
6987 break;
6988 case CLASS_CODE_SCTP_IPV4:
6989 *flow_type = SCTP_V4_FLOW;
6990 break;
6991 case CLASS_CODE_TCP_IPV6:
6992 *flow_type = TCP_V6_FLOW;
6993 break;
6994 case CLASS_CODE_UDP_IPV6:
6995 *flow_type = UDP_V6_FLOW;
6996 break;
6997 case CLASS_CODE_AH_ESP_IPV6:
6998 *flow_type = AH_V6_FLOW;
6999 break;
7000 case CLASS_CODE_SCTP_IPV6:
7001 *flow_type = SCTP_V6_FLOW;
7002 break;
7003 case CLASS_CODE_USER_PROG1:
7004 case CLASS_CODE_USER_PROG2:
7005 case CLASS_CODE_USER_PROG3:
7006 case CLASS_CODE_USER_PROG4:
7007 *flow_type = IP_USER_FLOW;
7008 break;
7009 default:
7010 return 0;
7011 }
7012
7013 return 1;
7014}
7015
b4653e99
SB		 7016static int niu_ethflow_to_class(int flow_type, u64 *class)
7017{
7018 switch (flow_type) {
7019 case TCP_V4_FLOW:
7020 *class = CLASS_CODE_TCP_IPV4;
7021 break;
7022 case UDP_V4_FLOW:
7023 *class = CLASS_CODE_UDP_IPV4;
7024 break;
c44d7995 7025 case AH_ESP_V4_FLOW:
2d96cf8c
SB		 7026 case AH_V4_FLOW:
7027 case ESP_V4_FLOW:
b4653e99
SB		 7028 *class = CLASS_CODE_AH_ESP_IPV4;
7029 break;
7030 case SCTP_V4_FLOW:
7031 *class = CLASS_CODE_SCTP_IPV4;
7032 break;
7033 case TCP_V6_FLOW:
7034 *class = CLASS_CODE_TCP_IPV6;
7035 break;
7036 case UDP_V6_FLOW:
7037 *class = CLASS_CODE_UDP_IPV6;
7038 break;
c44d7995 7039 case AH_ESP_V6_FLOW:
2d96cf8c
SB		 7040 case AH_V6_FLOW:
7041 case ESP_V6_FLOW:
b4653e99
SB		 7042 *class = CLASS_CODE_AH_ESP_IPV6;
7043 break;
7044 case SCTP_V6_FLOW:
7045 *class = CLASS_CODE_SCTP_IPV6;
7046 break;
7047 default:
38c080ff 7048 return 0;
b4653e99
SB		 7049 }
7050
7051 return 1;
7052}
7053
7054static u64 niu_flowkey_to_ethflow(u64 flow_key)
7055{
7056 u64 ethflow = 0;
7057
b4653e99
SB		 7058 if (flow_key & FLOW_KEY_L2DA)
7059 ethflow |= RXH_L2DA;
7060 if (flow_key & FLOW_KEY_VLAN)
7061 ethflow |= RXH_VLAN;
7062 if (flow_key & FLOW_KEY_IPSA)
7063 ethflow |= RXH_IP_SRC;
7064 if (flow_key & FLOW_KEY_IPDA)
7065 ethflow |= RXH_IP_DST;
7066 if (flow_key & FLOW_KEY_PROTO)
7067 ethflow |= RXH_L3_PROTO;
7068 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7069 ethflow |= RXH_L4_B_0_1;
7070 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7071 ethflow |= RXH_L4_B_2_3;
7072
7073 return ethflow;
7074
7075}
7076
7077static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7078{
7079 u64 key = 0;
7080
b4653e99
SB		 7081 if (ethflow & RXH_L2DA)
7082 key |= FLOW_KEY_L2DA;
7083 if (ethflow & RXH_VLAN)
7084 key |= FLOW_KEY_VLAN;
7085 if (ethflow & RXH_IP_SRC)
7086 key |= FLOW_KEY_IPSA;
7087 if (ethflow & RXH_IP_DST)
7088 key |= FLOW_KEY_IPDA;
7089 if (ethflow & RXH_L3_PROTO)
7090 key |= FLOW_KEY_PROTO;
7091 if (ethflow & RXH_L4_B_0_1)
7092 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7093 if (ethflow & RXH_L4_B_2_3)
7094 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7095
7096 *flow_key = key;
7097
7098 return 1;
7099
7100}
7101
2d96cf8c 7102static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7103{
b4653e99
SB		 7104 u64 class;
7105
2d96cf8c 7106 nfc->data = 0;
b4653e99 7107
2d96cf8c 7108 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7109 return -EINVAL;
7110
7111 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7112 TCAM_KEY_DISC)
2d96cf8c 7113 nfc->data = RXH_DISCARD;
b4653e99 7114 else
2d96cf8c 7115 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7116 CLASS_CODE_USER_PROG1]);
7117 return 0;
7118}
7119
2d96cf8c
SB		 7120static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7121 struct ethtool_rx_flow_spec *fsp)
7122{
ed440e82
HH		 7123 u32 tmp;
7124 u16 prt;
2d96cf8c 7125
ed440e82
HH		 7126 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7127 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7128
7129 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7130 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7131
7132 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7133 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7134
7135 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7136 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
2d96cf8c
SB		 7137
7138 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7139 TCAM_V4KEY2_TOS_SHIFT;
7140 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7141 TCAM_V4KEY2_TOS_SHIFT;
7142
7143 switch (fsp->flow_type) {
7144 case TCP_V4_FLOW:
7145 case UDP_V4_FLOW:
7146 case SCTP_V4_FLOW:
ed440e82
HH		 7147 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7148 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7149 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7150
7151 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7152 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7153 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c 7154
ed440e82
HH		 7155 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7156 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7157 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7158
7159 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7160 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7161 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c
SB		 7162 break;
7163 case AH_V4_FLOW:
7164 case ESP_V4_FLOW:
ed440e82 7165 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7166 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7167 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c 7168
ed440e82
HH		 7169 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7170 TCAM_V4KEY2_PORT_SPI_SHIFT;
7171 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c
SB		 7172 break;
7173 case IP_USER_FLOW:
ed440e82 7174 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7175 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7176 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c 7177
ed440e82
HH		 7178 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7179 TCAM_V4KEY2_PORT_SPI_SHIFT;
7180 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c
SB		 7181
7182 fsp->h_u.usr_ip4_spec.proto =
7183 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7184 TCAM_V4KEY2_PROTO_SHIFT;
7185 fsp->m_u.usr_ip4_spec.proto =
7186 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7187 TCAM_V4KEY2_PROTO_SHIFT;
7188
7189 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7190 break;
7191 default:
7192 break;
7193 }
7194}
7195
7196static int niu_get_ethtool_tcam_entry(struct niu *np,
7197 struct ethtool_rxnfc *nfc)
7198{
7199 struct niu_parent *parent = np->parent;
7200 struct niu_tcam_entry *tp;
7201 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7202 u16 idx;
7203 u64 class;
7204 int ret = 0;
7205
7206 idx = tcam_get_index(np, (u16)nfc->fs.location);
7207
7208 tp = &parent->tcam[idx];
7209 if (!tp->valid) {
f10a1f2e
JP		 7210 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7211 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7212 return -EINVAL;
7213 }
7214
7215 /* fill the flow spec entry */
7216 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7217 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7218 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7219
7220 if (ret < 0) {
f10a1f2e
JP		 7221 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7222 parent->index);
2d96cf8c
SB		 7223 ret = -EINVAL;
7224 goto out;
7225 }
7226
7227 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7228 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7229 TCAM_V4KEY2_PROTO_SHIFT;
7230 if (proto == IPPROTO_ESP) {
7231 if (fsp->flow_type == AH_V4_FLOW)
7232 fsp->flow_type = ESP_V4_FLOW;
7233 else
7234 fsp->flow_type = ESP_V6_FLOW;
7235 }
7236 }
7237
7238 switch (fsp->flow_type) {
7239 case TCP_V4_FLOW:
7240 case UDP_V4_FLOW:
7241 case SCTP_V4_FLOW:
7242 case AH_V4_FLOW:
7243 case ESP_V4_FLOW:
7244 niu_get_ip4fs_from_tcam_key(tp, fsp);
7245 break;
7246 case TCP_V6_FLOW:
7247 case UDP_V6_FLOW:
7248 case SCTP_V6_FLOW:
7249 case AH_V6_FLOW:
7250 case ESP_V6_FLOW:
7251 /* Not yet implemented */
7252 ret = -EINVAL;
7253 break;
7254 case IP_USER_FLOW:
7255 niu_get_ip4fs_from_tcam_key(tp, fsp);
7256 break;
7257 default:
7258 ret = -EINVAL;
7259 break;
7260 }
7261
7262 if (ret < 0)
7263 goto out;
7264
7265 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7266 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7267 else
7268 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7269 TCAM_ASSOCDATA_OFFSET_SHIFT;
7270
7271 /* put the tcam size here */
7272 nfc->data = tcam_get_size(np);
7273out:
7274 return ret;
7275}
7276
7277static int niu_get_ethtool_tcam_all(struct niu *np,
7278 struct ethtool_rxnfc *nfc,
7279 u32 *rule_locs)
7280{
7281 struct niu_parent *parent = np->parent;
7282 struct niu_tcam_entry *tp;
7283 int i, idx, cnt;
2d96cf8c 7284 unsigned long flags;
ee9c5cfa 7285 int ret = 0;
2d96cf8c
SB		 7286
7287 /* put the tcam size here */
7288 nfc->data = tcam_get_size(np);
7289
7290 niu_lock_parent(np, flags);
2d96cf8c
SB		 7291 for (cnt = 0, i = 0; i < nfc->data; i++) {
7292 idx = tcam_get_index(np, i);
7293 tp = &parent->tcam[idx];
7294 if (!tp->valid)
7295 continue;
ee9c5cfa
BH		 7296 if (cnt == nfc->rule_cnt) {
7297 ret = -EMSGSIZE;
7298 break;
7299 }
2d96cf8c
SB		 7300 rule_locs[cnt] = i;
7301 cnt++;
7302 }
7303 niu_unlock_parent(np, flags);
7304
ee9c5cfa 7305 return ret;
2d96cf8c
SB		 7306}
7307
7308static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7309 void *rule_locs)
b4653e99
SB		 7310{
7311 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7312 int ret = 0;
7313
7314 switch (cmd->cmd) {
7315 case ETHTOOL_GRXFH:
7316 ret = niu_get_hash_opts(np, cmd);
7317 break;
7318 case ETHTOOL_GRXRINGS:
7319 cmd->data = np->num_rx_rings;
7320 break;
7321 case ETHTOOL_GRXCLSRLCNT:
7322 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7323 break;
7324 case ETHTOOL_GRXCLSRULE:
7325 ret = niu_get_ethtool_tcam_entry(np, cmd);
7326 break;
7327 case ETHTOOL_GRXCLSRLALL:
7328 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7329 break;
7330 default:
7331 ret = -EINVAL;
7332 break;
7333 }
7334
7335 return ret;
7336}
7337
7338static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7339{
b4653e99
SB		 7340 u64 class;
7341 u64 flow_key = 0;
7342 unsigned long flags;
7343
2d96cf8c 7344 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7345 return -EINVAL;
7346
7347 if (class < CLASS_CODE_USER_PROG1 ||
7348 class > CLASS_CODE_SCTP_IPV6)
7349 return -EINVAL;
7350
2d96cf8c 7351 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7352 niu_lock_parent(np, flags);
7353 flow_key = np->parent->tcam_key[class -
7354 CLASS_CODE_USER_PROG1];
7355 flow_key |= TCAM_KEY_DISC;
7356 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7357 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7358 niu_unlock_parent(np, flags);
7359 return 0;
7360 } else {
7361 /* Discard was set before, but is not set now */
7362 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7363 TCAM_KEY_DISC) {
7364 niu_lock_parent(np, flags);
7365 flow_key = np->parent->tcam_key[class -
7366 CLASS_CODE_USER_PROG1];
7367 flow_key &= ~TCAM_KEY_DISC;
7368 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7369 flow_key);
7370 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7371 flow_key;
7372 niu_unlock_parent(np, flags);
7373 }
7374 }
7375
2d96cf8c 7376 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7377 return -EINVAL;
7378
7379 niu_lock_parent(np, flags);
7380 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7381 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7382 niu_unlock_parent(np, flags);
7383
7384 return 0;
7385}
7386
2d96cf8c
SB		 7387static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7388 struct niu_tcam_entry *tp,
7389 int l2_rdc_tab, u64 class)
7390{
7391 u8 pid = 0;
7392 u32 sip, dip, sipm, dipm, spi, spim;
7393 u16 sport, dport, spm, dpm;
7394
7395 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7396 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7397 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7398 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7399
7400 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7401 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7402 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7403 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7404
7405 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7406 tp->key[3] |= dip;
7407
7408 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7409 tp->key_mask[3] |= dipm;
7410
7411 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7412 TCAM_V4KEY2_TOS_SHIFT);
7413 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7414 TCAM_V4KEY2_TOS_SHIFT);
7415 switch (fsp->flow_type) {
7416 case TCP_V4_FLOW:
7417 case UDP_V4_FLOW:
7418 case SCTP_V4_FLOW:
7419 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7420 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7421 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7422 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7423
7424 tp->key[2] |= (((u64)sport << 16) | dport);
7425 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7426 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7427 break;
7428 case AH_V4_FLOW:
7429 case ESP_V4_FLOW:
7430 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7431 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7432
7433 tp->key[2] |= spi;
7434 tp->key_mask[2] |= spim;
7435 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7436 break;
7437 case IP_USER_FLOW:
7438 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7439 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7440
7441 tp->key[2] |= spi;
7442 tp->key_mask[2] |= spim;
7443 pid = fsp->h_u.usr_ip4_spec.proto;
7444 break;
7445 default:
7446 break;
7447 }
7448
7449 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7450 if (pid) {
7451 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7452 }
7453}
7454
7455static int niu_add_ethtool_tcam_entry(struct niu *np,
7456 struct ethtool_rxnfc *nfc)
7457{
7458 struct niu_parent *parent = np->parent;
7459 struct niu_tcam_entry *tp;
7460 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7461 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7462 int l2_rdc_table = rdc_table->first_table_num;
7463 u16 idx;
7464 u64 class;
7465 unsigned long flags;
7466 int err, ret;
7467
7468 ret = 0;
7469
7470 idx = nfc->fs.location;
7471 if (idx >= tcam_get_size(np))
7472 return -EINVAL;
7473
7474 if (fsp->flow_type == IP_USER_FLOW) {
7475 int i;
7476 int add_usr_cls = 0;
2d96cf8c
SB		 7477 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7478 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7479
e0de7c93
BH		 7480 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7481 return -EINVAL;
7482
2d96cf8c
SB		 7483 niu_lock_parent(np, flags);
7484
7485 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7486 if (parent->l3_cls[i]) {
7487 if (uspec->proto == parent->l3_cls_pid[i]) {
7488 class = parent->l3_cls[i];
7489 parent->l3_cls_refcnt[i]++;
7490 add_usr_cls = 1;
7491 break;
7492 }
7493 } else {
7494 /* Program new user IP class */
7495 switch (i) {
7496 case 0:
7497 class = CLASS_CODE_USER_PROG1;
7498 break;
7499 case 1:
7500 class = CLASS_CODE_USER_PROG2;
7501 break;
7502 case 2:
7503 class = CLASS_CODE_USER_PROG3;
7504 break;
7505 case 3:
7506 class = CLASS_CODE_USER_PROG4;
7507 break;
7508 default:
7509 break;
7510 }
e0de7c93 7511 ret = tcam_user_ip_class_set(np, class, 0,
2d96cf8c
SB		 7512 uspec->proto,
7513 uspec->tos,
7514 umask->tos);
7515 if (ret)
7516 goto out;
7517
7518 ret = tcam_user_ip_class_enable(np, class, 1);
7519 if (ret)
7520 goto out;
7521 parent->l3_cls[i] = class;
7522 parent->l3_cls_pid[i] = uspec->proto;
7523 parent->l3_cls_refcnt[i]++;
7524 add_usr_cls = 1;
7525 break;
7526 }
7527 }
7528 if (!add_usr_cls) {
f10a1f2e
JP		 7529 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7530 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7531 ret = -EINVAL;
7532 goto out;
7533 }
7534 niu_unlock_parent(np, flags);
7535 } else {
7536 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7537 return -EINVAL;
7538 }
7539 }
7540
7541 niu_lock_parent(np, flags);
7542
7543 idx = tcam_get_index(np, idx);
7544 tp = &parent->tcam[idx];
7545
7546 memset(tp, 0, sizeof(*tp));
7547
7548 /* fill in the tcam key and mask */
7549 switch (fsp->flow_type) {
7550 case TCP_V4_FLOW:
7551 case UDP_V4_FLOW:
7552 case SCTP_V4_FLOW:
7553 case AH_V4_FLOW:
7554 case ESP_V4_FLOW:
7555 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7556 break;
7557 case TCP_V6_FLOW:
7558 case UDP_V6_FLOW:
7559 case SCTP_V6_FLOW:
7560 case AH_V6_FLOW:
7561 case ESP_V6_FLOW:
7562 /* Not yet implemented */
f10a1f2e
JP		 7563 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7564 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7565 ret = -EINVAL;
7566 goto out;
7567 case IP_USER_FLOW:
e0de7c93 7568 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
2d96cf8c
SB		 7569 break;
7570 default:
f10a1f2e
JP		 7571 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7572 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7573 ret = -EINVAL;
7574 goto out;
7575 }
7576
7577 /* fill in the assoc data */
7578 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7579 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7580 } else {
7581 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7582 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7583 parent->index, __func__,
7584 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7585 ret = -EINVAL;
7586 goto out;
7587 }
7588 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7589 (fsp->ring_cookie <<
7590 TCAM_ASSOCDATA_OFFSET_SHIFT));
7591 }
7592
7593 err = tcam_write(np, idx, tp->key, tp->key_mask);
7594 if (err) {
7595 ret = -EINVAL;
7596 goto out;
7597 }
7598 err = tcam_assoc_write(np, idx, tp->assoc_data);
7599 if (err) {
7600 ret = -EINVAL;
7601 goto out;
7602 }
7603
7604 /* validate the entry */
7605 tp->valid = 1;
7606 np->clas.tcam_valid_entries++;
7607out:
7608 niu_unlock_parent(np, flags);
7609
7610 return ret;
7611}
7612
7613static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7614{
7615 struct niu_parent *parent = np->parent;
7616 struct niu_tcam_entry *tp;
7617 u16 idx;
7618 unsigned long flags;
7619 u64 class;
7620 int ret = 0;
7621
7622 if (loc >= tcam_get_size(np))
7623 return -EINVAL;
7624
7625 niu_lock_parent(np, flags);
7626
7627 idx = tcam_get_index(np, loc);
7628 tp = &parent->tcam[idx];
7629
7630 /* if the entry is of a user defined class, then update*/
7631 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7632 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7633
7634 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7635 int i;
7636 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7637 if (parent->l3_cls[i] == class) {
7638 parent->l3_cls_refcnt[i]--;
7639 if (!parent->l3_cls_refcnt[i]) {
7640 /* disable class */
7641 ret = tcam_user_ip_class_enable(np,
7642 class,
7643 0);
7644 if (ret)
7645 goto out;
7646 parent->l3_cls[i] = 0;
7647 parent->l3_cls_pid[i] = 0;
7648 }
7649 break;
7650 }
7651 }
7652 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7653 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7654 parent->index, __func__,
7655 (unsigned long long)class);
2d96cf8c
SB		 7656 ret = -EINVAL;
7657 goto out;
7658 }
7659 }
7660
7661 ret = tcam_flush(np, idx);
7662 if (ret)
7663 goto out;
7664
7665 /* invalidate the entry */
7666 tp->valid = 0;
7667 np->clas.tcam_valid_entries--;
7668out:
7669 niu_unlock_parent(np, flags);
7670
7671 return ret;
7672}
7673
7674static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7675{
7676 struct niu *np = netdev_priv(dev);
7677 int ret = 0;
7678
7679 switch (cmd->cmd) {
7680 case ETHTOOL_SRXFH:
7681 ret = niu_set_hash_opts(np, cmd);
7682 break;
7683 case ETHTOOL_SRXCLSRLINS:
7684 ret = niu_add_ethtool_tcam_entry(np, cmd);
7685 break;
7686 case ETHTOOL_SRXCLSRLDEL:
7687 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7688 break;
7689 default:
7690 ret = -EINVAL;
7691 break;
7692 }
7693
7694 return ret;
7695}
7696
a3138df9
DM		 7697static const struct {
7698 const char string[ETH_GSTRING_LEN];
7699} niu_xmac_stat_keys[] = {
7700 { "tx_frames" },
7701 { "tx_bytes" },
7702 { "tx_fifo_errors" },
7703 { "tx_overflow_errors" },
7704 { "tx_max_pkt_size_errors" },
7705 { "tx_underflow_errors" },
7706 { "rx_local_faults" },
7707 { "rx_remote_faults" },
7708 { "rx_link_faults" },
7709 { "rx_align_errors" },
7710 { "rx_frags" },
7711 { "rx_mcasts" },
7712 { "rx_bcasts" },
7713 { "rx_hist_cnt1" },
7714 { "rx_hist_cnt2" },
7715 { "rx_hist_cnt3" },
7716 { "rx_hist_cnt4" },
7717 { "rx_hist_cnt5" },
7718 { "rx_hist_cnt6" },
7719 { "rx_hist_cnt7" },
7720 { "rx_octets" },
7721 { "rx_code_violations" },
7722 { "rx_len_errors" },
7723 { "rx_crc_errors" },
7724 { "rx_underflows" },
7725 { "rx_overflows" },
7726 { "pause_off_state" },
7727 { "pause_on_state" },
7728 { "pause_received" },
7729};
7730
7731#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7732
7733static const struct {
7734 const char string[ETH_GSTRING_LEN];
7735} niu_bmac_stat_keys[] = {
7736 { "tx_underflow_errors" },
7737 { "tx_max_pkt_size_errors" },
7738 { "tx_bytes" },
7739 { "tx_frames" },
7740 { "rx_overflows" },
7741 { "rx_frames" },
7742 { "rx_align_errors" },
7743 { "rx_crc_errors" },
7744 { "rx_len_errors" },
7745 { "pause_off_state" },
7746 { "pause_on_state" },
7747 { "pause_received" },
7748};
7749
7750#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7751
7752static const struct {
7753 const char string[ETH_GSTRING_LEN];
7754} niu_rxchan_stat_keys[] = {
7755 { "rx_channel" },
7756 { "rx_packets" },
7757 { "rx_bytes" },
7758 { "rx_dropped" },
7759 { "rx_errors" },
7760};
7761
7762#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7763
7764static const struct {
7765 const char string[ETH_GSTRING_LEN];
7766} niu_txchan_stat_keys[] = {
7767 { "tx_channel" },
7768 { "tx_packets" },
7769 { "tx_bytes" },
7770 { "tx_errors" },
7771};
7772
7773#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7774
7775static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7776{
7777 struct niu *np = netdev_priv(dev);
7778 int i;
7779
7780 if (stringset != ETH_SS_STATS)
7781 return;
7782
7783 if (np->flags & NIU_FLAGS_XMAC) {
7784 memcpy(data, niu_xmac_stat_keys,
7785 sizeof(niu_xmac_stat_keys));
7786 data += sizeof(niu_xmac_stat_keys);
7787 } else {
7788 memcpy(data, niu_bmac_stat_keys,
7789 sizeof(niu_bmac_stat_keys));
7790 data += sizeof(niu_bmac_stat_keys);
7791 }
7792 for (i = 0; i < np->num_rx_rings; i++) {
7793 memcpy(data, niu_rxchan_stat_keys,
7794 sizeof(niu_rxchan_stat_keys));
7795 data += sizeof(niu_rxchan_stat_keys);
7796 }
7797 for (i = 0; i < np->num_tx_rings; i++) {
7798 memcpy(data, niu_txchan_stat_keys,
7799 sizeof(niu_txchan_stat_keys));
7800 data += sizeof(niu_txchan_stat_keys);
7801 }
7802}
7803
15f0a394 7804static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7805{
7806 struct niu *np = netdev_priv(dev);
7807
15f0a394
BH		 7808 if (stringset != ETH_SS_STATS)
7809 return -EINVAL;
7810
807540ba 7811 return (np->flags & NIU_FLAGS_XMAC ?
a3138df9
DM		 7812 NUM_XMAC_STAT_KEYS :
7813 NUM_BMAC_STAT_KEYS) +
7814 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
807540ba 7815 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
a3138df9
DM		 7816}
7817
7818static void niu_get_ethtool_stats(struct net_device *dev,
7819 struct ethtool_stats *stats, u64 *data)
7820{
7821 struct niu *np = netdev_priv(dev);
7822 int i;
7823
7824 niu_sync_mac_stats(np);
7825 if (np->flags & NIU_FLAGS_XMAC) {
7826 memcpy(data, &np->mac_stats.xmac,
7827 sizeof(struct niu_xmac_stats));
7828 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7829 } else {
7830 memcpy(data, &np->mac_stats.bmac,
7831 sizeof(struct niu_bmac_stats));
7832 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7833 }
7834 for (i = 0; i < np->num_rx_rings; i++) {
7835 struct rx_ring_info *rp = &np->rx_rings[i];
7836
b8a606b8
JDB		 7837 niu_sync_rx_discard_stats(np, rp, 0);
7838
a3138df9
DM		 7839 data[0] = rp->rx_channel;
7840 data[1] = rp->rx_packets;
7841 data[2] = rp->rx_bytes;
7842 data[3] = rp->rx_dropped;
7843 data[4] = rp->rx_errors;
7844 data += 5;
7845 }
7846 for (i = 0; i < np->num_tx_rings; i++) {
7847 struct tx_ring_info *rp = &np->tx_rings[i];
7848
7849 data[0] = rp->tx_channel;
7850 data[1] = rp->tx_packets;
7851 data[2] = rp->tx_bytes;
7852 data[3] = rp->tx_errors;
7853 data += 4;
7854 }
7855}
7856
7857static u64 niu_led_state_save(struct niu *np)
7858{
7859 if (np->flags & NIU_FLAGS_XMAC)
7860 return nr64_mac(XMAC_CONFIG);
7861 else
7862 return nr64_mac(BMAC_XIF_CONFIG);
7863}
7864
7865static void niu_led_state_restore(struct niu *np, u64 val)
7866{
7867 if (np->flags & NIU_FLAGS_XMAC)
7868 nw64_mac(XMAC_CONFIG, val);
7869 else
7870 nw64_mac(BMAC_XIF_CONFIG, val);
7871}
7872
7873static void niu_force_led(struct niu *np, int on)
7874{
7875 u64 val, reg, bit;
7876
7877 if (np->flags & NIU_FLAGS_XMAC) {
7878 reg = XMAC_CONFIG;
7879 bit = XMAC_CONFIG_FORCE_LED_ON;
7880 } else {
7881 reg = BMAC_XIF_CONFIG;
7882 bit = BMAC_XIF_CONFIG_LINK_LED;
7883 }
7884
7885 val = nr64_mac(reg);
7886 if (on)
7887 val |= bit;
7888 else
7889 val &= ~bit;
7890 nw64_mac(reg, val);
7891}
7892
7bc93714 7893static int niu_set_phys_id(struct net_device *dev,
7894 enum ethtool_phys_id_state state)
7895
a3138df9
DM		 7896{
7897 struct niu *np = netdev_priv(dev);
a3138df9
DM		 7898
7899 if (!netif_running(dev))
7900 return -EAGAIN;
7901
7bc93714 7902 switch (state) {
7903 case ETHTOOL_ID_ACTIVE:
7904 np->orig_led_state = niu_led_state_save(np);
fce55922 7905 return 1; /* cycle on/off once per second */
a3138df9 7906
7bc93714 7907 case ETHTOOL_ID_ON:
7908 niu_force_led(np, 1);
7909 break;
a3138df9 7910
7bc93714 7911 case ETHTOOL_ID_OFF:
7912 niu_force_led(np, 0);
7913 break;
a3138df9 7914
7bc93714 7915 case ETHTOOL_ID_INACTIVE:
7916 niu_led_state_restore(np, np->orig_led_state);
a3138df9 7917 }
a3138df9
DM		 7918
7919 return 0;
7920}
7921
7922static const struct ethtool_ops niu_ethtool_ops = {
7923 .get_drvinfo = niu_get_drvinfo,
7924 .get_link = ethtool_op_get_link,
7925 .get_msglevel = niu_get_msglevel,
7926 .set_msglevel = niu_set_msglevel,
38bb045d 7927 .nway_reset = niu_nway_reset,
a3138df9
DM		 7928 .get_eeprom_len = niu_get_eeprom_len,
7929 .get_eeprom = niu_get_eeprom,
7930 .get_settings = niu_get_settings,
7931 .set_settings = niu_set_settings,
7932 .get_strings = niu_get_strings,
15f0a394 7933 .get_sset_count = niu_get_sset_count,
a3138df9 7934 .get_ethtool_stats = niu_get_ethtool_stats,
7bc93714 7935 .set_phys_id = niu_set_phys_id,
2d96cf8c
SB		 7936 .get_rxnfc = niu_get_nfc,
7937 .set_rxnfc = niu_set_nfc,
a3138df9
DM		 7938};
7939
7940static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7941 int ldg, int ldn)
7942{
7943 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7944 return -EINVAL;
7945 if (ldn < 0 || ldn > LDN_MAX)
7946 return -EINVAL;
7947
7948 parent->ldg_map[ldn] = ldg;
7949
7950 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7951 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7952 * the firmware, and we're not supposed to change them.
7953 * Validate the mapping, because if it's wrong we probably
7954 * won't get any interrupts and that's painful to debug.
7955 */
7956 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7957 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7958 np->port, ldn, ldg,
7959 (unsigned long long) nr64(LDG_NUM(ldn)));
7960 return -EINVAL;
7961 }
7962 } else
7963 nw64(LDG_NUM(ldn), ldg);
7964
7965 return 0;
7966}
7967
7968static int niu_set_ldg_timer_res(struct niu *np, int res)
7969{
7970 if (res < 0 || res > LDG_TIMER_RES_VAL)
7971 return -EINVAL;
7972
7973
7974 nw64(LDG_TIMER_RES, res);
7975
7976 return 0;
7977}
7978
7979static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7980{
7981 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7982 (func < 0 || func > 3) ||
7983 (vector < 0 || vector > 0x1f))
7984 return -EINVAL;
7985
7986 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7987
7988 return 0;
7989}
7990
7991static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7992{
7993 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7994 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7995 int limit;
7996
7997 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7998 return -EINVAL;
7999
8000 frame = frame_base;
8001 nw64(ESPC_PIO_STAT, frame);
8002 limit = 64;
8003 do {
8004 udelay(5);
8005 frame = nr64(ESPC_PIO_STAT);
8006 if (frame & ESPC_PIO_STAT_READ_END)
8007 break;
8008 } while (limit--);
8009 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8010 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8011 (unsigned long long) frame);
8012 return -ENODEV;
8013 }
8014
8015 frame = frame_base;
8016 nw64(ESPC_PIO_STAT, frame);
8017 limit = 64;
8018 do {
8019 udelay(5);
8020 frame = nr64(ESPC_PIO_STAT);
8021 if (frame & ESPC_PIO_STAT_READ_END)
8022 break;
8023 } while (limit--);
8024 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8025 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8026 (unsigned long long) frame);
8027 return -ENODEV;
8028 }
8029
8030 frame = nr64(ESPC_PIO_STAT);
8031 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8032}
8033
8034static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8035{
8036 int err = niu_pci_eeprom_read(np, off);
8037 u16 val;
8038
8039 if (err < 0)
8040 return err;
8041 val = (err << 8);
8042 err = niu_pci_eeprom_read(np, off + 1);
8043 if (err < 0)
8044 return err;
8045 val |= (err & 0xff);
8046
8047 return val;
8048}
8049
8050static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8051{
8052 int err = niu_pci_eeprom_read(np, off);
8053 u16 val;
8054
8055 if (err < 0)
8056 return err;
8057
8058 val = (err & 0xff);
8059 err = niu_pci_eeprom_read(np, off + 1);
8060 if (err < 0)
8061 return err;
8062
8063 val |= (err & 0xff) << 8;
8064
8065 return val;
8066}
8067
8068static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8069 u32 off,
8070 char *namebuf,
8071 int namebuf_len)
8072{
8073 int i;
8074
8075 for (i = 0; i < namebuf_len; i++) {
8076 int err = niu_pci_eeprom_read(np, off + i);
8077 if (err < 0)
8078 return err;
8079 *namebuf++ = err;
8080 if (!err)
8081 break;
8082 }
8083 if (i >= namebuf_len)
8084 return -EINVAL;
8085
8086 return i + 1;
8087}
8088
8089static void __devinit niu_vpd_parse_version(struct niu *np)
8090{
8091 struct niu_vpd *vpd = &np->vpd;
8092 int len = strlen(vpd->version) + 1;
8093 const char *s = vpd->version;
8094 int i;
8095
8096 for (i = 0; i < len - 5; i++) {
9ea2bdab 8097 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8098 break;
8099 }
8100 if (i >= len - 5)
8101 return;
8102
8103 s += i + 5;
8104 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8105
f10a1f2e
JP		 8106 netif_printk(np, probe, KERN_DEBUG, np->dev,
8107 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8108 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8109 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8110 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8111 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8112 np->flags |= NIU_FLAGS_VPD_VALID;
8113}
8114
8115/* ESPC_PIO_EN_ENABLE must be set */
8116static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8117 u32 start, u32 end)
8118{
8119 unsigned int found_mask = 0;
8120#define FOUND_MASK_MODEL 0x00000001
8121#define FOUND_MASK_BMODEL 0x00000002
8122#define FOUND_MASK_VERS 0x00000004
8123#define FOUND_MASK_MAC 0x00000008
8124#define FOUND_MASK_NMAC 0x00000010
8125#define FOUND_MASK_PHY 0x00000020
8126#define FOUND_MASK_ALL 0x0000003f
8127
f10a1f2e
JP		 8128 netif_printk(np, probe, KERN_DEBUG, np->dev,
8129 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9 8130 while (start < end) {
f344c25d 8131 int len, err, prop_len;
a3138df9
DM		 8132 char namebuf[64];
8133 u8 *prop_buf;
8134 int max_len;
8135
8136 if (found_mask == FOUND_MASK_ALL) {
8137 niu_vpd_parse_version(np);
8138 return 1;
8139 }
8140
8141 err = niu_pci_eeprom_read(np, start + 2);
8142 if (err < 0)
8143 return err;
8144 len = err;
8145 start += 3;
8146
a3138df9
DM		 8147 prop_len = niu_pci_eeprom_read(np, start + 4);
8148 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8149 if (err < 0)
8150 return err;
8151
8152 prop_buf = NULL;
8153 max_len = 0;
8154 if (!strcmp(namebuf, "model")) {
8155 prop_buf = np->vpd.model;
8156 max_len = NIU_VPD_MODEL_MAX;
8157 found_mask |= FOUND_MASK_MODEL;
8158 } else if (!strcmp(namebuf, "board-model")) {
8159 prop_buf = np->vpd.board_model;
8160 max_len = NIU_VPD_BD_MODEL_MAX;
8161 found_mask |= FOUND_MASK_BMODEL;
8162 } else if (!strcmp(namebuf, "version")) {
8163 prop_buf = np->vpd.version;
8164 max_len = NIU_VPD_VERSION_MAX;
8165 found_mask |= FOUND_MASK_VERS;
8166 } else if (!strcmp(namebuf, "local-mac-address")) {
8167 prop_buf = np->vpd.local_mac;
8168 max_len = ETH_ALEN;
8169 found_mask |= FOUND_MASK_MAC;
8170 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8171 prop_buf = &np->vpd.mac_num;
8172 max_len = 1;
8173 found_mask |= FOUND_MASK_NMAC;
8174 } else if (!strcmp(namebuf, "phy-type")) {
8175 prop_buf = np->vpd.phy_type;
8176 max_len = NIU_VPD_PHY_TYPE_MAX;
8177 found_mask |= FOUND_MASK_PHY;
8178 }
8179
8180 if (max_len && prop_len > max_len) {
f10a1f2e 8181 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8182 return -EINVAL;
8183 }
8184
8185 if (prop_buf) {
8186 u32 off = start + 5 + err;
8187 int i;
8188
f10a1f2e
JP		 8189 netif_printk(np, probe, KERN_DEBUG, np->dev,
8190 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8191 namebuf, prop_len);
a3138df9
DM		 8192 for (i = 0; i < prop_len; i++)
8193 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8194 }
8195
8196 start += len;
8197 }
8198
8199 return 0;
8200}
8201
8202/* ESPC_PIO_EN_ENABLE must be set */
8203static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8204{
8205 u32 offset;
8206 int err;
8207
8208 err = niu_pci_eeprom_read16_swp(np, start + 1);
8209 if (err < 0)
8210 return;
8211
8212 offset = err + 3;
8213
8214 while (start + offset < ESPC_EEPROM_SIZE) {
8215 u32 here = start + offset;
8216 u32 end;
8217
8218 err = niu_pci_eeprom_read(np, here);
8219 if (err != 0x90)
8220 return;
8221
8222 err = niu_pci_eeprom_read16_swp(np, here + 1);
8223 if (err < 0)
8224 return;
8225
8226 here = start + offset + 3;
8227 end = start + offset + err;
8228
8229 offset += err;
8230
8231 err = niu_pci_vpd_scan_props(np, here, end);
8232 if (err < 0 || err == 1)
8233 return;
8234 }
8235}
8236
8237/* ESPC_PIO_EN_ENABLE must be set */
8238static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8239{
8240 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8241 int err;
8242
8243 while (start < end) {
8244 ret = start;
8245
8246 /* ROM header signature? */
8247 err = niu_pci_eeprom_read16(np, start + 0);
8248 if (err != 0x55aa)
8249 return 0;
8250
8251 /* Apply offset to PCI data structure. */
8252 err = niu_pci_eeprom_read16(np, start + 23);
8253 if (err < 0)
8254 return 0;
8255 start += err;
8256
8257 /* Check for "PCIR" signature. */
8258 err = niu_pci_eeprom_read16(np, start + 0);
8259 if (err != 0x5043)
8260 return 0;
8261 err = niu_pci_eeprom_read16(np, start + 2);
8262 if (err != 0x4952)
8263 return 0;
8264
8265 /* Check for OBP image type. */
8266 err = niu_pci_eeprom_read(np, start + 20);
8267 if (err < 0)
8268 return 0;
8269 if (err != 0x01) {
8270 err = niu_pci_eeprom_read(np, ret + 2);
8271 if (err < 0)
8272 return 0;
8273
8274 start = ret + (err * 512);
8275 continue;
8276 }
8277
8278 err = niu_pci_eeprom_read16_swp(np, start + 8);
8279 if (err < 0)
8280 return err;
8281 ret += err;
8282
8283 err = niu_pci_eeprom_read(np, ret + 0);
8284 if (err != 0x82)
8285 return 0;
8286
8287 return ret;
8288 }
8289
8290 return 0;
8291}
8292
8293static int __devinit niu_phy_type_prop_decode(struct niu *np,
8294 const char *phy_prop)
8295{
8296 if (!strcmp(phy_prop, "mif")) {
8297 /* 1G copper, MII */
8298 np->flags &= ~(NIU_FLAGS_FIBER |
8299 NIU_FLAGS_10G);
8300 np->mac_xcvr = MAC_XCVR_MII;
8301 } else if (!strcmp(phy_prop, "xgf")) {
8302 /* 10G fiber, XPCS */
8303 np->flags |= (NIU_FLAGS_10G |
8304 NIU_FLAGS_FIBER);
8305 np->mac_xcvr = MAC_XCVR_XPCS;
8306 } else if (!strcmp(phy_prop, "pcs")) {
8307 /* 1G fiber, PCS */
8308 np->flags &= ~NIU_FLAGS_10G;
8309 np->flags |= NIU_FLAGS_FIBER;
8310 np->mac_xcvr = MAC_XCVR_PCS;
8311 } else if (!strcmp(phy_prop, "xgc")) {
8312 /* 10G copper, XPCS */
8313 np->flags |= NIU_FLAGS_10G;
8314 np->flags &= ~NIU_FLAGS_FIBER;
8315 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8316 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8317 /* 10G Serdes or 1G Serdes, default to 10G */
8318 np->flags |= NIU_FLAGS_10G;
8319 np->flags &= ~NIU_FLAGS_FIBER;
8320 np->flags |= NIU_FLAGS_XCVR_SERDES;
8321 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8322 } else {
8323 return -EINVAL;
8324 }
8325 return 0;
8326}
8327
7f7c4072
MW		 8328static int niu_pci_vpd_get_nports(struct niu *np)
8329{
8330 int ports = 0;
8331
f9af8574
MW		 8332 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8333 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8335 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8336 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8337 ports = 4;
f9af8574
MW		 8338 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8339 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8340 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8341 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8342 ports = 2;
8343 }
8344
8345 return ports;
8346}
8347
a3138df9
DM		 8348static void __devinit niu_pci_vpd_validate(struct niu *np)
8349{
8350 struct net_device *dev = np->dev;
8351 struct niu_vpd *vpd = &np->vpd;
8352 u8 val8;
8353
8354 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8355 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8356
8357 np->flags &= ~NIU_FLAGS_VPD_VALID;
8358 return;
8359 }
8360
f9af8574
MW		 8361 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8362 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8363 np->flags |= NIU_FLAGS_10G;
8364 np->flags &= ~NIU_FLAGS_FIBER;
8365 np->flags |= NIU_FLAGS_XCVR_SERDES;
8366 np->mac_xcvr = MAC_XCVR_PCS;
8367 if (np->port > 1) {
8368 np->flags |= NIU_FLAGS_FIBER;
8369 np->flags &= ~NIU_FLAGS_10G;
8370 }
8371 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8372 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8373 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8374 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8375 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8376 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8377 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8378 np->vpd.phy_type);
f10a1f2e 8379 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8380 np->flags &= ~NIU_FLAGS_VPD_VALID;
8381 return;
8382 }
8383
8384 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8385
8386 val8 = dev->perm_addr[5];
8387 dev->perm_addr[5] += np->port;
8388 if (dev->perm_addr[5] < val8)
8389 dev->perm_addr[4]++;
8390
8391 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8392}
8393
8394static int __devinit niu_pci_probe_sprom(struct niu *np)
8395{
8396 struct net_device *dev = np->dev;
8397 int len, i;
8398 u64 val, sum;
8399 u8 val8;
8400
8401 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8402 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8403 len = val / 4;
8404
8405 np->eeprom_len = len;
8406
f10a1f2e
JP		 8407 netif_printk(np, probe, KERN_DEBUG, np->dev,
8408 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8409
8410 sum = 0;
8411 for (i = 0; i < len; i++) {
8412 val = nr64(ESPC_NCR(i));
8413 sum += (val >> 0) & 0xff;
8414 sum += (val >> 8) & 0xff;
8415 sum += (val >> 16) & 0xff;
8416 sum += (val >> 24) & 0xff;
8417 }
f10a1f2e
JP		 8418 netif_printk(np, probe, KERN_DEBUG, np->dev,
8419 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8420 if ((sum & 0xff) != 0xab) {
f10a1f2e 8421 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8422 return -EINVAL;
8423 }
8424
8425 val = nr64(ESPC_PHY_TYPE);
8426 switch (np->port) {
8427 case 0:
a9d41192 8428 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8429 ESPC_PHY_TYPE_PORT0_SHIFT;
8430 break;
8431 case 1:
a9d41192 8432 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8433 ESPC_PHY_TYPE_PORT1_SHIFT;
8434 break;
8435 case 2:
a9d41192 8436 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8437 ESPC_PHY_TYPE_PORT2_SHIFT;
8438 break;
8439 case 3:
a9d41192 8440 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8441 ESPC_PHY_TYPE_PORT3_SHIFT;
8442 break;
8443 default:
f10a1f2e 8444 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8445 np->port);
8446 return -EINVAL;
8447 }
f10a1f2e
JP		 8448 netif_printk(np, probe, KERN_DEBUG, np->dev,
8449 "SPROM: PHY type %x\n", val8);
a3138df9 8450
a9d41192 8451 switch (val8) {
a3138df9
DM		 8452 case ESPC_PHY_TYPE_1G_COPPER:
8453 /* 1G copper, MII */
8454 np->flags &= ~(NIU_FLAGS_FIBER |
8455 NIU_FLAGS_10G);
8456 np->mac_xcvr = MAC_XCVR_MII;
8457 break;
8458
8459 case ESPC_PHY_TYPE_1G_FIBER:
8460 /* 1G fiber, PCS */
8461 np->flags &= ~NIU_FLAGS_10G;
8462 np->flags |= NIU_FLAGS_FIBER;
8463 np->mac_xcvr = MAC_XCVR_PCS;
8464 break;
8465
8466 case ESPC_PHY_TYPE_10G_COPPER:
8467 /* 10G copper, XPCS */
8468 np->flags |= NIU_FLAGS_10G;
8469 np->flags &= ~NIU_FLAGS_FIBER;
8470 np->mac_xcvr = MAC_XCVR_XPCS;
8471 break;
8472
8473 case ESPC_PHY_TYPE_10G_FIBER:
8474 /* 10G fiber, XPCS */
8475 np->flags |= (NIU_FLAGS_10G |
8476 NIU_FLAGS_FIBER);
8477 np->mac_xcvr = MAC_XCVR_XPCS;
8478 break;
8479
8480 default:
f10a1f2e 8481 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8482 return -EINVAL;
8483 }
8484
8485 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8486 netif_printk(np, probe, KERN_DEBUG, np->dev,
8487 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8488 dev->perm_addr[0] = (val >> 0) & 0xff;
8489 dev->perm_addr[1] = (val >> 8) & 0xff;
8490 dev->perm_addr[2] = (val >> 16) & 0xff;
8491 dev->perm_addr[3] = (val >> 24) & 0xff;
8492
8493 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8494 netif_printk(np, probe, KERN_DEBUG, np->dev,
8495 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8496 dev->perm_addr[4] = (val >> 0) & 0xff;
8497 dev->perm_addr[5] = (val >> 8) & 0xff;
8498
8499 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8500 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8501 dev->perm_addr);
a3138df9
DM		 8502 return -EINVAL;
8503 }
8504
8505 val8 = dev->perm_addr[5];
8506 dev->perm_addr[5] += np->port;
8507 if (dev->perm_addr[5] < val8)
8508 dev->perm_addr[4]++;
8509
8510 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8511
8512 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8513 netif_printk(np, probe, KERN_DEBUG, np->dev,
8514 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8515 if (val >= 8 * 4)
a3138df9
DM		 8516 return -EINVAL;
8517
8518 for (i = 0; i < val; i += 4) {
8519 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8520
8521 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8522 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8523 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8524 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8525 }
8526 np->vpd.model[val] = '\0';
8527
8528 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8529 netif_printk(np, probe, KERN_DEBUG, np->dev,
8530 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8531 if (val >= 4 * 4)
a3138df9
DM		 8532 return -EINVAL;
8533
8534 for (i = 0; i < val; i += 4) {
8535 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8536
8537 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8538 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8539 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8540 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8541 }
8542 np->vpd.board_model[val] = '\0';
8543
8544 np->vpd.mac_num =
8545 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8546 netif_printk(np, probe, KERN_DEBUG, np->dev,
8547 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8548
8549 return 0;
8550}
8551
8552static int __devinit niu_get_and_validate_port(struct niu *np)
8553{
8554 struct niu_parent *parent = np->parent;
8555
8556 if (np->port <= 1)
8557 np->flags |= NIU_FLAGS_XMAC;
8558
8559 if (!parent->num_ports) {
8560 if (parent->plat_type == PLAT_TYPE_NIU) {
8561 parent->num_ports = 2;
8562 } else {
7f7c4072
MW		 8563 parent->num_ports = niu_pci_vpd_get_nports(np);
8564 if (!parent->num_ports) {
8565 /* Fall back to SPROM as last resort.
8566 * This will fail on most cards.
8567 */
8568 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8569 ESPC_NUM_PORTS_MACS_VAL;
8570
be0c007a
DM		 8571 /* All of the current probing methods fail on
8572 * Maramba on-board parts.
8573 */
7f7c4072 8574 if (!parent->num_ports)
be0c007a 8575 parent->num_ports = 4;
7f7c4072 8576 }
a3138df9
DM		 8577 }
8578 }
8579
a3138df9
DM		 8580 if (np->port >= parent->num_ports)
8581 return -ENODEV;
8582
8583 return 0;
8584}
8585
8586static int __devinit phy_record(struct niu_parent *parent,
8587 struct phy_probe_info *p,
8588 int dev_id_1, int dev_id_2, u8 phy_port,
8589 int type)
8590{
8591 u32 id = (dev_id_1 << 16) | dev_id_2;
8592 u8 idx;
8593
8594 if (dev_id_1 < 0 || dev_id_2 < 0)
8595 return 0;
8596 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8597 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8598 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8599 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8600 return 0;
8601 } else {
8602 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8603 return 0;
8604 }
8605
8606 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8607 parent->index, id,
f10a1f2e
JP		 8608 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8609 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8610 phy_port);
8611
8612 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8613 pr_err("Too many PHY ports\n");
a3138df9
DM		 8614 return -EINVAL;
8615 }
8616 idx = p->cur[type];
8617 p->phy_id[type][idx] = id;
8618 p->phy_port[type][idx] = phy_port;
8619 p->cur[type] = idx + 1;
8620 return 0;
8621}
8622
8623static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8624{
8625 int i;
8626
8627 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8628 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8629 return 1;
8630 }
8631 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8632 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8633 return 1;
8634 }
8635
8636 return 0;
8637}
8638
8639static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8640{
8641 int port, cnt;
8642
8643 cnt = 0;
8644 *lowest = 32;
8645 for (port = 8; port < 32; port++) {
8646 if (port_has_10g(p, port)) {
8647 if (!cnt)
8648 *lowest = port;
8649 cnt++;
8650 }
8651 }
8652
8653 return cnt;
8654}
8655
8656static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8657{
8658 *lowest = 32;
8659 if (p->cur[PHY_TYPE_MII])
8660 *lowest = p->phy_port[PHY_TYPE_MII][0];
8661
8662 return p->cur[PHY_TYPE_MII];
8663}
8664
8665static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8666{
8667 int num_ports = parent->num_ports;
8668 int i;
8669
8670 for (i = 0; i < num_ports; i++) {
8671 parent->rxchan_per_port[i] = (16 / num_ports);
8672 parent->txchan_per_port[i] = (16 / num_ports);
8673
f10a1f2e 8674 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8675 parent->index, i,
8676 parent->rxchan_per_port[i],
8677 parent->txchan_per_port[i]);
8678 }
8679}
8680
8681static void __devinit niu_divide_channels(struct niu_parent *parent,
8682 int num_10g, int num_1g)
8683{
8684 int num_ports = parent->num_ports;
8685 int rx_chans_per_10g, rx_chans_per_1g;
8686 int tx_chans_per_10g, tx_chans_per_1g;
8687 int i, tot_rx, tot_tx;
8688
8689 if (!num_10g || !num_1g) {
8690 rx_chans_per_10g = rx_chans_per_1g =
8691 (NIU_NUM_RXCHAN / num_ports);
8692 tx_chans_per_10g = tx_chans_per_1g =
8693 (NIU_NUM_TXCHAN / num_ports);
8694 } else {
8695 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8696 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8697 (rx_chans_per_1g * num_1g)) /
8698 num_10g;
8699
8700 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8701 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8702 (tx_chans_per_1g * num_1g)) /
8703 num_10g;
8704 }
8705
8706 tot_rx = tot_tx = 0;
8707 for (i = 0; i < num_ports; i++) {
8708 int type = phy_decode(parent->port_phy, i);
8709
8710 if (type == PORT_TYPE_10G) {
8711 parent->rxchan_per_port[i] = rx_chans_per_10g;
8712 parent->txchan_per_port[i] = tx_chans_per_10g;
8713 } else {
8714 parent->rxchan_per_port[i] = rx_chans_per_1g;
8715 parent->txchan_per_port[i] = tx_chans_per_1g;
8716 }
f10a1f2e 8717 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8718 parent->index, i,
8719 parent->rxchan_per_port[i],
8720 parent->txchan_per_port[i]);
8721 tot_rx += parent->rxchan_per_port[i];
8722 tot_tx += parent->txchan_per_port[i];
8723 }
8724
8725 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8726 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8727 parent->index, tot_rx);
8728 for (i = 0; i < num_ports; i++)
8729 parent->rxchan_per_port[i] = 1;
8730 }
8731 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8732 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8733 parent->index, tot_tx);
8734 for (i = 0; i < num_ports; i++)
8735 parent->txchan_per_port[i] = 1;
8736 }
8737 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8738 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8739 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8740 }
8741}
8742
8743static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8744 int num_10g, int num_1g)
8745{
8746 int i, num_ports = parent->num_ports;
8747 int rdc_group, rdc_groups_per_port;
8748 int rdc_channel_base;
8749
8750 rdc_group = 0;
8751 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8752
8753 rdc_channel_base = 0;
8754
8755 for (i = 0; i < num_ports; i++) {
8756 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8757 int grp, num_channels = parent->rxchan_per_port[i];
8758 int this_channel_offset;
8759
8760 tp->first_table_num = rdc_group;
8761 tp->num_tables = rdc_groups_per_port;
8762 this_channel_offset = 0;
8763 for (grp = 0; grp < tp->num_tables; grp++) {
8764 struct rdc_table *rt = &tp->tables[grp];
8765 int slot;
8766
f10a1f2e 8767 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8768 parent->index, i, tp->first_table_num + grp);
8769 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8770 rt->rxdma_channel[slot] =
8771 rdc_channel_base + this_channel_offset;
8772
f10a1f2e 8773 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8774
8775 if (++this_channel_offset == num_channels)
8776 this_channel_offset = 0;
8777 }
f10a1f2e 8778 pr_cont("]\n");
a3138df9
DM		 8779 }
8780
8781 parent->rdc_default[i] = rdc_channel_base;
8782
8783 rdc_channel_base += num_channels;
8784 rdc_group += rdc_groups_per_port;
8785 }
8786}
8787
8788static int __devinit fill_phy_probe_info(struct niu *np,
8789 struct niu_parent *parent,
8790 struct phy_probe_info *info)
8791{
8792 unsigned long flags;
8793 int port, err;
8794
8795 memset(info, 0, sizeof(*info));
8796
8797 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8798 niu_lock_parent(np, flags);
8799 err = 0;
8800 for (port = 8; port < 32; port++) {
8801 int dev_id_1, dev_id_2;
8802
8803 dev_id_1 = mdio_read(np, port,
8804 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8805 dev_id_2 = mdio_read(np, port,
8806 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8807 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8808 PHY_TYPE_PMA_PMD);
8809 if (err)
8810 break;
8811 dev_id_1 = mdio_read(np, port,
8812 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8813 dev_id_2 = mdio_read(np, port,
8814 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8815 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8816 PHY_TYPE_PCS);
8817 if (err)
8818 break;
8819 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8820 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8821 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8822 PHY_TYPE_MII);
8823 if (err)
8824 break;
8825 }
8826 niu_unlock_parent(np, flags);
8827
8828 return err;
8829}
8830
8831static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8832{
8833 struct phy_probe_info *info = &parent->phy_probe_info;
8834 int lowest_10g, lowest_1g;
8835 int num_10g, num_1g;
8836 u32 val;
8837 int err;
8838
e3e081e1
SB		 8839 num_10g = num_1g = 0;
8840
f9af8574
MW		 8841 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8842 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8843 num_10g = 0;
8844 num_1g = 2;
8845 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8846 parent->num_ports = 4;
8847 val = (phy_encode(PORT_TYPE_1G, 0) |
8848 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8849 phy_encode(PORT_TYPE_1G, 2) |
8850 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8851 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8852 num_10g = 2;
8853 num_1g = 0;
8854 parent->num_ports = 2;
8855 val = (phy_encode(PORT_TYPE_10G, 0) |
8856 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8857 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8858 (parent->plat_type == PLAT_TYPE_NIU)) {
8859 /* this is the Monza case */
8860 if (np->flags & NIU_FLAGS_10G) {
8861 val = (phy_encode(PORT_TYPE_10G, 0) |
8862 phy_encode(PORT_TYPE_10G, 1));
8863 } else {
8864 val = (phy_encode(PORT_TYPE_1G, 0) |
8865 phy_encode(PORT_TYPE_1G, 1));
8866 }
5fbd7e24
MW		 8867 } else {
8868 err = fill_phy_probe_info(np, parent, info);
8869 if (err)
8870 return err;
a3138df9 8871
5fbd7e24
MW		 8872 num_10g = count_10g_ports(info, &lowest_10g);
8873 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8874
5fbd7e24
MW		 8875 switch ((num_10g << 4) | num_1g) {
8876 case 0x24:
8877 if (lowest_1g == 10)
8878 parent->plat_type = PLAT_TYPE_VF_P0;
8879 else if (lowest_1g == 26)
8880 parent->plat_type = PLAT_TYPE_VF_P1;
8881 else
8882 goto unknown_vg_1g_port;
a3138df9 8883
5fbd7e24
MW		 8884 /* fallthru */
8885 case 0x22:
a3138df9 8886 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8887 phy_encode(PORT_TYPE_10G, 1) |
8888 phy_encode(PORT_TYPE_1G, 2) |
8889 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8890 break;
a3138df9 8891
5fbd7e24
MW		 8892 case 0x20:
8893 val = (phy_encode(PORT_TYPE_10G, 0) |
8894 phy_encode(PORT_TYPE_10G, 1));
8895 break;
a3138df9 8896
5fbd7e24
MW		 8897 case 0x10:
8898 val = phy_encode(PORT_TYPE_10G, np->port);
8899 break;
a3138df9 8900
5fbd7e24
MW		 8901 case 0x14:
8902 if (lowest_1g == 10)
8903 parent->plat_type = PLAT_TYPE_VF_P0;
8904 else if (lowest_1g == 26)
8905 parent->plat_type = PLAT_TYPE_VF_P1;
8906 else
8907 goto unknown_vg_1g_port;
8908
8909 /* fallthru */
8910 case 0x13:
8911 if ((lowest_10g & 0x7) == 0)
8912 val = (phy_encode(PORT_TYPE_10G, 0) |
8913 phy_encode(PORT_TYPE_1G, 1) |
8914 phy_encode(PORT_TYPE_1G, 2) |
8915 phy_encode(PORT_TYPE_1G, 3));
8916 else
8917 val = (phy_encode(PORT_TYPE_1G, 0) |
8918 phy_encode(PORT_TYPE_10G, 1) |
8919 phy_encode(PORT_TYPE_1G, 2) |
8920 phy_encode(PORT_TYPE_1G, 3));
8921 break;
8922
8923 case 0x04:
8924 if (lowest_1g == 10)
8925 parent->plat_type = PLAT_TYPE_VF_P0;
8926 else if (lowest_1g == 26)
8927 parent->plat_type = PLAT_TYPE_VF_P1;
8928 else
8929 goto unknown_vg_1g_port;
8930
8931 val = (phy_encode(PORT_TYPE_1G, 0) |
8932 phy_encode(PORT_TYPE_1G, 1) |
8933 phy_encode(PORT_TYPE_1G, 2) |
8934 phy_encode(PORT_TYPE_1G, 3));
8935 break;
8936
8937 default:
f10a1f2e 8938 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8939 num_10g, num_1g);
8940 return -EINVAL;
8941 }
a3138df9
DM		 8942 }
8943
8944 parent->port_phy = val;
8945
8946 if (parent->plat_type == PLAT_TYPE_NIU)
8947 niu_n2_divide_channels(parent);
8948 else
8949 niu_divide_channels(parent, num_10g, num_1g);
8950
8951 niu_divide_rdc_groups(parent, num_10g, num_1g);
8952
8953 return 0;
8954
8955unknown_vg_1g_port:
f10a1f2e 8956 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8957 return -EINVAL;
8958}
8959
8960static int __devinit niu_probe_ports(struct niu *np)
8961{
8962 struct niu_parent *parent = np->parent;
8963 int err, i;
8964
a3138df9
DM		 8965 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8966 err = walk_phys(np, parent);
8967 if (err)
8968 return err;
8969
8970 niu_set_ldg_timer_res(np, 2);
8971 for (i = 0; i <= LDN_MAX; i++)
8972 niu_ldn_irq_enable(np, i, 0);
8973 }
8974
8975 if (parent->port_phy == PORT_PHY_INVALID)
8976 return -EINVAL;
8977
8978 return 0;
8979}
8980
8981static int __devinit niu_classifier_swstate_init(struct niu *np)
8982{
8983 struct niu_classifier *cp = &np->clas;
8984
2d96cf8c
SB		 8985 cp->tcam_top = (u16) np->port;
8986 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8987 cp->h1_init = 0xffffffff;
8988 cp->h2_init = 0xffff;
8989
8990 return fflp_early_init(np);
8991}
8992
8993static void __devinit niu_link_config_init(struct niu *np)
8994{
8995 struct niu_link_config *lp = &np->link_config;
8996
8997 lp->advertising = (ADVERTISED_10baseT_Half |
8998 ADVERTISED_10baseT_Full |
8999 ADVERTISED_100baseT_Half |
9000 ADVERTISED_100baseT_Full |
9001 ADVERTISED_1000baseT_Half |
9002 ADVERTISED_1000baseT_Full |
9003 ADVERTISED_10000baseT_Full |
9004 ADVERTISED_Autoneg);
9005 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 9006 lp->duplex = DUPLEX_FULL;
9007 lp->active_duplex = DUPLEX_INVALID;
9008 lp->autoneg = 1;
a3138df9
DM		 9009#if 0
9010 lp->loopback_mode = LOOPBACK_MAC;
9011 lp->active_speed = SPEED_10000;
9012 lp->active_duplex = DUPLEX_FULL;
9013#else
9014 lp->loopback_mode = LOOPBACK_DISABLED;
9015#endif
9016}
9017
9018static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9019{
9020 switch (np->port) {
9021 case 0:
9022 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9023 np->ipp_off = 0x00000;
9024 np->pcs_off = 0x04000;
9025 np->xpcs_off = 0x02000;
9026 break;
9027
9028 case 1:
9029 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9030 np->ipp_off = 0x08000;
9031 np->pcs_off = 0x0a000;
9032 np->xpcs_off = 0x08000;
9033 break;
9034
9035 case 2:
9036 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9037 np->ipp_off = 0x04000;
9038 np->pcs_off = 0x0e000;
9039 np->xpcs_off = ~0UL;
9040 break;
9041
9042 case 3:
9043 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9044 np->ipp_off = 0x0c000;
9045 np->pcs_off = 0x12000;
9046 np->xpcs_off = ~0UL;
9047 break;
9048
9049 default:
f10a1f2e 9050 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9051 return -EINVAL;
9052 }
9053
9054 return 0;
9055}
9056
9057static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9058{
9059 struct msix_entry msi_vec[NIU_NUM_LDG];
9060 struct niu_parent *parent = np->parent;
9061 struct pci_dev *pdev = np->pdev;
9062 int i, num_irqs, err;
9063 u8 first_ldg;
9064
9065 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9066 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9067 ldg_num_map[i] = first_ldg + i;
9068
9069 num_irqs = (parent->rxchan_per_port[np->port] +
9070 parent->txchan_per_port[np->port] +
9071 (np->port == 0 ? 3 : 1));
9072 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9073
9074retry:
9075 for (i = 0; i < num_irqs; i++) {
9076 msi_vec[i].vector = 0;
9077 msi_vec[i].entry = i;
9078 }
9079
9080 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9081 if (err < 0) {
9082 np->flags &= ~NIU_FLAGS_MSIX;
9083 return;
9084 }
9085 if (err > 0) {
9086 num_irqs = err;
9087 goto retry;
9088 }
9089
9090 np->flags |= NIU_FLAGS_MSIX;
9091 for (i = 0; i < num_irqs; i++)
9092 np->ldg[i].irq = msi_vec[i].vector;
9093 np->num_ldg = num_irqs;
9094}
9095
9096static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9097{
9098#ifdef CONFIG_SPARC64
2dc11581 9099 struct platform_device *op = np->op;
a3138df9
DM		 9100 const u32 *int_prop;
9101 int i;
9102
61c7a080 9103 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
a3138df9
DM		 9104 if (!int_prop)
9105 return -ENODEV;
9106
1636f8ac 9107 for (i = 0; i < op->archdata.num_irqs; i++) {
a3138df9 9108 ldg_num_map[i] = int_prop[i];
1636f8ac 9109 np->ldg[i].irq = op->archdata.irqs[i];
a3138df9
DM		 9110 }
9111
1636f8ac 9112 np->num_ldg = op->archdata.num_irqs;
a3138df9
DM		 9113
9114 return 0;
9115#else
9116 return -EINVAL;
9117#endif
9118}
9119
9120static int __devinit niu_ldg_init(struct niu *np)
9121{
9122 struct niu_parent *parent = np->parent;
9123 u8 ldg_num_map[NIU_NUM_LDG];
9124 int first_chan, num_chan;
9125 int i, err, ldg_rotor;
9126 u8 port;
9127
9128 np->num_ldg = 1;
9129 np->ldg[0].irq = np->dev->irq;
9130 if (parent->plat_type == PLAT_TYPE_NIU) {
9131 err = niu_n2_irq_init(np, ldg_num_map);
9132 if (err)
9133 return err;
9134 } else
9135 niu_try_msix(np, ldg_num_map);
9136
9137 port = np->port;
9138 for (i = 0; i < np->num_ldg; i++) {
9139 struct niu_ldg *lp = &np->ldg[i];
9140
9141 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9142
9143 lp->np = np;
9144 lp->ldg_num = ldg_num_map[i];
9145 lp->timer = 2; /* XXX */
9146
9147 /* On N2 NIU the firmware has setup the SID mappings so they go
9148 * to the correct values that will route the LDG to the proper
9149 * interrupt in the NCU interrupt table.
9150 */
9151 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9152 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9153 if (err)
9154 return err;
9155 }
9156 }
9157
9158 /* We adopt the LDG assignment ordering used by the N2 NIU
9159 * 'interrupt' properties because that simplifies a lot of
9160 * things. This ordering is:
9161 *
9162 * MAC
9163 * MIF (if port zero)
9164 * SYSERR (if port zero)
9165 * RX channels
9166 * TX channels
9167 */
9168
9169 ldg_rotor = 0;
9170
9171 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9172 LDN_MAC(port));
9173 if (err)
9174 return err;
9175
9176 ldg_rotor++;
9177 if (ldg_rotor == np->num_ldg)
9178 ldg_rotor = 0;
9179
9180 if (port == 0) {
9181 err = niu_ldg_assign_ldn(np, parent,
9182 ldg_num_map[ldg_rotor],
9183 LDN_MIF);
9184 if (err)
9185 return err;
9186
9187 ldg_rotor++;
9188 if (ldg_rotor == np->num_ldg)
9189 ldg_rotor = 0;
9190
9191 err = niu_ldg_assign_ldn(np, parent,
9192 ldg_num_map[ldg_rotor],
9193 LDN_DEVICE_ERROR);
9194 if (err)
9195 return err;
9196
9197 ldg_rotor++;
9198 if (ldg_rotor == np->num_ldg)
9199 ldg_rotor = 0;
9200
9201 }
9202
9203 first_chan = 0;
9204 for (i = 0; i < port; i++)
956837f7 9205 first_chan += parent->rxchan_per_port[i];
a3138df9
DM		 9206 num_chan = parent->rxchan_per_port[port];
9207
9208 for (i = first_chan; i < (first_chan + num_chan); i++) {
9209 err = niu_ldg_assign_ldn(np, parent,
9210 ldg_num_map[ldg_rotor],
9211 LDN_RXDMA(i));
9212 if (err)
9213 return err;
9214 ldg_rotor++;
9215 if (ldg_rotor == np->num_ldg)
9216 ldg_rotor = 0;
9217 }
9218
9219 first_chan = 0;
9220 for (i = 0; i < port; i++)
956837f7 9221 first_chan += parent->txchan_per_port[i];
a3138df9
DM		 9222 num_chan = parent->txchan_per_port[port];
9223 for (i = first_chan; i < (first_chan + num_chan); i++) {
9224 err = niu_ldg_assign_ldn(np, parent,
9225 ldg_num_map[ldg_rotor],
9226 LDN_TXDMA(i));
9227 if (err)
9228 return err;
9229 ldg_rotor++;
9230 if (ldg_rotor == np->num_ldg)
9231 ldg_rotor = 0;
9232 }
9233
9234 return 0;
9235}
9236
9237static void __devexit niu_ldg_free(struct niu *np)
9238{
9239 if (np->flags & NIU_FLAGS_MSIX)
9240 pci_disable_msix(np->pdev);
9241}
9242
9243static int __devinit niu_get_of_props(struct niu *np)
9244{
9245#ifdef CONFIG_SPARC64
9246 struct net_device *dev = np->dev;
9247 struct device_node *dp;
9248 const char *phy_type;
9249 const u8 *mac_addr;
f9af8574 9250 const char *model;
a3138df9
DM		 9251 int prop_len;
9252
9253 if (np->parent->plat_type == PLAT_TYPE_NIU)
61c7a080 9254 dp = np->op->dev.of_node;
a3138df9
DM		 9255 else
9256 dp = pci_device_to_OF_node(np->pdev);
9257
9258 phy_type = of_get_property(dp, "phy-type", &prop_len);
9259 if (!phy_type) {
f10a1f2e
JP		 9260 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9261 dp->full_name);
a3138df9
DM		 9262 return -EINVAL;
9263 }
9264
9265 if (!strcmp(phy_type, "none"))
9266 return -ENODEV;
9267
9268 strcpy(np->vpd.phy_type, phy_type);
9269
9270 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9271 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9272 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9273 return -EINVAL;
9274 }
9275
9276 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9277 if (!mac_addr) {
f10a1f2e
JP		 9278 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9279 dp->full_name);
a3138df9
DM		 9280 return -EINVAL;
9281 }
9282 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9283 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9284 dp->full_name, prop_len);
a3138df9
DM		 9285 }
9286 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9287 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9288 netdev_err(dev, "%s: OF MAC address is invalid\n",
9289 dp->full_name);
9290 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9291 return -EINVAL;
9292 }
9293
9294 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9295
9296 model = of_get_property(dp, "model", &prop_len);
9297
9298 if (model)
9299 strcpy(np->vpd.model, model);
a3138df9 9300
9c5cd670
TC		 9301 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9302 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9303 NIU_FLAGS_HOTPLUG_PHY);
9304 }
9305
a3138df9
DM		 9306 return 0;
9307#else
9308 return -EINVAL;
9309#endif
9310}
9311
9312static int __devinit niu_get_invariants(struct niu *np)
9313{
9314 int err, have_props;
9315 u32 offset;
9316
9317 err = niu_get_of_props(np);
9318 if (err == -ENODEV)
9319 return err;
9320
9321 have_props = !err;
9322
a3138df9
DM		 9323 err = niu_init_mac_ipp_pcs_base(np);
9324 if (err)
9325 return err;
9326
7f7c4072
MW		 9327 if (have_props) {
9328 err = niu_get_and_validate_port(np);
9329 if (err)
9330 return err;
9331
9332 } else {
a3138df9
DM		 9333 if (np->parent->plat_type == PLAT_TYPE_NIU)
9334 return -EINVAL;
9335
9336 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9337 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9338 netif_printk(np, probe, KERN_DEBUG, np->dev,
9339 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9340 if (offset)
9341 niu_pci_vpd_fetch(np, offset);
9342 nw64(ESPC_PIO_EN, 0);
9343
7f7c4072 9344 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9345 niu_pci_vpd_validate(np);
7f7c4072
MW		 9346 err = niu_get_and_validate_port(np);
9347 if (err)
9348 return err;
9349 }
a3138df9
DM		 9350
9351 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9352 err = niu_get_and_validate_port(np);
9353 if (err)
9354 return err;
a3138df9
DM		 9355 err = niu_pci_probe_sprom(np);
9356 if (err)
9357 return err;
9358 }
9359 }
9360
9361 err = niu_probe_ports(np);
9362 if (err)
9363 return err;
9364
9365 niu_ldg_init(np);
9366
9367 niu_classifier_swstate_init(np);
9368 niu_link_config_init(np);
9369
9370 err = niu_determine_phy_disposition(np);
9371 if (!err)
9372 err = niu_init_link(np);
9373
9374 return err;
9375}
9376
9377static LIST_HEAD(niu_parent_list);
9378static DEFINE_MUTEX(niu_parent_lock);
9379static int niu_parent_index;
9380
9381static ssize_t show_port_phy(struct device *dev,
9382 struct device_attribute *attr, char *buf)
9383{
9384 struct platform_device *plat_dev = to_platform_device(dev);
9385 struct niu_parent *p = plat_dev->dev.platform_data;
9386 u32 port_phy = p->port_phy;
9387 char *orig_buf = buf;
9388 int i;
9389
9390 if (port_phy == PORT_PHY_UNKNOWN ||
9391 port_phy == PORT_PHY_INVALID)
9392 return 0;
9393
9394 for (i = 0; i < p->num_ports; i++) {
9395 const char *type_str;
9396 int type;
9397
9398 type = phy_decode(port_phy, i);
9399 if (type == PORT_TYPE_10G)
9400 type_str = "10G";
9401 else
9402 type_str = "1G";
9403 buf += sprintf(buf,
9404 (i == 0) ? "%s" : " %s",
9405 type_str);
9406 }
9407 buf += sprintf(buf, "\n");
9408 return buf - orig_buf;
9409}
9410
9411static ssize_t show_plat_type(struct device *dev,
9412 struct device_attribute *attr, char *buf)
9413{
9414 struct platform_device *plat_dev = to_platform_device(dev);
9415 struct niu_parent *p = plat_dev->dev.platform_data;
9416 const char *type_str;
9417
9418 switch (p->plat_type) {
9419 case PLAT_TYPE_ATLAS:
9420 type_str = "atlas";
9421 break;
9422 case PLAT_TYPE_NIU:
9423 type_str = "niu";
9424 break;
9425 case PLAT_TYPE_VF_P0:
9426 type_str = "vf_p0";
9427 break;
9428 case PLAT_TYPE_VF_P1:
9429 type_str = "vf_p1";
9430 break;
9431 default:
9432 type_str = "unknown";
9433 break;
9434 }
9435
9436 return sprintf(buf, "%s\n", type_str);
9437}
9438
9439static ssize_t __show_chan_per_port(struct device *dev,
9440 struct device_attribute *attr, char *buf,
9441 int rx)
9442{
9443 struct platform_device *plat_dev = to_platform_device(dev);
9444 struct niu_parent *p = plat_dev->dev.platform_data;
9445 char *orig_buf = buf;
9446 u8 *arr;
9447 int i;
9448
9449 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9450
9451 for (i = 0; i < p->num_ports; i++) {
9452 buf += sprintf(buf,
9453 (i == 0) ? "%d" : " %d",
9454 arr[i]);
9455 }
9456 buf += sprintf(buf, "\n");
9457
9458 return buf - orig_buf;
9459}
9460
9461static ssize_t show_rxchan_per_port(struct device *dev,
9462 struct device_attribute *attr, char *buf)
9463{
9464 return __show_chan_per_port(dev, attr, buf, 1);
9465}
9466
9467static ssize_t show_txchan_per_port(struct device *dev,
9468 struct device_attribute *attr, char *buf)
9469{
9470 return __show_chan_per_port(dev, attr, buf, 1);
9471}
9472
9473static ssize_t show_num_ports(struct device *dev,
9474 struct device_attribute *attr, char *buf)
9475{
9476 struct platform_device *plat_dev = to_platform_device(dev);
9477 struct niu_parent *p = plat_dev->dev.platform_data;
9478
9479 return sprintf(buf, "%d\n", p->num_ports);
9480}
9481
9482static struct device_attribute niu_parent_attributes[] = {
9483 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9484 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9485 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9486 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9487 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9488 {}
9489};
9490
9491static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9492 union niu_parent_id *id,
9493 u8 ptype)
9494{
9495 struct platform_device *plat_dev;
9496 struct niu_parent *p;
9497 int i;
9498
a769f496 9499 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
a3138df9 9500 NULL, 0);
58f3e0a8 9501 if (IS_ERR(plat_dev))
a3138df9
DM		 9502 return NULL;
9503
9504 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9505 int err = device_create_file(&plat_dev->dev,
9506 &niu_parent_attributes[i]);
9507 if (err)
9508 goto fail_unregister;
9509 }
9510
9511 p = kzalloc(sizeof(*p), GFP_KERNEL);
9512 if (!p)
9513 goto fail_unregister;
9514
9515 p->index = niu_parent_index++;
9516
9517 plat_dev->dev.platform_data = p;
9518 p->plat_dev = plat_dev;
9519
9520 memcpy(&p->id, id, sizeof(*id));
9521 p->plat_type = ptype;
9522 INIT_LIST_HEAD(&p->list);
9523 atomic_set(&p->refcnt, 0);
9524 list_add(&p->list, &niu_parent_list);
9525 spin_lock_init(&p->lock);
9526
9527 p->rxdma_clock_divider = 7500;
9528
9529 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9530 if (p->plat_type == PLAT_TYPE_NIU)
9531 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9532
9533 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9534 int index = i - CLASS_CODE_USER_PROG1;
9535
9536 p->tcam_key[index] = TCAM_KEY_TSEL;
9537 p->flow_key[index] = (FLOW_KEY_IPSA |
9538 FLOW_KEY_IPDA |
9539 FLOW_KEY_PROTO |
9540 (FLOW_KEY_L4_BYTE12 <<
9541 FLOW_KEY_L4_0_SHIFT) |
9542 (FLOW_KEY_L4_BYTE12 <<
9543 FLOW_KEY_L4_1_SHIFT));
9544 }
9545
9546 for (i = 0; i < LDN_MAX + 1; i++)
9547 p->ldg_map[i] = LDG_INVALID;
9548
9549 return p;
9550
9551fail_unregister:
9552 platform_device_unregister(plat_dev);
9553 return NULL;
9554}
9555
9556static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9557 union niu_parent_id *id,
9558 u8 ptype)
9559{
9560 struct niu_parent *p, *tmp;
9561 int port = np->port;
9562
a3138df9
DM		 9563 mutex_lock(&niu_parent_lock);
9564 p = NULL;
9565 list_for_each_entry(tmp, &niu_parent_list, list) {
9566 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9567 p = tmp;
9568 break;
9569 }
9570 }
9571 if (!p)
9572 p = niu_new_parent(np, id, ptype);
9573
9574 if (p) {
9575 char port_name[6];
9576 int err;
9577
9578 sprintf(port_name, "port%d", port);
9579 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9580 &np->device->kobj,
9581 port_name);
9582 if (!err) {
9583 p->ports[port] = np;
9584 atomic_inc(&p->refcnt);
9585 }
9586 }
9587 mutex_unlock(&niu_parent_lock);
9588
9589 return p;
9590}
9591
9592static void niu_put_parent(struct niu *np)
9593{
9594 struct niu_parent *p = np->parent;
9595 u8 port = np->port;
9596 char port_name[6];
9597
9598 BUG_ON(!p || p->ports[port] != np);
9599
f10a1f2e
JP		 9600 netif_printk(np, probe, KERN_DEBUG, np->dev,
9601 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9602
9603 sprintf(port_name, "port%d", port);
9604
9605 mutex_lock(&niu_parent_lock);
9606
9607 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9608
9609 p->ports[port] = NULL;
9610 np->parent = NULL;
9611
9612 if (atomic_dec_and_test(&p->refcnt)) {
9613 list_del(&p->list);
9614 platform_device_unregister(p->plat_dev);
9615 }
9616
9617 mutex_unlock(&niu_parent_lock);
9618}
9619
9620static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9621 u64 *handle, gfp_t flag)
9622{
9623 dma_addr_t dh;
9624 void *ret;
9625
9626 ret = dma_alloc_coherent(dev, size, &dh, flag);
9627 if (ret)
9628 *handle = dh;
9629 return ret;
9630}
9631
9632static void niu_pci_free_coherent(struct device *dev, size_t size,
9633 void *cpu_addr, u64 handle)
9634{
9635 dma_free_coherent(dev, size, cpu_addr, handle);
9636}
9637
9638static u64 niu_pci_map_page(struct device *dev, struct page *page,
9639 unsigned long offset, size_t size,
9640 enum dma_data_direction direction)
9641{
9642 return dma_map_page(dev, page, offset, size, direction);
9643}
9644
9645static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9646 size_t size, enum dma_data_direction direction)
9647{
a08b32df 9648 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9649}
9650
9651static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9652 size_t size,
9653 enum dma_data_direction direction)
9654{
9655 return dma_map_single(dev, cpu_addr, size, direction);
9656}
9657
9658static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9659 size_t size,
9660 enum dma_data_direction direction)
9661{
9662 dma_unmap_single(dev, dma_address, size, direction);
9663}
9664
9665static const struct niu_ops niu_pci_ops = {
9666 .alloc_coherent = niu_pci_alloc_coherent,
9667 .free_coherent = niu_pci_free_coherent,
9668 .map_page = niu_pci_map_page,
9669 .unmap_page = niu_pci_unmap_page,
9670 .map_single = niu_pci_map_single,
9671 .unmap_single = niu_pci_unmap_single,
9672};
9673
9674static void __devinit niu_driver_version(void)
9675{
9676 static int niu_version_printed;
9677
9678 if (niu_version_printed++ == 0)
9679 pr_info("%s", version);
9680}
9681
9682static struct net_device * __devinit niu_alloc_and_init(
9683 struct device *gen_dev, struct pci_dev *pdev,
2dc11581 9684 struct platform_device *op, const struct niu_ops *ops,
a3138df9
DM		 9685 u8 port)
9686{
b4c21639 9687 struct net_device *dev;
a3138df9
DM		 9688 struct niu *np;
9689
b4c21639 9690 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9691 if (!dev) {
f10a1f2e 9692 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9693 return NULL;
9694 }
9695
9696 SET_NETDEV_DEV(dev, gen_dev);
9697
9698 np = netdev_priv(dev);
9699 np->dev = dev;
9700 np->pdev = pdev;
9701 np->op = op;
9702 np->device = gen_dev;
9703 np->ops = ops;
9704
9705 np->msg_enable = niu_debug;
9706
9707 spin_lock_init(&np->lock);
9708 INIT_WORK(&np->reset_task, niu_reset_task);
9709
9710 np->port = port;
9711
9712 return dev;
9713}
9714
2c9171d4
SH		 9715static const struct net_device_ops niu_netdev_ops = {
9716 .ndo_open = niu_open,
9717 .ndo_stop = niu_close,
00829823 9718 .ndo_start_xmit = niu_start_xmit,
1a7a1032 9719 .ndo_get_stats64 = niu_get_stats,
01789349 9720 .ndo_set_rx_mode = niu_set_rx_mode,
2c9171d4
SH		 9721 .ndo_validate_addr = eth_validate_addr,
9722 .ndo_set_mac_address = niu_set_mac_addr,
9723 .ndo_do_ioctl = niu_ioctl,
9724 .ndo_tx_timeout = niu_tx_timeout,
9725 .ndo_change_mtu = niu_change_mtu,
9726};
9727
a3138df9
DM		 9728static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9729{
2c9171d4 9730 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9731 dev->ethtool_ops = &niu_ethtool_ops;
9732 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9733}
9734
9735static void __devinit niu_device_announce(struct niu *np)
9736{
9737 struct net_device *dev = np->dev;
a3138df9 9738
e174961c 9739 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9740
5fbd7e24
MW		 9741 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9742 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9743 dev->name,
9744 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9745 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9746 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9747 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9748 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9749 np->vpd.phy_type);
9750 } else {
9751 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9752 dev->name,
9753 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9754 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9755 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9756 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9757 "COPPER")),
5fbd7e24
MW		 9758 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9759 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9760 np->vpd.phy_type);
9761 }
a3138df9
DM		 9762}
9763
3cfa856d
DM		 9764static void __devinit niu_set_basic_features(struct net_device *dev)
9765{
3cd8ef4b
MM		 9766 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9767 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
3cfa856d
DM		 9768}
9769
a3138df9
DM		 9770static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9771 const struct pci_device_id *ent)
9772{
a3138df9
DM		 9773 union niu_parent_id parent_id;
9774 struct net_device *dev;
9775 struct niu *np;
9776 int err, pos;
9777 u64 dma_mask;
9778 u16 val16;
9779
9780 niu_driver_version();
9781
9782 err = pci_enable_device(pdev);
9783 if (err) {
f10a1f2e 9784 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9785 return err;
9786 }
9787
9788 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9789 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9790 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9791 err = -ENODEV;
9792 goto err_out_disable_pdev;
9793 }
9794
9795 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9796 if (err) {
f10a1f2e 9797 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9798 goto err_out_disable_pdev;
9799 }
9800
d3aa0cb4 9801 pos = pci_pcie_cap(pdev);
a3138df9 9802 if (pos <= 0) {
f10a1f2e 9803 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9804 goto err_out_free_res;
9805 }
9806
9807 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9808 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9809 if (!dev) {
9810 err = -ENOMEM;
9811 goto err_out_free_res;
9812 }
9813 np = netdev_priv(dev);
9814
9815 memset(&parent_id, 0, sizeof(parent_id));
9816 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9817 parent_id.pci.bus = pdev->bus->number;
9818 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9819
9820 np->parent = niu_get_parent(np, &parent_id,
9821 PLAT_TYPE_ATLAS);
9822 if (!np->parent) {
9823 err = -ENOMEM;
9824 goto err_out_free_dev;
9825 }
9826
9827 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9828 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9829 val16 |= (PCI_EXP_DEVCTL_CERE |
9830 PCI_EXP_DEVCTL_NFERE |
9831 PCI_EXP_DEVCTL_FERE |
9832 PCI_EXP_DEVCTL_URRE |
9833 PCI_EXP_DEVCTL_RELAX_EN);
9834 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9835
8cbd9623 9836 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9837 err = pci_set_dma_mask(pdev, dma_mask);
9838 if (!err) {
9839 dev->features |= NETIF_F_HIGHDMA;
9840 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9841 if (err) {
f10a1f2e 9842 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9843 goto err_out_release_parent;
9844 }
9845 }
284901a9
YH		 9846 if (err || dma_mask == DMA_BIT_MASK(32)) {
9847 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9848 if (err) {
f10a1f2e 9849 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9850 goto err_out_release_parent;
9851 }
9852 }
9853
3cfa856d 9854 niu_set_basic_features(dev);
a3138df9 9855
01789349
JP		 9856 dev->priv_flags |= IFF_UNICAST_FLT;
9857
19ecb6ba 9858 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9859 if (!np->regs) {
f10a1f2e 9860 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9861 err = -ENOMEM;
9862 goto err_out_release_parent;
9863 }
9864
9865 pci_set_master(pdev);
9866 pci_save_state(pdev);
9867
9868 dev->irq = pdev->irq;
9869
9870 niu_assign_netdev_ops(dev);
9871
9872 err = niu_get_invariants(np);
9873 if (err) {
9874 if (err != -ENODEV)
f10a1f2e 9875 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9876 goto err_out_iounmap;
9877 }
9878
9879 err = register_netdev(dev);
9880 if (err) {
f10a1f2e 9881 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9882 goto err_out_iounmap;
9883 }
9884
9885 pci_set_drvdata(pdev, dev);
9886
9887 niu_device_announce(np);
9888
9889 return 0;
9890
9891err_out_iounmap:
9892 if (np->regs) {
9893 iounmap(np->regs);
9894 np->regs = NULL;
9895 }
9896
9897err_out_release_parent:
9898 niu_put_parent(np);
9899
9900err_out_free_dev:
9901 free_netdev(dev);
9902
9903err_out_free_res:
9904 pci_release_regions(pdev);
9905
9906err_out_disable_pdev:
9907 pci_disable_device(pdev);
9908 pci_set_drvdata(pdev, NULL);
9909
9910 return err;
9911}
9912
9913static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9914{
9915 struct net_device *dev = pci_get_drvdata(pdev);
9916
9917 if (dev) {
9918 struct niu *np = netdev_priv(dev);
9919
9920 unregister_netdev(dev);
9921 if (np->regs) {
9922 iounmap(np->regs);
9923 np->regs = NULL;
9924 }
9925
9926 niu_ldg_free(np);
9927
9928 niu_put_parent(np);
9929
9930 free_netdev(dev);
9931 pci_release_regions(pdev);
9932 pci_disable_device(pdev);
9933 pci_set_drvdata(pdev, NULL);
9934 }
9935}
9936
9937static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9938{
9939 struct net_device *dev = pci_get_drvdata(pdev);
9940 struct niu *np = netdev_priv(dev);
9941 unsigned long flags;
9942
9943 if (!netif_running(dev))
9944 return 0;
9945
23f333a2 9946 flush_work_sync(&np->reset_task);
a3138df9
DM		 9947 niu_netif_stop(np);
9948
9949 del_timer_sync(&np->timer);
9950
9951 spin_lock_irqsave(&np->lock, flags);
9952 niu_enable_interrupts(np, 0);
9953 spin_unlock_irqrestore(&np->lock, flags);
9954
9955 netif_device_detach(dev);
9956
9957 spin_lock_irqsave(&np->lock, flags);
9958 niu_stop_hw(np);
9959 spin_unlock_irqrestore(&np->lock, flags);
9960
9961 pci_save_state(pdev);
9962
9963 return 0;
9964}
9965
9966static int niu_resume(struct pci_dev *pdev)
9967{
9968 struct net_device *dev = pci_get_drvdata(pdev);
9969 struct niu *np = netdev_priv(dev);
9970 unsigned long flags;
9971 int err;
9972
9973 if (!netif_running(dev))
9974 return 0;
9975
9976 pci_restore_state(pdev);
9977
9978 netif_device_attach(dev);
9979
9980 spin_lock_irqsave(&np->lock, flags);
9981
9982 err = niu_init_hw(np);
9983 if (!err) {
9984 np->timer.expires = jiffies + HZ;
9985 add_timer(&np->timer);
9986 niu_netif_start(np);
9987 }
9988
9989 spin_unlock_irqrestore(&np->lock, flags);
9990
9991 return err;
9992}
9993
9994static struct pci_driver niu_pci_driver = {
9995 .name = DRV_MODULE_NAME,
9996 .id_table = niu_pci_tbl,
9997 .probe = niu_pci_init_one,
9998 .remove = __devexit_p(niu_pci_remove_one),
9999 .suspend = niu_suspend,
10000 .resume = niu_resume,
10001};
10002
10003#ifdef CONFIG_SPARC64
10004static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10005 u64 *dma_addr, gfp_t flag)
10006{
10007 unsigned long order = get_order(size);
10008 unsigned long page = __get_free_pages(flag, order);
10009
10010 if (page == 0UL)
10011 return NULL;
10012 memset((char *)page, 0, PAGE_SIZE << order);
10013 *dma_addr = __pa(page);
10014
10015 return (void *) page;
10016}
10017
10018static void niu_phys_free_coherent(struct device *dev, size_t size,
10019 void *cpu_addr, u64 handle)
10020{
10021 unsigned long order = get_order(size);
10022
10023 free_pages((unsigned long) cpu_addr, order);
10024}
10025
10026static u64 niu_phys_map_page(struct device *dev, struct page *page,
10027 unsigned long offset, size_t size,
10028 enum dma_data_direction direction)
10029{
10030 return page_to_phys(page) + offset;
10031}
10032
10033static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10034 size_t size, enum dma_data_direction direction)
10035{
10036 /* Nothing to do. */
10037}
10038
10039static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10040 size_t size,
10041 enum dma_data_direction direction)
10042{
10043 return __pa(cpu_addr);
10044}
10045
10046static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10047 size_t size,
10048 enum dma_data_direction direction)
10049{
10050 /* Nothing to do. */
10051}
10052
10053static const struct niu_ops niu_phys_ops = {
10054 .alloc_coherent = niu_phys_alloc_coherent,
10055 .free_coherent = niu_phys_free_coherent,
10056 .map_page = niu_phys_map_page,
10057 .unmap_page = niu_phys_unmap_page,
10058 .map_single = niu_phys_map_single,
10059 .unmap_single = niu_phys_unmap_single,
10060};
10061
74888760 10062static int __devinit niu_of_probe(struct platform_device *op)
a3138df9
DM		 10063{
10064 union niu_parent_id parent_id;
10065 struct net_device *dev;
10066 struct niu *np;
10067 const u32 *reg;
10068 int err;
10069
10070 niu_driver_version();
10071
61c7a080 10072 reg = of_get_property(op->dev.of_node, "reg", NULL);
a3138df9 10073 if (!reg) {
f10a1f2e 10074 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
61c7a080 10075 op->dev.of_node->full_name);
a3138df9
DM		 10076 return -ENODEV;
10077 }
10078
10079 dev = niu_alloc_and_init(&op->dev, NULL, op,
10080 &niu_phys_ops, reg[0] & 0x1);
10081 if (!dev) {
10082 err = -ENOMEM;
10083 goto err_out;
10084 }
10085 np = netdev_priv(dev);
10086
10087 memset(&parent_id, 0, sizeof(parent_id));
61c7a080 10088 parent_id.of = of_get_parent(op->dev.of_node);
a3138df9
DM		 10089
10090 np->parent = niu_get_parent(np, &parent_id,
10091 PLAT_TYPE_NIU);
10092 if (!np->parent) {
10093 err = -ENOMEM;
10094 goto err_out_free_dev;
10095 }
10096
3cfa856d 10097 niu_set_basic_features(dev);
a3138df9
DM		 10098
10099 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10100 resource_size(&op->resource[1]),
a3138df9
DM		 10101 "niu regs");
10102 if (!np->regs) {
f10a1f2e 10103 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10104 err = -ENOMEM;
10105 goto err_out_release_parent;
10106 }
10107
10108 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10109 resource_size(&op->resource[2]),
a3138df9
DM		 10110 "niu vregs-1");
10111 if (!np->vir_regs_1) {
f10a1f2e 10112 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10113 err = -ENOMEM;
10114 goto err_out_iounmap;
10115 }
10116
10117 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10118 resource_size(&op->resource[3]),
a3138df9
DM		 10119 "niu vregs-2");
10120 if (!np->vir_regs_2) {
f10a1f2e 10121 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10122 err = -ENOMEM;
10123 goto err_out_iounmap;
10124 }
10125
10126 niu_assign_netdev_ops(dev);
10127
10128 err = niu_get_invariants(np);
10129 if (err) {
10130 if (err != -ENODEV)
f10a1f2e 10131 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10132 goto err_out_iounmap;
10133 }
10134
10135 err = register_netdev(dev);
10136 if (err) {
f10a1f2e 10137 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10138 goto err_out_iounmap;
10139 }
10140
10141 dev_set_drvdata(&op->dev, dev);
10142
10143 niu_device_announce(np);
10144
10145 return 0;
10146
10147err_out_iounmap:
10148 if (np->vir_regs_1) {
10149 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10150 resource_size(&op->resource[2]));
a3138df9
DM		 10151 np->vir_regs_1 = NULL;
10152 }
10153
10154 if (np->vir_regs_2) {
10155 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10156 resource_size(&op->resource[3]));
a3138df9
DM		 10157 np->vir_regs_2 = NULL;
10158 }
10159
10160 if (np->regs) {
10161 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10162 resource_size(&op->resource[1]));
a3138df9
DM		 10163 np->regs = NULL;
10164 }
10165
10166err_out_release_parent:
10167 niu_put_parent(np);
10168
10169err_out_free_dev:
10170 free_netdev(dev);
10171
10172err_out:
10173 return err;
10174}
10175
2dc11581 10176static int __devexit niu_of_remove(struct platform_device *op)
a3138df9
DM		 10177{
10178 struct net_device *dev = dev_get_drvdata(&op->dev);
10179
10180 if (dev) {
10181 struct niu *np = netdev_priv(dev);
10182
10183 unregister_netdev(dev);
10184
10185 if (np->vir_regs_1) {
10186 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10187 resource_size(&op->resource[2]));
a3138df9
DM		 10188 np->vir_regs_1 = NULL;
10189 }
10190
10191 if (np->vir_regs_2) {
10192 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10193 resource_size(&op->resource[3]));
a3138df9
DM		 10194 np->vir_regs_2 = NULL;
10195 }
10196
10197 if (np->regs) {
10198 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10199 resource_size(&op->resource[1]));
a3138df9
DM		 10200 np->regs = NULL;
10201 }
10202
10203 niu_ldg_free(np);
10204
10205 niu_put_parent(np);
10206
10207 free_netdev(dev);
10208 dev_set_drvdata(&op->dev, NULL);
10209 }
10210 return 0;
10211}
10212
fd098316 10213static const struct of_device_id niu_match[] = {
a3138df9
DM		 10214 {
10215 .name = "network",
10216 .compatible = "SUNW,niusl",
10217 },
10218 {},
10219};
10220MODULE_DEVICE_TABLE(of, niu_match);
10221
74888760 10222static struct platform_driver niu_of_driver = {
4018294b
GL		 10223 .driver = {
10224 .name = "niu",
10225 .owner = THIS_MODULE,
10226 .of_match_table = niu_match,
10227 },
a3138df9
DM		 10228 .probe = niu_of_probe,
10229 .remove = __devexit_p(niu_of_remove),
10230};
10231
10232#endif /* CONFIG_SPARC64 */
10233
10234static int __init niu_init(void)
10235{
10236 int err = 0;
10237
81429973 10238 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10239
10240 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10241
10242#ifdef CONFIG_SPARC64
74888760 10243 err = platform_driver_register(&niu_of_driver);
a3138df9
DM		 10244#endif
10245
10246 if (!err) {
10247 err = pci_register_driver(&niu_pci_driver);
10248#ifdef CONFIG_SPARC64
10249 if (err)
74888760 10250 platform_driver_unregister(&niu_of_driver);
a3138df9
DM		 10251#endif
10252 }
10253
10254 return err;
10255}
10256
10257static void __exit niu_exit(void)
10258{
10259 pci_unregister_driver(&niu_pci_driver);
10260#ifdef CONFIG_SPARC64
74888760 10261 platform_driver_unregister(&niu_of_driver);
a3138df9
DM		 10262#endif
10263}
10264
10265module_init(niu_init);
10266module_exit(niu_exit);
Linux kernel - Deliverables
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