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df828598 M |
1 | /* |
2 | * Texas Instruments Ethernet Switch Driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/timer.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/irqreturn.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/netdevice.h> | |
2e5b38ab | 27 | #include <linux/net_tstamp.h> |
df828598 M |
28 | #include <linux/phy.h> |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/delay.h> | |
f150bd7f | 31 | #include <linux/pm_runtime.h> |
2eb32b0a M |
32 | #include <linux/of.h> |
33 | #include <linux/of_net.h> | |
34 | #include <linux/of_device.h> | |
3b72c2fe | 35 | #include <linux/if_vlan.h> |
df828598 M |
36 | |
37 | #include <linux/platform_data/cpsw.h> | |
739683b4 | 38 | #include <linux/pinctrl/consumer.h> |
df828598 M |
39 | |
40 | #include "cpsw_ale.h" | |
2e5b38ab | 41 | #include "cpts.h" |
df828598 M |
42 | #include "davinci_cpdma.h" |
43 | ||
44 | #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ | |
45 | NETIF_MSG_DRV | NETIF_MSG_LINK | \ | |
46 | NETIF_MSG_IFUP | NETIF_MSG_INTR | \ | |
47 | NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ | |
48 | NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ | |
49 | NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ | |
50 | NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ | |
51 | NETIF_MSG_RX_STATUS) | |
52 | ||
53 | #define cpsw_info(priv, type, format, ...) \ | |
54 | do { \ | |
55 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
56 | dev_info(priv->dev, format, ## __VA_ARGS__); \ | |
57 | } while (0) | |
58 | ||
59 | #define cpsw_err(priv, type, format, ...) \ | |
60 | do { \ | |
61 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
62 | dev_err(priv->dev, format, ## __VA_ARGS__); \ | |
63 | } while (0) | |
64 | ||
65 | #define cpsw_dbg(priv, type, format, ...) \ | |
66 | do { \ | |
67 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
68 | dev_dbg(priv->dev, format, ## __VA_ARGS__); \ | |
69 | } while (0) | |
70 | ||
71 | #define cpsw_notice(priv, type, format, ...) \ | |
72 | do { \ | |
73 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
74 | dev_notice(priv->dev, format, ## __VA_ARGS__); \ | |
75 | } while (0) | |
76 | ||
5c50a856 M |
77 | #define ALE_ALL_PORTS 0x7 |
78 | ||
df828598 M |
79 | #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) |
80 | #define CPSW_MINOR_VERSION(reg) (reg & 0xff) | |
81 | #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) | |
82 | ||
e90cfac6 RC |
83 | #define CPSW_VERSION_1 0x19010a |
84 | #define CPSW_VERSION_2 0x19010c | |
549985ee RC |
85 | |
86 | #define HOST_PORT_NUM 0 | |
87 | #define SLIVER_SIZE 0x40 | |
88 | ||
89 | #define CPSW1_HOST_PORT_OFFSET 0x028 | |
90 | #define CPSW1_SLAVE_OFFSET 0x050 | |
91 | #define CPSW1_SLAVE_SIZE 0x040 | |
92 | #define CPSW1_CPDMA_OFFSET 0x100 | |
93 | #define CPSW1_STATERAM_OFFSET 0x200 | |
94 | #define CPSW1_CPTS_OFFSET 0x500 | |
95 | #define CPSW1_ALE_OFFSET 0x600 | |
96 | #define CPSW1_SLIVER_OFFSET 0x700 | |
97 | ||
98 | #define CPSW2_HOST_PORT_OFFSET 0x108 | |
99 | #define CPSW2_SLAVE_OFFSET 0x200 | |
100 | #define CPSW2_SLAVE_SIZE 0x100 | |
101 | #define CPSW2_CPDMA_OFFSET 0x800 | |
102 | #define CPSW2_STATERAM_OFFSET 0xa00 | |
103 | #define CPSW2_CPTS_OFFSET 0xc00 | |
104 | #define CPSW2_ALE_OFFSET 0xd00 | |
105 | #define CPSW2_SLIVER_OFFSET 0xd80 | |
106 | #define CPSW2_BD_OFFSET 0x2000 | |
107 | ||
df828598 M |
108 | #define CPDMA_RXTHRESH 0x0c0 |
109 | #define CPDMA_RXFREE 0x0e0 | |
110 | #define CPDMA_TXHDP 0x00 | |
111 | #define CPDMA_RXHDP 0x20 | |
112 | #define CPDMA_TXCP 0x40 | |
113 | #define CPDMA_RXCP 0x60 | |
114 | ||
df828598 M |
115 | #define CPSW_POLL_WEIGHT 64 |
116 | #define CPSW_MIN_PACKET_SIZE 60 | |
117 | #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) | |
118 | ||
119 | #define RX_PRIORITY_MAPPING 0x76543210 | |
120 | #define TX_PRIORITY_MAPPING 0x33221100 | |
121 | #define CPDMA_TX_PRIORITY_MAP 0x76543210 | |
122 | ||
3b72c2fe M |
123 | #define CPSW_VLAN_AWARE BIT(1) |
124 | #define CPSW_ALE_VLAN_AWARE 1 | |
125 | ||
d9ba8f9e M |
126 | #define CPSW_FIFO_NORMAL_MODE (0 << 15) |
127 | #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) | |
128 | #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) | |
129 | ||
ff5b8ef2 M |
130 | #define CPSW_INTPACEEN (0x3f << 16) |
131 | #define CPSW_INTPRESCALE_MASK (0x7FF << 0) | |
132 | #define CPSW_CMINTMAX_CNT 63 | |
133 | #define CPSW_CMINTMIN_CNT 2 | |
134 | #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) | |
135 | #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) | |
136 | ||
df828598 M |
137 | #define cpsw_enable_irq(priv) \ |
138 | do { \ | |
139 | u32 i; \ | |
140 | for (i = 0; i < priv->num_irqs; i++) \ | |
141 | enable_irq(priv->irqs_table[i]); \ | |
142 | } while (0); | |
143 | #define cpsw_disable_irq(priv) \ | |
144 | do { \ | |
145 | u32 i; \ | |
146 | for (i = 0; i < priv->num_irqs; i++) \ | |
147 | disable_irq_nosync(priv->irqs_table[i]); \ | |
148 | } while (0); | |
149 | ||
d3bb9c58 M |
150 | #define cpsw_slave_index(priv) \ |
151 | ((priv->data.dual_emac) ? priv->emac_port : \ | |
152 | priv->data.active_slave) | |
153 | ||
df828598 M |
154 | static int debug_level; |
155 | module_param(debug_level, int, 0); | |
156 | MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); | |
157 | ||
158 | static int ale_ageout = 10; | |
159 | module_param(ale_ageout, int, 0); | |
160 | MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); | |
161 | ||
162 | static int rx_packet_max = CPSW_MAX_PACKET_SIZE; | |
163 | module_param(rx_packet_max, int, 0); | |
164 | MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); | |
165 | ||
996a5c27 | 166 | struct cpsw_wr_regs { |
df828598 M |
167 | u32 id_ver; |
168 | u32 soft_reset; | |
169 | u32 control; | |
170 | u32 int_control; | |
171 | u32 rx_thresh_en; | |
172 | u32 rx_en; | |
173 | u32 tx_en; | |
174 | u32 misc_en; | |
ff5b8ef2 M |
175 | u32 mem_allign1[8]; |
176 | u32 rx_thresh_stat; | |
177 | u32 rx_stat; | |
178 | u32 tx_stat; | |
179 | u32 misc_stat; | |
180 | u32 mem_allign2[8]; | |
181 | u32 rx_imax; | |
182 | u32 tx_imax; | |
183 | ||
df828598 M |
184 | }; |
185 | ||
996a5c27 | 186 | struct cpsw_ss_regs { |
df828598 M |
187 | u32 id_ver; |
188 | u32 control; | |
189 | u32 soft_reset; | |
190 | u32 stat_port_en; | |
191 | u32 ptype; | |
bd357af2 RC |
192 | u32 soft_idle; |
193 | u32 thru_rate; | |
194 | u32 gap_thresh; | |
195 | u32 tx_start_wds; | |
196 | u32 flow_control; | |
197 | u32 vlan_ltype; | |
198 | u32 ts_ltype; | |
199 | u32 dlr_ltype; | |
df828598 M |
200 | }; |
201 | ||
9750a3ad RC |
202 | /* CPSW_PORT_V1 */ |
203 | #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ | |
204 | #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ | |
205 | #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ | |
206 | #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ | |
207 | #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ | |
208 | #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ | |
209 | #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ | |
210 | #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ | |
211 | ||
212 | /* CPSW_PORT_V2 */ | |
213 | #define CPSW2_CONTROL 0x00 /* Control Register */ | |
214 | #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ | |
215 | #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ | |
216 | #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ | |
217 | #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ | |
218 | #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ | |
219 | #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ | |
220 | ||
221 | /* CPSW_PORT_V1 and V2 */ | |
222 | #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ | |
223 | #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ | |
224 | #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ | |
225 | ||
226 | /* CPSW_PORT_V2 only */ | |
227 | #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ | |
228 | #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ | |
229 | #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ | |
230 | #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ | |
231 | #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ | |
232 | #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ | |
233 | #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ | |
234 | #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ | |
235 | ||
236 | /* Bit definitions for the CPSW2_CONTROL register */ | |
237 | #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ | |
238 | #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ | |
239 | #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ | |
240 | #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ | |
241 | #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ | |
242 | #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ | |
243 | #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ | |
244 | #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ | |
245 | #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ | |
246 | #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ | |
247 | #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ | |
248 | #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ | |
249 | #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ | |
250 | #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ | |
251 | #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ | |
252 | #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ | |
253 | ||
254 | #define CTRL_TS_BITS \ | |
255 | (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ | |
256 | TS_ANNEX_D_EN | TS_LTYPE1_EN) | |
257 | ||
258 | #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) | |
259 | #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) | |
260 | #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) | |
261 | ||
262 | /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ | |
263 | #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ | |
264 | #define TS_SEQ_ID_OFFSET_MASK (0x3f) | |
265 | #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ | |
266 | #define TS_MSG_TYPE_EN_MASK (0xffff) | |
267 | ||
268 | /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ | |
269 | #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) | |
df828598 | 270 | |
2e5b38ab RC |
271 | /* Bit definitions for the CPSW1_TS_CTL register */ |
272 | #define CPSW_V1_TS_RX_EN BIT(0) | |
273 | #define CPSW_V1_TS_TX_EN BIT(4) | |
274 | #define CPSW_V1_MSG_TYPE_OFS 16 | |
275 | ||
276 | /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ | |
277 | #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 | |
278 | ||
df828598 M |
279 | struct cpsw_host_regs { |
280 | u32 max_blks; | |
281 | u32 blk_cnt; | |
d9ba8f9e | 282 | u32 tx_in_ctl; |
df828598 M |
283 | u32 port_vlan; |
284 | u32 tx_pri_map; | |
285 | u32 cpdma_tx_pri_map; | |
286 | u32 cpdma_rx_chan_map; | |
287 | }; | |
288 | ||
289 | struct cpsw_sliver_regs { | |
290 | u32 id_ver; | |
291 | u32 mac_control; | |
292 | u32 mac_status; | |
293 | u32 soft_reset; | |
294 | u32 rx_maxlen; | |
295 | u32 __reserved_0; | |
296 | u32 rx_pause; | |
297 | u32 tx_pause; | |
298 | u32 __reserved_1; | |
299 | u32 rx_pri_map; | |
300 | }; | |
301 | ||
302 | struct cpsw_slave { | |
9750a3ad | 303 | void __iomem *regs; |
df828598 M |
304 | struct cpsw_sliver_regs __iomem *sliver; |
305 | int slave_num; | |
306 | u32 mac_control; | |
307 | struct cpsw_slave_data *data; | |
308 | struct phy_device *phy; | |
d9ba8f9e M |
309 | struct net_device *ndev; |
310 | u32 port_vlan; | |
311 | u32 open_stat; | |
df828598 M |
312 | }; |
313 | ||
9750a3ad RC |
314 | static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) |
315 | { | |
316 | return __raw_readl(slave->regs + offset); | |
317 | } | |
318 | ||
319 | static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) | |
320 | { | |
321 | __raw_writel(val, slave->regs + offset); | |
322 | } | |
323 | ||
df828598 M |
324 | struct cpsw_priv { |
325 | spinlock_t lock; | |
326 | struct platform_device *pdev; | |
327 | struct net_device *ndev; | |
328 | struct resource *cpsw_res; | |
a65dd5b2 | 329 | struct resource *cpsw_wr_res; |
df828598 M |
330 | struct napi_struct napi; |
331 | struct device *dev; | |
332 | struct cpsw_platform_data data; | |
996a5c27 RC |
333 | struct cpsw_ss_regs __iomem *regs; |
334 | struct cpsw_wr_regs __iomem *wr_regs; | |
df828598 M |
335 | struct cpsw_host_regs __iomem *host_port_regs; |
336 | u32 msg_enable; | |
e90cfac6 | 337 | u32 version; |
ff5b8ef2 M |
338 | u32 coal_intvl; |
339 | u32 bus_freq_mhz; | |
df828598 M |
340 | struct net_device_stats stats; |
341 | int rx_packet_max; | |
342 | int host_port; | |
343 | struct clk *clk; | |
344 | u8 mac_addr[ETH_ALEN]; | |
345 | struct cpsw_slave *slaves; | |
346 | struct cpdma_ctlr *dma; | |
347 | struct cpdma_chan *txch, *rxch; | |
348 | struct cpsw_ale *ale; | |
349 | /* snapshot of IRQ numbers */ | |
350 | u32 irqs_table[4]; | |
351 | u32 num_irqs; | |
a11fbba9 | 352 | bool irq_enabled; |
9232b16d | 353 | struct cpts *cpts; |
d9ba8f9e | 354 | u32 emac_port; |
df828598 M |
355 | }; |
356 | ||
357 | #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) | |
d9ba8f9e M |
358 | #define for_each_slave(priv, func, arg...) \ |
359 | do { \ | |
6e6ceaed SS |
360 | struct cpsw_slave *slave; \ |
361 | int n; \ | |
d9ba8f9e M |
362 | if (priv->data.dual_emac) \ |
363 | (func)((priv)->slaves + priv->emac_port, ##arg);\ | |
364 | else \ | |
6e6ceaed SS |
365 | for (n = (priv)->data.slaves, \ |
366 | slave = (priv)->slaves; \ | |
367 | n; n--) \ | |
368 | (func)(slave++, ##arg); \ | |
d9ba8f9e M |
369 | } while (0) |
370 | #define cpsw_get_slave_ndev(priv, __slave_no__) \ | |
371 | (priv->slaves[__slave_no__].ndev) | |
372 | #define cpsw_get_slave_priv(priv, __slave_no__) \ | |
373 | ((priv->slaves[__slave_no__].ndev) ? \ | |
374 | netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ | |
375 | ||
376 | #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ | |
377 | do { \ | |
378 | if (!priv->data.dual_emac) \ | |
379 | break; \ | |
380 | if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ | |
381 | ndev = cpsw_get_slave_ndev(priv, 0); \ | |
382 | priv = netdev_priv(ndev); \ | |
383 | skb->dev = ndev; \ | |
384 | } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ | |
385 | ndev = cpsw_get_slave_ndev(priv, 1); \ | |
386 | priv = netdev_priv(ndev); \ | |
387 | skb->dev = ndev; \ | |
388 | } \ | |
df828598 | 389 | } while (0) |
d9ba8f9e M |
390 | #define cpsw_add_mcast(priv, addr) \ |
391 | do { \ | |
392 | if (priv->data.dual_emac) { \ | |
393 | struct cpsw_slave *slave = priv->slaves + \ | |
394 | priv->emac_port; \ | |
395 | int slave_port = cpsw_get_slave_port(priv, \ | |
396 | slave->slave_num); \ | |
397 | cpsw_ale_add_mcast(priv->ale, addr, \ | |
398 | 1 << slave_port | 1 << priv->host_port, \ | |
399 | ALE_VLAN, slave->port_vlan, 0); \ | |
400 | } else { \ | |
401 | cpsw_ale_add_mcast(priv->ale, addr, \ | |
402 | ALE_ALL_PORTS << priv->host_port, \ | |
403 | 0, 0, 0); \ | |
404 | } \ | |
405 | } while (0) | |
406 | ||
407 | static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) | |
408 | { | |
409 | if (priv->host_port == 0) | |
410 | return slave_num + 1; | |
411 | else | |
412 | return slave_num; | |
413 | } | |
df828598 | 414 | |
5c50a856 M |
415 | static void cpsw_ndo_set_rx_mode(struct net_device *ndev) |
416 | { | |
417 | struct cpsw_priv *priv = netdev_priv(ndev); | |
418 | ||
419 | if (ndev->flags & IFF_PROMISC) { | |
420 | /* Enable promiscuous mode */ | |
421 | dev_err(priv->dev, "Ignoring Promiscuous mode\n"); | |
422 | return; | |
423 | } | |
424 | ||
425 | /* Clear all mcast from ALE */ | |
426 | cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); | |
427 | ||
428 | if (!netdev_mc_empty(ndev)) { | |
429 | struct netdev_hw_addr *ha; | |
430 | ||
431 | /* program multicast address list into ALE register */ | |
432 | netdev_for_each_mc_addr(ha, ndev) { | |
d9ba8f9e | 433 | cpsw_add_mcast(priv, (u8 *)ha->addr); |
5c50a856 M |
434 | } |
435 | } | |
436 | } | |
437 | ||
df828598 M |
438 | static void cpsw_intr_enable(struct cpsw_priv *priv) |
439 | { | |
996a5c27 RC |
440 | __raw_writel(0xFF, &priv->wr_regs->tx_en); |
441 | __raw_writel(0xFF, &priv->wr_regs->rx_en); | |
df828598 M |
442 | |
443 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
444 | return; | |
445 | } | |
446 | ||
447 | static void cpsw_intr_disable(struct cpsw_priv *priv) | |
448 | { | |
996a5c27 RC |
449 | __raw_writel(0, &priv->wr_regs->tx_en); |
450 | __raw_writel(0, &priv->wr_regs->rx_en); | |
df828598 M |
451 | |
452 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
453 | return; | |
454 | } | |
455 | ||
456 | void cpsw_tx_handler(void *token, int len, int status) | |
457 | { | |
458 | struct sk_buff *skb = token; | |
459 | struct net_device *ndev = skb->dev; | |
460 | struct cpsw_priv *priv = netdev_priv(ndev); | |
461 | ||
fae50823 M |
462 | /* Check whether the queue is stopped due to stalled tx dma, if the |
463 | * queue is stopped then start the queue as we have free desc for tx | |
464 | */ | |
df828598 | 465 | if (unlikely(netif_queue_stopped(ndev))) |
b56d6b3f | 466 | netif_wake_queue(ndev); |
9232b16d | 467 | cpts_tx_timestamp(priv->cpts, skb); |
df828598 M |
468 | priv->stats.tx_packets++; |
469 | priv->stats.tx_bytes += len; | |
470 | dev_kfree_skb_any(skb); | |
471 | } | |
472 | ||
473 | void cpsw_rx_handler(void *token, int len, int status) | |
474 | { | |
475 | struct sk_buff *skb = token; | |
b4727e69 | 476 | struct sk_buff *new_skb; |
df828598 M |
477 | struct net_device *ndev = skb->dev; |
478 | struct cpsw_priv *priv = netdev_priv(ndev); | |
479 | int ret = 0; | |
480 | ||
d9ba8f9e M |
481 | cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); |
482 | ||
b4727e69 SS |
483 | if (unlikely(status < 0)) { |
484 | /* the interface is going down, skbs are purged */ | |
df828598 M |
485 | dev_kfree_skb_any(skb); |
486 | return; | |
487 | } | |
b4727e69 SS |
488 | |
489 | new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); | |
490 | if (new_skb) { | |
df828598 | 491 | skb_put(skb, len); |
9232b16d | 492 | cpts_rx_timestamp(priv->cpts, skb); |
df828598 M |
493 | skb->protocol = eth_type_trans(skb, ndev); |
494 | netif_receive_skb(skb); | |
495 | priv->stats.rx_bytes += len; | |
496 | priv->stats.rx_packets++; | |
b4727e69 SS |
497 | } else { |
498 | priv->stats.rx_dropped++; | |
499 | new_skb = skb; | |
df828598 M |
500 | } |
501 | ||
b4727e69 SS |
502 | ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, |
503 | skb_tailroom(new_skb), 0); | |
504 | if (WARN_ON(ret < 0)) | |
505 | dev_kfree_skb_any(new_skb); | |
df828598 M |
506 | } |
507 | ||
508 | static irqreturn_t cpsw_interrupt(int irq, void *dev_id) | |
509 | { | |
510 | struct cpsw_priv *priv = dev_id; | |
fd51cf19 | 511 | u32 rx, tx, rx_thresh; |
df828598 | 512 | |
fd51cf19 SS |
513 | rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat); |
514 | rx = __raw_readl(&priv->wr_regs->rx_stat); | |
515 | tx = __raw_readl(&priv->wr_regs->tx_stat); | |
516 | if (!rx_thresh && !rx && !tx) | |
517 | return IRQ_NONE; | |
518 | ||
519 | cpsw_intr_disable(priv); | |
a11fbba9 SS |
520 | if (priv->irq_enabled == true) { |
521 | cpsw_disable_irq(priv); | |
522 | priv->irq_enabled = false; | |
523 | } | |
fd51cf19 SS |
524 | |
525 | if (netif_running(priv->ndev)) { | |
df828598 | 526 | napi_schedule(&priv->napi); |
fd51cf19 SS |
527 | return IRQ_HANDLED; |
528 | } | |
529 | ||
530 | priv = cpsw_get_slave_priv(priv, 1); | |
531 | if (!priv) | |
532 | return IRQ_NONE; | |
533 | ||
534 | if (netif_running(priv->ndev)) { | |
535 | napi_schedule(&priv->napi); | |
536 | return IRQ_HANDLED; | |
df828598 | 537 | } |
fd51cf19 | 538 | return IRQ_NONE; |
df828598 M |
539 | } |
540 | ||
df828598 M |
541 | static int cpsw_poll(struct napi_struct *napi, int budget) |
542 | { | |
543 | struct cpsw_priv *priv = napi_to_priv(napi); | |
544 | int num_tx, num_rx; | |
545 | ||
546 | num_tx = cpdma_chan_process(priv->txch, 128); | |
510a1e72 M |
547 | if (num_tx) |
548 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
df828598 | 549 | |
510a1e72 | 550 | num_rx = cpdma_chan_process(priv->rxch, budget); |
df828598 | 551 | if (num_rx < budget) { |
a11fbba9 SS |
552 | struct cpsw_priv *prim_cpsw; |
553 | ||
df828598 M |
554 | napi_complete(napi); |
555 | cpsw_intr_enable(priv); | |
510a1e72 | 556 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
a11fbba9 SS |
557 | prim_cpsw = cpsw_get_slave_priv(priv, 0); |
558 | if (prim_cpsw->irq_enabled == false) { | |
a11fbba9 | 559 | prim_cpsw->irq_enabled = true; |
af5c6df7 | 560 | cpsw_enable_irq(priv); |
a11fbba9 | 561 | } |
df828598 M |
562 | } |
563 | ||
510a1e72 M |
564 | if (num_rx || num_tx) |
565 | cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", | |
566 | num_rx, num_tx); | |
567 | ||
df828598 M |
568 | return num_rx; |
569 | } | |
570 | ||
571 | static inline void soft_reset(const char *module, void __iomem *reg) | |
572 | { | |
573 | unsigned long timeout = jiffies + HZ; | |
574 | ||
575 | __raw_writel(1, reg); | |
576 | do { | |
577 | cpu_relax(); | |
578 | } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); | |
579 | ||
580 | WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); | |
581 | } | |
582 | ||
583 | #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ | |
584 | ((mac)[2] << 16) | ((mac)[3] << 24)) | |
585 | #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) | |
586 | ||
587 | static void cpsw_set_slave_mac(struct cpsw_slave *slave, | |
588 | struct cpsw_priv *priv) | |
589 | { | |
9750a3ad RC |
590 | slave_write(slave, mac_hi(priv->mac_addr), SA_HI); |
591 | slave_write(slave, mac_lo(priv->mac_addr), SA_LO); | |
df828598 M |
592 | } |
593 | ||
594 | static void _cpsw_adjust_link(struct cpsw_slave *slave, | |
595 | struct cpsw_priv *priv, bool *link) | |
596 | { | |
597 | struct phy_device *phy = slave->phy; | |
598 | u32 mac_control = 0; | |
599 | u32 slave_port; | |
600 | ||
601 | if (!phy) | |
602 | return; | |
603 | ||
604 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
605 | ||
606 | if (phy->link) { | |
607 | mac_control = priv->data.mac_control; | |
608 | ||
609 | /* enable forwarding */ | |
610 | cpsw_ale_control_set(priv->ale, slave_port, | |
611 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
612 | ||
613 | if (phy->speed == 1000) | |
614 | mac_control |= BIT(7); /* GIGABITEN */ | |
615 | if (phy->duplex) | |
616 | mac_control |= BIT(0); /* FULLDUPLEXEN */ | |
342b7b74 DM |
617 | |
618 | /* set speed_in input in case RMII mode is used in 100Mbps */ | |
619 | if (phy->speed == 100) | |
620 | mac_control |= BIT(15); | |
621 | ||
df828598 M |
622 | *link = true; |
623 | } else { | |
624 | mac_control = 0; | |
625 | /* disable forwarding */ | |
626 | cpsw_ale_control_set(priv->ale, slave_port, | |
627 | ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); | |
628 | } | |
629 | ||
630 | if (mac_control != slave->mac_control) { | |
631 | phy_print_status(phy); | |
632 | __raw_writel(mac_control, &slave->sliver->mac_control); | |
633 | } | |
634 | ||
635 | slave->mac_control = mac_control; | |
636 | } | |
637 | ||
638 | static void cpsw_adjust_link(struct net_device *ndev) | |
639 | { | |
640 | struct cpsw_priv *priv = netdev_priv(ndev); | |
641 | bool link = false; | |
642 | ||
643 | for_each_slave(priv, _cpsw_adjust_link, priv, &link); | |
644 | ||
645 | if (link) { | |
646 | netif_carrier_on(ndev); | |
647 | if (netif_running(ndev)) | |
648 | netif_wake_queue(ndev); | |
649 | } else { | |
650 | netif_carrier_off(ndev); | |
651 | netif_stop_queue(ndev); | |
652 | } | |
653 | } | |
654 | ||
ff5b8ef2 M |
655 | static int cpsw_get_coalesce(struct net_device *ndev, |
656 | struct ethtool_coalesce *coal) | |
657 | { | |
658 | struct cpsw_priv *priv = netdev_priv(ndev); | |
659 | ||
660 | coal->rx_coalesce_usecs = priv->coal_intvl; | |
661 | return 0; | |
662 | } | |
663 | ||
664 | static int cpsw_set_coalesce(struct net_device *ndev, | |
665 | struct ethtool_coalesce *coal) | |
666 | { | |
667 | struct cpsw_priv *priv = netdev_priv(ndev); | |
668 | u32 int_ctrl; | |
669 | u32 num_interrupts = 0; | |
670 | u32 prescale = 0; | |
671 | u32 addnl_dvdr = 1; | |
672 | u32 coal_intvl = 0; | |
673 | ||
674 | if (!coal->rx_coalesce_usecs) | |
675 | return -EINVAL; | |
676 | ||
677 | coal_intvl = coal->rx_coalesce_usecs; | |
678 | ||
679 | int_ctrl = readl(&priv->wr_regs->int_control); | |
680 | prescale = priv->bus_freq_mhz * 4; | |
681 | ||
682 | if (coal_intvl < CPSW_CMINTMIN_INTVL) | |
683 | coal_intvl = CPSW_CMINTMIN_INTVL; | |
684 | ||
685 | if (coal_intvl > CPSW_CMINTMAX_INTVL) { | |
686 | /* Interrupt pacer works with 4us Pulse, we can | |
687 | * throttle further by dilating the 4us pulse. | |
688 | */ | |
689 | addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; | |
690 | ||
691 | if (addnl_dvdr > 1) { | |
692 | prescale *= addnl_dvdr; | |
693 | if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) | |
694 | coal_intvl = (CPSW_CMINTMAX_INTVL | |
695 | * addnl_dvdr); | |
696 | } else { | |
697 | addnl_dvdr = 1; | |
698 | coal_intvl = CPSW_CMINTMAX_INTVL; | |
699 | } | |
700 | } | |
701 | ||
702 | num_interrupts = (1000 * addnl_dvdr) / coal_intvl; | |
703 | writel(num_interrupts, &priv->wr_regs->rx_imax); | |
704 | writel(num_interrupts, &priv->wr_regs->tx_imax); | |
705 | ||
706 | int_ctrl |= CPSW_INTPACEEN; | |
707 | int_ctrl &= (~CPSW_INTPRESCALE_MASK); | |
708 | int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); | |
709 | writel(int_ctrl, &priv->wr_regs->int_control); | |
710 | ||
711 | cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); | |
712 | if (priv->data.dual_emac) { | |
713 | int i; | |
714 | ||
715 | for (i = 0; i < priv->data.slaves; i++) { | |
716 | priv = netdev_priv(priv->slaves[i].ndev); | |
717 | priv->coal_intvl = coal_intvl; | |
718 | } | |
719 | } else { | |
720 | priv->coal_intvl = coal_intvl; | |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
df828598 M |
726 | static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) |
727 | { | |
728 | static char *leader = "........................................"; | |
729 | ||
730 | if (!val) | |
731 | return 0; | |
732 | else | |
733 | return snprintf(buf, maxlen, "%s %s %10d\n", name, | |
734 | leader + strlen(name), val); | |
735 | } | |
736 | ||
d9ba8f9e M |
737 | static int cpsw_common_res_usage_state(struct cpsw_priv *priv) |
738 | { | |
739 | u32 i; | |
740 | u32 usage_count = 0; | |
741 | ||
742 | if (!priv->data.dual_emac) | |
743 | return 0; | |
744 | ||
745 | for (i = 0; i < priv->data.slaves; i++) | |
746 | if (priv->slaves[i].open_stat) | |
747 | usage_count++; | |
748 | ||
749 | return usage_count; | |
750 | } | |
751 | ||
752 | static inline int cpsw_tx_packet_submit(struct net_device *ndev, | |
753 | struct cpsw_priv *priv, struct sk_buff *skb) | |
754 | { | |
755 | if (!priv->data.dual_emac) | |
756 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
aef614e1 | 757 | skb->len, 0); |
d9ba8f9e M |
758 | |
759 | if (ndev == cpsw_get_slave_ndev(priv, 0)) | |
760 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
aef614e1 | 761 | skb->len, 1); |
d9ba8f9e M |
762 | else |
763 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
aef614e1 | 764 | skb->len, 2); |
d9ba8f9e M |
765 | } |
766 | ||
767 | static inline void cpsw_add_dual_emac_def_ale_entries( | |
768 | struct cpsw_priv *priv, struct cpsw_slave *slave, | |
769 | u32 slave_port) | |
770 | { | |
771 | u32 port_mask = 1 << slave_port | 1 << priv->host_port; | |
772 | ||
773 | if (priv->version == CPSW_VERSION_1) | |
774 | slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); | |
775 | else | |
776 | slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); | |
777 | cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, | |
778 | port_mask, port_mask, 0); | |
779 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
780 | port_mask, ALE_VLAN, slave->port_vlan, 0); | |
781 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, | |
782 | priv->host_port, ALE_VLAN, slave->port_vlan); | |
783 | } | |
784 | ||
df828598 M |
785 | static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) |
786 | { | |
787 | char name[32]; | |
788 | u32 slave_port; | |
789 | ||
790 | sprintf(name, "slave-%d", slave->slave_num); | |
791 | ||
792 | soft_reset(name, &slave->sliver->soft_reset); | |
793 | ||
794 | /* setup priority mapping */ | |
795 | __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); | |
9750a3ad RC |
796 | |
797 | switch (priv->version) { | |
798 | case CPSW_VERSION_1: | |
799 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); | |
800 | break; | |
801 | case CPSW_VERSION_2: | |
802 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); | |
803 | break; | |
804 | } | |
df828598 M |
805 | |
806 | /* setup max packet size, and mac address */ | |
807 | __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); | |
808 | cpsw_set_slave_mac(slave, priv); | |
809 | ||
810 | slave->mac_control = 0; /* no link yet */ | |
811 | ||
812 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
813 | ||
d9ba8f9e M |
814 | if (priv->data.dual_emac) |
815 | cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); | |
816 | else | |
817 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
818 | 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); | |
df828598 M |
819 | |
820 | slave->phy = phy_connect(priv->ndev, slave->data->phy_id, | |
f9a8f83b | 821 | &cpsw_adjust_link, slave->data->phy_if); |
df828598 M |
822 | if (IS_ERR(slave->phy)) { |
823 | dev_err(priv->dev, "phy %s not found on slave %d\n", | |
824 | slave->data->phy_id, slave->slave_num); | |
825 | slave->phy = NULL; | |
826 | } else { | |
827 | dev_info(priv->dev, "phy found : id is : 0x%x\n", | |
828 | slave->phy->phy_id); | |
829 | phy_start(slave->phy); | |
830 | } | |
831 | } | |
832 | ||
3b72c2fe M |
833 | static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) |
834 | { | |
835 | const int vlan = priv->data.default_vlan; | |
836 | const int port = priv->host_port; | |
837 | u32 reg; | |
838 | int i; | |
839 | ||
840 | reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : | |
841 | CPSW2_PORT_VLAN; | |
842 | ||
843 | writel(vlan, &priv->host_port_regs->port_vlan); | |
844 | ||
0237c110 | 845 | for (i = 0; i < priv->data.slaves; i++) |
3b72c2fe M |
846 | slave_write(priv->slaves + i, vlan, reg); |
847 | ||
848 | cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, | |
849 | ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, | |
850 | (ALE_PORT_1 | ALE_PORT_2) << port); | |
851 | } | |
852 | ||
df828598 M |
853 | static void cpsw_init_host_port(struct cpsw_priv *priv) |
854 | { | |
3b72c2fe | 855 | u32 control_reg; |
d9ba8f9e | 856 | u32 fifo_mode; |
3b72c2fe | 857 | |
df828598 M |
858 | /* soft reset the controller and initialize ale */ |
859 | soft_reset("cpsw", &priv->regs->soft_reset); | |
860 | cpsw_ale_start(priv->ale); | |
861 | ||
862 | /* switch to vlan unaware mode */ | |
3b72c2fe M |
863 | cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, |
864 | CPSW_ALE_VLAN_AWARE); | |
865 | control_reg = readl(&priv->regs->control); | |
866 | control_reg |= CPSW_VLAN_AWARE; | |
867 | writel(control_reg, &priv->regs->control); | |
d9ba8f9e M |
868 | fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : |
869 | CPSW_FIFO_NORMAL_MODE; | |
870 | writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); | |
df828598 M |
871 | |
872 | /* setup host port priority mapping */ | |
873 | __raw_writel(CPDMA_TX_PRIORITY_MAP, | |
874 | &priv->host_port_regs->cpdma_tx_pri_map); | |
875 | __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); | |
876 | ||
877 | cpsw_ale_control_set(priv->ale, priv->host_port, | |
878 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
879 | ||
d9ba8f9e M |
880 | if (!priv->data.dual_emac) { |
881 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, | |
882 | 0, 0); | |
883 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
884 | 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); | |
885 | } | |
df828598 M |
886 | } |
887 | ||
aacebbf8 SS |
888 | static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) |
889 | { | |
890 | if (!slave->phy) | |
891 | return; | |
892 | phy_stop(slave->phy); | |
893 | phy_disconnect(slave->phy); | |
894 | slave->phy = NULL; | |
895 | } | |
896 | ||
df828598 M |
897 | static int cpsw_ndo_open(struct net_device *ndev) |
898 | { | |
899 | struct cpsw_priv *priv = netdev_priv(ndev); | |
a11fbba9 | 900 | struct cpsw_priv *prim_cpsw; |
df828598 M |
901 | int i, ret; |
902 | u32 reg; | |
903 | ||
d9ba8f9e M |
904 | if (!cpsw_common_res_usage_state(priv)) |
905 | cpsw_intr_disable(priv); | |
df828598 M |
906 | netif_carrier_off(ndev); |
907 | ||
f150bd7f | 908 | pm_runtime_get_sync(&priv->pdev->dev); |
df828598 | 909 | |
549985ee | 910 | reg = priv->version; |
df828598 M |
911 | |
912 | dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", | |
913 | CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), | |
914 | CPSW_RTL_VERSION(reg)); | |
915 | ||
916 | /* initialize host and slave ports */ | |
d9ba8f9e M |
917 | if (!cpsw_common_res_usage_state(priv)) |
918 | cpsw_init_host_port(priv); | |
df828598 M |
919 | for_each_slave(priv, cpsw_slave_open, priv); |
920 | ||
3b72c2fe | 921 | /* Add default VLAN */ |
d9ba8f9e M |
922 | if (!priv->data.dual_emac) |
923 | cpsw_add_default_vlan(priv); | |
3b72c2fe | 924 | |
d9ba8f9e M |
925 | if (!cpsw_common_res_usage_state(priv)) { |
926 | /* setup tx dma to fixed prio and zero offset */ | |
927 | cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); | |
928 | cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); | |
df828598 | 929 | |
d9ba8f9e M |
930 | /* disable priority elevation */ |
931 | __raw_writel(0, &priv->regs->ptype); | |
df828598 | 932 | |
d9ba8f9e M |
933 | /* enable statistics collection only on all ports */ |
934 | __raw_writel(0x7, &priv->regs->stat_port_en); | |
df828598 | 935 | |
d9ba8f9e M |
936 | if (WARN_ON(!priv->data.rx_descs)) |
937 | priv->data.rx_descs = 128; | |
df828598 | 938 | |
d9ba8f9e M |
939 | for (i = 0; i < priv->data.rx_descs; i++) { |
940 | struct sk_buff *skb; | |
df828598 | 941 | |
d9ba8f9e | 942 | ret = -ENOMEM; |
aacebbf8 SS |
943 | skb = __netdev_alloc_skb_ip_align(priv->ndev, |
944 | priv->rx_packet_max, GFP_KERNEL); | |
d9ba8f9e | 945 | if (!skb) |
aacebbf8 | 946 | goto err_cleanup; |
d9ba8f9e | 947 | ret = cpdma_chan_submit(priv->rxch, skb, skb->data, |
aef614e1 | 948 | skb_tailroom(skb), 0); |
aacebbf8 SS |
949 | if (ret < 0) { |
950 | kfree_skb(skb); | |
951 | goto err_cleanup; | |
952 | } | |
d9ba8f9e M |
953 | } |
954 | /* continue even if we didn't manage to submit all | |
955 | * receive descs | |
956 | */ | |
957 | cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); | |
df828598 | 958 | } |
df828598 | 959 | |
ff5b8ef2 M |
960 | /* Enable Interrupt pacing if configured */ |
961 | if (priv->coal_intvl != 0) { | |
962 | struct ethtool_coalesce coal; | |
963 | ||
964 | coal.rx_coalesce_usecs = (priv->coal_intvl << 4); | |
965 | cpsw_set_coalesce(ndev, &coal); | |
966 | } | |
967 | ||
a11fbba9 SS |
968 | prim_cpsw = cpsw_get_slave_priv(priv, 0); |
969 | if (prim_cpsw->irq_enabled == false) { | |
970 | if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { | |
971 | prim_cpsw->irq_enabled = true; | |
972 | cpsw_enable_irq(prim_cpsw); | |
973 | } | |
974 | } | |
975 | ||
df828598 M |
976 | cpdma_ctlr_start(priv->dma); |
977 | cpsw_intr_enable(priv); | |
978 | napi_enable(&priv->napi); | |
510a1e72 M |
979 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
980 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
df828598 | 981 | |
d9ba8f9e M |
982 | if (priv->data.dual_emac) |
983 | priv->slaves[priv->emac_port].open_stat = true; | |
df828598 | 984 | return 0; |
df828598 | 985 | |
aacebbf8 SS |
986 | err_cleanup: |
987 | cpdma_ctlr_stop(priv->dma); | |
988 | for_each_slave(priv, cpsw_slave_stop, priv); | |
989 | pm_runtime_put_sync(&priv->pdev->dev); | |
990 | netif_carrier_off(priv->ndev); | |
991 | return ret; | |
df828598 M |
992 | } |
993 | ||
994 | static int cpsw_ndo_stop(struct net_device *ndev) | |
995 | { | |
996 | struct cpsw_priv *priv = netdev_priv(ndev); | |
997 | ||
998 | cpsw_info(priv, ifdown, "shutting down cpsw device\n"); | |
df828598 M |
999 | netif_stop_queue(priv->ndev); |
1000 | napi_disable(&priv->napi); | |
1001 | netif_carrier_off(priv->ndev); | |
d9ba8f9e M |
1002 | |
1003 | if (cpsw_common_res_usage_state(priv) <= 1) { | |
1004 | cpsw_intr_disable(priv); | |
1005 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1006 | cpdma_ctlr_stop(priv->dma); | |
1007 | cpsw_ale_stop(priv->ale); | |
1008 | } | |
df828598 | 1009 | for_each_slave(priv, cpsw_slave_stop, priv); |
f150bd7f | 1010 | pm_runtime_put_sync(&priv->pdev->dev); |
d9ba8f9e M |
1011 | if (priv->data.dual_emac) |
1012 | priv->slaves[priv->emac_port].open_stat = false; | |
df828598 M |
1013 | return 0; |
1014 | } | |
1015 | ||
1016 | static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, | |
1017 | struct net_device *ndev) | |
1018 | { | |
1019 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1020 | int ret; | |
1021 | ||
1022 | ndev->trans_start = jiffies; | |
1023 | ||
1024 | if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { | |
1025 | cpsw_err(priv, tx_err, "packet pad failed\n"); | |
1026 | priv->stats.tx_dropped++; | |
1027 | return NETDEV_TX_OK; | |
1028 | } | |
1029 | ||
9232b16d M |
1030 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
1031 | priv->cpts->tx_enable) | |
2e5b38ab RC |
1032 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
1033 | ||
1034 | skb_tx_timestamp(skb); | |
1035 | ||
d9ba8f9e | 1036 | ret = cpsw_tx_packet_submit(ndev, priv, skb); |
df828598 M |
1037 | if (unlikely(ret != 0)) { |
1038 | cpsw_err(priv, tx_err, "desc submit failed\n"); | |
1039 | goto fail; | |
1040 | } | |
1041 | ||
fae50823 M |
1042 | /* If there is no more tx desc left free then we need to |
1043 | * tell the kernel to stop sending us tx frames. | |
1044 | */ | |
d35162f8 | 1045 | if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) |
fae50823 M |
1046 | netif_stop_queue(ndev); |
1047 | ||
df828598 M |
1048 | return NETDEV_TX_OK; |
1049 | fail: | |
1050 | priv->stats.tx_dropped++; | |
1051 | netif_stop_queue(ndev); | |
1052 | return NETDEV_TX_BUSY; | |
1053 | } | |
1054 | ||
1055 | static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) | |
1056 | { | |
1057 | /* | |
1058 | * The switch cannot operate in promiscuous mode without substantial | |
1059 | * headache. For promiscuous mode to work, we would need to put the | |
1060 | * ALE in bypass mode and route all traffic to the host port. | |
1061 | * Subsequently, the host will need to operate as a "bridge", learn, | |
1062 | * and flood as needed. For now, we simply complain here and | |
1063 | * do nothing about it :-) | |
1064 | */ | |
1065 | if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) | |
1066 | dev_err(&ndev->dev, "promiscuity ignored!\n"); | |
1067 | ||
1068 | /* | |
1069 | * The switch cannot filter multicast traffic unless it is configured | |
1070 | * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a | |
1071 | * whole bunch of additional logic that this driver does not implement | |
1072 | * at present. | |
1073 | */ | |
1074 | if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) | |
1075 | dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); | |
1076 | } | |
1077 | ||
2e5b38ab RC |
1078 | #ifdef CONFIG_TI_CPTS |
1079 | ||
1080 | static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) | |
1081 | { | |
e86ac13b | 1082 | struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; |
2e5b38ab RC |
1083 | u32 ts_en, seq_id; |
1084 | ||
9232b16d | 1085 | if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { |
2e5b38ab RC |
1086 | slave_write(slave, 0, CPSW1_TS_CTL); |
1087 | return; | |
1088 | } | |
1089 | ||
1090 | seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; | |
1091 | ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; | |
1092 | ||
9232b16d | 1093 | if (priv->cpts->tx_enable) |
2e5b38ab RC |
1094 | ts_en |= CPSW_V1_TS_TX_EN; |
1095 | ||
9232b16d | 1096 | if (priv->cpts->rx_enable) |
2e5b38ab RC |
1097 | ts_en |= CPSW_V1_TS_RX_EN; |
1098 | ||
1099 | slave_write(slave, ts_en, CPSW1_TS_CTL); | |
1100 | slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); | |
1101 | } | |
1102 | ||
1103 | static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) | |
1104 | { | |
d9ba8f9e | 1105 | struct cpsw_slave *slave; |
2e5b38ab RC |
1106 | u32 ctrl, mtype; |
1107 | ||
d9ba8f9e M |
1108 | if (priv->data.dual_emac) |
1109 | slave = &priv->slaves[priv->emac_port]; | |
1110 | else | |
e86ac13b | 1111 | slave = &priv->slaves[priv->data.active_slave]; |
d9ba8f9e | 1112 | |
2e5b38ab RC |
1113 | ctrl = slave_read(slave, CPSW2_CONTROL); |
1114 | ctrl &= ~CTRL_ALL_TS_MASK; | |
1115 | ||
9232b16d | 1116 | if (priv->cpts->tx_enable) |
2e5b38ab RC |
1117 | ctrl |= CTRL_TX_TS_BITS; |
1118 | ||
9232b16d | 1119 | if (priv->cpts->rx_enable) |
2e5b38ab RC |
1120 | ctrl |= CTRL_RX_TS_BITS; |
1121 | ||
1122 | mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; | |
1123 | ||
1124 | slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); | |
1125 | slave_write(slave, ctrl, CPSW2_CONTROL); | |
1126 | __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); | |
1127 | } | |
1128 | ||
3177bf6f | 1129 | static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) |
2e5b38ab | 1130 | { |
3177bf6f | 1131 | struct cpsw_priv *priv = netdev_priv(dev); |
9232b16d | 1132 | struct cpts *cpts = priv->cpts; |
2e5b38ab RC |
1133 | struct hwtstamp_config cfg; |
1134 | ||
1135 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
1136 | return -EFAULT; | |
1137 | ||
1138 | /* reserved for future extensions */ | |
1139 | if (cfg.flags) | |
1140 | return -EINVAL; | |
1141 | ||
1142 | switch (cfg.tx_type) { | |
1143 | case HWTSTAMP_TX_OFF: | |
1144 | cpts->tx_enable = 0; | |
1145 | break; | |
1146 | case HWTSTAMP_TX_ON: | |
1147 | cpts->tx_enable = 1; | |
1148 | break; | |
1149 | default: | |
1150 | return -ERANGE; | |
1151 | } | |
1152 | ||
1153 | switch (cfg.rx_filter) { | |
1154 | case HWTSTAMP_FILTER_NONE: | |
1155 | cpts->rx_enable = 0; | |
1156 | break; | |
1157 | case HWTSTAMP_FILTER_ALL: | |
1158 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1159 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1160 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1161 | return -ERANGE; | |
1162 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1163 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1164 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1165 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1166 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1167 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1168 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1169 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1170 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1171 | cpts->rx_enable = 1; | |
1172 | cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
1173 | break; | |
1174 | default: | |
1175 | return -ERANGE; | |
1176 | } | |
1177 | ||
1178 | switch (priv->version) { | |
1179 | case CPSW_VERSION_1: | |
1180 | cpsw_hwtstamp_v1(priv); | |
1181 | break; | |
1182 | case CPSW_VERSION_2: | |
1183 | cpsw_hwtstamp_v2(priv); | |
1184 | break; | |
1185 | default: | |
1186 | return -ENOTSUPP; | |
1187 | } | |
1188 | ||
1189 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
1190 | } | |
1191 | ||
1192 | #endif /*CONFIG_TI_CPTS*/ | |
1193 | ||
1194 | static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
1195 | { | |
11f2c988 M |
1196 | struct cpsw_priv *priv = netdev_priv(dev); |
1197 | struct mii_ioctl_data *data = if_mii(req); | |
1198 | int slave_no = cpsw_slave_index(priv); | |
1199 | ||
2e5b38ab RC |
1200 | if (!netif_running(dev)) |
1201 | return -EINVAL; | |
1202 | ||
11f2c988 | 1203 | switch (cmd) { |
2e5b38ab | 1204 | #ifdef CONFIG_TI_CPTS |
11f2c988 | 1205 | case SIOCSHWTSTAMP: |
3177bf6f | 1206 | return cpsw_hwtstamp_ioctl(dev, req); |
2e5b38ab | 1207 | #endif |
11f2c988 M |
1208 | case SIOCGMIIPHY: |
1209 | data->phy_id = priv->slaves[slave_no].phy->addr; | |
1210 | break; | |
1211 | default: | |
1212 | return -ENOTSUPP; | |
1213 | } | |
1214 | ||
1215 | return 0; | |
2e5b38ab RC |
1216 | } |
1217 | ||
df828598 M |
1218 | static void cpsw_ndo_tx_timeout(struct net_device *ndev) |
1219 | { | |
1220 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1221 | ||
1222 | cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); | |
1223 | priv->stats.tx_errors++; | |
1224 | cpsw_intr_disable(priv); | |
1225 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1226 | cpdma_chan_stop(priv->txch); | |
1227 | cpdma_chan_start(priv->txch); | |
1228 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
1229 | cpsw_intr_enable(priv); | |
510a1e72 M |
1230 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1231 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
1232 | ||
df828598 M |
1233 | } |
1234 | ||
1235 | static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) | |
1236 | { | |
1237 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1238 | return &priv->stats; | |
1239 | } | |
1240 | ||
1241 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1242 | static void cpsw_ndo_poll_controller(struct net_device *ndev) | |
1243 | { | |
1244 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1245 | ||
1246 | cpsw_intr_disable(priv); | |
1247 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1248 | cpsw_interrupt(ndev->irq, priv); | |
1249 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
1250 | cpsw_intr_enable(priv); | |
510a1e72 M |
1251 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1252 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
1253 | ||
df828598 M |
1254 | } |
1255 | #endif | |
1256 | ||
3b72c2fe M |
1257 | static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, |
1258 | unsigned short vid) | |
1259 | { | |
1260 | int ret; | |
1261 | ||
1262 | ret = cpsw_ale_add_vlan(priv->ale, vid, | |
1263 | ALE_ALL_PORTS << priv->host_port, | |
1264 | 0, ALE_ALL_PORTS << priv->host_port, | |
1265 | (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); | |
1266 | if (ret != 0) | |
1267 | return ret; | |
1268 | ||
1269 | ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, | |
1270 | priv->host_port, ALE_VLAN, vid); | |
1271 | if (ret != 0) | |
1272 | goto clean_vid; | |
1273 | ||
1274 | ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
1275 | ALE_ALL_PORTS << priv->host_port, | |
1276 | ALE_VLAN, vid, 0); | |
1277 | if (ret != 0) | |
1278 | goto clean_vlan_ucast; | |
1279 | return 0; | |
1280 | ||
1281 | clean_vlan_ucast: | |
1282 | cpsw_ale_del_ucast(priv->ale, priv->mac_addr, | |
1283 | priv->host_port, ALE_VLAN, vid); | |
1284 | clean_vid: | |
1285 | cpsw_ale_del_vlan(priv->ale, vid, 0); | |
1286 | return ret; | |
1287 | } | |
1288 | ||
1289 | static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, | |
80d5c368 | 1290 | __be16 proto, u16 vid) |
3b72c2fe M |
1291 | { |
1292 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1293 | ||
1294 | if (vid == priv->data.default_vlan) | |
1295 | return 0; | |
1296 | ||
1297 | dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); | |
1298 | return cpsw_add_vlan_ale_entry(priv, vid); | |
1299 | } | |
1300 | ||
1301 | static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, | |
80d5c368 | 1302 | __be16 proto, u16 vid) |
3b72c2fe M |
1303 | { |
1304 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1305 | int ret; | |
1306 | ||
1307 | if (vid == priv->data.default_vlan) | |
1308 | return 0; | |
1309 | ||
1310 | dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); | |
1311 | ret = cpsw_ale_del_vlan(priv->ale, vid, 0); | |
1312 | if (ret != 0) | |
1313 | return ret; | |
1314 | ||
1315 | ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, | |
1316 | priv->host_port, ALE_VLAN, vid); | |
1317 | if (ret != 0) | |
1318 | return ret; | |
1319 | ||
1320 | return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, | |
1321 | 0, ALE_VLAN, vid); | |
1322 | } | |
1323 | ||
df828598 M |
1324 | static const struct net_device_ops cpsw_netdev_ops = { |
1325 | .ndo_open = cpsw_ndo_open, | |
1326 | .ndo_stop = cpsw_ndo_stop, | |
1327 | .ndo_start_xmit = cpsw_ndo_start_xmit, | |
1328 | .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, | |
2e5b38ab | 1329 | .ndo_do_ioctl = cpsw_ndo_ioctl, |
df828598 | 1330 | .ndo_validate_addr = eth_validate_addr, |
5c473ed2 | 1331 | .ndo_change_mtu = eth_change_mtu, |
df828598 M |
1332 | .ndo_tx_timeout = cpsw_ndo_tx_timeout, |
1333 | .ndo_get_stats = cpsw_ndo_get_stats, | |
5c50a856 | 1334 | .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, |
df828598 M |
1335 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1336 | .ndo_poll_controller = cpsw_ndo_poll_controller, | |
1337 | #endif | |
3b72c2fe M |
1338 | .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, |
1339 | .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, | |
df828598 M |
1340 | }; |
1341 | ||
1342 | static void cpsw_get_drvinfo(struct net_device *ndev, | |
1343 | struct ethtool_drvinfo *info) | |
1344 | { | |
1345 | struct cpsw_priv *priv = netdev_priv(ndev); | |
7826d43f JP |
1346 | |
1347 | strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); | |
1348 | strlcpy(info->version, "1.0", sizeof(info->version)); | |
1349 | strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); | |
df828598 M |
1350 | } |
1351 | ||
1352 | static u32 cpsw_get_msglevel(struct net_device *ndev) | |
1353 | { | |
1354 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1355 | return priv->msg_enable; | |
1356 | } | |
1357 | ||
1358 | static void cpsw_set_msglevel(struct net_device *ndev, u32 value) | |
1359 | { | |
1360 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1361 | priv->msg_enable = value; | |
1362 | } | |
1363 | ||
2e5b38ab RC |
1364 | static int cpsw_get_ts_info(struct net_device *ndev, |
1365 | struct ethtool_ts_info *info) | |
1366 | { | |
1367 | #ifdef CONFIG_TI_CPTS | |
1368 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1369 | ||
1370 | info->so_timestamping = | |
1371 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1372 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1373 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1374 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1375 | SOF_TIMESTAMPING_SOFTWARE | | |
1376 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
9232b16d | 1377 | info->phc_index = priv->cpts->phc_index; |
2e5b38ab RC |
1378 | info->tx_types = |
1379 | (1 << HWTSTAMP_TX_OFF) | | |
1380 | (1 << HWTSTAMP_TX_ON); | |
1381 | info->rx_filters = | |
1382 | (1 << HWTSTAMP_FILTER_NONE) | | |
1383 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); | |
1384 | #else | |
1385 | info->so_timestamping = | |
1386 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1387 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1388 | SOF_TIMESTAMPING_SOFTWARE; | |
1389 | info->phc_index = -1; | |
1390 | info->tx_types = 0; | |
1391 | info->rx_filters = 0; | |
1392 | #endif | |
1393 | return 0; | |
1394 | } | |
1395 | ||
d3bb9c58 M |
1396 | static int cpsw_get_settings(struct net_device *ndev, |
1397 | struct ethtool_cmd *ecmd) | |
1398 | { | |
1399 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1400 | int slave_no = cpsw_slave_index(priv); | |
1401 | ||
1402 | if (priv->slaves[slave_no].phy) | |
1403 | return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); | |
1404 | else | |
1405 | return -EOPNOTSUPP; | |
1406 | } | |
1407 | ||
1408 | static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
1409 | { | |
1410 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1411 | int slave_no = cpsw_slave_index(priv); | |
1412 | ||
1413 | if (priv->slaves[slave_no].phy) | |
1414 | return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); | |
1415 | else | |
1416 | return -EOPNOTSUPP; | |
1417 | } | |
1418 | ||
df828598 M |
1419 | static const struct ethtool_ops cpsw_ethtool_ops = { |
1420 | .get_drvinfo = cpsw_get_drvinfo, | |
1421 | .get_msglevel = cpsw_get_msglevel, | |
1422 | .set_msglevel = cpsw_set_msglevel, | |
1423 | .get_link = ethtool_op_get_link, | |
2e5b38ab | 1424 | .get_ts_info = cpsw_get_ts_info, |
d3bb9c58 M |
1425 | .get_settings = cpsw_get_settings, |
1426 | .set_settings = cpsw_set_settings, | |
ff5b8ef2 M |
1427 | .get_coalesce = cpsw_get_coalesce, |
1428 | .set_coalesce = cpsw_set_coalesce, | |
df828598 M |
1429 | }; |
1430 | ||
549985ee RC |
1431 | static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, |
1432 | u32 slave_reg_ofs, u32 sliver_reg_ofs) | |
df828598 M |
1433 | { |
1434 | void __iomem *regs = priv->regs; | |
1435 | int slave_num = slave->slave_num; | |
1436 | struct cpsw_slave_data *data = priv->data.slave_data + slave_num; | |
1437 | ||
1438 | slave->data = data; | |
549985ee RC |
1439 | slave->regs = regs + slave_reg_ofs; |
1440 | slave->sliver = regs + sliver_reg_ofs; | |
d9ba8f9e | 1441 | slave->port_vlan = data->dual_emac_res_vlan; |
df828598 M |
1442 | } |
1443 | ||
2eb32b0a M |
1444 | static int cpsw_probe_dt(struct cpsw_platform_data *data, |
1445 | struct platform_device *pdev) | |
1446 | { | |
1447 | struct device_node *node = pdev->dev.of_node; | |
1448 | struct device_node *slave_node; | |
1449 | int i = 0, ret; | |
1450 | u32 prop; | |
1451 | ||
1452 | if (!node) | |
1453 | return -EINVAL; | |
1454 | ||
1455 | if (of_property_read_u32(node, "slaves", &prop)) { | |
1456 | pr_err("Missing slaves property in the DT.\n"); | |
1457 | return -EINVAL; | |
1458 | } | |
1459 | data->slaves = prop; | |
1460 | ||
e86ac13b M |
1461 | if (of_property_read_u32(node, "active_slave", &prop)) { |
1462 | pr_err("Missing active_slave property in the DT.\n"); | |
78ca0b28 RC |
1463 | ret = -EINVAL; |
1464 | goto error_ret; | |
1465 | } | |
e86ac13b | 1466 | data->active_slave = prop; |
78ca0b28 | 1467 | |
00ab94ee RC |
1468 | if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { |
1469 | pr_err("Missing cpts_clock_mult property in the DT.\n"); | |
1470 | ret = -EINVAL; | |
1471 | goto error_ret; | |
1472 | } | |
1473 | data->cpts_clock_mult = prop; | |
1474 | ||
1475 | if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { | |
1476 | pr_err("Missing cpts_clock_shift property in the DT.\n"); | |
1477 | ret = -EINVAL; | |
1478 | goto error_ret; | |
1479 | } | |
1480 | data->cpts_clock_shift = prop; | |
1481 | ||
b2adaca9 JP |
1482 | data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), |
1483 | GFP_KERNEL); | |
1484 | if (!data->slave_data) | |
2eb32b0a | 1485 | return -EINVAL; |
2eb32b0a | 1486 | |
2eb32b0a M |
1487 | if (of_property_read_u32(node, "cpdma_channels", &prop)) { |
1488 | pr_err("Missing cpdma_channels property in the DT.\n"); | |
1489 | ret = -EINVAL; | |
1490 | goto error_ret; | |
1491 | } | |
1492 | data->channels = prop; | |
1493 | ||
2eb32b0a M |
1494 | if (of_property_read_u32(node, "ale_entries", &prop)) { |
1495 | pr_err("Missing ale_entries property in the DT.\n"); | |
1496 | ret = -EINVAL; | |
1497 | goto error_ret; | |
1498 | } | |
1499 | data->ale_entries = prop; | |
1500 | ||
2eb32b0a M |
1501 | if (of_property_read_u32(node, "bd_ram_size", &prop)) { |
1502 | pr_err("Missing bd_ram_size property in the DT.\n"); | |
1503 | ret = -EINVAL; | |
1504 | goto error_ret; | |
1505 | } | |
1506 | data->bd_ram_size = prop; | |
1507 | ||
1508 | if (of_property_read_u32(node, "rx_descs", &prop)) { | |
1509 | pr_err("Missing rx_descs property in the DT.\n"); | |
1510 | ret = -EINVAL; | |
1511 | goto error_ret; | |
1512 | } | |
1513 | data->rx_descs = prop; | |
1514 | ||
1515 | if (of_property_read_u32(node, "mac_control", &prop)) { | |
1516 | pr_err("Missing mac_control property in the DT.\n"); | |
1517 | ret = -EINVAL; | |
1518 | goto error_ret; | |
1519 | } | |
1520 | data->mac_control = prop; | |
1521 | ||
d9ba8f9e M |
1522 | if (!of_property_read_u32(node, "dual_emac", &prop)) |
1523 | data->dual_emac = prop; | |
1524 | ||
549985ee RC |
1525 | /* |
1526 | * Populate all the child nodes here... | |
1527 | */ | |
1528 | ret = of_platform_populate(node, NULL, NULL, &pdev->dev); | |
1529 | /* We do not want to force this, as in some cases may not have child */ | |
1530 | if (ret) | |
1531 | pr_warn("Doesn't have any child node\n"); | |
1532 | ||
1fb19aa7 | 1533 | for_each_node_by_name(slave_node, "slave") { |
2eb32b0a | 1534 | struct cpsw_slave_data *slave_data = data->slave_data + i; |
2eb32b0a | 1535 | const void *mac_addr = NULL; |
549985ee RC |
1536 | u32 phyid; |
1537 | int lenp; | |
1538 | const __be32 *parp; | |
1539 | struct device_node *mdio_node; | |
1540 | struct platform_device *mdio; | |
1541 | ||
1542 | parp = of_get_property(slave_node, "phy_id", &lenp); | |
ce16294f | 1543 | if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { |
2eb32b0a M |
1544 | pr_err("Missing slave[%d] phy_id property\n", i); |
1545 | ret = -EINVAL; | |
1546 | goto error_ret; | |
1547 | } | |
549985ee RC |
1548 | mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); |
1549 | phyid = be32_to_cpup(parp+1); | |
1550 | mdio = of_find_device_by_node(mdio_node); | |
1551 | snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), | |
1552 | PHY_ID_FMT, mdio->name, phyid); | |
2eb32b0a M |
1553 | |
1554 | mac_addr = of_get_mac_address(slave_node); | |
1555 | if (mac_addr) | |
1556 | memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); | |
1557 | ||
c5ceea7a M |
1558 | slave_data->phy_if = of_get_phy_mode(slave_node); |
1559 | ||
d9ba8f9e | 1560 | if (data->dual_emac) { |
91c4166c | 1561 | if (of_property_read_u32(slave_node, "dual_emac_res_vlan", |
d9ba8f9e M |
1562 | &prop)) { |
1563 | pr_err("Missing dual_emac_res_vlan in DT.\n"); | |
1564 | slave_data->dual_emac_res_vlan = i+1; | |
1565 | pr_err("Using %d as Reserved VLAN for %d slave\n", | |
1566 | slave_data->dual_emac_res_vlan, i); | |
1567 | } else { | |
1568 | slave_data->dual_emac_res_vlan = prop; | |
1569 | } | |
1570 | } | |
1571 | ||
2eb32b0a M |
1572 | i++; |
1573 | } | |
1574 | ||
1575 | return 0; | |
1576 | ||
1577 | error_ret: | |
1578 | kfree(data->slave_data); | |
1579 | return ret; | |
1580 | } | |
1581 | ||
d9ba8f9e M |
1582 | static int cpsw_probe_dual_emac(struct platform_device *pdev, |
1583 | struct cpsw_priv *priv) | |
1584 | { | |
1585 | struct cpsw_platform_data *data = &priv->data; | |
1586 | struct net_device *ndev; | |
1587 | struct cpsw_priv *priv_sl2; | |
1588 | int ret = 0, i; | |
1589 | ||
1590 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); | |
1591 | if (!ndev) { | |
1592 | pr_err("cpsw: error allocating net_device\n"); | |
1593 | return -ENOMEM; | |
1594 | } | |
1595 | ||
1596 | priv_sl2 = netdev_priv(ndev); | |
1597 | spin_lock_init(&priv_sl2->lock); | |
1598 | priv_sl2->data = *data; | |
1599 | priv_sl2->pdev = pdev; | |
1600 | priv_sl2->ndev = ndev; | |
1601 | priv_sl2->dev = &ndev->dev; | |
1602 | priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
1603 | priv_sl2->rx_packet_max = max(rx_packet_max, 128); | |
1604 | ||
1605 | if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { | |
1606 | memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, | |
1607 | ETH_ALEN); | |
1608 | pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); | |
1609 | } else { | |
1610 | random_ether_addr(priv_sl2->mac_addr); | |
1611 | pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); | |
1612 | } | |
1613 | memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); | |
1614 | ||
1615 | priv_sl2->slaves = priv->slaves; | |
1616 | priv_sl2->clk = priv->clk; | |
1617 | ||
ff5b8ef2 M |
1618 | priv_sl2->coal_intvl = 0; |
1619 | priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; | |
1620 | ||
d9ba8f9e M |
1621 | priv_sl2->cpsw_res = priv->cpsw_res; |
1622 | priv_sl2->regs = priv->regs; | |
1623 | priv_sl2->host_port = priv->host_port; | |
1624 | priv_sl2->host_port_regs = priv->host_port_regs; | |
1625 | priv_sl2->wr_regs = priv->wr_regs; | |
1626 | priv_sl2->dma = priv->dma; | |
1627 | priv_sl2->txch = priv->txch; | |
1628 | priv_sl2->rxch = priv->rxch; | |
1629 | priv_sl2->ale = priv->ale; | |
1630 | priv_sl2->emac_port = 1; | |
1631 | priv->slaves[1].ndev = ndev; | |
1632 | priv_sl2->cpts = priv->cpts; | |
1633 | priv_sl2->version = priv->version; | |
1634 | ||
1635 | for (i = 0; i < priv->num_irqs; i++) { | |
1636 | priv_sl2->irqs_table[i] = priv->irqs_table[i]; | |
1637 | priv_sl2->num_irqs = priv->num_irqs; | |
1638 | } | |
f646968f | 1639 | ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
d9ba8f9e M |
1640 | |
1641 | ndev->netdev_ops = &cpsw_netdev_ops; | |
1642 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
1643 | netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
1644 | ||
1645 | /* register the network device */ | |
1646 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1647 | ret = register_netdev(ndev); | |
1648 | if (ret) { | |
1649 | pr_err("cpsw: error registering net device\n"); | |
1650 | free_netdev(ndev); | |
1651 | ret = -ENODEV; | |
1652 | } | |
1653 | ||
1654 | return ret; | |
1655 | } | |
1656 | ||
663e12e6 | 1657 | static int cpsw_probe(struct platform_device *pdev) |
df828598 | 1658 | { |
d1bd9acf | 1659 | struct cpsw_platform_data *data; |
df828598 M |
1660 | struct net_device *ndev; |
1661 | struct cpsw_priv *priv; | |
1662 | struct cpdma_params dma_params; | |
1663 | struct cpsw_ale_params ale_params; | |
549985ee | 1664 | void __iomem *ss_regs, *wr_regs; |
df828598 | 1665 | struct resource *res; |
549985ee | 1666 | u32 slave_offset, sliver_offset, slave_size; |
df828598 M |
1667 | int ret = 0, i, k = 0; |
1668 | ||
df828598 M |
1669 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); |
1670 | if (!ndev) { | |
1671 | pr_err("error allocating net_device\n"); | |
1672 | return -ENOMEM; | |
1673 | } | |
1674 | ||
1675 | platform_set_drvdata(pdev, ndev); | |
1676 | priv = netdev_priv(ndev); | |
1677 | spin_lock_init(&priv->lock); | |
df828598 M |
1678 | priv->pdev = pdev; |
1679 | priv->ndev = ndev; | |
1680 | priv->dev = &ndev->dev; | |
1681 | priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
1682 | priv->rx_packet_max = max(rx_packet_max, 128); | |
9232b16d | 1683 | priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); |
7dcf313a | 1684 | priv->irq_enabled = true; |
ab8e99d2 | 1685 | if (!priv->cpts) { |
9232b16d M |
1686 | pr_err("error allocating cpts\n"); |
1687 | goto clean_ndev_ret; | |
1688 | } | |
df828598 | 1689 | |
1fb19aa7 VH |
1690 | /* |
1691 | * This may be required here for child devices. | |
1692 | */ | |
1693 | pm_runtime_enable(&pdev->dev); | |
1694 | ||
739683b4 M |
1695 | /* Select default pin state */ |
1696 | pinctrl_pm_select_default_state(&pdev->dev); | |
1697 | ||
2eb32b0a M |
1698 | if (cpsw_probe_dt(&priv->data, pdev)) { |
1699 | pr_err("cpsw: platform data missing\n"); | |
1700 | ret = -ENODEV; | |
1701 | goto clean_ndev_ret; | |
1702 | } | |
1703 | data = &priv->data; | |
1704 | ||
df828598 M |
1705 | if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { |
1706 | memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); | |
cf6122be | 1707 | pr_info("Detected MACID = %pM\n", priv->mac_addr); |
df828598 | 1708 | } else { |
7efd26d0 | 1709 | eth_random_addr(priv->mac_addr); |
cf6122be | 1710 | pr_info("Random MACID = %pM\n", priv->mac_addr); |
df828598 M |
1711 | } |
1712 | ||
1713 | memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); | |
1714 | ||
1715 | priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, | |
1716 | GFP_KERNEL); | |
1717 | if (!priv->slaves) { | |
1718 | ret = -EBUSY; | |
1719 | goto clean_ndev_ret; | |
1720 | } | |
1721 | for (i = 0; i < data->slaves; i++) | |
1722 | priv->slaves[i].slave_num = i; | |
1723 | ||
d9ba8f9e M |
1724 | priv->slaves[0].ndev = ndev; |
1725 | priv->emac_port = 0; | |
1726 | ||
f150bd7f | 1727 | priv->clk = clk_get(&pdev->dev, "fck"); |
df828598 | 1728 | if (IS_ERR(priv->clk)) { |
f150bd7f M |
1729 | dev_err(&pdev->dev, "fck is not found\n"); |
1730 | ret = -ENODEV; | |
1731 | goto clean_slave_ret; | |
df828598 | 1732 | } |
ff5b8ef2 M |
1733 | priv->coal_intvl = 0; |
1734 | priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; | |
df828598 M |
1735 | |
1736 | priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1737 | if (!priv->cpsw_res) { | |
1738 | dev_err(priv->dev, "error getting i/o resource\n"); | |
1739 | ret = -ENOENT; | |
1740 | goto clean_clk_ret; | |
1741 | } | |
df828598 M |
1742 | if (!request_mem_region(priv->cpsw_res->start, |
1743 | resource_size(priv->cpsw_res), ndev->name)) { | |
1744 | dev_err(priv->dev, "failed request i/o region\n"); | |
1745 | ret = -ENXIO; | |
1746 | goto clean_clk_ret; | |
1747 | } | |
549985ee RC |
1748 | ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); |
1749 | if (!ss_regs) { | |
df828598 M |
1750 | dev_err(priv->dev, "unable to map i/o region\n"); |
1751 | goto clean_cpsw_iores_ret; | |
1752 | } | |
549985ee RC |
1753 | priv->regs = ss_regs; |
1754 | priv->version = __raw_readl(&priv->regs->id_ver); | |
1755 | priv->host_port = HOST_PORT_NUM; | |
df828598 | 1756 | |
a65dd5b2 RC |
1757 | priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1758 | if (!priv->cpsw_wr_res) { | |
df828598 M |
1759 | dev_err(priv->dev, "error getting i/o resource\n"); |
1760 | ret = -ENOENT; | |
5250c969 | 1761 | goto clean_iomap_ret; |
df828598 | 1762 | } |
a65dd5b2 RC |
1763 | if (!request_mem_region(priv->cpsw_wr_res->start, |
1764 | resource_size(priv->cpsw_wr_res), ndev->name)) { | |
df828598 M |
1765 | dev_err(priv->dev, "failed request i/o region\n"); |
1766 | ret = -ENXIO; | |
5250c969 | 1767 | goto clean_iomap_ret; |
df828598 | 1768 | } |
549985ee | 1769 | wr_regs = ioremap(priv->cpsw_wr_res->start, |
a65dd5b2 | 1770 | resource_size(priv->cpsw_wr_res)); |
549985ee | 1771 | if (!wr_regs) { |
df828598 | 1772 | dev_err(priv->dev, "unable to map i/o region\n"); |
a65dd5b2 | 1773 | goto clean_cpsw_wr_iores_ret; |
df828598 | 1774 | } |
549985ee | 1775 | priv->wr_regs = wr_regs; |
df828598 M |
1776 | |
1777 | memset(&dma_params, 0, sizeof(dma_params)); | |
549985ee RC |
1778 | memset(&ale_params, 0, sizeof(ale_params)); |
1779 | ||
1780 | switch (priv->version) { | |
1781 | case CPSW_VERSION_1: | |
1782 | priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; | |
9232b16d | 1783 | priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; |
549985ee RC |
1784 | dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; |
1785 | dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; | |
1786 | ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; | |
1787 | slave_offset = CPSW1_SLAVE_OFFSET; | |
1788 | slave_size = CPSW1_SLAVE_SIZE; | |
1789 | sliver_offset = CPSW1_SLIVER_OFFSET; | |
1790 | dma_params.desc_mem_phys = 0; | |
1791 | break; | |
1792 | case CPSW_VERSION_2: | |
1793 | priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; | |
9232b16d | 1794 | priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; |
549985ee RC |
1795 | dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; |
1796 | dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; | |
1797 | ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; | |
1798 | slave_offset = CPSW2_SLAVE_OFFSET; | |
1799 | slave_size = CPSW2_SLAVE_SIZE; | |
1800 | sliver_offset = CPSW2_SLIVER_OFFSET; | |
1801 | dma_params.desc_mem_phys = | |
1802 | (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; | |
1803 | break; | |
1804 | default: | |
1805 | dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); | |
1806 | ret = -ENODEV; | |
1807 | goto clean_cpsw_wr_iores_ret; | |
1808 | } | |
1809 | for (i = 0; i < priv->data.slaves; i++) { | |
1810 | struct cpsw_slave *slave = &priv->slaves[i]; | |
1811 | cpsw_slave_init(slave, priv, slave_offset, sliver_offset); | |
1812 | slave_offset += slave_size; | |
1813 | sliver_offset += SLIVER_SIZE; | |
1814 | } | |
1815 | ||
df828598 | 1816 | dma_params.dev = &pdev->dev; |
549985ee RC |
1817 | dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; |
1818 | dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; | |
1819 | dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; | |
1820 | dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; | |
1821 | dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; | |
df828598 M |
1822 | |
1823 | dma_params.num_chan = data->channels; | |
1824 | dma_params.has_soft_reset = true; | |
1825 | dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; | |
1826 | dma_params.desc_mem_size = data->bd_ram_size; | |
1827 | dma_params.desc_align = 16; | |
1828 | dma_params.has_ext_regs = true; | |
549985ee | 1829 | dma_params.desc_hw_addr = dma_params.desc_mem_phys; |
df828598 M |
1830 | |
1831 | priv->dma = cpdma_ctlr_create(&dma_params); | |
1832 | if (!priv->dma) { | |
1833 | dev_err(priv->dev, "error initializing dma\n"); | |
1834 | ret = -ENOMEM; | |
5250c969 | 1835 | goto clean_wr_iomap_ret; |
df828598 M |
1836 | } |
1837 | ||
1838 | priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), | |
1839 | cpsw_tx_handler); | |
1840 | priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), | |
1841 | cpsw_rx_handler); | |
1842 | ||
1843 | if (WARN_ON(!priv->txch || !priv->rxch)) { | |
1844 | dev_err(priv->dev, "error initializing dma channels\n"); | |
1845 | ret = -ENOMEM; | |
1846 | goto clean_dma_ret; | |
1847 | } | |
1848 | ||
df828598 | 1849 | ale_params.dev = &ndev->dev; |
df828598 M |
1850 | ale_params.ale_ageout = ale_ageout; |
1851 | ale_params.ale_entries = data->ale_entries; | |
1852 | ale_params.ale_ports = data->slaves; | |
1853 | ||
1854 | priv->ale = cpsw_ale_create(&ale_params); | |
1855 | if (!priv->ale) { | |
1856 | dev_err(priv->dev, "error initializing ale engine\n"); | |
1857 | ret = -ENODEV; | |
1858 | goto clean_dma_ret; | |
1859 | } | |
1860 | ||
1861 | ndev->irq = platform_get_irq(pdev, 0); | |
1862 | if (ndev->irq < 0) { | |
1863 | dev_err(priv->dev, "error getting irq resource\n"); | |
1864 | ret = -ENOENT; | |
1865 | goto clean_ale_ret; | |
1866 | } | |
1867 | ||
1868 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { | |
1869 | for (i = res->start; i <= res->end; i++) { | |
1870 | if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, | |
1871 | dev_name(&pdev->dev), priv)) { | |
1872 | dev_err(priv->dev, "error attaching irq\n"); | |
1873 | goto clean_ale_ret; | |
1874 | } | |
1875 | priv->irqs_table[k] = i; | |
d1bd9acf | 1876 | priv->num_irqs = k + 1; |
df828598 M |
1877 | } |
1878 | k++; | |
1879 | } | |
1880 | ||
f646968f | 1881 | ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
df828598 M |
1882 | |
1883 | ndev->netdev_ops = &cpsw_netdev_ops; | |
1884 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
1885 | netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
1886 | ||
1887 | /* register the network device */ | |
1888 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1889 | ret = register_netdev(ndev); | |
1890 | if (ret) { | |
1891 | dev_err(priv->dev, "error registering net device\n"); | |
1892 | ret = -ENODEV; | |
1893 | goto clean_irq_ret; | |
1894 | } | |
1895 | ||
9232b16d | 1896 | if (cpts_register(&pdev->dev, priv->cpts, |
2e5b38ab RC |
1897 | data->cpts_clock_mult, data->cpts_clock_shift)) |
1898 | dev_err(priv->dev, "error registering cpts device\n"); | |
1899 | ||
df828598 M |
1900 | cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", |
1901 | priv->cpsw_res->start, ndev->irq); | |
1902 | ||
d9ba8f9e M |
1903 | if (priv->data.dual_emac) { |
1904 | ret = cpsw_probe_dual_emac(pdev, priv); | |
1905 | if (ret) { | |
1906 | cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); | |
1907 | goto clean_irq_ret; | |
1908 | } | |
1909 | } | |
1910 | ||
df828598 M |
1911 | return 0; |
1912 | ||
1913 | clean_irq_ret: | |
d1bd9acf SS |
1914 | for (i = 0; i < priv->num_irqs; i++) |
1915 | free_irq(priv->irqs_table[i], priv); | |
df828598 M |
1916 | clean_ale_ret: |
1917 | cpsw_ale_destroy(priv->ale); | |
1918 | clean_dma_ret: | |
1919 | cpdma_chan_destroy(priv->txch); | |
1920 | cpdma_chan_destroy(priv->rxch); | |
1921 | cpdma_ctlr_destroy(priv->dma); | |
5250c969 RC |
1922 | clean_wr_iomap_ret: |
1923 | iounmap(priv->wr_regs); | |
a65dd5b2 RC |
1924 | clean_cpsw_wr_iores_ret: |
1925 | release_mem_region(priv->cpsw_wr_res->start, | |
1926 | resource_size(priv->cpsw_wr_res)); | |
5250c969 RC |
1927 | clean_iomap_ret: |
1928 | iounmap(priv->regs); | |
df828598 M |
1929 | clean_cpsw_iores_ret: |
1930 | release_mem_region(priv->cpsw_res->start, | |
1931 | resource_size(priv->cpsw_res)); | |
1932 | clean_clk_ret: | |
1933 | clk_put(priv->clk); | |
f150bd7f M |
1934 | clean_slave_ret: |
1935 | pm_runtime_disable(&pdev->dev); | |
df828598 M |
1936 | kfree(priv->slaves); |
1937 | clean_ndev_ret: | |
d1bd9acf SS |
1938 | kfree(priv->data.slave_data); |
1939 | free_netdev(priv->ndev); | |
df828598 M |
1940 | return ret; |
1941 | } | |
1942 | ||
663e12e6 | 1943 | static int cpsw_remove(struct platform_device *pdev) |
df828598 M |
1944 | { |
1945 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1946 | struct cpsw_priv *priv = netdev_priv(ndev); | |
d1bd9acf | 1947 | int i; |
df828598 | 1948 | |
d1bd9acf SS |
1949 | if (priv->data.dual_emac) |
1950 | unregister_netdev(cpsw_get_slave_ndev(priv, 1)); | |
1951 | unregister_netdev(ndev); | |
df828598 | 1952 | |
9232b16d | 1953 | cpts_unregister(priv->cpts); |
d1bd9acf SS |
1954 | for (i = 0; i < priv->num_irqs; i++) |
1955 | free_irq(priv->irqs_table[i], priv); | |
1956 | ||
df828598 M |
1957 | cpsw_ale_destroy(priv->ale); |
1958 | cpdma_chan_destroy(priv->txch); | |
1959 | cpdma_chan_destroy(priv->rxch); | |
1960 | cpdma_ctlr_destroy(priv->dma); | |
1961 | iounmap(priv->regs); | |
1962 | release_mem_region(priv->cpsw_res->start, | |
1963 | resource_size(priv->cpsw_res)); | |
5250c969 | 1964 | iounmap(priv->wr_regs); |
a65dd5b2 RC |
1965 | release_mem_region(priv->cpsw_wr_res->start, |
1966 | resource_size(priv->cpsw_wr_res)); | |
f150bd7f | 1967 | pm_runtime_disable(&pdev->dev); |
df828598 M |
1968 | clk_put(priv->clk); |
1969 | kfree(priv->slaves); | |
d1bd9acf SS |
1970 | kfree(priv->data.slave_data); |
1971 | if (priv->data.dual_emac) | |
1972 | free_netdev(cpsw_get_slave_ndev(priv, 1)); | |
df828598 | 1973 | free_netdev(ndev); |
df828598 M |
1974 | return 0; |
1975 | } | |
1976 | ||
1977 | static int cpsw_suspend(struct device *dev) | |
1978 | { | |
1979 | struct platform_device *pdev = to_platform_device(dev); | |
1980 | struct net_device *ndev = platform_get_drvdata(pdev); | |
b90fc27a | 1981 | struct cpsw_priv *priv = netdev_priv(ndev); |
df828598 M |
1982 | |
1983 | if (netif_running(ndev)) | |
1984 | cpsw_ndo_stop(ndev); | |
6d3d76f8 M |
1985 | soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset); |
1986 | soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); | |
f150bd7f M |
1987 | pm_runtime_put_sync(&pdev->dev); |
1988 | ||
739683b4 M |
1989 | /* Select sleep pin state */ |
1990 | pinctrl_pm_select_sleep_state(&pdev->dev); | |
1991 | ||
df828598 M |
1992 | return 0; |
1993 | } | |
1994 | ||
1995 | static int cpsw_resume(struct device *dev) | |
1996 | { | |
1997 | struct platform_device *pdev = to_platform_device(dev); | |
1998 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1999 | ||
f150bd7f | 2000 | pm_runtime_get_sync(&pdev->dev); |
739683b4 M |
2001 | |
2002 | /* Select default pin state */ | |
2003 | pinctrl_pm_select_default_state(&pdev->dev); | |
2004 | ||
df828598 M |
2005 | if (netif_running(ndev)) |
2006 | cpsw_ndo_open(ndev); | |
2007 | return 0; | |
2008 | } | |
2009 | ||
2010 | static const struct dev_pm_ops cpsw_pm_ops = { | |
2011 | .suspend = cpsw_suspend, | |
2012 | .resume = cpsw_resume, | |
2013 | }; | |
2014 | ||
2eb32b0a M |
2015 | static const struct of_device_id cpsw_of_mtable[] = { |
2016 | { .compatible = "ti,cpsw", }, | |
2017 | { /* sentinel */ }, | |
2018 | }; | |
4bc21d41 | 2019 | MODULE_DEVICE_TABLE(of, cpsw_of_mtable); |
2eb32b0a | 2020 | |
df828598 M |
2021 | static struct platform_driver cpsw_driver = { |
2022 | .driver = { | |
2023 | .name = "cpsw", | |
2024 | .owner = THIS_MODULE, | |
2025 | .pm = &cpsw_pm_ops, | |
2eb32b0a | 2026 | .of_match_table = of_match_ptr(cpsw_of_mtable), |
df828598 M |
2027 | }, |
2028 | .probe = cpsw_probe, | |
663e12e6 | 2029 | .remove = cpsw_remove, |
df828598 M |
2030 | }; |
2031 | ||
2032 | static int __init cpsw_init(void) | |
2033 | { | |
2034 | return platform_driver_register(&cpsw_driver); | |
2035 | } | |
2036 | late_initcall(cpsw_init); | |
2037 | ||
2038 | static void __exit cpsw_exit(void) | |
2039 | { | |
2040 | platform_driver_unregister(&cpsw_driver); | |
2041 | } | |
2042 | module_exit(cpsw_exit); | |
2043 | ||
2044 | MODULE_LICENSE("GPL"); | |
2045 | MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); | |
2046 | MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); | |
2047 | MODULE_DESCRIPTION("TI CPSW Ethernet driver"); |