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net: sctp: remove unused multiple cookie keys
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
2eb32b0a
M		 32#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
3b72c2fe 35#include <linux/if_vlan.h>
df828598
M		 36
37#include <linux/platform_data/cpsw.h>
38
39#include "cpsw_ale.h"
2e5b38ab 40#include "cpts.h"
df828598
M		 41#include "davinci_cpdma.h"
42
43#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
44 NETIF_MSG_DRV | NETIF_MSG_LINK | \
45 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
46 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
49 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
50 NETIF_MSG_RX_STATUS)
51
52#define cpsw_info(priv, type, format, ...) \
53do { \
54 if (netif_msg_##type(priv) && net_ratelimit()) \
55 dev_info(priv->dev, format, ## __VA_ARGS__); \
56} while (0)
57
58#define cpsw_err(priv, type, format, ...) \
59do { \
60 if (netif_msg_##type(priv) && net_ratelimit()) \
61 dev_err(priv->dev, format, ## __VA_ARGS__); \
62} while (0)
63
64#define cpsw_dbg(priv, type, format, ...) \
65do { \
66 if (netif_msg_##type(priv) && net_ratelimit()) \
67 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
68} while (0)
69
70#define cpsw_notice(priv, type, format, ...) \
71do { \
72 if (netif_msg_##type(priv) && net_ratelimit()) \
73 dev_notice(priv->dev, format, ## __VA_ARGS__); \
74} while (0)
75
5c50a856
M		 76#define ALE_ALL_PORTS 0x7
77
df828598
M		 78#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
79#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
80#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
81
e90cfac6
RC		 82#define CPSW_VERSION_1 0x19010a
83#define CPSW_VERSION_2 0x19010c
549985ee
RC		 84
85#define HOST_PORT_NUM 0
86#define SLIVER_SIZE 0x40
87
88#define CPSW1_HOST_PORT_OFFSET 0x028
89#define CPSW1_SLAVE_OFFSET 0x050
90#define CPSW1_SLAVE_SIZE 0x040
91#define CPSW1_CPDMA_OFFSET 0x100
92#define CPSW1_STATERAM_OFFSET 0x200
93#define CPSW1_CPTS_OFFSET 0x500
94#define CPSW1_ALE_OFFSET 0x600
95#define CPSW1_SLIVER_OFFSET 0x700
96
97#define CPSW2_HOST_PORT_OFFSET 0x108
98#define CPSW2_SLAVE_OFFSET 0x200
99#define CPSW2_SLAVE_SIZE 0x100
100#define CPSW2_CPDMA_OFFSET 0x800
101#define CPSW2_STATERAM_OFFSET 0xa00
102#define CPSW2_CPTS_OFFSET 0xc00
103#define CPSW2_ALE_OFFSET 0xd00
104#define CPSW2_SLIVER_OFFSET 0xd80
105#define CPSW2_BD_OFFSET 0x2000
106
df828598
M		 107#define CPDMA_RXTHRESH 0x0c0
108#define CPDMA_RXFREE 0x0e0
109#define CPDMA_TXHDP 0x00
110#define CPDMA_RXHDP 0x20
111#define CPDMA_TXCP 0x40
112#define CPDMA_RXCP 0x60
113
df828598
M		 114#define CPSW_POLL_WEIGHT 64
115#define CPSW_MIN_PACKET_SIZE 60
116#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
117
118#define RX_PRIORITY_MAPPING 0x76543210
119#define TX_PRIORITY_MAPPING 0x33221100
120#define CPDMA_TX_PRIORITY_MAP 0x76543210
121
3b72c2fe
M		 122#define CPSW_VLAN_AWARE BIT(1)
123#define CPSW_ALE_VLAN_AWARE 1
124
df828598
M		 125#define cpsw_enable_irq(priv) \
126 do { \
127 u32 i; \
128 for (i = 0; i < priv->num_irqs; i++) \
129 enable_irq(priv->irqs_table[i]); \
130 } while (0);
131#define cpsw_disable_irq(priv) \
132 do { \
133 u32 i; \
134 for (i = 0; i < priv->num_irqs; i++) \
135 disable_irq_nosync(priv->irqs_table[i]); \
136 } while (0);
137
138static int debug_level;
139module_param(debug_level, int, 0);
140MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
141
142static int ale_ageout = 10;
143module_param(ale_ageout, int, 0);
144MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
145
146static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
147module_param(rx_packet_max, int, 0);
148MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
149
996a5c27 150struct cpsw_wr_regs {
df828598
M		 151 u32 id_ver;
152 u32 soft_reset;
153 u32 control;
154 u32 int_control;
155 u32 rx_thresh_en;
156 u32 rx_en;
157 u32 tx_en;
158 u32 misc_en;
159};
160
996a5c27 161struct cpsw_ss_regs {
df828598
M		 162 u32 id_ver;
163 u32 control;
164 u32 soft_reset;
165 u32 stat_port_en;
166 u32 ptype;
bd357af2
RC		 167 u32 soft_idle;
168 u32 thru_rate;
169 u32 gap_thresh;
170 u32 tx_start_wds;
171 u32 flow_control;
172 u32 vlan_ltype;
173 u32 ts_ltype;
174 u32 dlr_ltype;
df828598
M		 175};
176
9750a3ad
RC		 177/* CPSW_PORT_V1 */
178#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
179#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
180#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
181#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
182#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
183#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
184#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
185#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
186
187/* CPSW_PORT_V2 */
188#define CPSW2_CONTROL 0x00 /* Control Register */
189#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
190#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
191#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
192#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
193#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
194#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
195
196/* CPSW_PORT_V1 and V2 */
197#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
198#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
199#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
200
201/* CPSW_PORT_V2 only */
202#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
203#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
204#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
205#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
206#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
207#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
208#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
209#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
210
211/* Bit definitions for the CPSW2_CONTROL register */
212#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
213#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
214#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
215#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
216#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
217#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
218#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
219#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
220#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
221#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
222#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
223#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
224#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
225#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
226#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
227#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
228
229#define CTRL_TS_BITS \
230 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
231 TS_ANNEX_D_EN | TS_LTYPE1_EN)
232
233#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
234#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
235#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
236
237/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
238#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
239#define TS_SEQ_ID_OFFSET_MASK (0x3f)
240#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
241#define TS_MSG_TYPE_EN_MASK (0xffff)
242
243/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
244#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 245
2e5b38ab
RC		 246/* Bit definitions for the CPSW1_TS_CTL register */
247#define CPSW_V1_TS_RX_EN BIT(0)
248#define CPSW_V1_TS_TX_EN BIT(4)
249#define CPSW_V1_MSG_TYPE_OFS 16
250
251/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
252#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
253
df828598
M		 254struct cpsw_host_regs {
255 u32 max_blks;
256 u32 blk_cnt;
257 u32 flow_thresh;
258 u32 port_vlan;
259 u32 tx_pri_map;
260 u32 cpdma_tx_pri_map;
261 u32 cpdma_rx_chan_map;
262};
263
264struct cpsw_sliver_regs {
265 u32 id_ver;
266 u32 mac_control;
267 u32 mac_status;
268 u32 soft_reset;
269 u32 rx_maxlen;
270 u32 __reserved_0;
271 u32 rx_pause;
272 u32 tx_pause;
273 u32 __reserved_1;
274 u32 rx_pri_map;
275};
276
277struct cpsw_slave {
9750a3ad 278 void __iomem *regs;
df828598
M		 279 struct cpsw_sliver_regs __iomem *sliver;
280 int slave_num;
281 u32 mac_control;
282 struct cpsw_slave_data *data;
283 struct phy_device *phy;
284};
285
9750a3ad
RC		 286static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
287{
288 return __raw_readl(slave->regs + offset);
289}
290
291static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
292{
293 __raw_writel(val, slave->regs + offset);
294}
295
df828598
M		 296struct cpsw_priv {
297 spinlock_t lock;
298 struct platform_device *pdev;
299 struct net_device *ndev;
300 struct resource *cpsw_res;
a65dd5b2 301 struct resource *cpsw_wr_res;
df828598
M		 302 struct napi_struct napi;
303 struct device *dev;
304 struct cpsw_platform_data data;
996a5c27
RC		 305 struct cpsw_ss_regs __iomem *regs;
306 struct cpsw_wr_regs __iomem *wr_regs;
df828598
M		 307 struct cpsw_host_regs __iomem *host_port_regs;
308 u32 msg_enable;
e90cfac6 309 u32 version;
df828598
M		 310 struct net_device_stats stats;
311 int rx_packet_max;
312 int host_port;
313 struct clk *clk;
314 u8 mac_addr[ETH_ALEN];
315 struct cpsw_slave *slaves;
316 struct cpdma_ctlr *dma;
317 struct cpdma_chan *txch, *rxch;
318 struct cpsw_ale *ale;
319 /* snapshot of IRQ numbers */
320 u32 irqs_table[4];
321 u32 num_irqs;
2e5b38ab 322 struct cpts cpts;
df828598
M		 323};
324
325#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
326#define for_each_slave(priv, func, arg...) \
327 do { \
328 int idx; \
329 for (idx = 0; idx < (priv)->data.slaves; idx++) \
330 (func)((priv)->slaves + idx, ##arg); \
331 } while (0)
332
5c50a856
M		 333static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
334{
335 struct cpsw_priv *priv = netdev_priv(ndev);
336
337 if (ndev->flags & IFF_PROMISC) {
338 /* Enable promiscuous mode */
339 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
340 return;
341 }
342
343 /* Clear all mcast from ALE */
344 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
345
346 if (!netdev_mc_empty(ndev)) {
347 struct netdev_hw_addr *ha;
348
349 /* program multicast address list into ALE register */
350 netdev_for_each_mc_addr(ha, ndev) {
351 cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr,
e11b220f 352 ALE_ALL_PORTS << priv->host_port, 0, 0, 0);
5c50a856
M		 353 }
354 }
355}
356
df828598
M		 357static void cpsw_intr_enable(struct cpsw_priv *priv)
358{
996a5c27
RC		 359 __raw_writel(0xFF, &priv->wr_regs->tx_en);
360 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 361
362 cpdma_ctlr_int_ctrl(priv->dma, true);
363 return;
364}
365
366static void cpsw_intr_disable(struct cpsw_priv *priv)
367{
996a5c27
RC		 368 __raw_writel(0, &priv->wr_regs->tx_en);
369 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 370
371 cpdma_ctlr_int_ctrl(priv->dma, false);
372 return;
373}
374
375void cpsw_tx_handler(void *token, int len, int status)
376{
377 struct sk_buff *skb = token;
378 struct net_device *ndev = skb->dev;
379 struct cpsw_priv *priv = netdev_priv(ndev);
380
fae50823
M		 381 /* Check whether the queue is stopped due to stalled tx dma, if the
382 * queue is stopped then start the queue as we have free desc for tx
383 */
df828598
M		 384 if (unlikely(netif_queue_stopped(ndev)))
385 netif_start_queue(ndev);
2e5b38ab 386 cpts_tx_timestamp(&priv->cpts, skb);
df828598
M		 387 priv->stats.tx_packets++;
388 priv->stats.tx_bytes += len;
389 dev_kfree_skb_any(skb);
390}
391
392void cpsw_rx_handler(void *token, int len, int status)
393{
394 struct sk_buff *skb = token;
395 struct net_device *ndev = skb->dev;
396 struct cpsw_priv *priv = netdev_priv(ndev);
397 int ret = 0;
398
399 /* free and bail if we are shutting down */
400 if (unlikely(!netif_running(ndev)) ||
401 unlikely(!netif_carrier_ok(ndev))) {
402 dev_kfree_skb_any(skb);
403 return;
404 }
405 if (likely(status >= 0)) {
406 skb_put(skb, len);
2e5b38ab 407 cpts_rx_timestamp(&priv->cpts, skb);
df828598
M		 408 skb->protocol = eth_type_trans(skb, ndev);
409 netif_receive_skb(skb);
410 priv->stats.rx_bytes += len;
411 priv->stats.rx_packets++;
412 skb = NULL;
413 }
414
415 if (unlikely(!netif_running(ndev))) {
416 if (skb)
417 dev_kfree_skb_any(skb);
418 return;
419 }
420
421 if (likely(!skb)) {
422 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
423 if (WARN_ON(!skb))
424 return;
425
426 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
427 skb_tailroom(skb), GFP_KERNEL);
428 }
429 WARN_ON(ret < 0);
430}
431
432static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
433{
434 struct cpsw_priv *priv = dev_id;
435
436 if (likely(netif_running(priv->ndev))) {
437 cpsw_intr_disable(priv);
438 cpsw_disable_irq(priv);
439 napi_schedule(&priv->napi);
440 }
441 return IRQ_HANDLED;
442}
443
444static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
445{
446 if (priv->host_port == 0)
447 return slave_num + 1;
448 else
449 return slave_num;
450}
451
452static int cpsw_poll(struct napi_struct *napi, int budget)
453{
454 struct cpsw_priv *priv = napi_to_priv(napi);
455 int num_tx, num_rx;
456
457 num_tx = cpdma_chan_process(priv->txch, 128);
458 num_rx = cpdma_chan_process(priv->rxch, budget);
459
460 if (num_rx || num_tx)
461 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
462 num_rx, num_tx);
463
464 if (num_rx < budget) {
465 napi_complete(napi);
466 cpsw_intr_enable(priv);
467 cpdma_ctlr_eoi(priv->dma);
468 cpsw_enable_irq(priv);
469 }
470
471 return num_rx;
472}
473
474static inline void soft_reset(const char *module, void __iomem *reg)
475{
476 unsigned long timeout = jiffies + HZ;
477
478 __raw_writel(1, reg);
479 do {
480 cpu_relax();
481 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
482
483 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
484}
485
486#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
487 ((mac)[2] << 16) | ((mac)[3] << 24))
488#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
489
490static void cpsw_set_slave_mac(struct cpsw_slave *slave,
491 struct cpsw_priv *priv)
492{
9750a3ad
RC		 493 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
494 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 495}
496
497static void _cpsw_adjust_link(struct cpsw_slave *slave,
498 struct cpsw_priv *priv, bool *link)
499{
500 struct phy_device *phy = slave->phy;
501 u32 mac_control = 0;
502 u32 slave_port;
503
504 if (!phy)
505 return;
506
507 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
508
509 if (phy->link) {
510 mac_control = priv->data.mac_control;
511
512 /* enable forwarding */
513 cpsw_ale_control_set(priv->ale, slave_port,
514 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
515
516 if (phy->speed == 1000)
517 mac_control |= BIT(7); /* GIGABITEN */
518 if (phy->duplex)
519 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 520
521 /* set speed_in input in case RMII mode is used in 100Mbps */
522 if (phy->speed == 100)
523 mac_control |= BIT(15);
524
df828598
M		 525 *link = true;
526 } else {
527 mac_control = 0;
528 /* disable forwarding */
529 cpsw_ale_control_set(priv->ale, slave_port,
530 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
531 }
532
533 if (mac_control != slave->mac_control) {
534 phy_print_status(phy);
535 __raw_writel(mac_control, &slave->sliver->mac_control);
536 }
537
538 slave->mac_control = mac_control;
539}
540
541static void cpsw_adjust_link(struct net_device *ndev)
542{
543 struct cpsw_priv *priv = netdev_priv(ndev);
544 bool link = false;
545
546 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
547
548 if (link) {
549 netif_carrier_on(ndev);
550 if (netif_running(ndev))
551 netif_wake_queue(ndev);
552 } else {
553 netif_carrier_off(ndev);
554 netif_stop_queue(ndev);
555 }
556}
557
558static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
559{
560 static char *leader = "........................................";
561
562 if (!val)
563 return 0;
564 else
565 return snprintf(buf, maxlen, "%s %s %10d\n", name,
566 leader + strlen(name), val);
567}
568
569static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
570{
571 char name[32];
572 u32 slave_port;
573
574 sprintf(name, "slave-%d", slave->slave_num);
575
576 soft_reset(name, &slave->sliver->soft_reset);
577
578 /* setup priority mapping */
579 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 580
581 switch (priv->version) {
582 case CPSW_VERSION_1:
583 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
584 break;
585 case CPSW_VERSION_2:
586 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
587 break;
588 }
df828598
M		 589
590 /* setup max packet size, and mac address */
591 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
592 cpsw_set_slave_mac(slave, priv);
593
594 slave->mac_control = 0; /* no link yet */
595
596 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
597
598 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
e11b220f 599 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598
M		 600
601 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 602 &cpsw_adjust_link, slave->data->phy_if);
df828598
M		 603 if (IS_ERR(slave->phy)) {
604 dev_err(priv->dev, "phy %s not found on slave %d\n",
605 slave->data->phy_id, slave->slave_num);
606 slave->phy = NULL;
607 } else {
608 dev_info(priv->dev, "phy found : id is : 0x%x\n",
609 slave->phy->phy_id);
610 phy_start(slave->phy);
611 }
612}
613
3b72c2fe
M		 614static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
615{
616 const int vlan = priv->data.default_vlan;
617 const int port = priv->host_port;
618 u32 reg;
619 int i;
620
621 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
622 CPSW2_PORT_VLAN;
623
624 writel(vlan, &priv->host_port_regs->port_vlan);
625
626 for (i = 0; i < 2; i++)
627 slave_write(priv->slaves + i, vlan, reg);
628
629 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
630 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
631 (ALE_PORT_1 | ALE_PORT_2) << port);
632}
633
df828598
M		 634static void cpsw_init_host_port(struct cpsw_priv *priv)
635{
3b72c2fe
M		 636 u32 control_reg;
637
df828598
M		 638 /* soft reset the controller and initialize ale */
639 soft_reset("cpsw", &priv->regs->soft_reset);
640 cpsw_ale_start(priv->ale);
641
642 /* switch to vlan unaware mode */
3b72c2fe
M		 643 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
644 CPSW_ALE_VLAN_AWARE);
645 control_reg = readl(&priv->regs->control);
646 control_reg |= CPSW_VLAN_AWARE;
647 writel(control_reg, &priv->regs->control);
df828598
M		 648
649 /* setup host port priority mapping */
650 __raw_writel(CPDMA_TX_PRIORITY_MAP,
651 &priv->host_port_regs->cpdma_tx_pri_map);
652 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
653
654 cpsw_ale_control_set(priv->ale, priv->host_port,
655 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
656
e11b220f 657 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0, 0);
df828598 658 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
e11b220f 659 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
df828598
M		 660}
661
662static int cpsw_ndo_open(struct net_device *ndev)
663{
664 struct cpsw_priv *priv = netdev_priv(ndev);
665 int i, ret;
666 u32 reg;
667
668 cpsw_intr_disable(priv);
669 netif_carrier_off(ndev);
670
f150bd7f 671 pm_runtime_get_sync(&priv->pdev->dev);
df828598 672
549985ee 673 reg = priv->version;
df828598
M		 674
675 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
676 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
677 CPSW_RTL_VERSION(reg));
678
679 /* initialize host and slave ports */
680 cpsw_init_host_port(priv);
681 for_each_slave(priv, cpsw_slave_open, priv);
682
3b72c2fe
M		 683 /* Add default VLAN */
684 cpsw_add_default_vlan(priv);
685
df828598
M		 686 /* setup tx dma to fixed prio and zero offset */
687 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
688 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
689
690 /* disable priority elevation and enable statistics on all ports */
691 __raw_writel(0, &priv->regs->ptype);
692
693 /* enable statistics collection only on the host port */
694 __raw_writel(0x7, &priv->regs->stat_port_en);
695
696 if (WARN_ON(!priv->data.rx_descs))
697 priv->data.rx_descs = 128;
698
699 for (i = 0; i < priv->data.rx_descs; i++) {
700 struct sk_buff *skb;
701
702 ret = -ENOMEM;
703 skb = netdev_alloc_skb_ip_align(priv->ndev,
704 priv->rx_packet_max);
705 if (!skb)
706 break;
707 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
708 skb_tailroom(skb), GFP_KERNEL);
709 if (WARN_ON(ret < 0))
710 break;
711 }
712 /* continue even if we didn't manage to submit all receive descs */
713 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
714
715 cpdma_ctlr_start(priv->dma);
716 cpsw_intr_enable(priv);
717 napi_enable(&priv->napi);
718 cpdma_ctlr_eoi(priv->dma);
719
720 return 0;
721}
722
723static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
724{
725 if (!slave->phy)
726 return;
727 phy_stop(slave->phy);
728 phy_disconnect(slave->phy);
729 slave->phy = NULL;
730}
731
732static int cpsw_ndo_stop(struct net_device *ndev)
733{
734 struct cpsw_priv *priv = netdev_priv(ndev);
735
736 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598
M		 737 netif_stop_queue(priv->ndev);
738 napi_disable(&priv->napi);
739 netif_carrier_off(priv->ndev);
71380f9b
M		 740 cpsw_intr_disable(priv);
741 cpdma_ctlr_int_ctrl(priv->dma, false);
742 cpdma_ctlr_stop(priv->dma);
df828598
M		 743 cpsw_ale_stop(priv->ale);
744 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 745 pm_runtime_put_sync(&priv->pdev->dev);
df828598
M		 746 return 0;
747}
748
749static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
750 struct net_device *ndev)
751{
752 struct cpsw_priv *priv = netdev_priv(ndev);
753 int ret;
754
755 ndev->trans_start = jiffies;
756
757 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
758 cpsw_err(priv, tx_err, "packet pad failed\n");
759 priv->stats.tx_dropped++;
760 return NETDEV_TX_OK;
761 }
762
2e5b38ab
RC		 763 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable)
764 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
765
766 skb_tx_timestamp(skb);
767
df828598
M		 768 ret = cpdma_chan_submit(priv->txch, skb, skb->data,
769 skb->len, GFP_KERNEL);
770 if (unlikely(ret != 0)) {
771 cpsw_err(priv, tx_err, "desc submit failed\n");
772 goto fail;
773 }
774
fae50823
M		 775 /* If there is no more tx desc left free then we need to
776 * tell the kernel to stop sending us tx frames.
777 */
778 if (unlikely(cpdma_check_free_tx_desc(priv->txch)))
779 netif_stop_queue(ndev);
780
df828598
M		 781 return NETDEV_TX_OK;
782fail:
783 priv->stats.tx_dropped++;
784 netif_stop_queue(ndev);
785 return NETDEV_TX_BUSY;
786}
787
788static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
789{
790 /*
791 * The switch cannot operate in promiscuous mode without substantial
792 * headache. For promiscuous mode to work, we would need to put the
793 * ALE in bypass mode and route all traffic to the host port.
794 * Subsequently, the host will need to operate as a "bridge", learn,
795 * and flood as needed. For now, we simply complain here and
796 * do nothing about it :-)
797 */
798 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
799 dev_err(&ndev->dev, "promiscuity ignored!\n");
800
801 /*
802 * The switch cannot filter multicast traffic unless it is configured
803 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
804 * whole bunch of additional logic that this driver does not implement
805 * at present.
806 */
807 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
808 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
809}
810
2e5b38ab
RC		 811#ifdef CONFIG_TI_CPTS
812
813static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
814{
815 struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
816 u32 ts_en, seq_id;
817
818 if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) {
819 slave_write(slave, 0, CPSW1_TS_CTL);
820 return;
821 }
822
823 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
824 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
825
826 if (priv->cpts.tx_enable)
827 ts_en |= CPSW_V1_TS_TX_EN;
828
829 if (priv->cpts.rx_enable)
830 ts_en |= CPSW_V1_TS_RX_EN;
831
832 slave_write(slave, ts_en, CPSW1_TS_CTL);
833 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
834}
835
836static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
837{
838 struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
839 u32 ctrl, mtype;
840
841 ctrl = slave_read(slave, CPSW2_CONTROL);
842 ctrl &= ~CTRL_ALL_TS_MASK;
843
844 if (priv->cpts.tx_enable)
845 ctrl |= CTRL_TX_TS_BITS;
846
847 if (priv->cpts.rx_enable)
848 ctrl |= CTRL_RX_TS_BITS;
849
850 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
851
852 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
853 slave_write(slave, ctrl, CPSW2_CONTROL);
854 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
855}
856
3177bf6f 857static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 858{
3177bf6f 859 struct cpsw_priv *priv = netdev_priv(dev);
2e5b38ab
RC		 860 struct cpts *cpts = &priv->cpts;
861 struct hwtstamp_config cfg;
862
863 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
864 return -EFAULT;
865
866 /* reserved for future extensions */
867 if (cfg.flags)
868 return -EINVAL;
869
870 switch (cfg.tx_type) {
871 case HWTSTAMP_TX_OFF:
872 cpts->tx_enable = 0;
873 break;
874 case HWTSTAMP_TX_ON:
875 cpts->tx_enable = 1;
876 break;
877 default:
878 return -ERANGE;
879 }
880
881 switch (cfg.rx_filter) {
882 case HWTSTAMP_FILTER_NONE:
883 cpts->rx_enable = 0;
884 break;
885 case HWTSTAMP_FILTER_ALL:
886 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
887 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
888 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
889 return -ERANGE;
890 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
891 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
892 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
893 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
894 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
895 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
896 case HWTSTAMP_FILTER_PTP_V2_EVENT:
897 case HWTSTAMP_FILTER_PTP_V2_SYNC:
898 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
899 cpts->rx_enable = 1;
900 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
901 break;
902 default:
903 return -ERANGE;
904 }
905
906 switch (priv->version) {
907 case CPSW_VERSION_1:
908 cpsw_hwtstamp_v1(priv);
909 break;
910 case CPSW_VERSION_2:
911 cpsw_hwtstamp_v2(priv);
912 break;
913 default:
914 return -ENOTSUPP;
915 }
916
917 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
918}
919
920#endif /*CONFIG_TI_CPTS*/
921
922static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
923{
2e5b38ab
RC		 924 if (!netif_running(dev))
925 return -EINVAL;
926
927#ifdef CONFIG_TI_CPTS
928 if (cmd == SIOCSHWTSTAMP)
3177bf6f 929 return cpsw_hwtstamp_ioctl(dev, req);
2e5b38ab
RC		 930#endif
931 return -ENOTSUPP;
932}
933
df828598
M		 934static void cpsw_ndo_tx_timeout(struct net_device *ndev)
935{
936 struct cpsw_priv *priv = netdev_priv(ndev);
937
938 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
939 priv->stats.tx_errors++;
940 cpsw_intr_disable(priv);
941 cpdma_ctlr_int_ctrl(priv->dma, false);
942 cpdma_chan_stop(priv->txch);
943 cpdma_chan_start(priv->txch);
944 cpdma_ctlr_int_ctrl(priv->dma, true);
945 cpsw_intr_enable(priv);
946 cpdma_ctlr_eoi(priv->dma);
947}
948
949static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
950{
951 struct cpsw_priv *priv = netdev_priv(ndev);
952 return &priv->stats;
953}
954
955#ifdef CONFIG_NET_POLL_CONTROLLER
956static void cpsw_ndo_poll_controller(struct net_device *ndev)
957{
958 struct cpsw_priv *priv = netdev_priv(ndev);
959
960 cpsw_intr_disable(priv);
961 cpdma_ctlr_int_ctrl(priv->dma, false);
962 cpsw_interrupt(ndev->irq, priv);
963 cpdma_ctlr_int_ctrl(priv->dma, true);
964 cpsw_intr_enable(priv);
965 cpdma_ctlr_eoi(priv->dma);
966}
967#endif
968
3b72c2fe
M		 969static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
970 unsigned short vid)
971{
972 int ret;
973
974 ret = cpsw_ale_add_vlan(priv->ale, vid,
975 ALE_ALL_PORTS << priv->host_port,
976 0, ALE_ALL_PORTS << priv->host_port,
977 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
978 if (ret != 0)
979 return ret;
980
981 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
982 priv->host_port, ALE_VLAN, vid);
983 if (ret != 0)
984 goto clean_vid;
985
986 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
987 ALE_ALL_PORTS << priv->host_port,
988 ALE_VLAN, vid, 0);
989 if (ret != 0)
990 goto clean_vlan_ucast;
991 return 0;
992
993clean_vlan_ucast:
994 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
995 priv->host_port, ALE_VLAN, vid);
996clean_vid:
997 cpsw_ale_del_vlan(priv->ale, vid, 0);
998 return ret;
999}
1000
1001static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1002 unsigned short vid)
1003{
1004 struct cpsw_priv *priv = netdev_priv(ndev);
1005
1006 if (vid == priv->data.default_vlan)
1007 return 0;
1008
1009 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1010 return cpsw_add_vlan_ale_entry(priv, vid);
1011}
1012
1013static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1014 unsigned short vid)
1015{
1016 struct cpsw_priv *priv = netdev_priv(ndev);
1017 int ret;
1018
1019 if (vid == priv->data.default_vlan)
1020 return 0;
1021
1022 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1023 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1024 if (ret != 0)
1025 return ret;
1026
1027 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1028 priv->host_port, ALE_VLAN, vid);
1029 if (ret != 0)
1030 return ret;
1031
1032 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1033 0, ALE_VLAN, vid);
1034}
1035
df828598
M		 1036static const struct net_device_ops cpsw_netdev_ops = {
1037 .ndo_open = cpsw_ndo_open,
1038 .ndo_stop = cpsw_ndo_stop,
1039 .ndo_start_xmit = cpsw_ndo_start_xmit,
1040 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
2e5b38ab 1041 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1042 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1043 .ndo_change_mtu = eth_change_mtu,
df828598
M		 1044 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1045 .ndo_get_stats = cpsw_ndo_get_stats,
5c50a856 1046 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1047#ifdef CONFIG_NET_POLL_CONTROLLER
1048 .ndo_poll_controller = cpsw_ndo_poll_controller,
1049#endif
3b72c2fe
M		 1050 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1051 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1052};
1053
1054static void cpsw_get_drvinfo(struct net_device *ndev,
1055 struct ethtool_drvinfo *info)
1056{
1057 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f
JP		 1058
1059 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1060 strlcpy(info->version, "1.0", sizeof(info->version));
1061 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
df828598
M		 1062}
1063
1064static u32 cpsw_get_msglevel(struct net_device *ndev)
1065{
1066 struct cpsw_priv *priv = netdev_priv(ndev);
1067 return priv->msg_enable;
1068}
1069
1070static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1071{
1072 struct cpsw_priv *priv = netdev_priv(ndev);
1073 priv->msg_enable = value;
1074}
1075
2e5b38ab
RC		 1076static int cpsw_get_ts_info(struct net_device *ndev,
1077 struct ethtool_ts_info *info)
1078{
1079#ifdef CONFIG_TI_CPTS
1080 struct cpsw_priv *priv = netdev_priv(ndev);
1081
1082 info->so_timestamping =
1083 SOF_TIMESTAMPING_TX_HARDWARE |
1084 SOF_TIMESTAMPING_TX_SOFTWARE |
1085 SOF_TIMESTAMPING_RX_HARDWARE |
1086 SOF_TIMESTAMPING_RX_SOFTWARE |
1087 SOF_TIMESTAMPING_SOFTWARE |
1088 SOF_TIMESTAMPING_RAW_HARDWARE;
1089 info->phc_index = priv->cpts.phc_index;
1090 info->tx_types =
1091 (1 << HWTSTAMP_TX_OFF) |
1092 (1 << HWTSTAMP_TX_ON);
1093 info->rx_filters =
1094 (1 << HWTSTAMP_FILTER_NONE) |
1095 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1096#else
1097 info->so_timestamping =
1098 SOF_TIMESTAMPING_TX_SOFTWARE |
1099 SOF_TIMESTAMPING_RX_SOFTWARE |
1100 SOF_TIMESTAMPING_SOFTWARE;
1101 info->phc_index = -1;
1102 info->tx_types = 0;
1103 info->rx_filters = 0;
1104#endif
1105 return 0;
1106}
1107
df828598
M		 1108static const struct ethtool_ops cpsw_ethtool_ops = {
1109 .get_drvinfo = cpsw_get_drvinfo,
1110 .get_msglevel = cpsw_get_msglevel,
1111 .set_msglevel = cpsw_set_msglevel,
1112 .get_link = ethtool_op_get_link,
2e5b38ab 1113 .get_ts_info = cpsw_get_ts_info,
df828598
M		 1114};
1115
549985ee
RC		 1116static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1117 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1118{
1119 void __iomem *regs = priv->regs;
1120 int slave_num = slave->slave_num;
1121 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1122
1123 slave->data = data;
549985ee
RC		 1124 slave->regs = regs + slave_reg_ofs;
1125 slave->sliver = regs + sliver_reg_ofs;
df828598
M		 1126}
1127
2eb32b0a
M		 1128static int cpsw_probe_dt(struct cpsw_platform_data *data,
1129 struct platform_device *pdev)
1130{
1131 struct device_node *node = pdev->dev.of_node;
1132 struct device_node *slave_node;
1133 int i = 0, ret;
1134 u32 prop;
1135
1136 if (!node)
1137 return -EINVAL;
1138
1139 if (of_property_read_u32(node, "slaves", &prop)) {
1140 pr_err("Missing slaves property in the DT.\n");
1141 return -EINVAL;
1142 }
1143 data->slaves = prop;
1144
78ca0b28
RC		 1145 if (of_property_read_u32(node, "cpts_active_slave", &prop)) {
1146 pr_err("Missing cpts_active_slave property in the DT.\n");
1147 ret = -EINVAL;
1148 goto error_ret;
1149 }
1150 data->cpts_active_slave = prop;
1151
00ab94ee
RC		 1152 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1153 pr_err("Missing cpts_clock_mult property in the DT.\n");
1154 ret = -EINVAL;
1155 goto error_ret;
1156 }
1157 data->cpts_clock_mult = prop;
1158
1159 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1160 pr_err("Missing cpts_clock_shift property in the DT.\n");
1161 ret = -EINVAL;
1162 goto error_ret;
1163 }
1164 data->cpts_clock_shift = prop;
1165
b2adaca9
JP		 1166 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1167 GFP_KERNEL);
1168 if (!data->slave_data)
2eb32b0a 1169 return -EINVAL;
2eb32b0a 1170
2eb32b0a
M		 1171 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1172 pr_err("Missing cpdma_channels property in the DT.\n");
1173 ret = -EINVAL;
1174 goto error_ret;
1175 }
1176 data->channels = prop;
1177
2eb32b0a
M		 1178 if (of_property_read_u32(node, "ale_entries", &prop)) {
1179 pr_err("Missing ale_entries property in the DT.\n");
1180 ret = -EINVAL;
1181 goto error_ret;
1182 }
1183 data->ale_entries = prop;
1184
2eb32b0a
M		 1185 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1186 pr_err("Missing bd_ram_size property in the DT.\n");
1187 ret = -EINVAL;
1188 goto error_ret;
1189 }
1190 data->bd_ram_size = prop;
1191
1192 if (of_property_read_u32(node, "rx_descs", &prop)) {
1193 pr_err("Missing rx_descs property in the DT.\n");
1194 ret = -EINVAL;
1195 goto error_ret;
1196 }
1197 data->rx_descs = prop;
1198
1199 if (of_property_read_u32(node, "mac_control", &prop)) {
1200 pr_err("Missing mac_control property in the DT.\n");
1201 ret = -EINVAL;
1202 goto error_ret;
1203 }
1204 data->mac_control = prop;
1205
549985ee
RC		 1206 /*
1207 * Populate all the child nodes here...
1208 */
1209 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1210 /* We do not want to force this, as in some cases may not have child */
1211 if (ret)
1212 pr_warn("Doesn't have any child node\n");
1213
1fb19aa7 1214 for_each_node_by_name(slave_node, "slave") {
2eb32b0a 1215 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 1216 const void *mac_addr = NULL;
549985ee
RC		 1217 u32 phyid;
1218 int lenp;
1219 const __be32 *parp;
1220 struct device_node *mdio_node;
1221 struct platform_device *mdio;
1222
1223 parp = of_get_property(slave_node, "phy_id", &lenp);
1224 if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) {
2eb32b0a
M		 1225 pr_err("Missing slave[%d] phy_id property\n", i);
1226 ret = -EINVAL;
1227 goto error_ret;
1228 }
549985ee
RC		 1229 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1230 phyid = be32_to_cpup(parp+1);
1231 mdio = of_find_device_by_node(mdio_node);
1232 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1233 PHY_ID_FMT, mdio->name, phyid);
2eb32b0a
M		 1234
1235 mac_addr = of_get_mac_address(slave_node);
1236 if (mac_addr)
1237 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1238
1239 i++;
1240 }
1241
1242 return 0;
1243
1244error_ret:
1245 kfree(data->slave_data);
1246 return ret;
1247}
1248
663e12e6 1249static int cpsw_probe(struct platform_device *pdev)
df828598
M		 1250{
1251 struct cpsw_platform_data *data = pdev->dev.platform_data;
1252 struct net_device *ndev;
1253 struct cpsw_priv *priv;
1254 struct cpdma_params dma_params;
1255 struct cpsw_ale_params ale_params;
549985ee 1256 void __iomem *ss_regs, *wr_regs;
df828598 1257 struct resource *res;
549985ee 1258 u32 slave_offset, sliver_offset, slave_size;
df828598
M		 1259 int ret = 0, i, k = 0;
1260
df828598
M		 1261 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1262 if (!ndev) {
1263 pr_err("error allocating net_device\n");
1264 return -ENOMEM;
1265 }
1266
1267 platform_set_drvdata(pdev, ndev);
1268 priv = netdev_priv(ndev);
1269 spin_lock_init(&priv->lock);
df828598
M		 1270 priv->pdev = pdev;
1271 priv->ndev = ndev;
1272 priv->dev = &ndev->dev;
1273 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1274 priv->rx_packet_max = max(rx_packet_max, 128);
1275
1fb19aa7
VH		 1276 /*
1277 * This may be required here for child devices.
1278 */
1279 pm_runtime_enable(&pdev->dev);
1280
2eb32b0a
M		 1281 if (cpsw_probe_dt(&priv->data, pdev)) {
1282 pr_err("cpsw: platform data missing\n");
1283 ret = -ENODEV;
1284 goto clean_ndev_ret;
1285 }
1286 data = &priv->data;
1287
df828598
M		 1288 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1289 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1290 pr_info("Detected MACID = %pM", priv->mac_addr);
1291 } else {
7efd26d0 1292 eth_random_addr(priv->mac_addr);
df828598
M		 1293 pr_info("Random MACID = %pM", priv->mac_addr);
1294 }
1295
1296 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1297
1298 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1299 GFP_KERNEL);
1300 if (!priv->slaves) {
1301 ret = -EBUSY;
1302 goto clean_ndev_ret;
1303 }
1304 for (i = 0; i < data->slaves; i++)
1305 priv->slaves[i].slave_num = i;
1306
f150bd7f 1307 priv->clk = clk_get(&pdev->dev, "fck");
df828598 1308 if (IS_ERR(priv->clk)) {
f150bd7f
M		 1309 dev_err(&pdev->dev, "fck is not found\n");
1310 ret = -ENODEV;
1311 goto clean_slave_ret;
df828598
M		 1312 }
1313
1314 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1315 if (!priv->cpsw_res) {
1316 dev_err(priv->dev, "error getting i/o resource\n");
1317 ret = -ENOENT;
1318 goto clean_clk_ret;
1319 }
df828598
M		 1320 if (!request_mem_region(priv->cpsw_res->start,
1321 resource_size(priv->cpsw_res), ndev->name)) {
1322 dev_err(priv->dev, "failed request i/o region\n");
1323 ret = -ENXIO;
1324 goto clean_clk_ret;
1325 }
549985ee
RC		 1326 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1327 if (!ss_regs) {
df828598
M		 1328 dev_err(priv->dev, "unable to map i/o region\n");
1329 goto clean_cpsw_iores_ret;
1330 }
549985ee
RC		 1331 priv->regs = ss_regs;
1332 priv->version = __raw_readl(&priv->regs->id_ver);
1333 priv->host_port = HOST_PORT_NUM;
df828598 1334
a65dd5b2
RC		 1335 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1336 if (!priv->cpsw_wr_res) {
df828598
M		 1337 dev_err(priv->dev, "error getting i/o resource\n");
1338 ret = -ENOENT;
5250c969 1339 goto clean_iomap_ret;
df828598 1340 }
a65dd5b2
RC		 1341 if (!request_mem_region(priv->cpsw_wr_res->start,
1342 resource_size(priv->cpsw_wr_res), ndev->name)) {
df828598
M		 1343 dev_err(priv->dev, "failed request i/o region\n");
1344 ret = -ENXIO;
5250c969 1345 goto clean_iomap_ret;
df828598 1346 }
549985ee 1347 wr_regs = ioremap(priv->cpsw_wr_res->start,
a65dd5b2 1348 resource_size(priv->cpsw_wr_res));
549985ee 1349 if (!wr_regs) {
df828598 1350 dev_err(priv->dev, "unable to map i/o region\n");
a65dd5b2 1351 goto clean_cpsw_wr_iores_ret;
df828598 1352 }
549985ee 1353 priv->wr_regs = wr_regs;
df828598
M		 1354
1355 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 1356 memset(&ale_params, 0, sizeof(ale_params));
1357
1358 switch (priv->version) {
1359 case CPSW_VERSION_1:
1360 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
1361 priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET;
1362 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
1363 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
1364 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
1365 slave_offset = CPSW1_SLAVE_OFFSET;
1366 slave_size = CPSW1_SLAVE_SIZE;
1367 sliver_offset = CPSW1_SLIVER_OFFSET;
1368 dma_params.desc_mem_phys = 0;
1369 break;
1370 case CPSW_VERSION_2:
1371 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
1372 priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET;
1373 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
1374 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
1375 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
1376 slave_offset = CPSW2_SLAVE_OFFSET;
1377 slave_size = CPSW2_SLAVE_SIZE;
1378 sliver_offset = CPSW2_SLIVER_OFFSET;
1379 dma_params.desc_mem_phys =
1380 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
1381 break;
1382 default:
1383 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
1384 ret = -ENODEV;
1385 goto clean_cpsw_wr_iores_ret;
1386 }
1387 for (i = 0; i < priv->data.slaves; i++) {
1388 struct cpsw_slave *slave = &priv->slaves[i];
1389 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
1390 slave_offset += slave_size;
1391 sliver_offset += SLIVER_SIZE;
1392 }
1393
df828598 1394 dma_params.dev = &pdev->dev;
549985ee
RC		 1395 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
1396 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
1397 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
1398 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
1399 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 1400
1401 dma_params.num_chan = data->channels;
1402 dma_params.has_soft_reset = true;
1403 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
1404 dma_params.desc_mem_size = data->bd_ram_size;
1405 dma_params.desc_align = 16;
1406 dma_params.has_ext_regs = true;
549985ee 1407 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 1408
1409 priv->dma = cpdma_ctlr_create(&dma_params);
1410 if (!priv->dma) {
1411 dev_err(priv->dev, "error initializing dma\n");
1412 ret = -ENOMEM;
5250c969 1413 goto clean_wr_iomap_ret;
df828598
M		 1414 }
1415
1416 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1417 cpsw_tx_handler);
1418 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1419 cpsw_rx_handler);
1420
1421 if (WARN_ON(!priv->txch || !priv->rxch)) {
1422 dev_err(priv->dev, "error initializing dma channels\n");
1423 ret = -ENOMEM;
1424 goto clean_dma_ret;
1425 }
1426
df828598 1427 ale_params.dev = &ndev->dev;
df828598
M		 1428 ale_params.ale_ageout = ale_ageout;
1429 ale_params.ale_entries = data->ale_entries;
1430 ale_params.ale_ports = data->slaves;
1431
1432 priv->ale = cpsw_ale_create(&ale_params);
1433 if (!priv->ale) {
1434 dev_err(priv->dev, "error initializing ale engine\n");
1435 ret = -ENODEV;
1436 goto clean_dma_ret;
1437 }
1438
1439 ndev->irq = platform_get_irq(pdev, 0);
1440 if (ndev->irq < 0) {
1441 dev_err(priv->dev, "error getting irq resource\n");
1442 ret = -ENOENT;
1443 goto clean_ale_ret;
1444 }
1445
1446 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1447 for (i = res->start; i <= res->end; i++) {
1448 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1449 dev_name(&pdev->dev), priv)) {
1450 dev_err(priv->dev, "error attaching irq\n");
1451 goto clean_ale_ret;
1452 }
1453 priv->irqs_table[k] = i;
1454 priv->num_irqs = k;
1455 }
1456 k++;
1457 }
1458
3b72c2fe 1459 ndev->features |= NETIF_F_HW_VLAN_FILTER;
df828598
M		 1460
1461 ndev->netdev_ops = &cpsw_netdev_ops;
1462 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1463 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1464
1465 /* register the network device */
1466 SET_NETDEV_DEV(ndev, &pdev->dev);
1467 ret = register_netdev(ndev);
1468 if (ret) {
1469 dev_err(priv->dev, "error registering net device\n");
1470 ret = -ENODEV;
1471 goto clean_irq_ret;
1472 }
1473
2e5b38ab
RC		 1474 if (cpts_register(&pdev->dev, &priv->cpts,
1475 data->cpts_clock_mult, data->cpts_clock_shift))
1476 dev_err(priv->dev, "error registering cpts device\n");
1477
df828598
M		 1478 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1479 priv->cpsw_res->start, ndev->irq);
1480
1481 return 0;
1482
1483clean_irq_ret:
1484 free_irq(ndev->irq, priv);
1485clean_ale_ret:
1486 cpsw_ale_destroy(priv->ale);
1487clean_dma_ret:
1488 cpdma_chan_destroy(priv->txch);
1489 cpdma_chan_destroy(priv->rxch);
1490 cpdma_ctlr_destroy(priv->dma);
5250c969
RC		 1491clean_wr_iomap_ret:
1492 iounmap(priv->wr_regs);
a65dd5b2
RC		 1493clean_cpsw_wr_iores_ret:
1494 release_mem_region(priv->cpsw_wr_res->start,
1495 resource_size(priv->cpsw_wr_res));
5250c969
RC		 1496clean_iomap_ret:
1497 iounmap(priv->regs);
df828598
M		 1498clean_cpsw_iores_ret:
1499 release_mem_region(priv->cpsw_res->start,
1500 resource_size(priv->cpsw_res));
1501clean_clk_ret:
1502 clk_put(priv->clk);
f150bd7f
M		 1503clean_slave_ret:
1504 pm_runtime_disable(&pdev->dev);
df828598
M		 1505 kfree(priv->slaves);
1506clean_ndev_ret:
1507 free_netdev(ndev);
1508 return ret;
1509}
1510
663e12e6 1511static int cpsw_remove(struct platform_device *pdev)
df828598
M		 1512{
1513 struct net_device *ndev = platform_get_drvdata(pdev);
1514 struct cpsw_priv *priv = netdev_priv(ndev);
1515
1516 pr_info("removing device");
1517 platform_set_drvdata(pdev, NULL);
1518
2e5b38ab 1519 cpts_unregister(&priv->cpts);
df828598
M		 1520 free_irq(ndev->irq, priv);
1521 cpsw_ale_destroy(priv->ale);
1522 cpdma_chan_destroy(priv->txch);
1523 cpdma_chan_destroy(priv->rxch);
1524 cpdma_ctlr_destroy(priv->dma);
1525 iounmap(priv->regs);
1526 release_mem_region(priv->cpsw_res->start,
1527 resource_size(priv->cpsw_res));
5250c969 1528 iounmap(priv->wr_regs);
a65dd5b2
RC		 1529 release_mem_region(priv->cpsw_wr_res->start,
1530 resource_size(priv->cpsw_wr_res));
f150bd7f 1531 pm_runtime_disable(&pdev->dev);
df828598
M		 1532 clk_put(priv->clk);
1533 kfree(priv->slaves);
1534 free_netdev(ndev);
1535
1536 return 0;
1537}
1538
1539static int cpsw_suspend(struct device *dev)
1540{
1541 struct platform_device *pdev = to_platform_device(dev);
1542 struct net_device *ndev = platform_get_drvdata(pdev);
1543
1544 if (netif_running(ndev))
1545 cpsw_ndo_stop(ndev);
f150bd7f
M		 1546 pm_runtime_put_sync(&pdev->dev);
1547
df828598
M		 1548 return 0;
1549}
1550
1551static int cpsw_resume(struct device *dev)
1552{
1553 struct platform_device *pdev = to_platform_device(dev);
1554 struct net_device *ndev = platform_get_drvdata(pdev);
1555
f150bd7f 1556 pm_runtime_get_sync(&pdev->dev);
df828598
M		 1557 if (netif_running(ndev))
1558 cpsw_ndo_open(ndev);
1559 return 0;
1560}
1561
1562static const struct dev_pm_ops cpsw_pm_ops = {
1563 .suspend = cpsw_suspend,
1564 .resume = cpsw_resume,
1565};
1566
2eb32b0a
M		 1567static const struct of_device_id cpsw_of_mtable[] = {
1568 { .compatible = "ti,cpsw", },
1569 { /* sentinel */ },
1570};
1571
df828598
M		 1572static struct platform_driver cpsw_driver = {
1573 .driver = {
1574 .name = "cpsw",
1575 .owner = THIS_MODULE,
1576 .pm = &cpsw_pm_ops,
2eb32b0a 1577 .of_match_table = of_match_ptr(cpsw_of_mtable),
df828598
M		 1578 },
1579 .probe = cpsw_probe,
663e12e6 1580 .remove = cpsw_remove,
df828598
M		 1581};
1582
1583static int __init cpsw_init(void)
1584{
1585 return platform_driver_register(&cpsw_driver);
1586}
1587late_initcall(cpsw_init);
1588
1589static void __exit cpsw_exit(void)
1590{
1591 platform_driver_unregister(&cpsw_driver);
1592}
1593module_exit(cpsw_exit);
1594
1595MODULE_LICENSE("GPL");
1596MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
1597MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
1598MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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