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df828598 M |
1 | /* |
2 | * Texas Instruments Ethernet Switch Driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/timer.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/irqreturn.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/netdevice.h> | |
2e5b38ab | 27 | #include <linux/net_tstamp.h> |
df828598 M |
28 | #include <linux/phy.h> |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/delay.h> | |
f150bd7f | 31 | #include <linux/pm_runtime.h> |
2eb32b0a M |
32 | #include <linux/of.h> |
33 | #include <linux/of_net.h> | |
34 | #include <linux/of_device.h> | |
3b72c2fe | 35 | #include <linux/if_vlan.h> |
df828598 M |
36 | |
37 | #include <linux/platform_data/cpsw.h> | |
38 | ||
39 | #include "cpsw_ale.h" | |
2e5b38ab | 40 | #include "cpts.h" |
df828598 M |
41 | #include "davinci_cpdma.h" |
42 | ||
43 | #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ | |
44 | NETIF_MSG_DRV | NETIF_MSG_LINK | \ | |
45 | NETIF_MSG_IFUP | NETIF_MSG_INTR | \ | |
46 | NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ | |
47 | NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ | |
48 | NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ | |
49 | NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ | |
50 | NETIF_MSG_RX_STATUS) | |
51 | ||
52 | #define cpsw_info(priv, type, format, ...) \ | |
53 | do { \ | |
54 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
55 | dev_info(priv->dev, format, ## __VA_ARGS__); \ | |
56 | } while (0) | |
57 | ||
58 | #define cpsw_err(priv, type, format, ...) \ | |
59 | do { \ | |
60 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
61 | dev_err(priv->dev, format, ## __VA_ARGS__); \ | |
62 | } while (0) | |
63 | ||
64 | #define cpsw_dbg(priv, type, format, ...) \ | |
65 | do { \ | |
66 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
67 | dev_dbg(priv->dev, format, ## __VA_ARGS__); \ | |
68 | } while (0) | |
69 | ||
70 | #define cpsw_notice(priv, type, format, ...) \ | |
71 | do { \ | |
72 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
73 | dev_notice(priv->dev, format, ## __VA_ARGS__); \ | |
74 | } while (0) | |
75 | ||
5c50a856 M |
76 | #define ALE_ALL_PORTS 0x7 |
77 | ||
df828598 M |
78 | #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) |
79 | #define CPSW_MINOR_VERSION(reg) (reg & 0xff) | |
80 | #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) | |
81 | ||
e90cfac6 RC |
82 | #define CPSW_VERSION_1 0x19010a |
83 | #define CPSW_VERSION_2 0x19010c | |
549985ee RC |
84 | |
85 | #define HOST_PORT_NUM 0 | |
86 | #define SLIVER_SIZE 0x40 | |
87 | ||
88 | #define CPSW1_HOST_PORT_OFFSET 0x028 | |
89 | #define CPSW1_SLAVE_OFFSET 0x050 | |
90 | #define CPSW1_SLAVE_SIZE 0x040 | |
91 | #define CPSW1_CPDMA_OFFSET 0x100 | |
92 | #define CPSW1_STATERAM_OFFSET 0x200 | |
93 | #define CPSW1_CPTS_OFFSET 0x500 | |
94 | #define CPSW1_ALE_OFFSET 0x600 | |
95 | #define CPSW1_SLIVER_OFFSET 0x700 | |
96 | ||
97 | #define CPSW2_HOST_PORT_OFFSET 0x108 | |
98 | #define CPSW2_SLAVE_OFFSET 0x200 | |
99 | #define CPSW2_SLAVE_SIZE 0x100 | |
100 | #define CPSW2_CPDMA_OFFSET 0x800 | |
101 | #define CPSW2_STATERAM_OFFSET 0xa00 | |
102 | #define CPSW2_CPTS_OFFSET 0xc00 | |
103 | #define CPSW2_ALE_OFFSET 0xd00 | |
104 | #define CPSW2_SLIVER_OFFSET 0xd80 | |
105 | #define CPSW2_BD_OFFSET 0x2000 | |
106 | ||
df828598 M |
107 | #define CPDMA_RXTHRESH 0x0c0 |
108 | #define CPDMA_RXFREE 0x0e0 | |
109 | #define CPDMA_TXHDP 0x00 | |
110 | #define CPDMA_RXHDP 0x20 | |
111 | #define CPDMA_TXCP 0x40 | |
112 | #define CPDMA_RXCP 0x60 | |
113 | ||
df828598 M |
114 | #define CPSW_POLL_WEIGHT 64 |
115 | #define CPSW_MIN_PACKET_SIZE 60 | |
116 | #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) | |
117 | ||
118 | #define RX_PRIORITY_MAPPING 0x76543210 | |
119 | #define TX_PRIORITY_MAPPING 0x33221100 | |
120 | #define CPDMA_TX_PRIORITY_MAP 0x76543210 | |
121 | ||
3b72c2fe M |
122 | #define CPSW_VLAN_AWARE BIT(1) |
123 | #define CPSW_ALE_VLAN_AWARE 1 | |
124 | ||
d9ba8f9e M |
125 | #define CPSW_FIFO_NORMAL_MODE (0 << 15) |
126 | #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) | |
127 | #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) | |
128 | ||
df828598 M |
129 | #define cpsw_enable_irq(priv) \ |
130 | do { \ | |
131 | u32 i; \ | |
132 | for (i = 0; i < priv->num_irqs; i++) \ | |
133 | enable_irq(priv->irqs_table[i]); \ | |
134 | } while (0); | |
135 | #define cpsw_disable_irq(priv) \ | |
136 | do { \ | |
137 | u32 i; \ | |
138 | for (i = 0; i < priv->num_irqs; i++) \ | |
139 | disable_irq_nosync(priv->irqs_table[i]); \ | |
140 | } while (0); | |
141 | ||
142 | static int debug_level; | |
143 | module_param(debug_level, int, 0); | |
144 | MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); | |
145 | ||
146 | static int ale_ageout = 10; | |
147 | module_param(ale_ageout, int, 0); | |
148 | MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); | |
149 | ||
150 | static int rx_packet_max = CPSW_MAX_PACKET_SIZE; | |
151 | module_param(rx_packet_max, int, 0); | |
152 | MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); | |
153 | ||
996a5c27 | 154 | struct cpsw_wr_regs { |
df828598 M |
155 | u32 id_ver; |
156 | u32 soft_reset; | |
157 | u32 control; | |
158 | u32 int_control; | |
159 | u32 rx_thresh_en; | |
160 | u32 rx_en; | |
161 | u32 tx_en; | |
162 | u32 misc_en; | |
163 | }; | |
164 | ||
996a5c27 | 165 | struct cpsw_ss_regs { |
df828598 M |
166 | u32 id_ver; |
167 | u32 control; | |
168 | u32 soft_reset; | |
169 | u32 stat_port_en; | |
170 | u32 ptype; | |
bd357af2 RC |
171 | u32 soft_idle; |
172 | u32 thru_rate; | |
173 | u32 gap_thresh; | |
174 | u32 tx_start_wds; | |
175 | u32 flow_control; | |
176 | u32 vlan_ltype; | |
177 | u32 ts_ltype; | |
178 | u32 dlr_ltype; | |
df828598 M |
179 | }; |
180 | ||
9750a3ad RC |
181 | /* CPSW_PORT_V1 */ |
182 | #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ | |
183 | #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ | |
184 | #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ | |
185 | #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ | |
186 | #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ | |
187 | #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ | |
188 | #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ | |
189 | #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ | |
190 | ||
191 | /* CPSW_PORT_V2 */ | |
192 | #define CPSW2_CONTROL 0x00 /* Control Register */ | |
193 | #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ | |
194 | #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ | |
195 | #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ | |
196 | #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ | |
197 | #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ | |
198 | #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ | |
199 | ||
200 | /* CPSW_PORT_V1 and V2 */ | |
201 | #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ | |
202 | #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ | |
203 | #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ | |
204 | ||
205 | /* CPSW_PORT_V2 only */ | |
206 | #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ | |
207 | #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ | |
208 | #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ | |
209 | #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ | |
210 | #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ | |
211 | #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ | |
212 | #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ | |
213 | #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ | |
214 | ||
215 | /* Bit definitions for the CPSW2_CONTROL register */ | |
216 | #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ | |
217 | #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ | |
218 | #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ | |
219 | #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ | |
220 | #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ | |
221 | #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ | |
222 | #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ | |
223 | #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ | |
224 | #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ | |
225 | #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ | |
226 | #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ | |
227 | #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ | |
228 | #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ | |
229 | #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ | |
230 | #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ | |
231 | #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ | |
232 | ||
233 | #define CTRL_TS_BITS \ | |
234 | (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ | |
235 | TS_ANNEX_D_EN | TS_LTYPE1_EN) | |
236 | ||
237 | #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) | |
238 | #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) | |
239 | #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) | |
240 | ||
241 | /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ | |
242 | #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ | |
243 | #define TS_SEQ_ID_OFFSET_MASK (0x3f) | |
244 | #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ | |
245 | #define TS_MSG_TYPE_EN_MASK (0xffff) | |
246 | ||
247 | /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ | |
248 | #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) | |
df828598 | 249 | |
2e5b38ab RC |
250 | /* Bit definitions for the CPSW1_TS_CTL register */ |
251 | #define CPSW_V1_TS_RX_EN BIT(0) | |
252 | #define CPSW_V1_TS_TX_EN BIT(4) | |
253 | #define CPSW_V1_MSG_TYPE_OFS 16 | |
254 | ||
255 | /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ | |
256 | #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 | |
257 | ||
df828598 M |
258 | struct cpsw_host_regs { |
259 | u32 max_blks; | |
260 | u32 blk_cnt; | |
d9ba8f9e | 261 | u32 tx_in_ctl; |
df828598 M |
262 | u32 port_vlan; |
263 | u32 tx_pri_map; | |
264 | u32 cpdma_tx_pri_map; | |
265 | u32 cpdma_rx_chan_map; | |
266 | }; | |
267 | ||
268 | struct cpsw_sliver_regs { | |
269 | u32 id_ver; | |
270 | u32 mac_control; | |
271 | u32 mac_status; | |
272 | u32 soft_reset; | |
273 | u32 rx_maxlen; | |
274 | u32 __reserved_0; | |
275 | u32 rx_pause; | |
276 | u32 tx_pause; | |
277 | u32 __reserved_1; | |
278 | u32 rx_pri_map; | |
279 | }; | |
280 | ||
281 | struct cpsw_slave { | |
9750a3ad | 282 | void __iomem *regs; |
df828598 M |
283 | struct cpsw_sliver_regs __iomem *sliver; |
284 | int slave_num; | |
285 | u32 mac_control; | |
286 | struct cpsw_slave_data *data; | |
287 | struct phy_device *phy; | |
d9ba8f9e M |
288 | struct net_device *ndev; |
289 | u32 port_vlan; | |
290 | u32 open_stat; | |
df828598 M |
291 | }; |
292 | ||
9750a3ad RC |
293 | static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) |
294 | { | |
295 | return __raw_readl(slave->regs + offset); | |
296 | } | |
297 | ||
298 | static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) | |
299 | { | |
300 | __raw_writel(val, slave->regs + offset); | |
301 | } | |
302 | ||
df828598 M |
303 | struct cpsw_priv { |
304 | spinlock_t lock; | |
305 | struct platform_device *pdev; | |
306 | struct net_device *ndev; | |
307 | struct resource *cpsw_res; | |
a65dd5b2 | 308 | struct resource *cpsw_wr_res; |
df828598 M |
309 | struct napi_struct napi; |
310 | struct device *dev; | |
311 | struct cpsw_platform_data data; | |
996a5c27 RC |
312 | struct cpsw_ss_regs __iomem *regs; |
313 | struct cpsw_wr_regs __iomem *wr_regs; | |
df828598 M |
314 | struct cpsw_host_regs __iomem *host_port_regs; |
315 | u32 msg_enable; | |
e90cfac6 | 316 | u32 version; |
df828598 M |
317 | struct net_device_stats stats; |
318 | int rx_packet_max; | |
319 | int host_port; | |
320 | struct clk *clk; | |
321 | u8 mac_addr[ETH_ALEN]; | |
322 | struct cpsw_slave *slaves; | |
323 | struct cpdma_ctlr *dma; | |
324 | struct cpdma_chan *txch, *rxch; | |
325 | struct cpsw_ale *ale; | |
326 | /* snapshot of IRQ numbers */ | |
327 | u32 irqs_table[4]; | |
328 | u32 num_irqs; | |
9232b16d | 329 | struct cpts *cpts; |
d9ba8f9e | 330 | u32 emac_port; |
df828598 M |
331 | }; |
332 | ||
333 | #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) | |
d9ba8f9e M |
334 | #define for_each_slave(priv, func, arg...) \ |
335 | do { \ | |
336 | int idx; \ | |
337 | if (priv->data.dual_emac) \ | |
338 | (func)((priv)->slaves + priv->emac_port, ##arg);\ | |
339 | else \ | |
340 | for (idx = 0; idx < (priv)->data.slaves; idx++) \ | |
341 | (func)((priv)->slaves + idx, ##arg); \ | |
342 | } while (0) | |
343 | #define cpsw_get_slave_ndev(priv, __slave_no__) \ | |
344 | (priv->slaves[__slave_no__].ndev) | |
345 | #define cpsw_get_slave_priv(priv, __slave_no__) \ | |
346 | ((priv->slaves[__slave_no__].ndev) ? \ | |
347 | netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ | |
348 | ||
349 | #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ | |
350 | do { \ | |
351 | if (!priv->data.dual_emac) \ | |
352 | break; \ | |
353 | if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ | |
354 | ndev = cpsw_get_slave_ndev(priv, 0); \ | |
355 | priv = netdev_priv(ndev); \ | |
356 | skb->dev = ndev; \ | |
357 | } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ | |
358 | ndev = cpsw_get_slave_ndev(priv, 1); \ | |
359 | priv = netdev_priv(ndev); \ | |
360 | skb->dev = ndev; \ | |
361 | } \ | |
df828598 | 362 | } while (0) |
d9ba8f9e M |
363 | #define cpsw_add_mcast(priv, addr) \ |
364 | do { \ | |
365 | if (priv->data.dual_emac) { \ | |
366 | struct cpsw_slave *slave = priv->slaves + \ | |
367 | priv->emac_port; \ | |
368 | int slave_port = cpsw_get_slave_port(priv, \ | |
369 | slave->slave_num); \ | |
370 | cpsw_ale_add_mcast(priv->ale, addr, \ | |
371 | 1 << slave_port | 1 << priv->host_port, \ | |
372 | ALE_VLAN, slave->port_vlan, 0); \ | |
373 | } else { \ | |
374 | cpsw_ale_add_mcast(priv->ale, addr, \ | |
375 | ALE_ALL_PORTS << priv->host_port, \ | |
376 | 0, 0, 0); \ | |
377 | } \ | |
378 | } while (0) | |
379 | ||
380 | static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) | |
381 | { | |
382 | if (priv->host_port == 0) | |
383 | return slave_num + 1; | |
384 | else | |
385 | return slave_num; | |
386 | } | |
df828598 | 387 | |
5c50a856 M |
388 | static void cpsw_ndo_set_rx_mode(struct net_device *ndev) |
389 | { | |
390 | struct cpsw_priv *priv = netdev_priv(ndev); | |
391 | ||
392 | if (ndev->flags & IFF_PROMISC) { | |
393 | /* Enable promiscuous mode */ | |
394 | dev_err(priv->dev, "Ignoring Promiscuous mode\n"); | |
395 | return; | |
396 | } | |
397 | ||
398 | /* Clear all mcast from ALE */ | |
399 | cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); | |
400 | ||
401 | if (!netdev_mc_empty(ndev)) { | |
402 | struct netdev_hw_addr *ha; | |
403 | ||
404 | /* program multicast address list into ALE register */ | |
405 | netdev_for_each_mc_addr(ha, ndev) { | |
d9ba8f9e | 406 | cpsw_add_mcast(priv, (u8 *)ha->addr); |
5c50a856 M |
407 | } |
408 | } | |
409 | } | |
410 | ||
df828598 M |
411 | static void cpsw_intr_enable(struct cpsw_priv *priv) |
412 | { | |
996a5c27 RC |
413 | __raw_writel(0xFF, &priv->wr_regs->tx_en); |
414 | __raw_writel(0xFF, &priv->wr_regs->rx_en); | |
df828598 M |
415 | |
416 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
417 | return; | |
418 | } | |
419 | ||
420 | static void cpsw_intr_disable(struct cpsw_priv *priv) | |
421 | { | |
996a5c27 RC |
422 | __raw_writel(0, &priv->wr_regs->tx_en); |
423 | __raw_writel(0, &priv->wr_regs->rx_en); | |
df828598 M |
424 | |
425 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
426 | return; | |
427 | } | |
428 | ||
429 | void cpsw_tx_handler(void *token, int len, int status) | |
430 | { | |
431 | struct sk_buff *skb = token; | |
432 | struct net_device *ndev = skb->dev; | |
433 | struct cpsw_priv *priv = netdev_priv(ndev); | |
434 | ||
fae50823 M |
435 | /* Check whether the queue is stopped due to stalled tx dma, if the |
436 | * queue is stopped then start the queue as we have free desc for tx | |
437 | */ | |
df828598 M |
438 | if (unlikely(netif_queue_stopped(ndev))) |
439 | netif_start_queue(ndev); | |
9232b16d | 440 | cpts_tx_timestamp(priv->cpts, skb); |
df828598 M |
441 | priv->stats.tx_packets++; |
442 | priv->stats.tx_bytes += len; | |
443 | dev_kfree_skb_any(skb); | |
444 | } | |
445 | ||
446 | void cpsw_rx_handler(void *token, int len, int status) | |
447 | { | |
448 | struct sk_buff *skb = token; | |
449 | struct net_device *ndev = skb->dev; | |
450 | struct cpsw_priv *priv = netdev_priv(ndev); | |
451 | int ret = 0; | |
452 | ||
d9ba8f9e M |
453 | cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); |
454 | ||
df828598 M |
455 | /* free and bail if we are shutting down */ |
456 | if (unlikely(!netif_running(ndev)) || | |
457 | unlikely(!netif_carrier_ok(ndev))) { | |
458 | dev_kfree_skb_any(skb); | |
459 | return; | |
460 | } | |
461 | if (likely(status >= 0)) { | |
462 | skb_put(skb, len); | |
9232b16d | 463 | cpts_rx_timestamp(priv->cpts, skb); |
df828598 M |
464 | skb->protocol = eth_type_trans(skb, ndev); |
465 | netif_receive_skb(skb); | |
466 | priv->stats.rx_bytes += len; | |
467 | priv->stats.rx_packets++; | |
468 | skb = NULL; | |
469 | } | |
470 | ||
471 | if (unlikely(!netif_running(ndev))) { | |
472 | if (skb) | |
473 | dev_kfree_skb_any(skb); | |
474 | return; | |
475 | } | |
476 | ||
477 | if (likely(!skb)) { | |
478 | skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); | |
479 | if (WARN_ON(!skb)) | |
480 | return; | |
481 | ||
482 | ret = cpdma_chan_submit(priv->rxch, skb, skb->data, | |
f6e135c8 | 483 | skb_tailroom(skb), 0, GFP_KERNEL); |
df828598 M |
484 | } |
485 | WARN_ON(ret < 0); | |
486 | } | |
487 | ||
488 | static irqreturn_t cpsw_interrupt(int irq, void *dev_id) | |
489 | { | |
490 | struct cpsw_priv *priv = dev_id; | |
491 | ||
492 | if (likely(netif_running(priv->ndev))) { | |
493 | cpsw_intr_disable(priv); | |
494 | cpsw_disable_irq(priv); | |
495 | napi_schedule(&priv->napi); | |
d9ba8f9e M |
496 | } else { |
497 | priv = cpsw_get_slave_priv(priv, 1); | |
498 | if (likely(priv) && likely(netif_running(priv->ndev))) { | |
499 | cpsw_intr_disable(priv); | |
500 | cpsw_disable_irq(priv); | |
501 | napi_schedule(&priv->napi); | |
502 | } | |
df828598 M |
503 | } |
504 | return IRQ_HANDLED; | |
505 | } | |
506 | ||
df828598 M |
507 | static int cpsw_poll(struct napi_struct *napi, int budget) |
508 | { | |
509 | struct cpsw_priv *priv = napi_to_priv(napi); | |
510 | int num_tx, num_rx; | |
511 | ||
512 | num_tx = cpdma_chan_process(priv->txch, 128); | |
510a1e72 M |
513 | if (num_tx) |
514 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
df828598 | 515 | |
510a1e72 | 516 | num_rx = cpdma_chan_process(priv->rxch, budget); |
df828598 M |
517 | if (num_rx < budget) { |
518 | napi_complete(napi); | |
519 | cpsw_intr_enable(priv); | |
510a1e72 | 520 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
df828598 M |
521 | cpsw_enable_irq(priv); |
522 | } | |
523 | ||
510a1e72 M |
524 | if (num_rx || num_tx) |
525 | cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", | |
526 | num_rx, num_tx); | |
527 | ||
df828598 M |
528 | return num_rx; |
529 | } | |
530 | ||
531 | static inline void soft_reset(const char *module, void __iomem *reg) | |
532 | { | |
533 | unsigned long timeout = jiffies + HZ; | |
534 | ||
535 | __raw_writel(1, reg); | |
536 | do { | |
537 | cpu_relax(); | |
538 | } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); | |
539 | ||
540 | WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); | |
541 | } | |
542 | ||
543 | #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ | |
544 | ((mac)[2] << 16) | ((mac)[3] << 24)) | |
545 | #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) | |
546 | ||
547 | static void cpsw_set_slave_mac(struct cpsw_slave *slave, | |
548 | struct cpsw_priv *priv) | |
549 | { | |
9750a3ad RC |
550 | slave_write(slave, mac_hi(priv->mac_addr), SA_HI); |
551 | slave_write(slave, mac_lo(priv->mac_addr), SA_LO); | |
df828598 M |
552 | } |
553 | ||
554 | static void _cpsw_adjust_link(struct cpsw_slave *slave, | |
555 | struct cpsw_priv *priv, bool *link) | |
556 | { | |
557 | struct phy_device *phy = slave->phy; | |
558 | u32 mac_control = 0; | |
559 | u32 slave_port; | |
560 | ||
561 | if (!phy) | |
562 | return; | |
563 | ||
564 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
565 | ||
566 | if (phy->link) { | |
567 | mac_control = priv->data.mac_control; | |
568 | ||
569 | /* enable forwarding */ | |
570 | cpsw_ale_control_set(priv->ale, slave_port, | |
571 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
572 | ||
573 | if (phy->speed == 1000) | |
574 | mac_control |= BIT(7); /* GIGABITEN */ | |
575 | if (phy->duplex) | |
576 | mac_control |= BIT(0); /* FULLDUPLEXEN */ | |
342b7b74 DM |
577 | |
578 | /* set speed_in input in case RMII mode is used in 100Mbps */ | |
579 | if (phy->speed == 100) | |
580 | mac_control |= BIT(15); | |
581 | ||
df828598 M |
582 | *link = true; |
583 | } else { | |
584 | mac_control = 0; | |
585 | /* disable forwarding */ | |
586 | cpsw_ale_control_set(priv->ale, slave_port, | |
587 | ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); | |
588 | } | |
589 | ||
590 | if (mac_control != slave->mac_control) { | |
591 | phy_print_status(phy); | |
592 | __raw_writel(mac_control, &slave->sliver->mac_control); | |
593 | } | |
594 | ||
595 | slave->mac_control = mac_control; | |
596 | } | |
597 | ||
598 | static void cpsw_adjust_link(struct net_device *ndev) | |
599 | { | |
600 | struct cpsw_priv *priv = netdev_priv(ndev); | |
601 | bool link = false; | |
602 | ||
603 | for_each_slave(priv, _cpsw_adjust_link, priv, &link); | |
604 | ||
605 | if (link) { | |
606 | netif_carrier_on(ndev); | |
607 | if (netif_running(ndev)) | |
608 | netif_wake_queue(ndev); | |
609 | } else { | |
610 | netif_carrier_off(ndev); | |
611 | netif_stop_queue(ndev); | |
612 | } | |
613 | } | |
614 | ||
615 | static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) | |
616 | { | |
617 | static char *leader = "........................................"; | |
618 | ||
619 | if (!val) | |
620 | return 0; | |
621 | else | |
622 | return snprintf(buf, maxlen, "%s %s %10d\n", name, | |
623 | leader + strlen(name), val); | |
624 | } | |
625 | ||
d9ba8f9e M |
626 | static int cpsw_common_res_usage_state(struct cpsw_priv *priv) |
627 | { | |
628 | u32 i; | |
629 | u32 usage_count = 0; | |
630 | ||
631 | if (!priv->data.dual_emac) | |
632 | return 0; | |
633 | ||
634 | for (i = 0; i < priv->data.slaves; i++) | |
635 | if (priv->slaves[i].open_stat) | |
636 | usage_count++; | |
637 | ||
638 | return usage_count; | |
639 | } | |
640 | ||
641 | static inline int cpsw_tx_packet_submit(struct net_device *ndev, | |
642 | struct cpsw_priv *priv, struct sk_buff *skb) | |
643 | { | |
644 | if (!priv->data.dual_emac) | |
645 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
646 | skb->len, 0, GFP_KERNEL); | |
647 | ||
648 | if (ndev == cpsw_get_slave_ndev(priv, 0)) | |
649 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
650 | skb->len, 1, GFP_KERNEL); | |
651 | else | |
652 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
653 | skb->len, 2, GFP_KERNEL); | |
654 | } | |
655 | ||
656 | static inline void cpsw_add_dual_emac_def_ale_entries( | |
657 | struct cpsw_priv *priv, struct cpsw_slave *slave, | |
658 | u32 slave_port) | |
659 | { | |
660 | u32 port_mask = 1 << slave_port | 1 << priv->host_port; | |
661 | ||
662 | if (priv->version == CPSW_VERSION_1) | |
663 | slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); | |
664 | else | |
665 | slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); | |
666 | cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, | |
667 | port_mask, port_mask, 0); | |
668 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
669 | port_mask, ALE_VLAN, slave->port_vlan, 0); | |
670 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, | |
671 | priv->host_port, ALE_VLAN, slave->port_vlan); | |
672 | } | |
673 | ||
df828598 M |
674 | static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) |
675 | { | |
676 | char name[32]; | |
677 | u32 slave_port; | |
678 | ||
679 | sprintf(name, "slave-%d", slave->slave_num); | |
680 | ||
681 | soft_reset(name, &slave->sliver->soft_reset); | |
682 | ||
683 | /* setup priority mapping */ | |
684 | __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); | |
9750a3ad RC |
685 | |
686 | switch (priv->version) { | |
687 | case CPSW_VERSION_1: | |
688 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); | |
689 | break; | |
690 | case CPSW_VERSION_2: | |
691 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); | |
692 | break; | |
693 | } | |
df828598 M |
694 | |
695 | /* setup max packet size, and mac address */ | |
696 | __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); | |
697 | cpsw_set_slave_mac(slave, priv); | |
698 | ||
699 | slave->mac_control = 0; /* no link yet */ | |
700 | ||
701 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
702 | ||
d9ba8f9e M |
703 | if (priv->data.dual_emac) |
704 | cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); | |
705 | else | |
706 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
707 | 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); | |
df828598 M |
708 | |
709 | slave->phy = phy_connect(priv->ndev, slave->data->phy_id, | |
f9a8f83b | 710 | &cpsw_adjust_link, slave->data->phy_if); |
df828598 M |
711 | if (IS_ERR(slave->phy)) { |
712 | dev_err(priv->dev, "phy %s not found on slave %d\n", | |
713 | slave->data->phy_id, slave->slave_num); | |
714 | slave->phy = NULL; | |
715 | } else { | |
716 | dev_info(priv->dev, "phy found : id is : 0x%x\n", | |
717 | slave->phy->phy_id); | |
718 | phy_start(slave->phy); | |
719 | } | |
720 | } | |
721 | ||
3b72c2fe M |
722 | static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) |
723 | { | |
724 | const int vlan = priv->data.default_vlan; | |
725 | const int port = priv->host_port; | |
726 | u32 reg; | |
727 | int i; | |
728 | ||
729 | reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : | |
730 | CPSW2_PORT_VLAN; | |
731 | ||
732 | writel(vlan, &priv->host_port_regs->port_vlan); | |
733 | ||
0237c110 | 734 | for (i = 0; i < priv->data.slaves; i++) |
3b72c2fe M |
735 | slave_write(priv->slaves + i, vlan, reg); |
736 | ||
737 | cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, | |
738 | ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, | |
739 | (ALE_PORT_1 | ALE_PORT_2) << port); | |
740 | } | |
741 | ||
df828598 M |
742 | static void cpsw_init_host_port(struct cpsw_priv *priv) |
743 | { | |
3b72c2fe | 744 | u32 control_reg; |
d9ba8f9e | 745 | u32 fifo_mode; |
3b72c2fe | 746 | |
df828598 M |
747 | /* soft reset the controller and initialize ale */ |
748 | soft_reset("cpsw", &priv->regs->soft_reset); | |
749 | cpsw_ale_start(priv->ale); | |
750 | ||
751 | /* switch to vlan unaware mode */ | |
3b72c2fe M |
752 | cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, |
753 | CPSW_ALE_VLAN_AWARE); | |
754 | control_reg = readl(&priv->regs->control); | |
755 | control_reg |= CPSW_VLAN_AWARE; | |
756 | writel(control_reg, &priv->regs->control); | |
d9ba8f9e M |
757 | fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : |
758 | CPSW_FIFO_NORMAL_MODE; | |
759 | writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); | |
df828598 M |
760 | |
761 | /* setup host port priority mapping */ | |
762 | __raw_writel(CPDMA_TX_PRIORITY_MAP, | |
763 | &priv->host_port_regs->cpdma_tx_pri_map); | |
764 | __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); | |
765 | ||
766 | cpsw_ale_control_set(priv->ale, priv->host_port, | |
767 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
768 | ||
d9ba8f9e M |
769 | if (!priv->data.dual_emac) { |
770 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, | |
771 | 0, 0); | |
772 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
773 | 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); | |
774 | } | |
df828598 M |
775 | } |
776 | ||
777 | static int cpsw_ndo_open(struct net_device *ndev) | |
778 | { | |
779 | struct cpsw_priv *priv = netdev_priv(ndev); | |
780 | int i, ret; | |
781 | u32 reg; | |
782 | ||
d9ba8f9e M |
783 | if (!cpsw_common_res_usage_state(priv)) |
784 | cpsw_intr_disable(priv); | |
df828598 M |
785 | netif_carrier_off(ndev); |
786 | ||
f150bd7f | 787 | pm_runtime_get_sync(&priv->pdev->dev); |
df828598 | 788 | |
549985ee | 789 | reg = priv->version; |
df828598 M |
790 | |
791 | dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", | |
792 | CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), | |
793 | CPSW_RTL_VERSION(reg)); | |
794 | ||
795 | /* initialize host and slave ports */ | |
d9ba8f9e M |
796 | if (!cpsw_common_res_usage_state(priv)) |
797 | cpsw_init_host_port(priv); | |
df828598 M |
798 | for_each_slave(priv, cpsw_slave_open, priv); |
799 | ||
3b72c2fe | 800 | /* Add default VLAN */ |
d9ba8f9e M |
801 | if (!priv->data.dual_emac) |
802 | cpsw_add_default_vlan(priv); | |
3b72c2fe | 803 | |
d9ba8f9e M |
804 | if (!cpsw_common_res_usage_state(priv)) { |
805 | /* setup tx dma to fixed prio and zero offset */ | |
806 | cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); | |
807 | cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); | |
df828598 | 808 | |
d9ba8f9e M |
809 | /* disable priority elevation */ |
810 | __raw_writel(0, &priv->regs->ptype); | |
df828598 | 811 | |
d9ba8f9e M |
812 | /* enable statistics collection only on all ports */ |
813 | __raw_writel(0x7, &priv->regs->stat_port_en); | |
df828598 | 814 | |
d9ba8f9e M |
815 | if (WARN_ON(!priv->data.rx_descs)) |
816 | priv->data.rx_descs = 128; | |
df828598 | 817 | |
d9ba8f9e M |
818 | for (i = 0; i < priv->data.rx_descs; i++) { |
819 | struct sk_buff *skb; | |
df828598 | 820 | |
d9ba8f9e M |
821 | ret = -ENOMEM; |
822 | skb = netdev_alloc_skb_ip_align(priv->ndev, | |
823 | priv->rx_packet_max); | |
824 | if (!skb) | |
825 | break; | |
826 | ret = cpdma_chan_submit(priv->rxch, skb, skb->data, | |
f6e135c8 | 827 | skb_tailroom(skb), 0, GFP_KERNEL); |
d9ba8f9e M |
828 | if (WARN_ON(ret < 0)) |
829 | break; | |
830 | } | |
831 | /* continue even if we didn't manage to submit all | |
832 | * receive descs | |
833 | */ | |
834 | cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); | |
df828598 | 835 | } |
df828598 M |
836 | |
837 | cpdma_ctlr_start(priv->dma); | |
838 | cpsw_intr_enable(priv); | |
839 | napi_enable(&priv->napi); | |
510a1e72 M |
840 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
841 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
df828598 | 842 | |
d9ba8f9e M |
843 | if (priv->data.dual_emac) |
844 | priv->slaves[priv->emac_port].open_stat = true; | |
df828598 M |
845 | return 0; |
846 | } | |
847 | ||
848 | static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) | |
849 | { | |
850 | if (!slave->phy) | |
851 | return; | |
852 | phy_stop(slave->phy); | |
853 | phy_disconnect(slave->phy); | |
854 | slave->phy = NULL; | |
855 | } | |
856 | ||
857 | static int cpsw_ndo_stop(struct net_device *ndev) | |
858 | { | |
859 | struct cpsw_priv *priv = netdev_priv(ndev); | |
860 | ||
861 | cpsw_info(priv, ifdown, "shutting down cpsw device\n"); | |
df828598 M |
862 | netif_stop_queue(priv->ndev); |
863 | napi_disable(&priv->napi); | |
864 | netif_carrier_off(priv->ndev); | |
d9ba8f9e M |
865 | |
866 | if (cpsw_common_res_usage_state(priv) <= 1) { | |
867 | cpsw_intr_disable(priv); | |
868 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
869 | cpdma_ctlr_stop(priv->dma); | |
870 | cpsw_ale_stop(priv->ale); | |
871 | } | |
df828598 | 872 | for_each_slave(priv, cpsw_slave_stop, priv); |
f150bd7f | 873 | pm_runtime_put_sync(&priv->pdev->dev); |
d9ba8f9e M |
874 | if (priv->data.dual_emac) |
875 | priv->slaves[priv->emac_port].open_stat = false; | |
df828598 M |
876 | return 0; |
877 | } | |
878 | ||
879 | static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, | |
880 | struct net_device *ndev) | |
881 | { | |
882 | struct cpsw_priv *priv = netdev_priv(ndev); | |
883 | int ret; | |
884 | ||
885 | ndev->trans_start = jiffies; | |
886 | ||
887 | if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { | |
888 | cpsw_err(priv, tx_err, "packet pad failed\n"); | |
889 | priv->stats.tx_dropped++; | |
890 | return NETDEV_TX_OK; | |
891 | } | |
892 | ||
9232b16d M |
893 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
894 | priv->cpts->tx_enable) | |
2e5b38ab RC |
895 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
896 | ||
897 | skb_tx_timestamp(skb); | |
898 | ||
d9ba8f9e | 899 | ret = cpsw_tx_packet_submit(ndev, priv, skb); |
df828598 M |
900 | if (unlikely(ret != 0)) { |
901 | cpsw_err(priv, tx_err, "desc submit failed\n"); | |
902 | goto fail; | |
903 | } | |
904 | ||
fae50823 M |
905 | /* If there is no more tx desc left free then we need to |
906 | * tell the kernel to stop sending us tx frames. | |
907 | */ | |
908 | if (unlikely(cpdma_check_free_tx_desc(priv->txch))) | |
909 | netif_stop_queue(ndev); | |
910 | ||
df828598 M |
911 | return NETDEV_TX_OK; |
912 | fail: | |
913 | priv->stats.tx_dropped++; | |
914 | netif_stop_queue(ndev); | |
915 | return NETDEV_TX_BUSY; | |
916 | } | |
917 | ||
918 | static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) | |
919 | { | |
920 | /* | |
921 | * The switch cannot operate in promiscuous mode without substantial | |
922 | * headache. For promiscuous mode to work, we would need to put the | |
923 | * ALE in bypass mode and route all traffic to the host port. | |
924 | * Subsequently, the host will need to operate as a "bridge", learn, | |
925 | * and flood as needed. For now, we simply complain here and | |
926 | * do nothing about it :-) | |
927 | */ | |
928 | if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) | |
929 | dev_err(&ndev->dev, "promiscuity ignored!\n"); | |
930 | ||
931 | /* | |
932 | * The switch cannot filter multicast traffic unless it is configured | |
933 | * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a | |
934 | * whole bunch of additional logic that this driver does not implement | |
935 | * at present. | |
936 | */ | |
937 | if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) | |
938 | dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); | |
939 | } | |
940 | ||
2e5b38ab RC |
941 | #ifdef CONFIG_TI_CPTS |
942 | ||
943 | static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) | |
944 | { | |
945 | struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; | |
946 | u32 ts_en, seq_id; | |
947 | ||
9232b16d | 948 | if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { |
2e5b38ab RC |
949 | slave_write(slave, 0, CPSW1_TS_CTL); |
950 | return; | |
951 | } | |
952 | ||
953 | seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; | |
954 | ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; | |
955 | ||
9232b16d | 956 | if (priv->cpts->tx_enable) |
2e5b38ab RC |
957 | ts_en |= CPSW_V1_TS_TX_EN; |
958 | ||
9232b16d | 959 | if (priv->cpts->rx_enable) |
2e5b38ab RC |
960 | ts_en |= CPSW_V1_TS_RX_EN; |
961 | ||
962 | slave_write(slave, ts_en, CPSW1_TS_CTL); | |
963 | slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); | |
964 | } | |
965 | ||
966 | static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) | |
967 | { | |
d9ba8f9e | 968 | struct cpsw_slave *slave; |
2e5b38ab RC |
969 | u32 ctrl, mtype; |
970 | ||
d9ba8f9e M |
971 | if (priv->data.dual_emac) |
972 | slave = &priv->slaves[priv->emac_port]; | |
973 | else | |
974 | slave = &priv->slaves[priv->data.cpts_active_slave]; | |
975 | ||
2e5b38ab RC |
976 | ctrl = slave_read(slave, CPSW2_CONTROL); |
977 | ctrl &= ~CTRL_ALL_TS_MASK; | |
978 | ||
9232b16d | 979 | if (priv->cpts->tx_enable) |
2e5b38ab RC |
980 | ctrl |= CTRL_TX_TS_BITS; |
981 | ||
9232b16d | 982 | if (priv->cpts->rx_enable) |
2e5b38ab RC |
983 | ctrl |= CTRL_RX_TS_BITS; |
984 | ||
985 | mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; | |
986 | ||
987 | slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); | |
988 | slave_write(slave, ctrl, CPSW2_CONTROL); | |
989 | __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); | |
990 | } | |
991 | ||
3177bf6f | 992 | static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) |
2e5b38ab | 993 | { |
3177bf6f | 994 | struct cpsw_priv *priv = netdev_priv(dev); |
9232b16d | 995 | struct cpts *cpts = priv->cpts; |
2e5b38ab RC |
996 | struct hwtstamp_config cfg; |
997 | ||
998 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
999 | return -EFAULT; | |
1000 | ||
1001 | /* reserved for future extensions */ | |
1002 | if (cfg.flags) | |
1003 | return -EINVAL; | |
1004 | ||
1005 | switch (cfg.tx_type) { | |
1006 | case HWTSTAMP_TX_OFF: | |
1007 | cpts->tx_enable = 0; | |
1008 | break; | |
1009 | case HWTSTAMP_TX_ON: | |
1010 | cpts->tx_enable = 1; | |
1011 | break; | |
1012 | default: | |
1013 | return -ERANGE; | |
1014 | } | |
1015 | ||
1016 | switch (cfg.rx_filter) { | |
1017 | case HWTSTAMP_FILTER_NONE: | |
1018 | cpts->rx_enable = 0; | |
1019 | break; | |
1020 | case HWTSTAMP_FILTER_ALL: | |
1021 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1022 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1023 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1024 | return -ERANGE; | |
1025 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1026 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1027 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1028 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1029 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1030 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1031 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1032 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1033 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1034 | cpts->rx_enable = 1; | |
1035 | cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
1036 | break; | |
1037 | default: | |
1038 | return -ERANGE; | |
1039 | } | |
1040 | ||
1041 | switch (priv->version) { | |
1042 | case CPSW_VERSION_1: | |
1043 | cpsw_hwtstamp_v1(priv); | |
1044 | break; | |
1045 | case CPSW_VERSION_2: | |
1046 | cpsw_hwtstamp_v2(priv); | |
1047 | break; | |
1048 | default: | |
1049 | return -ENOTSUPP; | |
1050 | } | |
1051 | ||
1052 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
1053 | } | |
1054 | ||
1055 | #endif /*CONFIG_TI_CPTS*/ | |
1056 | ||
1057 | static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
1058 | { | |
2e5b38ab RC |
1059 | if (!netif_running(dev)) |
1060 | return -EINVAL; | |
1061 | ||
1062 | #ifdef CONFIG_TI_CPTS | |
1063 | if (cmd == SIOCSHWTSTAMP) | |
3177bf6f | 1064 | return cpsw_hwtstamp_ioctl(dev, req); |
2e5b38ab RC |
1065 | #endif |
1066 | return -ENOTSUPP; | |
1067 | } | |
1068 | ||
df828598 M |
1069 | static void cpsw_ndo_tx_timeout(struct net_device *ndev) |
1070 | { | |
1071 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1072 | ||
1073 | cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); | |
1074 | priv->stats.tx_errors++; | |
1075 | cpsw_intr_disable(priv); | |
1076 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1077 | cpdma_chan_stop(priv->txch); | |
1078 | cpdma_chan_start(priv->txch); | |
1079 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
1080 | cpsw_intr_enable(priv); | |
510a1e72 M |
1081 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1082 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
1083 | ||
df828598 M |
1084 | } |
1085 | ||
1086 | static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) | |
1087 | { | |
1088 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1089 | return &priv->stats; | |
1090 | } | |
1091 | ||
1092 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1093 | static void cpsw_ndo_poll_controller(struct net_device *ndev) | |
1094 | { | |
1095 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1096 | ||
1097 | cpsw_intr_disable(priv); | |
1098 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1099 | cpsw_interrupt(ndev->irq, priv); | |
1100 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
1101 | cpsw_intr_enable(priv); | |
510a1e72 M |
1102 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1103 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
1104 | ||
df828598 M |
1105 | } |
1106 | #endif | |
1107 | ||
3b72c2fe M |
1108 | static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, |
1109 | unsigned short vid) | |
1110 | { | |
1111 | int ret; | |
1112 | ||
1113 | ret = cpsw_ale_add_vlan(priv->ale, vid, | |
1114 | ALE_ALL_PORTS << priv->host_port, | |
1115 | 0, ALE_ALL_PORTS << priv->host_port, | |
1116 | (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); | |
1117 | if (ret != 0) | |
1118 | return ret; | |
1119 | ||
1120 | ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, | |
1121 | priv->host_port, ALE_VLAN, vid); | |
1122 | if (ret != 0) | |
1123 | goto clean_vid; | |
1124 | ||
1125 | ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
1126 | ALE_ALL_PORTS << priv->host_port, | |
1127 | ALE_VLAN, vid, 0); | |
1128 | if (ret != 0) | |
1129 | goto clean_vlan_ucast; | |
1130 | return 0; | |
1131 | ||
1132 | clean_vlan_ucast: | |
1133 | cpsw_ale_del_ucast(priv->ale, priv->mac_addr, | |
1134 | priv->host_port, ALE_VLAN, vid); | |
1135 | clean_vid: | |
1136 | cpsw_ale_del_vlan(priv->ale, vid, 0); | |
1137 | return ret; | |
1138 | } | |
1139 | ||
1140 | static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, | |
1141 | unsigned short vid) | |
1142 | { | |
1143 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1144 | ||
1145 | if (vid == priv->data.default_vlan) | |
1146 | return 0; | |
1147 | ||
1148 | dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); | |
1149 | return cpsw_add_vlan_ale_entry(priv, vid); | |
1150 | } | |
1151 | ||
1152 | static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, | |
1153 | unsigned short vid) | |
1154 | { | |
1155 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1156 | int ret; | |
1157 | ||
1158 | if (vid == priv->data.default_vlan) | |
1159 | return 0; | |
1160 | ||
1161 | dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); | |
1162 | ret = cpsw_ale_del_vlan(priv->ale, vid, 0); | |
1163 | if (ret != 0) | |
1164 | return ret; | |
1165 | ||
1166 | ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, | |
1167 | priv->host_port, ALE_VLAN, vid); | |
1168 | if (ret != 0) | |
1169 | return ret; | |
1170 | ||
1171 | return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, | |
1172 | 0, ALE_VLAN, vid); | |
1173 | } | |
1174 | ||
df828598 M |
1175 | static const struct net_device_ops cpsw_netdev_ops = { |
1176 | .ndo_open = cpsw_ndo_open, | |
1177 | .ndo_stop = cpsw_ndo_stop, | |
1178 | .ndo_start_xmit = cpsw_ndo_start_xmit, | |
1179 | .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, | |
2e5b38ab | 1180 | .ndo_do_ioctl = cpsw_ndo_ioctl, |
df828598 | 1181 | .ndo_validate_addr = eth_validate_addr, |
5c473ed2 | 1182 | .ndo_change_mtu = eth_change_mtu, |
df828598 M |
1183 | .ndo_tx_timeout = cpsw_ndo_tx_timeout, |
1184 | .ndo_get_stats = cpsw_ndo_get_stats, | |
5c50a856 | 1185 | .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, |
df828598 M |
1186 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1187 | .ndo_poll_controller = cpsw_ndo_poll_controller, | |
1188 | #endif | |
3b72c2fe M |
1189 | .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, |
1190 | .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, | |
df828598 M |
1191 | }; |
1192 | ||
1193 | static void cpsw_get_drvinfo(struct net_device *ndev, | |
1194 | struct ethtool_drvinfo *info) | |
1195 | { | |
1196 | struct cpsw_priv *priv = netdev_priv(ndev); | |
7826d43f JP |
1197 | |
1198 | strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); | |
1199 | strlcpy(info->version, "1.0", sizeof(info->version)); | |
1200 | strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); | |
df828598 M |
1201 | } |
1202 | ||
1203 | static u32 cpsw_get_msglevel(struct net_device *ndev) | |
1204 | { | |
1205 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1206 | return priv->msg_enable; | |
1207 | } | |
1208 | ||
1209 | static void cpsw_set_msglevel(struct net_device *ndev, u32 value) | |
1210 | { | |
1211 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1212 | priv->msg_enable = value; | |
1213 | } | |
1214 | ||
2e5b38ab RC |
1215 | static int cpsw_get_ts_info(struct net_device *ndev, |
1216 | struct ethtool_ts_info *info) | |
1217 | { | |
1218 | #ifdef CONFIG_TI_CPTS | |
1219 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1220 | ||
1221 | info->so_timestamping = | |
1222 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1223 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1224 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1225 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1226 | SOF_TIMESTAMPING_SOFTWARE | | |
1227 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
9232b16d | 1228 | info->phc_index = priv->cpts->phc_index; |
2e5b38ab RC |
1229 | info->tx_types = |
1230 | (1 << HWTSTAMP_TX_OFF) | | |
1231 | (1 << HWTSTAMP_TX_ON); | |
1232 | info->rx_filters = | |
1233 | (1 << HWTSTAMP_FILTER_NONE) | | |
1234 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); | |
1235 | #else | |
1236 | info->so_timestamping = | |
1237 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1238 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1239 | SOF_TIMESTAMPING_SOFTWARE; | |
1240 | info->phc_index = -1; | |
1241 | info->tx_types = 0; | |
1242 | info->rx_filters = 0; | |
1243 | #endif | |
1244 | return 0; | |
1245 | } | |
1246 | ||
df828598 M |
1247 | static const struct ethtool_ops cpsw_ethtool_ops = { |
1248 | .get_drvinfo = cpsw_get_drvinfo, | |
1249 | .get_msglevel = cpsw_get_msglevel, | |
1250 | .set_msglevel = cpsw_set_msglevel, | |
1251 | .get_link = ethtool_op_get_link, | |
2e5b38ab | 1252 | .get_ts_info = cpsw_get_ts_info, |
df828598 M |
1253 | }; |
1254 | ||
549985ee RC |
1255 | static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, |
1256 | u32 slave_reg_ofs, u32 sliver_reg_ofs) | |
df828598 M |
1257 | { |
1258 | void __iomem *regs = priv->regs; | |
1259 | int slave_num = slave->slave_num; | |
1260 | struct cpsw_slave_data *data = priv->data.slave_data + slave_num; | |
1261 | ||
1262 | slave->data = data; | |
549985ee RC |
1263 | slave->regs = regs + slave_reg_ofs; |
1264 | slave->sliver = regs + sliver_reg_ofs; | |
d9ba8f9e | 1265 | slave->port_vlan = data->dual_emac_res_vlan; |
df828598 M |
1266 | } |
1267 | ||
2eb32b0a M |
1268 | static int cpsw_probe_dt(struct cpsw_platform_data *data, |
1269 | struct platform_device *pdev) | |
1270 | { | |
1271 | struct device_node *node = pdev->dev.of_node; | |
1272 | struct device_node *slave_node; | |
1273 | int i = 0, ret; | |
1274 | u32 prop; | |
1275 | ||
1276 | if (!node) | |
1277 | return -EINVAL; | |
1278 | ||
1279 | if (of_property_read_u32(node, "slaves", &prop)) { | |
1280 | pr_err("Missing slaves property in the DT.\n"); | |
1281 | return -EINVAL; | |
1282 | } | |
1283 | data->slaves = prop; | |
1284 | ||
78ca0b28 RC |
1285 | if (of_property_read_u32(node, "cpts_active_slave", &prop)) { |
1286 | pr_err("Missing cpts_active_slave property in the DT.\n"); | |
1287 | ret = -EINVAL; | |
1288 | goto error_ret; | |
1289 | } | |
1290 | data->cpts_active_slave = prop; | |
1291 | ||
00ab94ee RC |
1292 | if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { |
1293 | pr_err("Missing cpts_clock_mult property in the DT.\n"); | |
1294 | ret = -EINVAL; | |
1295 | goto error_ret; | |
1296 | } | |
1297 | data->cpts_clock_mult = prop; | |
1298 | ||
1299 | if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { | |
1300 | pr_err("Missing cpts_clock_shift property in the DT.\n"); | |
1301 | ret = -EINVAL; | |
1302 | goto error_ret; | |
1303 | } | |
1304 | data->cpts_clock_shift = prop; | |
1305 | ||
b2adaca9 JP |
1306 | data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), |
1307 | GFP_KERNEL); | |
1308 | if (!data->slave_data) | |
2eb32b0a | 1309 | return -EINVAL; |
2eb32b0a | 1310 | |
2eb32b0a M |
1311 | if (of_property_read_u32(node, "cpdma_channels", &prop)) { |
1312 | pr_err("Missing cpdma_channels property in the DT.\n"); | |
1313 | ret = -EINVAL; | |
1314 | goto error_ret; | |
1315 | } | |
1316 | data->channels = prop; | |
1317 | ||
2eb32b0a M |
1318 | if (of_property_read_u32(node, "ale_entries", &prop)) { |
1319 | pr_err("Missing ale_entries property in the DT.\n"); | |
1320 | ret = -EINVAL; | |
1321 | goto error_ret; | |
1322 | } | |
1323 | data->ale_entries = prop; | |
1324 | ||
2eb32b0a M |
1325 | if (of_property_read_u32(node, "bd_ram_size", &prop)) { |
1326 | pr_err("Missing bd_ram_size property in the DT.\n"); | |
1327 | ret = -EINVAL; | |
1328 | goto error_ret; | |
1329 | } | |
1330 | data->bd_ram_size = prop; | |
1331 | ||
1332 | if (of_property_read_u32(node, "rx_descs", &prop)) { | |
1333 | pr_err("Missing rx_descs property in the DT.\n"); | |
1334 | ret = -EINVAL; | |
1335 | goto error_ret; | |
1336 | } | |
1337 | data->rx_descs = prop; | |
1338 | ||
1339 | if (of_property_read_u32(node, "mac_control", &prop)) { | |
1340 | pr_err("Missing mac_control property in the DT.\n"); | |
1341 | ret = -EINVAL; | |
1342 | goto error_ret; | |
1343 | } | |
1344 | data->mac_control = prop; | |
1345 | ||
d9ba8f9e M |
1346 | if (!of_property_read_u32(node, "dual_emac", &prop)) |
1347 | data->dual_emac = prop; | |
1348 | ||
549985ee RC |
1349 | /* |
1350 | * Populate all the child nodes here... | |
1351 | */ | |
1352 | ret = of_platform_populate(node, NULL, NULL, &pdev->dev); | |
1353 | /* We do not want to force this, as in some cases may not have child */ | |
1354 | if (ret) | |
1355 | pr_warn("Doesn't have any child node\n"); | |
1356 | ||
1fb19aa7 | 1357 | for_each_node_by_name(slave_node, "slave") { |
2eb32b0a | 1358 | struct cpsw_slave_data *slave_data = data->slave_data + i; |
2eb32b0a | 1359 | const void *mac_addr = NULL; |
549985ee RC |
1360 | u32 phyid; |
1361 | int lenp; | |
1362 | const __be32 *parp; | |
1363 | struct device_node *mdio_node; | |
1364 | struct platform_device *mdio; | |
1365 | ||
1366 | parp = of_get_property(slave_node, "phy_id", &lenp); | |
1367 | if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { | |
2eb32b0a M |
1368 | pr_err("Missing slave[%d] phy_id property\n", i); |
1369 | ret = -EINVAL; | |
1370 | goto error_ret; | |
1371 | } | |
549985ee RC |
1372 | mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); |
1373 | phyid = be32_to_cpup(parp+1); | |
1374 | mdio = of_find_device_by_node(mdio_node); | |
1375 | snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), | |
1376 | PHY_ID_FMT, mdio->name, phyid); | |
2eb32b0a M |
1377 | |
1378 | mac_addr = of_get_mac_address(slave_node); | |
1379 | if (mac_addr) | |
1380 | memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); | |
1381 | ||
d9ba8f9e M |
1382 | if (data->dual_emac) { |
1383 | if (of_property_read_u32(node, "dual_emac_res_vlan", | |
1384 | &prop)) { | |
1385 | pr_err("Missing dual_emac_res_vlan in DT.\n"); | |
1386 | slave_data->dual_emac_res_vlan = i+1; | |
1387 | pr_err("Using %d as Reserved VLAN for %d slave\n", | |
1388 | slave_data->dual_emac_res_vlan, i); | |
1389 | } else { | |
1390 | slave_data->dual_emac_res_vlan = prop; | |
1391 | } | |
1392 | } | |
1393 | ||
2eb32b0a M |
1394 | i++; |
1395 | } | |
1396 | ||
1397 | return 0; | |
1398 | ||
1399 | error_ret: | |
1400 | kfree(data->slave_data); | |
1401 | return ret; | |
1402 | } | |
1403 | ||
d9ba8f9e M |
1404 | static int cpsw_probe_dual_emac(struct platform_device *pdev, |
1405 | struct cpsw_priv *priv) | |
1406 | { | |
1407 | struct cpsw_platform_data *data = &priv->data; | |
1408 | struct net_device *ndev; | |
1409 | struct cpsw_priv *priv_sl2; | |
1410 | int ret = 0, i; | |
1411 | ||
1412 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); | |
1413 | if (!ndev) { | |
1414 | pr_err("cpsw: error allocating net_device\n"); | |
1415 | return -ENOMEM; | |
1416 | } | |
1417 | ||
1418 | priv_sl2 = netdev_priv(ndev); | |
1419 | spin_lock_init(&priv_sl2->lock); | |
1420 | priv_sl2->data = *data; | |
1421 | priv_sl2->pdev = pdev; | |
1422 | priv_sl2->ndev = ndev; | |
1423 | priv_sl2->dev = &ndev->dev; | |
1424 | priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
1425 | priv_sl2->rx_packet_max = max(rx_packet_max, 128); | |
1426 | ||
1427 | if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { | |
1428 | memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, | |
1429 | ETH_ALEN); | |
1430 | pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); | |
1431 | } else { | |
1432 | random_ether_addr(priv_sl2->mac_addr); | |
1433 | pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); | |
1434 | } | |
1435 | memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); | |
1436 | ||
1437 | priv_sl2->slaves = priv->slaves; | |
1438 | priv_sl2->clk = priv->clk; | |
1439 | ||
1440 | priv_sl2->cpsw_res = priv->cpsw_res; | |
1441 | priv_sl2->regs = priv->regs; | |
1442 | priv_sl2->host_port = priv->host_port; | |
1443 | priv_sl2->host_port_regs = priv->host_port_regs; | |
1444 | priv_sl2->wr_regs = priv->wr_regs; | |
1445 | priv_sl2->dma = priv->dma; | |
1446 | priv_sl2->txch = priv->txch; | |
1447 | priv_sl2->rxch = priv->rxch; | |
1448 | priv_sl2->ale = priv->ale; | |
1449 | priv_sl2->emac_port = 1; | |
1450 | priv->slaves[1].ndev = ndev; | |
1451 | priv_sl2->cpts = priv->cpts; | |
1452 | priv_sl2->version = priv->version; | |
1453 | ||
1454 | for (i = 0; i < priv->num_irqs; i++) { | |
1455 | priv_sl2->irqs_table[i] = priv->irqs_table[i]; | |
1456 | priv_sl2->num_irqs = priv->num_irqs; | |
1457 | } | |
1458 | ||
1459 | ndev->features |= NETIF_F_HW_VLAN_FILTER; | |
1460 | ||
1461 | ndev->netdev_ops = &cpsw_netdev_ops; | |
1462 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
1463 | netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
1464 | ||
1465 | /* register the network device */ | |
1466 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1467 | ret = register_netdev(ndev); | |
1468 | if (ret) { | |
1469 | pr_err("cpsw: error registering net device\n"); | |
1470 | free_netdev(ndev); | |
1471 | ret = -ENODEV; | |
1472 | } | |
1473 | ||
1474 | return ret; | |
1475 | } | |
1476 | ||
663e12e6 | 1477 | static int cpsw_probe(struct platform_device *pdev) |
df828598 M |
1478 | { |
1479 | struct cpsw_platform_data *data = pdev->dev.platform_data; | |
1480 | struct net_device *ndev; | |
1481 | struct cpsw_priv *priv; | |
1482 | struct cpdma_params dma_params; | |
1483 | struct cpsw_ale_params ale_params; | |
549985ee | 1484 | void __iomem *ss_regs, *wr_regs; |
df828598 | 1485 | struct resource *res; |
549985ee | 1486 | u32 slave_offset, sliver_offset, slave_size; |
df828598 M |
1487 | int ret = 0, i, k = 0; |
1488 | ||
df828598 M |
1489 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); |
1490 | if (!ndev) { | |
1491 | pr_err("error allocating net_device\n"); | |
1492 | return -ENOMEM; | |
1493 | } | |
1494 | ||
1495 | platform_set_drvdata(pdev, ndev); | |
1496 | priv = netdev_priv(ndev); | |
1497 | spin_lock_init(&priv->lock); | |
df828598 M |
1498 | priv->pdev = pdev; |
1499 | priv->ndev = ndev; | |
1500 | priv->dev = &ndev->dev; | |
1501 | priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
1502 | priv->rx_packet_max = max(rx_packet_max, 128); | |
9232b16d M |
1503 | priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); |
1504 | if (!ndev) { | |
1505 | pr_err("error allocating cpts\n"); | |
1506 | goto clean_ndev_ret; | |
1507 | } | |
df828598 | 1508 | |
1fb19aa7 VH |
1509 | /* |
1510 | * This may be required here for child devices. | |
1511 | */ | |
1512 | pm_runtime_enable(&pdev->dev); | |
1513 | ||
2eb32b0a M |
1514 | if (cpsw_probe_dt(&priv->data, pdev)) { |
1515 | pr_err("cpsw: platform data missing\n"); | |
1516 | ret = -ENODEV; | |
1517 | goto clean_ndev_ret; | |
1518 | } | |
1519 | data = &priv->data; | |
1520 | ||
df828598 M |
1521 | if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { |
1522 | memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); | |
1523 | pr_info("Detected MACID = %pM", priv->mac_addr); | |
1524 | } else { | |
7efd26d0 | 1525 | eth_random_addr(priv->mac_addr); |
df828598 M |
1526 | pr_info("Random MACID = %pM", priv->mac_addr); |
1527 | } | |
1528 | ||
1529 | memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); | |
1530 | ||
1531 | priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, | |
1532 | GFP_KERNEL); | |
1533 | if (!priv->slaves) { | |
1534 | ret = -EBUSY; | |
1535 | goto clean_ndev_ret; | |
1536 | } | |
1537 | for (i = 0; i < data->slaves; i++) | |
1538 | priv->slaves[i].slave_num = i; | |
1539 | ||
d9ba8f9e M |
1540 | priv->slaves[0].ndev = ndev; |
1541 | priv->emac_port = 0; | |
1542 | ||
f150bd7f | 1543 | priv->clk = clk_get(&pdev->dev, "fck"); |
df828598 | 1544 | if (IS_ERR(priv->clk)) { |
f150bd7f M |
1545 | dev_err(&pdev->dev, "fck is not found\n"); |
1546 | ret = -ENODEV; | |
1547 | goto clean_slave_ret; | |
df828598 M |
1548 | } |
1549 | ||
1550 | priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1551 | if (!priv->cpsw_res) { | |
1552 | dev_err(priv->dev, "error getting i/o resource\n"); | |
1553 | ret = -ENOENT; | |
1554 | goto clean_clk_ret; | |
1555 | } | |
df828598 M |
1556 | if (!request_mem_region(priv->cpsw_res->start, |
1557 | resource_size(priv->cpsw_res), ndev->name)) { | |
1558 | dev_err(priv->dev, "failed request i/o region\n"); | |
1559 | ret = -ENXIO; | |
1560 | goto clean_clk_ret; | |
1561 | } | |
549985ee RC |
1562 | ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); |
1563 | if (!ss_regs) { | |
df828598 M |
1564 | dev_err(priv->dev, "unable to map i/o region\n"); |
1565 | goto clean_cpsw_iores_ret; | |
1566 | } | |
549985ee RC |
1567 | priv->regs = ss_regs; |
1568 | priv->version = __raw_readl(&priv->regs->id_ver); | |
1569 | priv->host_port = HOST_PORT_NUM; | |
df828598 | 1570 | |
a65dd5b2 RC |
1571 | priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1572 | if (!priv->cpsw_wr_res) { | |
df828598 M |
1573 | dev_err(priv->dev, "error getting i/o resource\n"); |
1574 | ret = -ENOENT; | |
5250c969 | 1575 | goto clean_iomap_ret; |
df828598 | 1576 | } |
a65dd5b2 RC |
1577 | if (!request_mem_region(priv->cpsw_wr_res->start, |
1578 | resource_size(priv->cpsw_wr_res), ndev->name)) { | |
df828598 M |
1579 | dev_err(priv->dev, "failed request i/o region\n"); |
1580 | ret = -ENXIO; | |
5250c969 | 1581 | goto clean_iomap_ret; |
df828598 | 1582 | } |
549985ee | 1583 | wr_regs = ioremap(priv->cpsw_wr_res->start, |
a65dd5b2 | 1584 | resource_size(priv->cpsw_wr_res)); |
549985ee | 1585 | if (!wr_regs) { |
df828598 | 1586 | dev_err(priv->dev, "unable to map i/o region\n"); |
a65dd5b2 | 1587 | goto clean_cpsw_wr_iores_ret; |
df828598 | 1588 | } |
549985ee | 1589 | priv->wr_regs = wr_regs; |
df828598 M |
1590 | |
1591 | memset(&dma_params, 0, sizeof(dma_params)); | |
549985ee RC |
1592 | memset(&ale_params, 0, sizeof(ale_params)); |
1593 | ||
1594 | switch (priv->version) { | |
1595 | case CPSW_VERSION_1: | |
1596 | priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; | |
9232b16d | 1597 | priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; |
549985ee RC |
1598 | dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; |
1599 | dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; | |
1600 | ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; | |
1601 | slave_offset = CPSW1_SLAVE_OFFSET; | |
1602 | slave_size = CPSW1_SLAVE_SIZE; | |
1603 | sliver_offset = CPSW1_SLIVER_OFFSET; | |
1604 | dma_params.desc_mem_phys = 0; | |
1605 | break; | |
1606 | case CPSW_VERSION_2: | |
1607 | priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; | |
9232b16d | 1608 | priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; |
549985ee RC |
1609 | dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; |
1610 | dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; | |
1611 | ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; | |
1612 | slave_offset = CPSW2_SLAVE_OFFSET; | |
1613 | slave_size = CPSW2_SLAVE_SIZE; | |
1614 | sliver_offset = CPSW2_SLIVER_OFFSET; | |
1615 | dma_params.desc_mem_phys = | |
1616 | (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; | |
1617 | break; | |
1618 | default: | |
1619 | dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); | |
1620 | ret = -ENODEV; | |
1621 | goto clean_cpsw_wr_iores_ret; | |
1622 | } | |
1623 | for (i = 0; i < priv->data.slaves; i++) { | |
1624 | struct cpsw_slave *slave = &priv->slaves[i]; | |
1625 | cpsw_slave_init(slave, priv, slave_offset, sliver_offset); | |
1626 | slave_offset += slave_size; | |
1627 | sliver_offset += SLIVER_SIZE; | |
1628 | } | |
1629 | ||
df828598 | 1630 | dma_params.dev = &pdev->dev; |
549985ee RC |
1631 | dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; |
1632 | dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; | |
1633 | dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; | |
1634 | dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; | |
1635 | dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; | |
df828598 M |
1636 | |
1637 | dma_params.num_chan = data->channels; | |
1638 | dma_params.has_soft_reset = true; | |
1639 | dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; | |
1640 | dma_params.desc_mem_size = data->bd_ram_size; | |
1641 | dma_params.desc_align = 16; | |
1642 | dma_params.has_ext_regs = true; | |
549985ee | 1643 | dma_params.desc_hw_addr = dma_params.desc_mem_phys; |
df828598 M |
1644 | |
1645 | priv->dma = cpdma_ctlr_create(&dma_params); | |
1646 | if (!priv->dma) { | |
1647 | dev_err(priv->dev, "error initializing dma\n"); | |
1648 | ret = -ENOMEM; | |
5250c969 | 1649 | goto clean_wr_iomap_ret; |
df828598 M |
1650 | } |
1651 | ||
1652 | priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), | |
1653 | cpsw_tx_handler); | |
1654 | priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), | |
1655 | cpsw_rx_handler); | |
1656 | ||
1657 | if (WARN_ON(!priv->txch || !priv->rxch)) { | |
1658 | dev_err(priv->dev, "error initializing dma channels\n"); | |
1659 | ret = -ENOMEM; | |
1660 | goto clean_dma_ret; | |
1661 | } | |
1662 | ||
df828598 | 1663 | ale_params.dev = &ndev->dev; |
df828598 M |
1664 | ale_params.ale_ageout = ale_ageout; |
1665 | ale_params.ale_entries = data->ale_entries; | |
1666 | ale_params.ale_ports = data->slaves; | |
1667 | ||
1668 | priv->ale = cpsw_ale_create(&ale_params); | |
1669 | if (!priv->ale) { | |
1670 | dev_err(priv->dev, "error initializing ale engine\n"); | |
1671 | ret = -ENODEV; | |
1672 | goto clean_dma_ret; | |
1673 | } | |
1674 | ||
1675 | ndev->irq = platform_get_irq(pdev, 0); | |
1676 | if (ndev->irq < 0) { | |
1677 | dev_err(priv->dev, "error getting irq resource\n"); | |
1678 | ret = -ENOENT; | |
1679 | goto clean_ale_ret; | |
1680 | } | |
1681 | ||
1682 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { | |
1683 | for (i = res->start; i <= res->end; i++) { | |
1684 | if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, | |
1685 | dev_name(&pdev->dev), priv)) { | |
1686 | dev_err(priv->dev, "error attaching irq\n"); | |
1687 | goto clean_ale_ret; | |
1688 | } | |
1689 | priv->irqs_table[k] = i; | |
1690 | priv->num_irqs = k; | |
1691 | } | |
1692 | k++; | |
1693 | } | |
1694 | ||
3b72c2fe | 1695 | ndev->features |= NETIF_F_HW_VLAN_FILTER; |
df828598 M |
1696 | |
1697 | ndev->netdev_ops = &cpsw_netdev_ops; | |
1698 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
1699 | netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
1700 | ||
1701 | /* register the network device */ | |
1702 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1703 | ret = register_netdev(ndev); | |
1704 | if (ret) { | |
1705 | dev_err(priv->dev, "error registering net device\n"); | |
1706 | ret = -ENODEV; | |
1707 | goto clean_irq_ret; | |
1708 | } | |
1709 | ||
9232b16d | 1710 | if (cpts_register(&pdev->dev, priv->cpts, |
2e5b38ab RC |
1711 | data->cpts_clock_mult, data->cpts_clock_shift)) |
1712 | dev_err(priv->dev, "error registering cpts device\n"); | |
1713 | ||
df828598 M |
1714 | cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", |
1715 | priv->cpsw_res->start, ndev->irq); | |
1716 | ||
d9ba8f9e M |
1717 | if (priv->data.dual_emac) { |
1718 | ret = cpsw_probe_dual_emac(pdev, priv); | |
1719 | if (ret) { | |
1720 | cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); | |
1721 | goto clean_irq_ret; | |
1722 | } | |
1723 | } | |
1724 | ||
df828598 M |
1725 | return 0; |
1726 | ||
1727 | clean_irq_ret: | |
1728 | free_irq(ndev->irq, priv); | |
1729 | clean_ale_ret: | |
1730 | cpsw_ale_destroy(priv->ale); | |
1731 | clean_dma_ret: | |
1732 | cpdma_chan_destroy(priv->txch); | |
1733 | cpdma_chan_destroy(priv->rxch); | |
1734 | cpdma_ctlr_destroy(priv->dma); | |
5250c969 RC |
1735 | clean_wr_iomap_ret: |
1736 | iounmap(priv->wr_regs); | |
a65dd5b2 RC |
1737 | clean_cpsw_wr_iores_ret: |
1738 | release_mem_region(priv->cpsw_wr_res->start, | |
1739 | resource_size(priv->cpsw_wr_res)); | |
5250c969 RC |
1740 | clean_iomap_ret: |
1741 | iounmap(priv->regs); | |
df828598 M |
1742 | clean_cpsw_iores_ret: |
1743 | release_mem_region(priv->cpsw_res->start, | |
1744 | resource_size(priv->cpsw_res)); | |
1745 | clean_clk_ret: | |
1746 | clk_put(priv->clk); | |
f150bd7f M |
1747 | clean_slave_ret: |
1748 | pm_runtime_disable(&pdev->dev); | |
df828598 M |
1749 | kfree(priv->slaves); |
1750 | clean_ndev_ret: | |
1751 | free_netdev(ndev); | |
1752 | return ret; | |
1753 | } | |
1754 | ||
663e12e6 | 1755 | static int cpsw_remove(struct platform_device *pdev) |
df828598 M |
1756 | { |
1757 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1758 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1759 | ||
1760 | pr_info("removing device"); | |
1761 | platform_set_drvdata(pdev, NULL); | |
1762 | ||
9232b16d | 1763 | cpts_unregister(priv->cpts); |
df828598 M |
1764 | free_irq(ndev->irq, priv); |
1765 | cpsw_ale_destroy(priv->ale); | |
1766 | cpdma_chan_destroy(priv->txch); | |
1767 | cpdma_chan_destroy(priv->rxch); | |
1768 | cpdma_ctlr_destroy(priv->dma); | |
1769 | iounmap(priv->regs); | |
1770 | release_mem_region(priv->cpsw_res->start, | |
1771 | resource_size(priv->cpsw_res)); | |
5250c969 | 1772 | iounmap(priv->wr_regs); |
a65dd5b2 RC |
1773 | release_mem_region(priv->cpsw_wr_res->start, |
1774 | resource_size(priv->cpsw_wr_res)); | |
f150bd7f | 1775 | pm_runtime_disable(&pdev->dev); |
df828598 M |
1776 | clk_put(priv->clk); |
1777 | kfree(priv->slaves); | |
1778 | free_netdev(ndev); | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | static int cpsw_suspend(struct device *dev) | |
1784 | { | |
1785 | struct platform_device *pdev = to_platform_device(dev); | |
1786 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1787 | ||
1788 | if (netif_running(ndev)) | |
1789 | cpsw_ndo_stop(ndev); | |
f150bd7f M |
1790 | pm_runtime_put_sync(&pdev->dev); |
1791 | ||
df828598 M |
1792 | return 0; |
1793 | } | |
1794 | ||
1795 | static int cpsw_resume(struct device *dev) | |
1796 | { | |
1797 | struct platform_device *pdev = to_platform_device(dev); | |
1798 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1799 | ||
f150bd7f | 1800 | pm_runtime_get_sync(&pdev->dev); |
df828598 M |
1801 | if (netif_running(ndev)) |
1802 | cpsw_ndo_open(ndev); | |
1803 | return 0; | |
1804 | } | |
1805 | ||
1806 | static const struct dev_pm_ops cpsw_pm_ops = { | |
1807 | .suspend = cpsw_suspend, | |
1808 | .resume = cpsw_resume, | |
1809 | }; | |
1810 | ||
2eb32b0a M |
1811 | static const struct of_device_id cpsw_of_mtable[] = { |
1812 | { .compatible = "ti,cpsw", }, | |
1813 | { /* sentinel */ }, | |
1814 | }; | |
1815 | ||
df828598 M |
1816 | static struct platform_driver cpsw_driver = { |
1817 | .driver = { | |
1818 | .name = "cpsw", | |
1819 | .owner = THIS_MODULE, | |
1820 | .pm = &cpsw_pm_ops, | |
2eb32b0a | 1821 | .of_match_table = of_match_ptr(cpsw_of_mtable), |
df828598 M |
1822 | }, |
1823 | .probe = cpsw_probe, | |
663e12e6 | 1824 | .remove = cpsw_remove, |
df828598 M |
1825 | }; |
1826 | ||
1827 | static int __init cpsw_init(void) | |
1828 | { | |
1829 | return platform_driver_register(&cpsw_driver); | |
1830 | } | |
1831 | late_initcall(cpsw_init); | |
1832 | ||
1833 | static void __exit cpsw_exit(void) | |
1834 | { | |
1835 | platform_driver_unregister(&cpsw_driver); | |
1836 | } | |
1837 | module_exit(cpsw_exit); | |
1838 | ||
1839 | MODULE_LICENSE("GPL"); | |
1840 | MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); | |
1841 | MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); | |
1842 | MODULE_DESCRIPTION("TI CPSW Ethernet driver"); |