projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: ethernet: ti: cpsw: don't check slave num in runtime
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
d3bb9c58
M		 143#define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
df828598
M		 147static int debug_level;
148module_param(debug_level, int, 0);
149MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151static int ale_ageout = 10;
152module_param(ale_ageout, int, 0);
153MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156module_param(rx_packet_max, int, 0);
157MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
996a5c27 159struct cpsw_wr_regs {
df828598
M		 160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
ff5b8ef2
M		 168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
df828598
M		 177};
178
996a5c27 179struct cpsw_ss_regs {
df828598
M		 180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
bd357af2
RC		 185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
df828598
M		 193};
194
9750a3ad
RC		 195/* CPSW_PORT_V1 */
196#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205/* CPSW_PORT_V2 */
206#define CPSW2_CONTROL 0x00 /* Control Register */
207#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214/* CPSW_PORT_V1 and V2 */
215#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219/* CPSW_PORT_V2 only */
220#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229/* Bit definitions for the CPSW2_CONTROL register */
230#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 240#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 242#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
09c55372
GC		 248#define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 251
09c55372
GC		 252#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257#define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
df828598 366struct cpsw_priv {
df828598
M		 367 struct platform_device *pdev;
368 struct net_device *ndev;
32a7432c
M		 369 struct napi_struct napi_rx;
370 struct napi_struct napi_tx;
df828598
M		 371 struct device *dev;
372 struct cpsw_platform_data data;
996a5c27
RC		 373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 375 u8 __iomem *hw_stats;
df828598
M		 376 struct cpsw_host_regs __iomem *host_port_regs;
377 u32 msg_enable;
e90cfac6 378 u32 version;
ff5b8ef2
M		 379 u32 coal_intvl;
380 u32 bus_freq_mhz;
df828598 381 int rx_packet_max;
df828598
M		 382 u8 mac_addr[ETH_ALEN];
383 struct cpsw_slave *slaves;
384 struct cpdma_ctlr *dma;
385 struct cpdma_chan *txch, *rxch;
386 struct cpsw_ale *ale;
1923d6e4
M		 387 bool rx_pause;
388 bool tx_pause;
7da11600
M		 389 bool quirk_irq;
390 bool rx_irq_disabled;
391 bool tx_irq_disabled;
df828598
M		 392 /* snapshot of IRQ numbers */
393 u32 irqs_table[4];
394 u32 num_irqs;
9232b16d 395 struct cpts *cpts;
d9ba8f9e 396 u32 emac_port;
df828598
M		 397};
398
d9718546
M		 399struct cpsw_stats {
400 char stat_string[ETH_GSTRING_LEN];
401 int type;
402 int sizeof_stat;
403 int stat_offset;
404};
405
406enum {
407 CPSW_STATS,
408 CPDMA_RX_STATS,
409 CPDMA_TX_STATS,
410};
411
412#define CPSW_STAT(m) CPSW_STATS, \
413 sizeof(((struct cpsw_hw_stats *)0)->m), \
414 offsetof(struct cpsw_hw_stats, m)
415#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
416 sizeof(((struct cpdma_chan_stats *)0)->m), \
417 offsetof(struct cpdma_chan_stats, m)
418#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
419 sizeof(((struct cpdma_chan_stats *)0)->m), \
420 offsetof(struct cpdma_chan_stats, m)
421
422static const struct cpsw_stats cpsw_gstrings_stats[] = {
423 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
424 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
425 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
426 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
427 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
428 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
429 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
430 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
431 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
432 { "Rx Fragments", CPSW_STAT(rxfragments) },
433 { "Rx Octets", CPSW_STAT(rxoctets) },
434 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
435 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
436 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
437 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
438 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
439 { "Collisions", CPSW_STAT(txcollisionframes) },
440 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
441 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
442 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
443 { "Late Collisions", CPSW_STAT(txlatecollisions) },
444 { "Tx Underrun", CPSW_STAT(txunderrun) },
445 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
446 { "Tx Octets", CPSW_STAT(txoctets) },
447 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
448 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
449 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
450 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
451 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
452 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
453 { "Net Octets", CPSW_STAT(netoctets) },
454 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
455 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
456 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
457 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
458 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
459 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
460 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
461 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
462 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
463 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
464 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
465 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
466 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
467 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
468 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
469 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
470 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
471 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
472 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
473 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
474 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
475 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
476 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
477 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
478 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
479 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
480 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
481 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
482 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
483};
484
485#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
486
df828598 487#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 488#define for_each_slave(priv, func, arg...) \
489 do { \
6e6ceaed
SS		 490 struct cpsw_slave *slave; \
491 int n; \
d9ba8f9e
M		 492 if (priv->data.dual_emac) \
493 (func)((priv)->slaves + priv->emac_port, ##arg);\
494 else \
6e6ceaed
SS		 495 for (n = (priv)->data.slaves, \
496 slave = (priv)->slaves; \
497 n; n--) \
498 (func)(slave++, ##arg); \
d9ba8f9e 499 } while (0)
d9ba8f9e 500#define cpsw_get_slave_priv(priv, __slave_no__) \
1973db0d
M		 501 (((__slave_no__ < priv->data.slaves) && \
502 (priv->slaves[__slave_no__].ndev)) ? \
d9ba8f9e
M		 503 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
504
505#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
506 do { \
507 if (!priv->data.dual_emac) \
508 break; \
509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
82b52104 510 ndev = priv->slaves[0].ndev; \
d9ba8f9e
M		 511 priv = netdev_priv(ndev); \
512 skb->dev = ndev; \
513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
82b52104 514 ndev = priv->slaves[1].ndev; \
d9ba8f9e
M		 515 priv = netdev_priv(ndev); \
516 skb->dev = ndev; \
517 } \
df828598 518 } while (0)
d9ba8f9e
M		 519#define cpsw_add_mcast(priv, addr) \
520 do { \
521 if (priv->data.dual_emac) { \
522 struct cpsw_slave *slave = priv->slaves + \
523 priv->emac_port; \
6f1f5836 524 int slave_port = cpsw_get_slave_port( \
d9ba8f9e
M		 525 slave->slave_num); \
526 cpsw_ale_add_mcast(priv->ale, addr, \
71a2cbb7 527 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 528 ALE_VLAN, slave->port_vlan, 0); \
529 } else { \
530 cpsw_ale_add_mcast(priv->ale, addr, \
61f1cef9 531 ALE_ALL_PORTS, \
d9ba8f9e
M		 532 0, 0, 0); \
533 } \
534 } while (0)
535
6f1f5836 536static inline int cpsw_get_slave_port(u32 slave_num)
d9ba8f9e 537{
71a2cbb7 538 return slave_num + 1;
d9ba8f9e 539}
df828598 540
0cd8f9cc
M		 541static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
542{
543 struct cpsw_priv *priv = netdev_priv(ndev);
544 struct cpsw_ale *ale = priv->ale;
545 int i;
546
547 if (priv->data.dual_emac) {
548 bool flag = false;
549
550 /* Enabling promiscuous mode for one interface will be
551 * common for both the interface as the interface shares
552 * the same hardware resource.
553 */
0d961b3b 554 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 555 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
556 flag = true;
557
558 if (!enable && flag) {
559 enable = true;
560 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
561 }
562
563 if (enable) {
564 /* Enable Bypass */
565 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
566
567 dev_dbg(&ndev->dev, "promiscuity enabled\n");
568 } else {
569 /* Disable Bypass */
570 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
571 dev_dbg(&ndev->dev, "promiscuity disabled\n");
572 }
573 } else {
574 if (enable) {
575 unsigned long timeout = jiffies + HZ;
576
6f979eb3
LS		 577 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
578 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 579 cpsw_ale_control_set(ale, i,
580 ALE_PORT_NOLEARN, 1);
581 cpsw_ale_control_set(ale, i,
582 ALE_PORT_NO_SA_UPDATE, 1);
583 }
584
585 /* Clear All Untouched entries */
586 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
587 do {
588 cpu_relax();
589 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
590 break;
591 } while (time_after(timeout, jiffies));
592 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
593
594 /* Clear all mcast from ALE */
61f1cef9 595 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 596
597 /* Flood All Unicast Packets to Host port */
598 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
599 dev_dbg(&ndev->dev, "promiscuity enabled\n");
600 } else {
6f979eb3 601 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 602 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
603
6f979eb3
LS		 604 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
605 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 606 cpsw_ale_control_set(ale, i,
607 ALE_PORT_NOLEARN, 0);
608 cpsw_ale_control_set(ale, i,
609 ALE_PORT_NO_SA_UPDATE, 0);
610 }
611 dev_dbg(&ndev->dev, "promiscuity disabled\n");
612 }
613 }
614}
615
5c50a856
M		 616static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
617{
618 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 619 int vid;
620
621 if (priv->data.dual_emac)
622 vid = priv->slaves[priv->emac_port].port_vlan;
623 else
624 vid = priv->data.default_vlan;
5c50a856
M		 625
626 if (ndev->flags & IFF_PROMISC) {
627 /* Enable promiscuous mode */
0cd8f9cc 628 cpsw_set_promiscious(ndev, true);
1e5c4bc4 629 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 630 return;
0cd8f9cc
M		 631 } else {
632 /* Disable promiscuous mode */
633 cpsw_set_promiscious(ndev, false);
5c50a856
M		 634 }
635
1e5c4bc4
LS		 636 /* Restore allmulti on vlans if necessary */
637 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
638
5c50a856 639 /* Clear all mcast from ALE */
61f1cef9 640 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 641
642 if (!netdev_mc_empty(ndev)) {
643 struct netdev_hw_addr *ha;
644
645 /* program multicast address list into ALE register */
646 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 647 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 648 }
649 }
650}
651
df828598
M		 652static void cpsw_intr_enable(struct cpsw_priv *priv)
653{
996a5c27
RC		 654 __raw_writel(0xFF, &priv->wr_regs->tx_en);
655 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 656
657 cpdma_ctlr_int_ctrl(priv->dma, true);
658 return;
659}
660
661static void cpsw_intr_disable(struct cpsw_priv *priv)
662{
996a5c27
RC		 663 __raw_writel(0, &priv->wr_regs->tx_en);
664 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 665
666 cpdma_ctlr_int_ctrl(priv->dma, false);
667 return;
668}
669
1a3b5056 670static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 671{
672 struct sk_buff *skb = token;
673 struct net_device *ndev = skb->dev;
674 struct cpsw_priv *priv = netdev_priv(ndev);
675
fae50823
M		 676 /* Check whether the queue is stopped due to stalled tx dma, if the
677 * queue is stopped then start the queue as we have free desc for tx
678 */
df828598 679 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 680 netif_wake_queue(ndev);
9232b16d 681 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 682 ndev->stats.tx_packets++;
683 ndev->stats.tx_bytes += len;
df828598
M		 684 dev_kfree_skb_any(skb);
685}
686
1a3b5056 687static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 688{
689 struct sk_buff *skb = token;
b4727e69 690 struct sk_buff *new_skb;
df828598
M		 691 struct net_device *ndev = skb->dev;
692 struct cpsw_priv *priv = netdev_priv(ndev);
693 int ret = 0;
694
d9ba8f9e
M		 695 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
696
16e5c57d 697 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 698 bool ndev_status = false;
699 struct cpsw_slave *slave = priv->slaves;
700 int n;
701
702 if (priv->data.dual_emac) {
703 /* In dual emac mode check for all interfaces */
704 for (n = priv->data.slaves; n; n--, slave++)
705 if (netif_running(slave->ndev))
706 ndev_status = true;
707 }
708
709 if (ndev_status && (status >= 0)) {
710 /* The packet received is for the interface which
711 * is already down and the other interface is up
dbedd44e 712 * and running, instead of freeing which results
a0e2c822
M		 713 * in reducing of the number of rx descriptor in
714 * DMA engine, requeue skb back to cpdma.
715 */
716 new_skb = skb;
717 goto requeue;
718 }
719
b4727e69 720 /* the interface is going down, skbs are purged */
df828598
M		 721 dev_kfree_skb_any(skb);
722 return;
723 }
b4727e69
SS		 724
725 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
726 if (new_skb) {
df828598 727 skb_put(skb, len);
9232b16d 728 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 729 skb->protocol = eth_type_trans(skb, ndev);
730 netif_receive_skb(skb);
8dc43ddc
TK		 731 ndev->stats.rx_bytes += len;
732 ndev->stats.rx_packets++;
b4727e69 733 } else {
8dc43ddc 734 ndev->stats.rx_dropped++;
b4727e69 735 new_skb = skb;
df828598
M		 736 }
737
a0e2c822 738requeue:
b4727e69
SS		 739 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
740 skb_tailroom(new_skb), 0);
741 if (WARN_ON(ret < 0))
742 dev_kfree_skb_any(new_skb);
df828598
M		 743}
744
c03abd84 745static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 746{
747 struct cpsw_priv *priv = dev_id;
7ce67a38 748
32a7432c 749 writel(0, &priv->wr_regs->tx_en);
c03abd84 750 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
c03abd84 751
7da11600
M		 752 if (priv->quirk_irq) {
753 disable_irq_nosync(priv->irqs_table[1]);
754 priv->tx_irq_disabled = true;
755 }
756
32a7432c 757 napi_schedule(&priv->napi_tx);
c03abd84
FB		 758 return IRQ_HANDLED;
759}
760
761static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
762{
763 struct cpsw_priv *priv = dev_id;
764
765 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
870915fe 766 writel(0, &priv->wr_regs->rx_en);
fd51cf19 767
7da11600
M		 768 if (priv->quirk_irq) {
769 disable_irq_nosync(priv->irqs_table[0]);
770 priv->rx_irq_disabled = true;
771 }
772
32a7432c 773 napi_schedule(&priv->napi_rx);
d354eb85 774 return IRQ_HANDLED;
df828598
M		 775}
776
32a7432c
M		 777static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
778{
779 struct cpsw_priv *priv = napi_to_priv(napi_tx);
780 int num_tx;
781
782 num_tx = cpdma_chan_process(priv->txch, budget);
783 if (num_tx < budget) {
784 napi_complete(napi_tx);
785 writel(0xff, &priv->wr_regs->tx_en);
7da11600
M		 786 if (priv->quirk_irq && priv->tx_irq_disabled) {
787 priv->tx_irq_disabled = false;
788 enable_irq(priv->irqs_table[1]);
789 }
32a7432c
M		 790 }
791
32a7432c
M		 792 return num_tx;
793}
794
795static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 796{
32a7432c 797 struct cpsw_priv *priv = napi_to_priv(napi_rx);
1e353cdd 798 int num_rx;
df828598 799
510a1e72 800 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 801 if (num_rx < budget) {
32a7432c 802 napi_complete(napi_rx);
870915fe 803 writel(0xff, &priv->wr_regs->rx_en);
7da11600
M		 804 if (priv->quirk_irq && priv->rx_irq_disabled) {
805 priv->rx_irq_disabled = false;
806 enable_irq(priv->irqs_table[0]);
807 }
df828598
M		 808 }
809
810 return num_rx;
811}
812
813static inline void soft_reset(const char *module, void __iomem *reg)
814{
815 unsigned long timeout = jiffies + HZ;
816
817 __raw_writel(1, reg);
818 do {
819 cpu_relax();
820 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
821
822 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
823}
824
825#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
826 ((mac)[2] << 16) | ((mac)[3] << 24))
827#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
828
829static void cpsw_set_slave_mac(struct cpsw_slave *slave,
830 struct cpsw_priv *priv)
831{
9750a3ad
RC		 832 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
833 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 834}
835
836static void _cpsw_adjust_link(struct cpsw_slave *slave,
837 struct cpsw_priv *priv, bool *link)
838{
839 struct phy_device *phy = slave->phy;
840 u32 mac_control = 0;
841 u32 slave_port;
842
843 if (!phy)
844 return;
845
6f1f5836 846 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598
M		 847
848 if (phy->link) {
849 mac_control = priv->data.mac_control;
850
851 /* enable forwarding */
852 cpsw_ale_control_set(priv->ale, slave_port,
853 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
854
855 if (phy->speed == 1000)
856 mac_control |= BIT(7); /* GIGABITEN */
857 if (phy->duplex)
858 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 859
860 /* set speed_in input in case RMII mode is used in 100Mbps */
861 if (phy->speed == 100)
862 mac_control |= BIT(15);
a81d8762
M		 863 else if (phy->speed == 10)
864 mac_control |= BIT(18); /* In Band mode */
342b7b74 865
1923d6e4
M		 866 if (priv->rx_pause)
867 mac_control |= BIT(3);
868
869 if (priv->tx_pause)
870 mac_control |= BIT(4);
871
df828598
M		 872 *link = true;
873 } else {
874 mac_control = 0;
875 /* disable forwarding */
876 cpsw_ale_control_set(priv->ale, slave_port,
877 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
878 }
879
880 if (mac_control != slave->mac_control) {
881 phy_print_status(phy);
882 __raw_writel(mac_control, &slave->sliver->mac_control);
883 }
884
885 slave->mac_control = mac_control;
886}
887
888static void cpsw_adjust_link(struct net_device *ndev)
889{
890 struct cpsw_priv *priv = netdev_priv(ndev);
891 bool link = false;
892
893 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
894
895 if (link) {
896 netif_carrier_on(ndev);
897 if (netif_running(ndev))
898 netif_wake_queue(ndev);
899 } else {
900 netif_carrier_off(ndev);
901 netif_stop_queue(ndev);
902 }
903}
904
ff5b8ef2
M		 905static int cpsw_get_coalesce(struct net_device *ndev,
906 struct ethtool_coalesce *coal)
907{
908 struct cpsw_priv *priv = netdev_priv(ndev);
909
910 coal->rx_coalesce_usecs = priv->coal_intvl;
911 return 0;
912}
913
914static int cpsw_set_coalesce(struct net_device *ndev,
915 struct ethtool_coalesce *coal)
916{
917 struct cpsw_priv *priv = netdev_priv(ndev);
918 u32 int_ctrl;
919 u32 num_interrupts = 0;
920 u32 prescale = 0;
921 u32 addnl_dvdr = 1;
922 u32 coal_intvl = 0;
923
ff5b8ef2
M		 924 coal_intvl = coal->rx_coalesce_usecs;
925
926 int_ctrl = readl(&priv->wr_regs->int_control);
927 prescale = priv->bus_freq_mhz * 4;
928
a84bc2a9
M		 929 if (!coal->rx_coalesce_usecs) {
930 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
931 goto update_return;
932 }
933
ff5b8ef2
M		 934 if (coal_intvl < CPSW_CMINTMIN_INTVL)
935 coal_intvl = CPSW_CMINTMIN_INTVL;
936
937 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
938 /* Interrupt pacer works with 4us Pulse, we can
939 * throttle further by dilating the 4us pulse.
940 */
941 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
942
943 if (addnl_dvdr > 1) {
944 prescale *= addnl_dvdr;
945 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
946 coal_intvl = (CPSW_CMINTMAX_INTVL
947 * addnl_dvdr);
948 } else {
949 addnl_dvdr = 1;
950 coal_intvl = CPSW_CMINTMAX_INTVL;
951 }
952 }
953
954 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
955 writel(num_interrupts, &priv->wr_regs->rx_imax);
956 writel(num_interrupts, &priv->wr_regs->tx_imax);
957
958 int_ctrl |= CPSW_INTPACEEN;
959 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
960 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 961
962update_return:
ff5b8ef2
M		 963 writel(int_ctrl, &priv->wr_regs->int_control);
964
965 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
966 if (priv->data.dual_emac) {
967 int i;
968
969 for (i = 0; i < priv->data.slaves; i++) {
970 priv = netdev_priv(priv->slaves[i].ndev);
971 priv->coal_intvl = coal_intvl;
972 }
973 } else {
974 priv->coal_intvl = coal_intvl;
975 }
976
977 return 0;
978}
979
d9718546
M		 980static int cpsw_get_sset_count(struct net_device *ndev, int sset)
981{
982 switch (sset) {
983 case ETH_SS_STATS:
984 return CPSW_STATS_LEN;
985 default:
986 return -EOPNOTSUPP;
987 }
988}
989
990static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
991{
992 u8 *p = data;
993 int i;
994
995 switch (stringset) {
996 case ETH_SS_STATS:
997 for (i = 0; i < CPSW_STATS_LEN; i++) {
998 memcpy(p, cpsw_gstrings_stats[i].stat_string,
999 ETH_GSTRING_LEN);
1000 p += ETH_GSTRING_LEN;
1001 }
1002 break;
1003 }
1004}
1005
1006static void cpsw_get_ethtool_stats(struct net_device *ndev,
1007 struct ethtool_stats *stats, u64 *data)
1008{
1009 struct cpsw_priv *priv = netdev_priv(ndev);
1010 struct cpdma_chan_stats rx_stats;
1011 struct cpdma_chan_stats tx_stats;
1012 u32 val;
1013 u8 *p;
1014 int i;
1015
1016 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1017 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1018 cpdma_chan_get_stats(priv->txch, &tx_stats);
1019
1020 for (i = 0; i < CPSW_STATS_LEN; i++) {
1021 switch (cpsw_gstrings_stats[i].type) {
1022 case CPSW_STATS:
1023 val = readl(priv->hw_stats +
1024 cpsw_gstrings_stats[i].stat_offset);
1025 data[i] = val;
1026 break;
1027
1028 case CPDMA_RX_STATS:
1029 p = (u8 *)&rx_stats +
1030 cpsw_gstrings_stats[i].stat_offset;
1031 data[i] = *(u32 *)p;
1032 break;
1033
1034 case CPDMA_TX_STATS:
1035 p = (u8 *)&tx_stats +
1036 cpsw_gstrings_stats[i].stat_offset;
1037 data[i] = *(u32 *)p;
1038 break;
1039 }
1040 }
1041}
1042
d9ba8f9e
M		 1043static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1044{
1045 u32 i;
1046 u32 usage_count = 0;
1047
1048 if (!priv->data.dual_emac)
1049 return 0;
1050
1051 for (i = 0; i < priv->data.slaves; i++)
1052 if (priv->slaves[i].open_stat)
1053 usage_count++;
1054
1055 return usage_count;
1056}
1057
27e9e103
IK		 1058static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1059 struct sk_buff *skb)
d9ba8f9e 1060{
27e9e103
IK		 1061 return cpdma_chan_submit(priv->txch, skb, skb->data, skb->len,
1062 priv->emac_port + priv->data.dual_emac);
d9ba8f9e
M		 1063}
1064
1065static inline void cpsw_add_dual_emac_def_ale_entries(
1066 struct cpsw_priv *priv, struct cpsw_slave *slave,
1067 u32 slave_port)
1068{
71a2cbb7 1069 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e
M		 1070
1071 if (priv->version == CPSW_VERSION_1)
1072 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1073 else
1074 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1075 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1076 port_mask, port_mask, 0);
1077 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1078 port_mask, ALE_VLAN, slave->port_vlan, 0);
1079 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1080 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1081}
1082
1e7a2e21 1083static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1084{
1085 char name[32];
df828598 1086
1e7a2e21 1087 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1088 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1089}
1090
1091static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1092{
1093 u32 slave_port;
1094
1095 soft_reset_slave(slave);
df828598
M		 1096
1097 /* setup priority mapping */
1098 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1099
1100 switch (priv->version) {
1101 case CPSW_VERSION_1:
1102 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1103 break;
1104 case CPSW_VERSION_2:
c193f365 1105 case CPSW_VERSION_3:
926489be 1106 case CPSW_VERSION_4:
9750a3ad
RC		 1107 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1108 break;
1109 }
df828598
M		 1110
1111 /* setup max packet size, and mac address */
1112 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1113 cpsw_set_slave_mac(slave, priv);
1114
1115 slave->mac_control = 0; /* no link yet */
1116
6f1f5836 1117 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598 1118
d9ba8f9e
M		 1119 if (priv->data.dual_emac)
1120 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1121 else
1122 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1123 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1124
d733f754 1125 if (slave->data->phy_node) {
552165bc 1126 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1127 &cpsw_adjust_link, 0, slave->data->phy_if);
d733f754
DR		 1128 if (!slave->phy) {
1129 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1130 slave->data->phy_node->full_name,
1131 slave->slave_num);
1132 return;
1133 }
1134 } else {
9e42f715 1135 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1136 &cpsw_adjust_link, slave->data->phy_if);
d733f754
DR		 1137 if (IS_ERR(slave->phy)) {
1138 dev_err(priv->dev,
1139 "phy \"%s\" not found on slave %d, err %ld\n",
1140 slave->data->phy_id, slave->slave_num,
1141 PTR_ERR(slave->phy));
1142 slave->phy = NULL;
1143 return;
1144 }
1145 }
2220943a 1146
d733f754 1147 phy_attached_info(slave->phy);
388367a5 1148
d733f754
DR		 1149 phy_start(slave->phy);
1150
1151 /* Configure GMII_SEL register */
1152 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1153}
1154
3b72c2fe
M		 1155static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1156{
1157 const int vlan = priv->data.default_vlan;
3b72c2fe
M		 1158 u32 reg;
1159 int i;
1e5c4bc4 1160 int unreg_mcast_mask;
3b72c2fe
M		 1161
1162 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1163 CPSW2_PORT_VLAN;
1164
1165 writel(vlan, &priv->host_port_regs->port_vlan);
1166
0237c110 1167 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1168 slave_write(priv->slaves + i, vlan, reg);
1169
1e5c4bc4
LS		 1170 if (priv->ndev->flags & IFF_ALLMULTI)
1171 unreg_mcast_mask = ALE_ALL_PORTS;
1172 else
1173 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1174
61f1cef9
GS		 1175 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1176 ALE_ALL_PORTS, ALE_ALL_PORTS,
1177 unreg_mcast_mask);
3b72c2fe
M		 1178}
1179
df828598
M		 1180static void cpsw_init_host_port(struct cpsw_priv *priv)
1181{
3b72c2fe 1182 u32 control_reg;
d9ba8f9e 1183 u32 fifo_mode;
3b72c2fe 1184
df828598
M		 1185 /* soft reset the controller and initialize ale */
1186 soft_reset("cpsw", &priv->regs->soft_reset);
1187 cpsw_ale_start(priv->ale);
1188
1189 /* switch to vlan unaware mode */
71a2cbb7 1190 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe
M		 1191 CPSW_ALE_VLAN_AWARE);
1192 control_reg = readl(&priv->regs->control);
1193 control_reg |= CPSW_VLAN_AWARE;
1194 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1195 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1196 CPSW_FIFO_NORMAL_MODE;
1197 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1198
1199 /* setup host port priority mapping */
1200 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1201 &priv->host_port_regs->cpdma_tx_pri_map);
1202 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1203
71a2cbb7 1204 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
df828598
M		 1205 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1206
d9ba8f9e 1207 if (!priv->data.dual_emac) {
71a2cbb7 1208 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e
M		 1209 0, 0);
1210 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
71a2cbb7 1211 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1212 }
df828598
M		 1213}
1214
aacebbf8
SS		 1215static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1216{
3995d265
SP		 1217 u32 slave_port;
1218
6f1f5836 1219 slave_port = cpsw_get_slave_port(slave->slave_num);
3995d265 1220
aacebbf8
SS		 1221 if (!slave->phy)
1222 return;
1223 phy_stop(slave->phy);
1224 phy_disconnect(slave->phy);
1225 slave->phy = NULL;
3995d265
SP		 1226 cpsw_ale_control_set(priv->ale, slave_port,
1227 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1f95ba00 1228 soft_reset_slave(slave);
aacebbf8
SS		 1229}
1230
df828598
M		 1231static int cpsw_ndo_open(struct net_device *ndev)
1232{
1233 struct cpsw_priv *priv = netdev_priv(ndev);
1234 int i, ret;
1235 u32 reg;
1236
108a6537
GS		 1237 ret = pm_runtime_get_sync(&priv->pdev->dev);
1238 if (ret < 0) {
1239 pm_runtime_put_noidle(&priv->pdev->dev);
1240 return ret;
1241 }
3fa88c51 1242
d9ba8f9e
M		 1243 if (!cpsw_common_res_usage_state(priv))
1244 cpsw_intr_disable(priv);
df828598
M		 1245 netif_carrier_off(ndev);
1246
549985ee 1247 reg = priv->version;
df828598
M		 1248
1249 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1250 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1251 CPSW_RTL_VERSION(reg));
1252
1253 /* initialize host and slave ports */
d9ba8f9e
M		 1254 if (!cpsw_common_res_usage_state(priv))
1255 cpsw_init_host_port(priv);
df828598
M		 1256 for_each_slave(priv, cpsw_slave_open, priv);
1257
3b72c2fe 1258 /* Add default VLAN */
e6afea0b
M		 1259 if (!priv->data.dual_emac)
1260 cpsw_add_default_vlan(priv);
1261 else
1262 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
61f1cef9 1263 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1264
d9ba8f9e 1265 if (!cpsw_common_res_usage_state(priv)) {
d354eb85 1266 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1793331e 1267 int buf_num;
d354eb85 1268
d9ba8f9e
M		 1269 /* setup tx dma to fixed prio and zero offset */
1270 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1271 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1272
d9ba8f9e
M		 1273 /* disable priority elevation */
1274 __raw_writel(0, &priv->regs->ptype);
df828598 1275
d9ba8f9e
M		 1276 /* enable statistics collection only on all ports */
1277 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1278
1923d6e4
M		 1279 /* Enable internal fifo flow control */
1280 writel(0x7, &priv->regs->flow_control);
1281
32a7432c
M		 1282 napi_enable(&priv_sl0->napi_rx);
1283 napi_enable(&priv_sl0->napi_tx);
d354eb85 1284
7da11600
M		 1285 if (priv_sl0->tx_irq_disabled) {
1286 priv_sl0->tx_irq_disabled = false;
1287 enable_irq(priv->irqs_table[1]);
1288 }
1289
1290 if (priv_sl0->rx_irq_disabled) {
1291 priv_sl0->rx_irq_disabled = false;
1292 enable_irq(priv->irqs_table[0]);
1293 }
1294
1793331e
IK		 1295 buf_num = cpdma_chan_get_rx_buf_num(priv->dma);
1296 for (i = 0; i < buf_num; i++) {
d9ba8f9e 1297 struct sk_buff *skb;
df828598 1298
d9ba8f9e 1299 ret = -ENOMEM;
aacebbf8
SS		 1300 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1301 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1302 if (!skb)
aacebbf8 1303 goto err_cleanup;
d9ba8f9e 1304 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1305 skb_tailroom(skb), 0);
aacebbf8
SS		 1306 if (ret < 0) {
1307 kfree_skb(skb);
1308 goto err_cleanup;
1309 }
d9ba8f9e
M		 1310 }
1311 /* continue even if we didn't manage to submit all
1312 * receive descs
1313 */
1314 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a
M		 1315
1316 if (cpts_register(&priv->pdev->dev, priv->cpts,
1317 priv->data.cpts_clock_mult,
1318 priv->data.cpts_clock_shift))
1319 dev_err(priv->dev, "error registering cpts device\n");
1320
df828598 1321 }
df828598 1322
ff5b8ef2
M		 1323 /* Enable Interrupt pacing if configured */
1324 if (priv->coal_intvl != 0) {
1325 struct ethtool_coalesce coal;
1326
8478b6cd 1327 coal.rx_coalesce_usecs = priv->coal_intvl;
ff5b8ef2
M		 1328 cpsw_set_coalesce(ndev, &coal);
1329 }
1330
f63a975e
M		 1331 cpdma_ctlr_start(priv->dma);
1332 cpsw_intr_enable(priv);
f63a975e 1333
d9ba8f9e
M		 1334 if (priv->data.dual_emac)
1335 priv->slaves[priv->emac_port].open_stat = true;
df828598 1336 return 0;
df828598 1337
aacebbf8
SS		 1338err_cleanup:
1339 cpdma_ctlr_stop(priv->dma);
1340 for_each_slave(priv, cpsw_slave_stop, priv);
1341 pm_runtime_put_sync(&priv->pdev->dev);
1342 netif_carrier_off(priv->ndev);
1343 return ret;
df828598
M		 1344}
1345
1346static int cpsw_ndo_stop(struct net_device *ndev)
1347{
1348 struct cpsw_priv *priv = netdev_priv(ndev);
1349
1350 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598 1351 netif_stop_queue(priv->ndev);
df828598 1352 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1353
1354 if (cpsw_common_res_usage_state(priv) <= 1) {
d354eb85
M		 1355 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1356
32a7432c
M		 1357 napi_disable(&priv_sl0->napi_rx);
1358 napi_disable(&priv_sl0->napi_tx);
f280e89a 1359 cpts_unregister(priv->cpts);
d9ba8f9e 1360 cpsw_intr_disable(priv);
d9ba8f9e
M		 1361 cpdma_ctlr_stop(priv->dma);
1362 cpsw_ale_stop(priv->ale);
1363 }
df828598 1364 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1365 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1366 if (priv->data.dual_emac)
1367 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1368 return 0;
1369}
1370
1371static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1372 struct net_device *ndev)
1373{
1374 struct cpsw_priv *priv = netdev_priv(ndev);
1375 int ret;
1376
860e9538 1377 netif_trans_update(ndev);
df828598
M		 1378
1379 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1380 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1381 ndev->stats.tx_dropped++;
df828598
M		 1382 return NETDEV_TX_OK;
1383 }
1384
9232b16d
M		 1385 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1386 priv->cpts->tx_enable)
2e5b38ab
RC		 1387 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1388
1389 skb_tx_timestamp(skb);
1390
27e9e103 1391 ret = cpsw_tx_packet_submit(priv, skb);
df828598
M		 1392 if (unlikely(ret != 0)) {
1393 cpsw_err(priv, tx_err, "desc submit failed\n");
1394 goto fail;
1395 }
1396
fae50823
M		 1397 /* If there is no more tx desc left free then we need to
1398 * tell the kernel to stop sending us tx frames.
1399 */
d35162f8 1400 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1401 netif_stop_queue(ndev);
1402
df828598
M		 1403 return NETDEV_TX_OK;
1404fail:
8dc43ddc 1405 ndev->stats.tx_dropped++;
df828598
M		 1406 netif_stop_queue(ndev);
1407 return NETDEV_TX_BUSY;
1408}
1409
2e5b38ab
RC		 1410#ifdef CONFIG_TI_CPTS
1411
1412static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1413{
e86ac13b 1414 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1415 u32 ts_en, seq_id;
1416
9232b16d 1417 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1418 slave_write(slave, 0, CPSW1_TS_CTL);
1419 return;
1420 }
1421
1422 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1423 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1424
9232b16d 1425 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1426 ts_en |= CPSW_V1_TS_TX_EN;
1427
9232b16d 1428 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1429 ts_en |= CPSW_V1_TS_RX_EN;
1430
1431 slave_write(slave, ts_en, CPSW1_TS_CTL);
1432 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1433}
1434
1435static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1436{
d9ba8f9e 1437 struct cpsw_slave *slave;
2e5b38ab
RC		 1438 u32 ctrl, mtype;
1439
d9ba8f9e
M		 1440 if (priv->data.dual_emac)
1441 slave = &priv->slaves[priv->emac_port];
1442 else
e86ac13b 1443 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1444
2e5b38ab 1445 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1446 switch (priv->version) {
1447 case CPSW_VERSION_2:
1448 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1449
09c55372
GC		 1450 if (priv->cpts->tx_enable)
1451 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1452
09c55372
GC		 1453 if (priv->cpts->rx_enable)
1454 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1455 break;
09c55372
GC		 1456 case CPSW_VERSION_3:
1457 default:
1458 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1459
1460 if (priv->cpts->tx_enable)
1461 ctrl |= CTRL_V3_TX_TS_BITS;
1462
1463 if (priv->cpts->rx_enable)
1464 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1465 break;
09c55372 1466 }
2e5b38ab
RC		 1467
1468 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1469
1470 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1471 slave_write(slave, ctrl, CPSW2_CONTROL);
1472 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1473}
1474
a5b4145b 1475static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1476{
3177bf6f 1477 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1478 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1479 struct hwtstamp_config cfg;
1480
2ee91e54 1481 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1482 priv->version != CPSW_VERSION_2 &&
1483 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1484 return -EOPNOTSUPP;
1485
2e5b38ab
RC		 1486 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1487 return -EFAULT;
1488
1489 /* reserved for future extensions */
1490 if (cfg.flags)
1491 return -EINVAL;
1492
2ee91e54 1493 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1494 return -ERANGE;
2e5b38ab
RC		 1495
1496 switch (cfg.rx_filter) {
1497 case HWTSTAMP_FILTER_NONE:
1498 cpts->rx_enable = 0;
1499 break;
1500 case HWTSTAMP_FILTER_ALL:
1501 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1502 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1503 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1504 return -ERANGE;
1505 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1506 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1507 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1508 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1509 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1510 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1511 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1512 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1513 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1514 cpts->rx_enable = 1;
1515 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1516 break;
1517 default:
1518 return -ERANGE;
1519 }
1520
2ee91e54
BH		 1521 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1522
2e5b38ab
RC		 1523 switch (priv->version) {
1524 case CPSW_VERSION_1:
1525 cpsw_hwtstamp_v1(priv);
1526 break;
1527 case CPSW_VERSION_2:
f7d403cb 1528 case CPSW_VERSION_3:
2e5b38ab
RC		 1529 cpsw_hwtstamp_v2(priv);
1530 break;
1531 default:
2ee91e54 1532 WARN_ON(1);
2e5b38ab
RC		 1533 }
1534
1535 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1536}
1537
a5b4145b
BH		 1538static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1539{
1540 struct cpsw_priv *priv = netdev_priv(dev);
1541 struct cpts *cpts = priv->cpts;
1542 struct hwtstamp_config cfg;
1543
1544 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1545 priv->version != CPSW_VERSION_2 &&
1546 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1547 return -EOPNOTSUPP;
1548
1549 cfg.flags = 0;
1550 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1551 cfg.rx_filter = (cpts->rx_enable ?
1552 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1553
1554 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1555}
1556
2e5b38ab
RC		 1557#endif /*CONFIG_TI_CPTS*/
1558
1559static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1560{
11f2c988 1561 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1562 int slave_no = cpsw_slave_index(priv);
1563
2e5b38ab
RC		 1564 if (!netif_running(dev))
1565 return -EINVAL;
1566
11f2c988 1567 switch (cmd) {
2e5b38ab 1568#ifdef CONFIG_TI_CPTS
11f2c988 1569 case SIOCSHWTSTAMP:
a5b4145b
BH		 1570 return cpsw_hwtstamp_set(dev, req);
1571 case SIOCGHWTSTAMP:
1572 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1573#endif
11f2c988
M		 1574 }
1575
c1b59947
SS		 1576 if (!priv->slaves[slave_no].phy)
1577 return -EOPNOTSUPP;
1578 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1579}
1580
df828598
M		 1581static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1582{
1583 struct cpsw_priv *priv = netdev_priv(ndev);
1584
1585 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1586 ndev->stats.tx_errors++;
df828598 1587 cpsw_intr_disable(priv);
df828598
M		 1588 cpdma_chan_stop(priv->txch);
1589 cpdma_chan_start(priv->txch);
df828598 1590 cpsw_intr_enable(priv);
df828598
M		 1591}
1592
dcfd8d58
M		 1593static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1594{
1595 struct cpsw_priv *priv = netdev_priv(ndev);
1596 struct sockaddr *addr = (struct sockaddr *)p;
1597 int flags = 0;
1598 u16 vid = 0;
a6c5d14f 1599 int ret;
dcfd8d58
M		 1600
1601 if (!is_valid_ether_addr(addr->sa_data))
1602 return -EADDRNOTAVAIL;
1603
a6c5d14f
GS		 1604 ret = pm_runtime_get_sync(&priv->pdev->dev);
1605 if (ret < 0) {
1606 pm_runtime_put_noidle(&priv->pdev->dev);
1607 return ret;
1608 }
1609
dcfd8d58
M		 1610 if (priv->data.dual_emac) {
1611 vid = priv->slaves[priv->emac_port].port_vlan;
1612 flags = ALE_VLAN;
1613 }
1614
71a2cbb7 1615 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1616 flags, vid);
71a2cbb7 1617 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1618 flags, vid);
1619
1620 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1621 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1622 for_each_slave(priv, cpsw_set_slave_mac, priv);
1623
a6c5d14f
GS		 1624 pm_runtime_put(&priv->pdev->dev);
1625
dcfd8d58
M		 1626 return 0;
1627}
1628
df828598
M		 1629#ifdef CONFIG_NET_POLL_CONTROLLER
1630static void cpsw_ndo_poll_controller(struct net_device *ndev)
1631{
1632 struct cpsw_priv *priv = netdev_priv(ndev);
1633
1634 cpsw_intr_disable(priv);
92cb13fb
FB		 1635 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1636 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598 1637 cpsw_intr_enable(priv);
df828598
M		 1638}
1639#endif
1640
3b72c2fe
M		 1641static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1642 unsigned short vid)
1643{
1644 int ret;
9f6bd8fa
M		 1645 int unreg_mcast_mask = 0;
1646 u32 port_mask;
1e5c4bc4 1647
9f6bd8fa
M		 1648 if (priv->data.dual_emac) {
1649 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1650
9f6bd8fa
M		 1651 if (priv->ndev->flags & IFF_ALLMULTI)
1652 unreg_mcast_mask = port_mask;
1653 } else {
1654 port_mask = ALE_ALL_PORTS;
1655
1656 if (priv->ndev->flags & IFF_ALLMULTI)
1657 unreg_mcast_mask = ALE_ALL_PORTS;
1658 else
1659 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1660 }
3b72c2fe 1661
9f6bd8fa 1662 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
61f1cef9 1663 unreg_mcast_mask);
3b72c2fe
M		 1664 if (ret != 0)
1665 return ret;
1666
1667 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1668 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1669 if (ret != 0)
1670 goto clean_vid;
1671
1672 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1673 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1674 if (ret != 0)
1675 goto clean_vlan_ucast;
1676 return 0;
1677
1678clean_vlan_ucast:
1679 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1680 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1681clean_vid:
1682 cpsw_ale_del_vlan(priv->ale, vid, 0);
1683 return ret;
1684}
1685
1686static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1687 __be16 proto, u16 vid)
3b72c2fe
M		 1688{
1689 struct cpsw_priv *priv = netdev_priv(ndev);
a6c5d14f 1690 int ret;
3b72c2fe
M		 1691
1692 if (vid == priv->data.default_vlan)
1693 return 0;
1694
a6c5d14f
GS		 1695 ret = pm_runtime_get_sync(&priv->pdev->dev);
1696 if (ret < 0) {
1697 pm_runtime_put_noidle(&priv->pdev->dev);
1698 return ret;
1699 }
1700
02a54164
M		 1701 if (priv->data.dual_emac) {
1702 /* In dual EMAC, reserved VLAN id should not be used for
1703 * creating VLAN interfaces as this can break the dual
1704 * EMAC port separation
1705 */
1706 int i;
1707
1708 for (i = 0; i < priv->data.slaves; i++) {
1709 if (vid == priv->slaves[i].port_vlan)
1710 return -EINVAL;
1711 }
1712 }
1713
3b72c2fe 1714 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
a6c5d14f
GS		 1715 ret = cpsw_add_vlan_ale_entry(priv, vid);
1716
1717 pm_runtime_put(&priv->pdev->dev);
1718 return ret;
3b72c2fe
M		 1719}
1720
1721static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1722 __be16 proto, u16 vid)
3b72c2fe
M		 1723{
1724 struct cpsw_priv *priv = netdev_priv(ndev);
1725 int ret;
1726
1727 if (vid == priv->data.default_vlan)
1728 return 0;
1729
a6c5d14f
GS		 1730 ret = pm_runtime_get_sync(&priv->pdev->dev);
1731 if (ret < 0) {
1732 pm_runtime_put_noidle(&priv->pdev->dev);
1733 return ret;
1734 }
1735
02a54164
M		 1736 if (priv->data.dual_emac) {
1737 int i;
1738
1739 for (i = 0; i < priv->data.slaves; i++) {
1740 if (vid == priv->slaves[i].port_vlan)
1741 return -EINVAL;
1742 }
1743 }
1744
3b72c2fe
M		 1745 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1746 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1747 if (ret != 0)
1748 return ret;
1749
1750 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
61f1cef9 1751 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1752 if (ret != 0)
1753 return ret;
1754
a6c5d14f
GS		 1755 ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1756 0, ALE_VLAN, vid);
1757 pm_runtime_put(&priv->pdev->dev);
1758 return ret;
3b72c2fe
M		 1759}
1760
df828598
M		 1761static const struct net_device_ops cpsw_netdev_ops = {
1762 .ndo_open = cpsw_ndo_open,
1763 .ndo_stop = cpsw_ndo_stop,
1764 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1765 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1766 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1767 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1768 .ndo_change_mtu = eth_change_mtu,
df828598 1769 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1770 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1771#ifdef CONFIG_NET_POLL_CONTROLLER
1772 .ndo_poll_controller = cpsw_ndo_poll_controller,
1773#endif
3b72c2fe
M		 1774 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1775 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1776};
1777
52c4f0ec
M		 1778static int cpsw_get_regs_len(struct net_device *ndev)
1779{
1780 struct cpsw_priv *priv = netdev_priv(ndev);
1781
1782 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1783}
1784
1785static void cpsw_get_regs(struct net_device *ndev,
1786 struct ethtool_regs *regs, void *p)
1787{
1788 struct cpsw_priv *priv = netdev_priv(ndev);
1789 u32 *reg = p;
1790
1791 /* update CPSW IP version */
1792 regs->version = priv->version;
1793
1794 cpsw_ale_dump(priv->ale, reg);
1795}
1796
df828598
M		 1797static void cpsw_get_drvinfo(struct net_device *ndev,
1798 struct ethtool_drvinfo *info)
1799{
1800 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f 1801
52c4f0ec 1802 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f
JP		 1803 strlcpy(info->version, "1.0", sizeof(info->version));
1804 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
df828598
M		 1805}
1806
1807static u32 cpsw_get_msglevel(struct net_device *ndev)
1808{
1809 struct cpsw_priv *priv = netdev_priv(ndev);
1810 return priv->msg_enable;
1811}
1812
1813static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1814{
1815 struct cpsw_priv *priv = netdev_priv(ndev);
1816 priv->msg_enable = value;
1817}
1818
2e5b38ab
RC		 1819static int cpsw_get_ts_info(struct net_device *ndev,
1820 struct ethtool_ts_info *info)
1821{
1822#ifdef CONFIG_TI_CPTS
1823 struct cpsw_priv *priv = netdev_priv(ndev);
1824
1825 info->so_timestamping =
1826 SOF_TIMESTAMPING_TX_HARDWARE |
1827 SOF_TIMESTAMPING_TX_SOFTWARE |
1828 SOF_TIMESTAMPING_RX_HARDWARE |
1829 SOF_TIMESTAMPING_RX_SOFTWARE |
1830 SOF_TIMESTAMPING_SOFTWARE |
1831 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1832 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1833 info->tx_types =
1834 (1 << HWTSTAMP_TX_OFF) |
1835 (1 << HWTSTAMP_TX_ON);
1836 info->rx_filters =
1837 (1 << HWTSTAMP_FILTER_NONE) |
1838 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1839#else
1840 info->so_timestamping =
1841 SOF_TIMESTAMPING_TX_SOFTWARE |
1842 SOF_TIMESTAMPING_RX_SOFTWARE |
1843 SOF_TIMESTAMPING_SOFTWARE;
1844 info->phc_index = -1;
1845 info->tx_types = 0;
1846 info->rx_filters = 0;
1847#endif
1848 return 0;
1849}
1850
d3bb9c58
M		 1851static int cpsw_get_settings(struct net_device *ndev,
1852 struct ethtool_cmd *ecmd)
1853{
1854 struct cpsw_priv *priv = netdev_priv(ndev);
1855 int slave_no = cpsw_slave_index(priv);
1856
1857 if (priv->slaves[slave_no].phy)
1858 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1859 else
1860 return -EOPNOTSUPP;
1861}
1862
1863static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1864{
1865 struct cpsw_priv *priv = netdev_priv(ndev);
1866 int slave_no = cpsw_slave_index(priv);
1867
1868 if (priv->slaves[slave_no].phy)
1869 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1870 else
1871 return -EOPNOTSUPP;
1872}
1873
d8a64420
MU		 1874static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1875{
1876 struct cpsw_priv *priv = netdev_priv(ndev);
1877 int slave_no = cpsw_slave_index(priv);
1878
1879 wol->supported = 0;
1880 wol->wolopts = 0;
1881
1882 if (priv->slaves[slave_no].phy)
1883 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1884}
1885
1886static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1887{
1888 struct cpsw_priv *priv = netdev_priv(ndev);
1889 int slave_no = cpsw_slave_index(priv);
1890
1891 if (priv->slaves[slave_no].phy)
1892 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1893 else
1894 return -EOPNOTSUPP;
1895}
1896
1923d6e4
M		 1897static void cpsw_get_pauseparam(struct net_device *ndev,
1898 struct ethtool_pauseparam *pause)
1899{
1900 struct cpsw_priv *priv = netdev_priv(ndev);
1901
1902 pause->autoneg = AUTONEG_DISABLE;
1903 pause->rx_pause = priv->rx_pause ? true : false;
1904 pause->tx_pause = priv->tx_pause ? true : false;
1905}
1906
1907static int cpsw_set_pauseparam(struct net_device *ndev,
1908 struct ethtool_pauseparam *pause)
1909{
1910 struct cpsw_priv *priv = netdev_priv(ndev);
1911 bool link;
1912
1913 priv->rx_pause = pause->rx_pause ? true : false;
1914 priv->tx_pause = pause->tx_pause ? true : false;
1915
1916 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1923d6e4
M		 1917 return 0;
1918}
1919
7898b1da
GS		 1920static int cpsw_ethtool_op_begin(struct net_device *ndev)
1921{
1922 struct cpsw_priv *priv = netdev_priv(ndev);
1923 int ret;
1924
1925 ret = pm_runtime_get_sync(&priv->pdev->dev);
1926 if (ret < 0) {
1927 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
1928 pm_runtime_put_noidle(&priv->pdev->dev);
1929 }
1930
1931 return ret;
1932}
1933
1934static void cpsw_ethtool_op_complete(struct net_device *ndev)
1935{
1936 struct cpsw_priv *priv = netdev_priv(ndev);
1937 int ret;
1938
1939 ret = pm_runtime_put(&priv->pdev->dev);
1940 if (ret < 0)
1941 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
1942}
1943
df828598
M		 1944static const struct ethtool_ops cpsw_ethtool_ops = {
1945 .get_drvinfo = cpsw_get_drvinfo,
1946 .get_msglevel = cpsw_get_msglevel,
1947 .set_msglevel = cpsw_set_msglevel,
1948 .get_link = ethtool_op_get_link,
2e5b38ab 1949 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1950 .get_settings = cpsw_get_settings,
1951 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1952 .get_coalesce = cpsw_get_coalesce,
1953 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1954 .get_sset_count = cpsw_get_sset_count,
1955 .get_strings = cpsw_get_strings,
1956 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1957 .get_pauseparam = cpsw_get_pauseparam,
1958 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1959 .get_wol = cpsw_get_wol,
1960 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1961 .get_regs_len = cpsw_get_regs_len,
1962 .get_regs = cpsw_get_regs,
7898b1da
GS		 1963 .begin = cpsw_ethtool_op_begin,
1964 .complete = cpsw_ethtool_op_complete,
df828598
M		 1965};
1966
549985ee
RC		 1967static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1968 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1969{
1970 void __iomem *regs = priv->regs;
1971 int slave_num = slave->slave_num;
1972 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1973
1974 slave->data = data;
549985ee
RC		 1975 slave->regs = regs + slave_reg_ofs;
1976 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1977 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1978}
1979
552165bc 1980static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 1981 struct platform_device *pdev)
1982{
1983 struct device_node *node = pdev->dev.of_node;
1984 struct device_node *slave_node;
1985 int i = 0, ret;
1986 u32 prop;
1987
1988 if (!node)
1989 return -EINVAL;
1990
1991 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 1992 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 1993 return -EINVAL;
1994 }
1995 data->slaves = prop;
1996
e86ac13b 1997 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 1998 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 1999 return -EINVAL;
78ca0b28 2000 }
e86ac13b 2001 data->active_slave = prop;
78ca0b28 2002
00ab94ee 2003 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 2004 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 2005 return -EINVAL;
00ab94ee
RC		 2006 }
2007 data->cpts_clock_mult = prop;
2008
2009 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 2010 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 2011 return -EINVAL;
00ab94ee
RC		 2012 }
2013 data->cpts_clock_shift = prop;
2014
aa1a15e2
DM		 2015 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2016 * sizeof(struct cpsw_slave_data),
2017 GFP_KERNEL);
b2adaca9 2018 if (!data->slave_data)
aa1a15e2 2019 return -ENOMEM;
2eb32b0a 2020
2eb32b0a 2021 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2022 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2023 return -EINVAL;
2eb32b0a
M		 2024 }
2025 data->channels = prop;
2026
2eb32b0a 2027 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2028 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2029 return -EINVAL;
2eb32b0a
M		 2030 }
2031 data->ale_entries = prop;
2032
2eb32b0a 2033 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2034 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2035 return -EINVAL;
2eb32b0a
M		 2036 }
2037 data->bd_ram_size = prop;
2038
2eb32b0a 2039 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2040 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2041 return -EINVAL;
2eb32b0a
M		 2042 }
2043 data->mac_control = prop;
2044
281abd96
MP		 2045 if (of_property_read_bool(node, "dual_emac"))
2046 data->dual_emac = 1;
d9ba8f9e 2047
549985ee
RC		 2048 /*
2049 * Populate all the child nodes here...
2050 */
2051 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2052 /* We do not want to force this, as in some cases may not have child */
2053 if (ret)
88c99ff6 2054 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2055
8658aaf2 2056 for_each_available_child_of_node(node, slave_node) {
2eb32b0a 2057 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2058 const void *mac_addr = NULL;
549985ee
RC		 2059 int lenp;
2060 const __be32 *parp;
549985ee 2061
f468b10e
MP		 2062 /* This is no slave child node, continue */
2063 if (strcmp(slave_node->name, "slave"))
2064 continue;
2065
552165bc
DR		 2066 slave_data->phy_node = of_parse_phandle(slave_node,
2067 "phy-handle", 0);
f1eea5c1 2068 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2069 if (slave_data->phy_node) {
2070 dev_dbg(&pdev->dev,
2071 "slave[%d] using phy-handle=\"%s\"\n",
2072 i, slave_data->phy_node->full_name);
2073 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2074 /* In the case of a fixed PHY, the DT node associated
2075 * to the PHY is the Ethernet MAC DT node.
2076 */
1f71e8c9
MB		 2077 ret = of_phy_register_fixed_link(slave_node);
2078 if (ret)
2079 return ret;
06cd6d6e 2080 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2081 } else if (parp) {
2082 u32 phyid;
2083 struct device_node *mdio_node;
2084 struct platform_device *mdio;
2085
2086 if (lenp != (sizeof(__be32) * 2)) {
2087 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2088 goto no_phy_slave;
2089 }
2090 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2091 phyid = be32_to_cpup(parp+1);
2092 mdio = of_find_device_by_node(mdio_node);
2093 of_node_put(mdio_node);
2094 if (!mdio) {
2095 dev_err(&pdev->dev, "Missing mdio platform device\n");
2096 return -EINVAL;
2097 }
2098 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2099 PHY_ID_FMT, mdio->name, phyid);
2100 } else {
ae092b5b
DR		 2101 dev_err(&pdev->dev,
2102 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2103 i);
47276fcc 2104 goto no_phy_slave;
2eb32b0a 2105 }
47276fcc
M		 2106 slave_data->phy_if = of_get_phy_mode(slave_node);
2107 if (slave_data->phy_if < 0) {
2108 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2109 i);
2110 return slave_data->phy_if;
2111 }
2112
2113no_phy_slave:
2eb32b0a 2114 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2115 if (mac_addr) {
2eb32b0a 2116 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2117 } else {
b6745f6e
M		 2118 ret = ti_cm_get_macid(&pdev->dev, i,
2119 slave_data->mac_addr);
2120 if (ret)
2121 return ret;
0ba517b1 2122 }
d9ba8f9e 2123 if (data->dual_emac) {
91c4166c 2124 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2125 &prop)) {
88c99ff6 2126 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2127 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2128 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2129 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2130 } else {
2131 slave_data->dual_emac_res_vlan = prop;
2132 }
2133 }
2134
2eb32b0a 2135 i++;
3a27bfac
M		 2136 if (i == data->slaves)
2137 break;
2eb32b0a
M		 2138 }
2139
2140 return 0;
2eb32b0a
M		 2141}
2142
d9ba8f9e
M		 2143static int cpsw_probe_dual_emac(struct platform_device *pdev,
2144 struct cpsw_priv *priv)
2145{
2146 struct cpsw_platform_data *data = &priv->data;
2147 struct net_device *ndev;
2148 struct cpsw_priv *priv_sl2;
2149 int ret = 0, i;
2150
2151 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2152 if (!ndev) {
88c99ff6 2153 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2154 return -ENOMEM;
2155 }
2156
2157 priv_sl2 = netdev_priv(ndev);
d9ba8f9e
M		 2158 priv_sl2->data = *data;
2159 priv_sl2->pdev = pdev;
2160 priv_sl2->ndev = ndev;
2161 priv_sl2->dev = &ndev->dev;
2162 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2163 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2164
2165 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2166 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2167 ETH_ALEN);
88c99ff6 2168 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2169 } else {
2170 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2171 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2172 }
2173 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2174
2175 priv_sl2->slaves = priv->slaves;
ff5b8ef2
M		 2176 priv_sl2->coal_intvl = 0;
2177 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2178
d9ba8f9e 2179 priv_sl2->regs = priv->regs;
d9ba8f9e
M		 2180 priv_sl2->host_port_regs = priv->host_port_regs;
2181 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2182 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2183 priv_sl2->dma = priv->dma;
2184 priv_sl2->txch = priv->txch;
2185 priv_sl2->rxch = priv->rxch;
2186 priv_sl2->ale = priv->ale;
2187 priv_sl2->emac_port = 1;
2188 priv->slaves[1].ndev = ndev;
2189 priv_sl2->cpts = priv->cpts;
2190 priv_sl2->version = priv->version;
2191
2192 for (i = 0; i < priv->num_irqs; i++) {
2193 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2194 priv_sl2->num_irqs = priv->num_irqs;
2195 }
f646968f 2196 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2197
2198 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2199 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2200
2201 /* register the network device */
2202 SET_NETDEV_DEV(ndev, &pdev->dev);
2203 ret = register_netdev(ndev);
2204 if (ret) {
88c99ff6 2205 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2206 free_netdev(ndev);
2207 ret = -ENODEV;
2208 }
2209
2210 return ret;
2211}
2212
7da11600
M		 2213#define CPSW_QUIRK_IRQ BIT(0)
2214
2215static struct platform_device_id cpsw_devtype[] = {
2216 {
2217 /* keep it for existing comaptibles */
2218 .name = "cpsw",
2219 .driver_data = CPSW_QUIRK_IRQ,
2220 }, {
2221 .name = "am335x-cpsw",
2222 .driver_data = CPSW_QUIRK_IRQ,
2223 }, {
2224 .name = "am4372-cpsw",
2225 .driver_data = 0,
2226 }, {
2227 .name = "dra7-cpsw",
2228 .driver_data = 0,
2229 }, {
2230 /* sentinel */
2231 }
2232};
2233MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2234
2235enum ti_cpsw_type {
2236 CPSW = 0,
2237 AM335X_CPSW,
2238 AM4372_CPSW,
2239 DRA7_CPSW,
2240};
2241
2242static const struct of_device_id cpsw_of_mtable[] = {
2243 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2244 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2245 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2246 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2247 { /* sentinel */ },
2248};
2249MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2250
663e12e6 2251static int cpsw_probe(struct platform_device *pdev)
df828598 2252{
ef4183a1 2253 struct clk *clk;
d1bd9acf 2254 struct cpsw_platform_data *data;
df828598
M		 2255 struct net_device *ndev;
2256 struct cpsw_priv *priv;
2257 struct cpdma_params dma_params;
2258 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2259 void __iomem *ss_regs;
2260 struct resource *res, *ss_res;
7da11600 2261 const struct of_device_id *of_id;
1d147ccb 2262 struct gpio_descs *mode;
549985ee 2263 u32 slave_offset, sliver_offset, slave_size;
5087b915
FB		 2264 int ret = 0, i;
2265 int irq;
df828598 2266
df828598
M		 2267 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2268 if (!ndev) {
88c99ff6 2269 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2270 return -ENOMEM;
2271 }
2272
2273 platform_set_drvdata(pdev, ndev);
2274 priv = netdev_priv(ndev);
df828598
M		 2275 priv->pdev = pdev;
2276 priv->ndev = ndev;
2277 priv->dev = &ndev->dev;
2278 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2279 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2280 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
ab8e99d2 2281 if (!priv->cpts) {
88c99ff6 2282 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2283 ret = -ENOMEM;
9232b16d
M		 2284 goto clean_ndev_ret;
2285 }
df828598 2286
1d147ccb
M		 2287 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2288 if (IS_ERR(mode)) {
2289 ret = PTR_ERR(mode);
2290 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2291 goto clean_ndev_ret;
2292 }
2293
1fb19aa7
VH		 2294 /*
2295 * This may be required here for child devices.
2296 */
2297 pm_runtime_enable(&pdev->dev);
2298
739683b4
M		 2299 /* Select default pin state */
2300 pinctrl_pm_select_default_state(&pdev->dev);
2301
552165bc 2302 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2303 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2304 ret = -ENODEV;
aa1a15e2 2305 goto clean_runtime_disable_ret;
2eb32b0a
M		 2306 }
2307 data = &priv->data;
2308
df828598
M		 2309 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2310 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2311 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2312 } else {
7efd26d0 2313 eth_random_addr(priv->mac_addr);
88c99ff6 2314 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2315 }
2316
2317 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2318
aa1a15e2
DM		 2319 priv->slaves = devm_kzalloc(&pdev->dev,
2320 sizeof(struct cpsw_slave) * data->slaves,
2321 GFP_KERNEL);
df828598 2322 if (!priv->slaves) {
aa1a15e2
DM		 2323 ret = -ENOMEM;
2324 goto clean_runtime_disable_ret;
df828598
M		 2325 }
2326 for (i = 0; i < data->slaves; i++)
2327 priv->slaves[i].slave_num = i;
2328
d9ba8f9e
M		 2329 priv->slaves[0].ndev = ndev;
2330 priv->emac_port = 0;
2331
ef4183a1
IK		 2332 clk = devm_clk_get(&pdev->dev, "fck");
2333 if (IS_ERR(clk)) {
aa1a15e2 2334 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2335 ret = -ENODEV;
aa1a15e2 2336 goto clean_runtime_disable_ret;
df828598 2337 }
ff5b8ef2 2338 priv->coal_intvl = 0;
ef4183a1 2339 priv->bus_freq_mhz = clk_get_rate(clk) / 1000000;
df828598 2340
aa1a15e2
DM		 2341 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2342 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2343 if (IS_ERR(ss_regs)) {
2344 ret = PTR_ERR(ss_regs);
2345 goto clean_runtime_disable_ret;
df828598 2346 }
549985ee 2347 priv->regs = ss_regs;
df828598 2348
f280e89a
M		 2349 /* Need to enable clocks with runtime PM api to access module
2350 * registers
2351 */
108a6537
GS		 2352 ret = pm_runtime_get_sync(&pdev->dev);
2353 if (ret < 0) {
2354 pm_runtime_put_noidle(&pdev->dev);
2355 goto clean_runtime_disable_ret;
2356 }
f280e89a
M		 2357 priv->version = readl(&priv->regs->id_ver);
2358 pm_runtime_put_sync(&pdev->dev);
2359
aa1a15e2
DM		 2360 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2361 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2362 if (IS_ERR(priv->wr_regs)) {
2363 ret = PTR_ERR(priv->wr_regs);
2364 goto clean_runtime_disable_ret;
df828598 2365 }
df828598
M		 2366
2367 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2368 memset(&ale_params, 0, sizeof(ale_params));
2369
2370 switch (priv->version) {
2371 case CPSW_VERSION_1:
2372 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2373 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2374 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2375 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2376 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2377 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2378 slave_offset = CPSW1_SLAVE_OFFSET;
2379 slave_size = CPSW1_SLAVE_SIZE;
2380 sliver_offset = CPSW1_SLIVER_OFFSET;
2381 dma_params.desc_mem_phys = 0;
2382 break;
2383 case CPSW_VERSION_2:
c193f365 2384 case CPSW_VERSION_3:
926489be 2385 case CPSW_VERSION_4:
549985ee 2386 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2387 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2388 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2389 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2390 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2391 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2392 slave_offset = CPSW2_SLAVE_OFFSET;
2393 slave_size = CPSW2_SLAVE_SIZE;
2394 sliver_offset = CPSW2_SLIVER_OFFSET;
2395 dma_params.desc_mem_phys =
aa1a15e2 2396 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2397 break;
2398 default:
2399 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2400 ret = -ENODEV;
aa1a15e2 2401 goto clean_runtime_disable_ret;
549985ee
RC		 2402 }
2403 for (i = 0; i < priv->data.slaves; i++) {
2404 struct cpsw_slave *slave = &priv->slaves[i];
2405 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2406 slave_offset += slave_size;
2407 sliver_offset += SLIVER_SIZE;
2408 }
2409
df828598 2410 dma_params.dev = &pdev->dev;
549985ee
RC		 2411 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2412 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2413 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2414 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2415 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2416
2417 dma_params.num_chan = data->channels;
2418 dma_params.has_soft_reset = true;
2419 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2420 dma_params.desc_mem_size = data->bd_ram_size;
2421 dma_params.desc_align = 16;
2422 dma_params.has_ext_regs = true;
549985ee 2423 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2424
2425 priv->dma = cpdma_ctlr_create(&dma_params);
2426 if (!priv->dma) {
2427 dev_err(priv->dev, "error initializing dma\n");
2428 ret = -ENOMEM;
aa1a15e2 2429 goto clean_runtime_disable_ret;
df828598
M		 2430 }
2431
2432 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2433 cpsw_tx_handler);
2434 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2435 cpsw_rx_handler);
2436
2437 if (WARN_ON(!priv->txch || !priv->rxch)) {
2438 dev_err(priv->dev, "error initializing dma channels\n");
2439 ret = -ENOMEM;
2440 goto clean_dma_ret;
2441 }
2442
df828598 2443 ale_params.dev = &ndev->dev;
df828598
M		 2444 ale_params.ale_ageout = ale_ageout;
2445 ale_params.ale_entries = data->ale_entries;
2446 ale_params.ale_ports = data->slaves;
2447
2448 priv->ale = cpsw_ale_create(&ale_params);
2449 if (!priv->ale) {
2450 dev_err(priv->dev, "error initializing ale engine\n");
2451 ret = -ENODEV;
2452 goto clean_dma_ret;
2453 }
2454
c03abd84 2455 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2456 if (ndev->irq < 0) {
2457 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2458 ret = ndev->irq;
df828598
M		 2459 goto clean_ale_ret;
2460 }
2461
7da11600
M		 2462 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2463 if (of_id) {
2464 pdev->id_entry = of_id->data;
2465 if (pdev->id_entry->driver_data)
2466 priv->quirk_irq = true;
2467 }
2468
c03abd84
FB		 2469 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2470 * MISC IRQs which are always kept disabled with this driver so
2471 * we will not request them.
2472 *
2473 * If anyone wants to implement support for those, make sure to
2474 * first request and append them to irqs_table array.
2475 */
c2b32e58 2476
c03abd84 2477 /* RX IRQ */
5087b915 2478 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2479 if (irq < 0) {
2480 ret = irq;
5087b915 2481 goto clean_ale_ret;
c1e3334f 2482 }
5087b915 2483
c03abd84
FB		 2484 priv->irqs_table[0] = irq;
2485 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2486 0, dev_name(&pdev->dev), priv);
2487 if (ret < 0) {
2488 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2489 goto clean_ale_ret;
2490 }
2491
c03abd84 2492 /* TX IRQ */
5087b915 2493 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2494 if (irq < 0) {
2495 ret = irq;
5087b915 2496 goto clean_ale_ret;
c1e3334f 2497 }
5087b915 2498
c03abd84
FB		 2499 priv->irqs_table[1] = irq;
2500 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2501 0, dev_name(&pdev->dev), priv);
2502 if (ret < 0) {
2503 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2504 goto clean_ale_ret;
df828598 2505 }
c03abd84 2506 priv->num_irqs = 2;
c2b32e58 2507
f646968f 2508 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2509
2510 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2511 ndev->ethtool_ops = &cpsw_ethtool_ops;
32a7432c 2512 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
d64b5e85 2513 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2514
2515 /* register the network device */
2516 SET_NETDEV_DEV(ndev, &pdev->dev);
2517 ret = register_netdev(ndev);
2518 if (ret) {
2519 dev_err(priv->dev, "error registering net device\n");
2520 ret = -ENODEV;
aa1a15e2 2521 goto clean_ale_ret;
df828598
M		 2522 }
2523
1a3b5056
OJ		 2524 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2525 &ss_res->start, ndev->irq);
df828598 2526
d9ba8f9e
M		 2527 if (priv->data.dual_emac) {
2528 ret = cpsw_probe_dual_emac(pdev, priv);
2529 if (ret) {
2530 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2531 goto clean_ale_ret;
d9ba8f9e
M		 2532 }
2533 }
2534
df828598
M		 2535 return 0;
2536
df828598
M		 2537clean_ale_ret:
2538 cpsw_ale_destroy(priv->ale);
2539clean_dma_ret:
df828598 2540 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2541clean_runtime_disable_ret:
f150bd7f 2542 pm_runtime_disable(&pdev->dev);
df828598 2543clean_ndev_ret:
d1bd9acf 2544 free_netdev(priv->ndev);
df828598
M		 2545 return ret;
2546}
2547
663e12e6 2548static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2549{
2550 struct net_device *ndev = platform_get_drvdata(pdev);
2551 struct cpsw_priv *priv = netdev_priv(ndev);
8a0b6dc9
GS		 2552 int ret;
2553
2554 ret = pm_runtime_get_sync(&pdev->dev);
2555 if (ret < 0) {
2556 pm_runtime_put_noidle(&pdev->dev);
2557 return ret;
2558 }
df828598 2559
d1bd9acf 2560 if (priv->data.dual_emac)
82b52104 2561 unregister_netdev(priv->slaves[1].ndev);
d1bd9acf 2562 unregister_netdev(ndev);
df828598 2563
df828598 2564 cpsw_ale_destroy(priv->ale);
df828598 2565 cpdma_ctlr_destroy(priv->dma);
3bf2cb3a 2566 of_platform_depopulate(&pdev->dev);
8a0b6dc9
GS		 2567 pm_runtime_put_sync(&pdev->dev);
2568 pm_runtime_disable(&pdev->dev);
d1bd9acf 2569 if (priv->data.dual_emac)
82b52104 2570 free_netdev(priv->slaves[1].ndev);
df828598 2571 free_netdev(ndev);
df828598
M		 2572 return 0;
2573}
2574
8963a504 2575#ifdef CONFIG_PM_SLEEP
df828598
M		 2576static int cpsw_suspend(struct device *dev)
2577{
2578 struct platform_device *pdev = to_platform_device(dev);
2579 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2580 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2581
618073e3
M		 2582 if (priv->data.dual_emac) {
2583 int i;
1e7a2e21 2584
618073e3
M		 2585 for (i = 0; i < priv->data.slaves; i++) {
2586 if (netif_running(priv->slaves[i].ndev))
2587 cpsw_ndo_stop(priv->slaves[i].ndev);
618073e3
M		 2588 }
2589 } else {
2590 if (netif_running(ndev))
2591 cpsw_ndo_stop(ndev);
618073e3 2592 }
1e7a2e21 2593
739683b4
M		 2594 /* Select sleep pin state */
2595 pinctrl_pm_select_sleep_state(&pdev->dev);
2596
df828598
M		 2597 return 0;
2598}
2599
2600static int cpsw_resume(struct device *dev)
2601{
2602 struct platform_device *pdev = to_platform_device(dev);
2603 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2604 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2605
739683b4
M		 2606 /* Select default pin state */
2607 pinctrl_pm_select_default_state(&pdev->dev);
2608
618073e3
M		 2609 if (priv->data.dual_emac) {
2610 int i;
2611
2612 for (i = 0; i < priv->data.slaves; i++) {
2613 if (netif_running(priv->slaves[i].ndev))
2614 cpsw_ndo_open(priv->slaves[i].ndev);
2615 }
2616 } else {
2617 if (netif_running(ndev))
2618 cpsw_ndo_open(ndev);
2619 }
df828598
M		 2620 return 0;
2621}
8963a504 2622#endif
df828598 2623
8963a504 2624static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2625
2626static struct platform_driver cpsw_driver = {
2627 .driver = {
2628 .name = "cpsw",
df828598 2629 .pm = &cpsw_pm_ops,
1e5c76d4 2630 .of_match_table = cpsw_of_mtable,
df828598
M		 2631 },
2632 .probe = cpsw_probe,
663e12e6 2633 .remove = cpsw_remove,
df828598
M		 2634};
2635
6fb3b6b5 2636module_platform_driver(cpsw_driver);
df828598
M		 2637
2638MODULE_LICENSE("GPL");
2639MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2640MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2641MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
This page took 0.51434 seconds and 5 git commands to generate.