projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: ethernet: ti: cpsw: use destroy ctlr to destroy channels
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
d3bb9c58
M		 143#define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
df828598
M		 147static int debug_level;
148module_param(debug_level, int, 0);
149MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151static int ale_ageout = 10;
152module_param(ale_ageout, int, 0);
153MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156module_param(rx_packet_max, int, 0);
157MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
996a5c27 159struct cpsw_wr_regs {
df828598
M		 160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
ff5b8ef2
M		 168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
df828598
M		 177};
178
996a5c27 179struct cpsw_ss_regs {
df828598
M		 180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
bd357af2
RC		 185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
df828598
M		 193};
194
9750a3ad
RC		 195/* CPSW_PORT_V1 */
196#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205/* CPSW_PORT_V2 */
206#define CPSW2_CONTROL 0x00 /* Control Register */
207#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214/* CPSW_PORT_V1 and V2 */
215#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219/* CPSW_PORT_V2 only */
220#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229/* Bit definitions for the CPSW2_CONTROL register */
230#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 240#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 242#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
09c55372
GC		 248#define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 251
09c55372
GC		 252#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257#define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
df828598
M		 366struct cpsw_priv {
367 spinlock_t lock;
368 struct platform_device *pdev;
369 struct net_device *ndev;
32a7432c
M		 370 struct napi_struct napi_rx;
371 struct napi_struct napi_tx;
df828598
M		 372 struct device *dev;
373 struct cpsw_platform_data data;
996a5c27
RC		 374 struct cpsw_ss_regs __iomem *regs;
375 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 376 u8 __iomem *hw_stats;
df828598
M		 377 struct cpsw_host_regs __iomem *host_port_regs;
378 u32 msg_enable;
e90cfac6 379 u32 version;
ff5b8ef2
M		 380 u32 coal_intvl;
381 u32 bus_freq_mhz;
df828598 382 int rx_packet_max;
df828598
M		 383 struct clk *clk;
384 u8 mac_addr[ETH_ALEN];
385 struct cpsw_slave *slaves;
386 struct cpdma_ctlr *dma;
387 struct cpdma_chan *txch, *rxch;
388 struct cpsw_ale *ale;
1923d6e4
M		 389 bool rx_pause;
390 bool tx_pause;
7da11600
M		 391 bool quirk_irq;
392 bool rx_irq_disabled;
393 bool tx_irq_disabled;
df828598
M		 394 /* snapshot of IRQ numbers */
395 u32 irqs_table[4];
396 u32 num_irqs;
9232b16d 397 struct cpts *cpts;
d9ba8f9e 398 u32 emac_port;
df828598
M		 399};
400
d9718546
M		 401struct cpsw_stats {
402 char stat_string[ETH_GSTRING_LEN];
403 int type;
404 int sizeof_stat;
405 int stat_offset;
406};
407
408enum {
409 CPSW_STATS,
410 CPDMA_RX_STATS,
411 CPDMA_TX_STATS,
412};
413
414#define CPSW_STAT(m) CPSW_STATS, \
415 sizeof(((struct cpsw_hw_stats *)0)->m), \
416 offsetof(struct cpsw_hw_stats, m)
417#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
418 sizeof(((struct cpdma_chan_stats *)0)->m), \
419 offsetof(struct cpdma_chan_stats, m)
420#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
421 sizeof(((struct cpdma_chan_stats *)0)->m), \
422 offsetof(struct cpdma_chan_stats, m)
423
424static const struct cpsw_stats cpsw_gstrings_stats[] = {
425 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
426 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
427 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
428 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
429 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
430 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
431 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
432 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
433 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
434 { "Rx Fragments", CPSW_STAT(rxfragments) },
435 { "Rx Octets", CPSW_STAT(rxoctets) },
436 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
437 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
438 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
439 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
440 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
441 { "Collisions", CPSW_STAT(txcollisionframes) },
442 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
443 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
444 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
445 { "Late Collisions", CPSW_STAT(txlatecollisions) },
446 { "Tx Underrun", CPSW_STAT(txunderrun) },
447 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
448 { "Tx Octets", CPSW_STAT(txoctets) },
449 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
450 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
451 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
452 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
453 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
454 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
455 { "Net Octets", CPSW_STAT(netoctets) },
456 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
457 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
458 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
459 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
460 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
461 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
462 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
463 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
464 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
465 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
466 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
467 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
468 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
469 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
470 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
471 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
472 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
473 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
474 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
475 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
476 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
477 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
478 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
479 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
480 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
481 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
482 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
483 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
484 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
485};
486
487#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
488
df828598 489#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 490#define for_each_slave(priv, func, arg...) \
491 do { \
6e6ceaed
SS		 492 struct cpsw_slave *slave; \
493 int n; \
d9ba8f9e
M		 494 if (priv->data.dual_emac) \
495 (func)((priv)->slaves + priv->emac_port, ##arg);\
496 else \
6e6ceaed
SS		 497 for (n = (priv)->data.slaves, \
498 slave = (priv)->slaves; \
499 n; n--) \
500 (func)(slave++, ##arg); \
d9ba8f9e
M		 501 } while (0)
502#define cpsw_get_slave_ndev(priv, __slave_no__) \
1973db0d
M		 503 ((__slave_no__ < priv->data.slaves) ? \
504 priv->slaves[__slave_no__].ndev : NULL)
d9ba8f9e 505#define cpsw_get_slave_priv(priv, __slave_no__) \
1973db0d
M		 506 (((__slave_no__ < priv->data.slaves) && \
507 (priv->slaves[__slave_no__].ndev)) ? \
d9ba8f9e
M		 508 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
509
510#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
511 do { \
512 if (!priv->data.dual_emac) \
513 break; \
514 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
515 ndev = cpsw_get_slave_ndev(priv, 0); \
516 priv = netdev_priv(ndev); \
517 skb->dev = ndev; \
518 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
519 ndev = cpsw_get_slave_ndev(priv, 1); \
520 priv = netdev_priv(ndev); \
521 skb->dev = ndev; \
522 } \
df828598 523 } while (0)
d9ba8f9e
M		 524#define cpsw_add_mcast(priv, addr) \
525 do { \
526 if (priv->data.dual_emac) { \
527 struct cpsw_slave *slave = priv->slaves + \
528 priv->emac_port; \
529 int slave_port = cpsw_get_slave_port(priv, \
530 slave->slave_num); \
531 cpsw_ale_add_mcast(priv->ale, addr, \
71a2cbb7 532 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 533 ALE_VLAN, slave->port_vlan, 0); \
534 } else { \
535 cpsw_ale_add_mcast(priv->ale, addr, \
61f1cef9 536 ALE_ALL_PORTS, \
d9ba8f9e
M		 537 0, 0, 0); \
538 } \
539 } while (0)
540
541static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
542{
71a2cbb7 543 return slave_num + 1;
d9ba8f9e 544}
df828598 545
0cd8f9cc
M		 546static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
547{
548 struct cpsw_priv *priv = netdev_priv(ndev);
549 struct cpsw_ale *ale = priv->ale;
550 int i;
551
552 if (priv->data.dual_emac) {
553 bool flag = false;
554
555 /* Enabling promiscuous mode for one interface will be
556 * common for both the interface as the interface shares
557 * the same hardware resource.
558 */
0d961b3b 559 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 560 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
561 flag = true;
562
563 if (!enable && flag) {
564 enable = true;
565 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
566 }
567
568 if (enable) {
569 /* Enable Bypass */
570 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
571
572 dev_dbg(&ndev->dev, "promiscuity enabled\n");
573 } else {
574 /* Disable Bypass */
575 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
576 dev_dbg(&ndev->dev, "promiscuity disabled\n");
577 }
578 } else {
579 if (enable) {
580 unsigned long timeout = jiffies + HZ;
581
6f979eb3
LS		 582 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
583 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 584 cpsw_ale_control_set(ale, i,
585 ALE_PORT_NOLEARN, 1);
586 cpsw_ale_control_set(ale, i,
587 ALE_PORT_NO_SA_UPDATE, 1);
588 }
589
590 /* Clear All Untouched entries */
591 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
592 do {
593 cpu_relax();
594 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
595 break;
596 } while (time_after(timeout, jiffies));
597 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
598
599 /* Clear all mcast from ALE */
61f1cef9 600 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 601
602 /* Flood All Unicast Packets to Host port */
603 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
604 dev_dbg(&ndev->dev, "promiscuity enabled\n");
605 } else {
6f979eb3 606 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 607 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
608
6f979eb3
LS		 609 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
610 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NOLEARN, 0);
613 cpsw_ale_control_set(ale, i,
614 ALE_PORT_NO_SA_UPDATE, 0);
615 }
616 dev_dbg(&ndev->dev, "promiscuity disabled\n");
617 }
618 }
619}
620
5c50a856
M		 621static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
622{
623 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 624 int vid;
625
626 if (priv->data.dual_emac)
627 vid = priv->slaves[priv->emac_port].port_vlan;
628 else
629 vid = priv->data.default_vlan;
5c50a856
M		 630
631 if (ndev->flags & IFF_PROMISC) {
632 /* Enable promiscuous mode */
0cd8f9cc 633 cpsw_set_promiscious(ndev, true);
1e5c4bc4 634 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 635 return;
0cd8f9cc
M		 636 } else {
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev, false);
5c50a856
M		 639 }
640
1e5c4bc4
LS		 641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
643
5c50a856 644 /* Clear all mcast from ALE */
61f1cef9 645 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 646
647 if (!netdev_mc_empty(ndev)) {
648 struct netdev_hw_addr *ha;
649
650 /* program multicast address list into ALE register */
651 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 652 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 653 }
654 }
655}
656
df828598
M		 657static void cpsw_intr_enable(struct cpsw_priv *priv)
658{
996a5c27
RC		 659 __raw_writel(0xFF, &priv->wr_regs->tx_en);
660 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 661
662 cpdma_ctlr_int_ctrl(priv->dma, true);
663 return;
664}
665
666static void cpsw_intr_disable(struct cpsw_priv *priv)
667{
996a5c27
RC		 668 __raw_writel(0, &priv->wr_regs->tx_en);
669 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 670
671 cpdma_ctlr_int_ctrl(priv->dma, false);
672 return;
673}
674
1a3b5056 675static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 676{
677 struct sk_buff *skb = token;
678 struct net_device *ndev = skb->dev;
679 struct cpsw_priv *priv = netdev_priv(ndev);
680
fae50823
M		 681 /* Check whether the queue is stopped due to stalled tx dma, if the
682 * queue is stopped then start the queue as we have free desc for tx
683 */
df828598 684 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 685 netif_wake_queue(ndev);
9232b16d 686 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 687 ndev->stats.tx_packets++;
688 ndev->stats.tx_bytes += len;
df828598
M		 689 dev_kfree_skb_any(skb);
690}
691
1a3b5056 692static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 693{
694 struct sk_buff *skb = token;
b4727e69 695 struct sk_buff *new_skb;
df828598
M		 696 struct net_device *ndev = skb->dev;
697 struct cpsw_priv *priv = netdev_priv(ndev);
698 int ret = 0;
699
d9ba8f9e
M		 700 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
701
16e5c57d 702 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 703 bool ndev_status = false;
704 struct cpsw_slave *slave = priv->slaves;
705 int n;
706
707 if (priv->data.dual_emac) {
708 /* In dual emac mode check for all interfaces */
709 for (n = priv->data.slaves; n; n--, slave++)
710 if (netif_running(slave->ndev))
711 ndev_status = true;
712 }
713
714 if (ndev_status && (status >= 0)) {
715 /* The packet received is for the interface which
716 * is already down and the other interface is up
dbedd44e 717 * and running, instead of freeing which results
a0e2c822
M		 718 * in reducing of the number of rx descriptor in
719 * DMA engine, requeue skb back to cpdma.
720 */
721 new_skb = skb;
722 goto requeue;
723 }
724
b4727e69 725 /* the interface is going down, skbs are purged */
df828598
M		 726 dev_kfree_skb_any(skb);
727 return;
728 }
b4727e69
SS		 729
730 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
731 if (new_skb) {
df828598 732 skb_put(skb, len);
9232b16d 733 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 734 skb->protocol = eth_type_trans(skb, ndev);
735 netif_receive_skb(skb);
8dc43ddc
TK		 736 ndev->stats.rx_bytes += len;
737 ndev->stats.rx_packets++;
b4727e69 738 } else {
8dc43ddc 739 ndev->stats.rx_dropped++;
b4727e69 740 new_skb = skb;
df828598
M		 741 }
742
a0e2c822 743requeue:
b4727e69
SS		 744 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
745 skb_tailroom(new_skb), 0);
746 if (WARN_ON(ret < 0))
747 dev_kfree_skb_any(new_skb);
df828598
M		 748}
749
c03abd84 750static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 751{
752 struct cpsw_priv *priv = dev_id;
7ce67a38 753
32a7432c 754 writel(0, &priv->wr_regs->tx_en);
c03abd84 755 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
c03abd84 756
7da11600
M		 757 if (priv->quirk_irq) {
758 disable_irq_nosync(priv->irqs_table[1]);
759 priv->tx_irq_disabled = true;
760 }
761
32a7432c 762 napi_schedule(&priv->napi_tx);
c03abd84
FB		 763 return IRQ_HANDLED;
764}
765
766static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
767{
768 struct cpsw_priv *priv = dev_id;
769
770 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
870915fe 771 writel(0, &priv->wr_regs->rx_en);
fd51cf19 772
7da11600
M		 773 if (priv->quirk_irq) {
774 disable_irq_nosync(priv->irqs_table[0]);
775 priv->rx_irq_disabled = true;
776 }
777
32a7432c 778 napi_schedule(&priv->napi_rx);
d354eb85 779 return IRQ_HANDLED;
df828598
M		 780}
781
32a7432c
M		 782static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
783{
784 struct cpsw_priv *priv = napi_to_priv(napi_tx);
785 int num_tx;
786
787 num_tx = cpdma_chan_process(priv->txch, budget);
788 if (num_tx < budget) {
789 napi_complete(napi_tx);
790 writel(0xff, &priv->wr_regs->tx_en);
7da11600
M		 791 if (priv->quirk_irq && priv->tx_irq_disabled) {
792 priv->tx_irq_disabled = false;
793 enable_irq(priv->irqs_table[1]);
794 }
32a7432c
M		 795 }
796
797 if (num_tx)
798 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
799
800 return num_tx;
801}
802
803static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 804{
32a7432c 805 struct cpsw_priv *priv = napi_to_priv(napi_rx);
1e353cdd 806 int num_rx;
df828598 807
510a1e72 808 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 809 if (num_rx < budget) {
32a7432c 810 napi_complete(napi_rx);
870915fe 811 writel(0xff, &priv->wr_regs->rx_en);
7da11600
M		 812 if (priv->quirk_irq && priv->rx_irq_disabled) {
813 priv->rx_irq_disabled = false;
814 enable_irq(priv->irqs_table[0]);
815 }
df828598
M		 816 }
817
1e353cdd
M		 818 if (num_rx)
819 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
510a1e72 820
df828598
M		 821 return num_rx;
822}
823
824static inline void soft_reset(const char *module, void __iomem *reg)
825{
826 unsigned long timeout = jiffies + HZ;
827
828 __raw_writel(1, reg);
829 do {
830 cpu_relax();
831 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
832
833 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
834}
835
836#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
837 ((mac)[2] << 16) | ((mac)[3] << 24))
838#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
839
840static void cpsw_set_slave_mac(struct cpsw_slave *slave,
841 struct cpsw_priv *priv)
842{
9750a3ad
RC		 843 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
844 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 845}
846
847static void _cpsw_adjust_link(struct cpsw_slave *slave,
848 struct cpsw_priv *priv, bool *link)
849{
850 struct phy_device *phy = slave->phy;
851 u32 mac_control = 0;
852 u32 slave_port;
853
854 if (!phy)
855 return;
856
857 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
858
859 if (phy->link) {
860 mac_control = priv->data.mac_control;
861
862 /* enable forwarding */
863 cpsw_ale_control_set(priv->ale, slave_port,
864 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
865
866 if (phy->speed == 1000)
867 mac_control |= BIT(7); /* GIGABITEN */
868 if (phy->duplex)
869 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 870
871 /* set speed_in input in case RMII mode is used in 100Mbps */
872 if (phy->speed == 100)
873 mac_control |= BIT(15);
a81d8762
M		 874 else if (phy->speed == 10)
875 mac_control |= BIT(18); /* In Band mode */
342b7b74 876
1923d6e4
M		 877 if (priv->rx_pause)
878 mac_control |= BIT(3);
879
880 if (priv->tx_pause)
881 mac_control |= BIT(4);
882
df828598
M		 883 *link = true;
884 } else {
885 mac_control = 0;
886 /* disable forwarding */
887 cpsw_ale_control_set(priv->ale, slave_port,
888 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
889 }
890
891 if (mac_control != slave->mac_control) {
892 phy_print_status(phy);
893 __raw_writel(mac_control, &slave->sliver->mac_control);
894 }
895
896 slave->mac_control = mac_control;
897}
898
899static void cpsw_adjust_link(struct net_device *ndev)
900{
901 struct cpsw_priv *priv = netdev_priv(ndev);
902 bool link = false;
903
904 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
905
906 if (link) {
907 netif_carrier_on(ndev);
908 if (netif_running(ndev))
909 netif_wake_queue(ndev);
910 } else {
911 netif_carrier_off(ndev);
912 netif_stop_queue(ndev);
913 }
914}
915
ff5b8ef2
M		 916static int cpsw_get_coalesce(struct net_device *ndev,
917 struct ethtool_coalesce *coal)
918{
919 struct cpsw_priv *priv = netdev_priv(ndev);
920
921 coal->rx_coalesce_usecs = priv->coal_intvl;
922 return 0;
923}
924
925static int cpsw_set_coalesce(struct net_device *ndev,
926 struct ethtool_coalesce *coal)
927{
928 struct cpsw_priv *priv = netdev_priv(ndev);
929 u32 int_ctrl;
930 u32 num_interrupts = 0;
931 u32 prescale = 0;
932 u32 addnl_dvdr = 1;
933 u32 coal_intvl = 0;
934
ff5b8ef2
M		 935 coal_intvl = coal->rx_coalesce_usecs;
936
937 int_ctrl = readl(&priv->wr_regs->int_control);
938 prescale = priv->bus_freq_mhz * 4;
939
a84bc2a9
M		 940 if (!coal->rx_coalesce_usecs) {
941 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
942 goto update_return;
943 }
944
ff5b8ef2
M		 945 if (coal_intvl < CPSW_CMINTMIN_INTVL)
946 coal_intvl = CPSW_CMINTMIN_INTVL;
947
948 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
949 /* Interrupt pacer works with 4us Pulse, we can
950 * throttle further by dilating the 4us pulse.
951 */
952 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
953
954 if (addnl_dvdr > 1) {
955 prescale *= addnl_dvdr;
956 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
957 coal_intvl = (CPSW_CMINTMAX_INTVL
958 * addnl_dvdr);
959 } else {
960 addnl_dvdr = 1;
961 coal_intvl = CPSW_CMINTMAX_INTVL;
962 }
963 }
964
965 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
966 writel(num_interrupts, &priv->wr_regs->rx_imax);
967 writel(num_interrupts, &priv->wr_regs->tx_imax);
968
969 int_ctrl |= CPSW_INTPACEEN;
970 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
971 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 972
973update_return:
ff5b8ef2
M		 974 writel(int_ctrl, &priv->wr_regs->int_control);
975
976 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
977 if (priv->data.dual_emac) {
978 int i;
979
980 for (i = 0; i < priv->data.slaves; i++) {
981 priv = netdev_priv(priv->slaves[i].ndev);
982 priv->coal_intvl = coal_intvl;
983 }
984 } else {
985 priv->coal_intvl = coal_intvl;
986 }
987
988 return 0;
989}
990
d9718546
M		 991static int cpsw_get_sset_count(struct net_device *ndev, int sset)
992{
993 switch (sset) {
994 case ETH_SS_STATS:
995 return CPSW_STATS_LEN;
996 default:
997 return -EOPNOTSUPP;
998 }
999}
1000
1001static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1002{
1003 u8 *p = data;
1004 int i;
1005
1006 switch (stringset) {
1007 case ETH_SS_STATS:
1008 for (i = 0; i < CPSW_STATS_LEN; i++) {
1009 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1010 ETH_GSTRING_LEN);
1011 p += ETH_GSTRING_LEN;
1012 }
1013 break;
1014 }
1015}
1016
1017static void cpsw_get_ethtool_stats(struct net_device *ndev,
1018 struct ethtool_stats *stats, u64 *data)
1019{
1020 struct cpsw_priv *priv = netdev_priv(ndev);
1021 struct cpdma_chan_stats rx_stats;
1022 struct cpdma_chan_stats tx_stats;
1023 u32 val;
1024 u8 *p;
1025 int i;
1026
1027 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1028 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1029 cpdma_chan_get_stats(priv->txch, &tx_stats);
1030
1031 for (i = 0; i < CPSW_STATS_LEN; i++) {
1032 switch (cpsw_gstrings_stats[i].type) {
1033 case CPSW_STATS:
1034 val = readl(priv->hw_stats +
1035 cpsw_gstrings_stats[i].stat_offset);
1036 data[i] = val;
1037 break;
1038
1039 case CPDMA_RX_STATS:
1040 p = (u8 *)&rx_stats +
1041 cpsw_gstrings_stats[i].stat_offset;
1042 data[i] = *(u32 *)p;
1043 break;
1044
1045 case CPDMA_TX_STATS:
1046 p = (u8 *)&tx_stats +
1047 cpsw_gstrings_stats[i].stat_offset;
1048 data[i] = *(u32 *)p;
1049 break;
1050 }
1051 }
1052}
1053
d9ba8f9e
M		 1054static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1055{
1056 u32 i;
1057 u32 usage_count = 0;
1058
1059 if (!priv->data.dual_emac)
1060 return 0;
1061
1062 for (i = 0; i < priv->data.slaves; i++)
1063 if (priv->slaves[i].open_stat)
1064 usage_count++;
1065
1066 return usage_count;
1067}
1068
1069static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1070 struct cpsw_priv *priv, struct sk_buff *skb)
1071{
1072 if (!priv->data.dual_emac)
1073 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1074 skb->len, 0);
d9ba8f9e
M		 1075
1076 if (ndev == cpsw_get_slave_ndev(priv, 0))
1077 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1078 skb->len, 1);
d9ba8f9e
M		 1079 else
1080 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1081 skb->len, 2);
d9ba8f9e
M		 1082}
1083
1084static inline void cpsw_add_dual_emac_def_ale_entries(
1085 struct cpsw_priv *priv, struct cpsw_slave *slave,
1086 u32 slave_port)
1087{
71a2cbb7 1088 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e
M		 1089
1090 if (priv->version == CPSW_VERSION_1)
1091 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1092 else
1093 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1094 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1095 port_mask, port_mask, 0);
1096 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1097 port_mask, ALE_VLAN, slave->port_vlan, 0);
1098 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1099 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1100}
1101
1e7a2e21 1102static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1103{
1104 char name[32];
df828598 1105
1e7a2e21 1106 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1107 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1108}
1109
1110static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1111{
1112 u32 slave_port;
1113
1114 soft_reset_slave(slave);
df828598
M		 1115
1116 /* setup priority mapping */
1117 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1118
1119 switch (priv->version) {
1120 case CPSW_VERSION_1:
1121 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1122 break;
1123 case CPSW_VERSION_2:
c193f365 1124 case CPSW_VERSION_3:
926489be 1125 case CPSW_VERSION_4:
9750a3ad
RC		 1126 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1127 break;
1128 }
df828598
M		 1129
1130 /* setup max packet size, and mac address */
1131 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1132 cpsw_set_slave_mac(slave, priv);
1133
1134 slave->mac_control = 0; /* no link yet */
1135
1136 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1137
d9ba8f9e
M		 1138 if (priv->data.dual_emac)
1139 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1140 else
1141 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1142 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1143
d733f754 1144 if (slave->data->phy_node) {
552165bc 1145 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1146 &cpsw_adjust_link, 0, slave->data->phy_if);
d733f754
DR		 1147 if (!slave->phy) {
1148 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1149 slave->data->phy_node->full_name,
1150 slave->slave_num);
1151 return;
1152 }
1153 } else {
9e42f715 1154 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1155 &cpsw_adjust_link, slave->data->phy_if);
d733f754
DR		 1156 if (IS_ERR(slave->phy)) {
1157 dev_err(priv->dev,
1158 "phy \"%s\" not found on slave %d, err %ld\n",
1159 slave->data->phy_id, slave->slave_num,
1160 PTR_ERR(slave->phy));
1161 slave->phy = NULL;
1162 return;
1163 }
1164 }
2220943a 1165
d733f754 1166 phy_attached_info(slave->phy);
388367a5 1167
d733f754
DR		 1168 phy_start(slave->phy);
1169
1170 /* Configure GMII_SEL register */
1171 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1172}
1173
3b72c2fe
M		 1174static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1175{
1176 const int vlan = priv->data.default_vlan;
3b72c2fe
M		 1177 u32 reg;
1178 int i;
1e5c4bc4 1179 int unreg_mcast_mask;
3b72c2fe
M		 1180
1181 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1182 CPSW2_PORT_VLAN;
1183
1184 writel(vlan, &priv->host_port_regs->port_vlan);
1185
0237c110 1186 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1187 slave_write(priv->slaves + i, vlan, reg);
1188
1e5c4bc4
LS		 1189 if (priv->ndev->flags & IFF_ALLMULTI)
1190 unreg_mcast_mask = ALE_ALL_PORTS;
1191 else
1192 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1193
61f1cef9
GS		 1194 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1195 ALE_ALL_PORTS, ALE_ALL_PORTS,
1196 unreg_mcast_mask);
3b72c2fe
M		 1197}
1198
df828598
M		 1199static void cpsw_init_host_port(struct cpsw_priv *priv)
1200{
3b72c2fe 1201 u32 control_reg;
d9ba8f9e 1202 u32 fifo_mode;
3b72c2fe 1203
df828598
M		 1204 /* soft reset the controller and initialize ale */
1205 soft_reset("cpsw", &priv->regs->soft_reset);
1206 cpsw_ale_start(priv->ale);
1207
1208 /* switch to vlan unaware mode */
71a2cbb7 1209 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe
M		 1210 CPSW_ALE_VLAN_AWARE);
1211 control_reg = readl(&priv->regs->control);
1212 control_reg |= CPSW_VLAN_AWARE;
1213 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1214 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1215 CPSW_FIFO_NORMAL_MODE;
1216 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1217
1218 /* setup host port priority mapping */
1219 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1220 &priv->host_port_regs->cpdma_tx_pri_map);
1221 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1222
71a2cbb7 1223 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
df828598
M		 1224 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1225
d9ba8f9e 1226 if (!priv->data.dual_emac) {
71a2cbb7 1227 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e
M		 1228 0, 0);
1229 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
71a2cbb7 1230 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1231 }
df828598
M		 1232}
1233
aacebbf8
SS		 1234static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1235{
3995d265
SP		 1236 u32 slave_port;
1237
1238 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1239
aacebbf8
SS		 1240 if (!slave->phy)
1241 return;
1242 phy_stop(slave->phy);
1243 phy_disconnect(slave->phy);
1244 slave->phy = NULL;
3995d265
SP		 1245 cpsw_ale_control_set(priv->ale, slave_port,
1246 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
aacebbf8
SS		 1247}
1248
df828598
M		 1249static int cpsw_ndo_open(struct net_device *ndev)
1250{
1251 struct cpsw_priv *priv = netdev_priv(ndev);
1252 int i, ret;
1253 u32 reg;
1254
3fa88c51
GS		 1255 pm_runtime_get_sync(&priv->pdev->dev);
1256
d9ba8f9e
M		 1257 if (!cpsw_common_res_usage_state(priv))
1258 cpsw_intr_disable(priv);
df828598
M		 1259 netif_carrier_off(ndev);
1260
549985ee 1261 reg = priv->version;
df828598
M		 1262
1263 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1264 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1265 CPSW_RTL_VERSION(reg));
1266
1267 /* initialize host and slave ports */
d9ba8f9e
M		 1268 if (!cpsw_common_res_usage_state(priv))
1269 cpsw_init_host_port(priv);
df828598
M		 1270 for_each_slave(priv, cpsw_slave_open, priv);
1271
3b72c2fe 1272 /* Add default VLAN */
e6afea0b
M		 1273 if (!priv->data.dual_emac)
1274 cpsw_add_default_vlan(priv);
1275 else
1276 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
61f1cef9 1277 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1278
d9ba8f9e 1279 if (!cpsw_common_res_usage_state(priv)) {
d354eb85
M		 1280 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1281
d9ba8f9e
M		 1282 /* setup tx dma to fixed prio and zero offset */
1283 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1284 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1285
d9ba8f9e
M		 1286 /* disable priority elevation */
1287 __raw_writel(0, &priv->regs->ptype);
df828598 1288
d9ba8f9e
M		 1289 /* enable statistics collection only on all ports */
1290 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1291
1923d6e4
M		 1292 /* Enable internal fifo flow control */
1293 writel(0x7, &priv->regs->flow_control);
1294
32a7432c
M		 1295 napi_enable(&priv_sl0->napi_rx);
1296 napi_enable(&priv_sl0->napi_tx);
d354eb85 1297
7da11600
M		 1298 if (priv_sl0->tx_irq_disabled) {
1299 priv_sl0->tx_irq_disabled = false;
1300 enable_irq(priv->irqs_table[1]);
1301 }
1302
1303 if (priv_sl0->rx_irq_disabled) {
1304 priv_sl0->rx_irq_disabled = false;
1305 enable_irq(priv->irqs_table[0]);
1306 }
1307
d9ba8f9e
M		 1308 if (WARN_ON(!priv->data.rx_descs))
1309 priv->data.rx_descs = 128;
df828598 1310
d9ba8f9e
M		 1311 for (i = 0; i < priv->data.rx_descs; i++) {
1312 struct sk_buff *skb;
df828598 1313
d9ba8f9e 1314 ret = -ENOMEM;
aacebbf8
SS		 1315 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1316 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1317 if (!skb)
aacebbf8 1318 goto err_cleanup;
d9ba8f9e 1319 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1320 skb_tailroom(skb), 0);
aacebbf8
SS		 1321 if (ret < 0) {
1322 kfree_skb(skb);
1323 goto err_cleanup;
1324 }
d9ba8f9e
M		 1325 }
1326 /* continue even if we didn't manage to submit all
1327 * receive descs
1328 */
1329 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a
M		 1330
1331 if (cpts_register(&priv->pdev->dev, priv->cpts,
1332 priv->data.cpts_clock_mult,
1333 priv->data.cpts_clock_shift))
1334 dev_err(priv->dev, "error registering cpts device\n");
1335
df828598 1336 }
df828598 1337
ff5b8ef2
M		 1338 /* Enable Interrupt pacing if configured */
1339 if (priv->coal_intvl != 0) {
1340 struct ethtool_coalesce coal;
1341
8478b6cd 1342 coal.rx_coalesce_usecs = priv->coal_intvl;
ff5b8ef2
M		 1343 cpsw_set_coalesce(ndev, &coal);
1344 }
1345
f63a975e
M		 1346 cpdma_ctlr_start(priv->dma);
1347 cpsw_intr_enable(priv);
f63a975e 1348
d9ba8f9e
M		 1349 if (priv->data.dual_emac)
1350 priv->slaves[priv->emac_port].open_stat = true;
df828598 1351 return 0;
df828598 1352
aacebbf8
SS		 1353err_cleanup:
1354 cpdma_ctlr_stop(priv->dma);
1355 for_each_slave(priv, cpsw_slave_stop, priv);
1356 pm_runtime_put_sync(&priv->pdev->dev);
1357 netif_carrier_off(priv->ndev);
1358 return ret;
df828598
M		 1359}
1360
1361static int cpsw_ndo_stop(struct net_device *ndev)
1362{
1363 struct cpsw_priv *priv = netdev_priv(ndev);
1364
1365 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598 1366 netif_stop_queue(priv->ndev);
df828598 1367 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1368
1369 if (cpsw_common_res_usage_state(priv) <= 1) {
d354eb85
M		 1370 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1371
32a7432c
M		 1372 napi_disable(&priv_sl0->napi_rx);
1373 napi_disable(&priv_sl0->napi_tx);
f280e89a 1374 cpts_unregister(priv->cpts);
d9ba8f9e 1375 cpsw_intr_disable(priv);
d9ba8f9e
M		 1376 cpdma_ctlr_stop(priv->dma);
1377 cpsw_ale_stop(priv->ale);
1378 }
df828598 1379 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1380 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1381 if (priv->data.dual_emac)
1382 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1383 return 0;
1384}
1385
1386static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1387 struct net_device *ndev)
1388{
1389 struct cpsw_priv *priv = netdev_priv(ndev);
1390 int ret;
1391
860e9538 1392 netif_trans_update(ndev);
df828598
M		 1393
1394 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1395 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1396 ndev->stats.tx_dropped++;
df828598
M		 1397 return NETDEV_TX_OK;
1398 }
1399
9232b16d
M		 1400 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1401 priv->cpts->tx_enable)
2e5b38ab
RC		 1402 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1403
1404 skb_tx_timestamp(skb);
1405
d9ba8f9e 1406 ret = cpsw_tx_packet_submit(ndev, priv, skb);
df828598
M		 1407 if (unlikely(ret != 0)) {
1408 cpsw_err(priv, tx_err, "desc submit failed\n");
1409 goto fail;
1410 }
1411
fae50823
M		 1412 /* If there is no more tx desc left free then we need to
1413 * tell the kernel to stop sending us tx frames.
1414 */
d35162f8 1415 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1416 netif_stop_queue(ndev);
1417
df828598
M		 1418 return NETDEV_TX_OK;
1419fail:
8dc43ddc 1420 ndev->stats.tx_dropped++;
df828598
M		 1421 netif_stop_queue(ndev);
1422 return NETDEV_TX_BUSY;
1423}
1424
2e5b38ab
RC		 1425#ifdef CONFIG_TI_CPTS
1426
1427static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1428{
e86ac13b 1429 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1430 u32 ts_en, seq_id;
1431
9232b16d 1432 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1433 slave_write(slave, 0, CPSW1_TS_CTL);
1434 return;
1435 }
1436
1437 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1438 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1439
9232b16d 1440 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1441 ts_en |= CPSW_V1_TS_TX_EN;
1442
9232b16d 1443 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1444 ts_en |= CPSW_V1_TS_RX_EN;
1445
1446 slave_write(slave, ts_en, CPSW1_TS_CTL);
1447 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1448}
1449
1450static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1451{
d9ba8f9e 1452 struct cpsw_slave *slave;
2e5b38ab
RC		 1453 u32 ctrl, mtype;
1454
d9ba8f9e
M		 1455 if (priv->data.dual_emac)
1456 slave = &priv->slaves[priv->emac_port];
1457 else
e86ac13b 1458 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1459
2e5b38ab 1460 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1461 switch (priv->version) {
1462 case CPSW_VERSION_2:
1463 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1464
09c55372
GC		 1465 if (priv->cpts->tx_enable)
1466 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1467
09c55372
GC		 1468 if (priv->cpts->rx_enable)
1469 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1470 break;
09c55372
GC		 1471 case CPSW_VERSION_3:
1472 default:
1473 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1474
1475 if (priv->cpts->tx_enable)
1476 ctrl |= CTRL_V3_TX_TS_BITS;
1477
1478 if (priv->cpts->rx_enable)
1479 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1480 break;
09c55372 1481 }
2e5b38ab
RC		 1482
1483 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1484
1485 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1486 slave_write(slave, ctrl, CPSW2_CONTROL);
1487 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1488}
1489
a5b4145b 1490static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1491{
3177bf6f 1492 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1493 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1494 struct hwtstamp_config cfg;
1495
2ee91e54 1496 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1497 priv->version != CPSW_VERSION_2 &&
1498 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1499 return -EOPNOTSUPP;
1500
2e5b38ab
RC		 1501 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1502 return -EFAULT;
1503
1504 /* reserved for future extensions */
1505 if (cfg.flags)
1506 return -EINVAL;
1507
2ee91e54 1508 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1509 return -ERANGE;
2e5b38ab
RC		 1510
1511 switch (cfg.rx_filter) {
1512 case HWTSTAMP_FILTER_NONE:
1513 cpts->rx_enable = 0;
1514 break;
1515 case HWTSTAMP_FILTER_ALL:
1516 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1517 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1518 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1519 return -ERANGE;
1520 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1521 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1523 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1524 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1525 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1526 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1527 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1528 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1529 cpts->rx_enable = 1;
1530 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1531 break;
1532 default:
1533 return -ERANGE;
1534 }
1535
2ee91e54
BH		 1536 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1537
2e5b38ab
RC		 1538 switch (priv->version) {
1539 case CPSW_VERSION_1:
1540 cpsw_hwtstamp_v1(priv);
1541 break;
1542 case CPSW_VERSION_2:
f7d403cb 1543 case CPSW_VERSION_3:
2e5b38ab
RC		 1544 cpsw_hwtstamp_v2(priv);
1545 break;
1546 default:
2ee91e54 1547 WARN_ON(1);
2e5b38ab
RC		 1548 }
1549
1550 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1551}
1552
a5b4145b
BH		 1553static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1554{
1555 struct cpsw_priv *priv = netdev_priv(dev);
1556 struct cpts *cpts = priv->cpts;
1557 struct hwtstamp_config cfg;
1558
1559 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1560 priv->version != CPSW_VERSION_2 &&
1561 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1562 return -EOPNOTSUPP;
1563
1564 cfg.flags = 0;
1565 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1566 cfg.rx_filter = (cpts->rx_enable ?
1567 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1568
1569 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1570}
1571
2e5b38ab
RC		 1572#endif /*CONFIG_TI_CPTS*/
1573
1574static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1575{
11f2c988 1576 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1577 int slave_no = cpsw_slave_index(priv);
1578
2e5b38ab
RC		 1579 if (!netif_running(dev))
1580 return -EINVAL;
1581
11f2c988 1582 switch (cmd) {
2e5b38ab 1583#ifdef CONFIG_TI_CPTS
11f2c988 1584 case SIOCSHWTSTAMP:
a5b4145b
BH		 1585 return cpsw_hwtstamp_set(dev, req);
1586 case SIOCGHWTSTAMP:
1587 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1588#endif
11f2c988
M		 1589 }
1590
c1b59947
SS		 1591 if (!priv->slaves[slave_no].phy)
1592 return -EOPNOTSUPP;
1593 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1594}
1595
df828598
M		 1596static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1597{
1598 struct cpsw_priv *priv = netdev_priv(ndev);
1599
1600 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1601 ndev->stats.tx_errors++;
df828598 1602 cpsw_intr_disable(priv);
df828598
M		 1603 cpdma_chan_stop(priv->txch);
1604 cpdma_chan_start(priv->txch);
df828598 1605 cpsw_intr_enable(priv);
df828598
M		 1606}
1607
dcfd8d58
M		 1608static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1609{
1610 struct cpsw_priv *priv = netdev_priv(ndev);
1611 struct sockaddr *addr = (struct sockaddr *)p;
1612 int flags = 0;
1613 u16 vid = 0;
1614
1615 if (!is_valid_ether_addr(addr->sa_data))
1616 return -EADDRNOTAVAIL;
1617
1618 if (priv->data.dual_emac) {
1619 vid = priv->slaves[priv->emac_port].port_vlan;
1620 flags = ALE_VLAN;
1621 }
1622
71a2cbb7 1623 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1624 flags, vid);
71a2cbb7 1625 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1626 flags, vid);
1627
1628 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1629 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1630 for_each_slave(priv, cpsw_set_slave_mac, priv);
1631
1632 return 0;
1633}
1634
df828598
M		 1635#ifdef CONFIG_NET_POLL_CONTROLLER
1636static void cpsw_ndo_poll_controller(struct net_device *ndev)
1637{
1638 struct cpsw_priv *priv = netdev_priv(ndev);
1639
1640 cpsw_intr_disable(priv);
92cb13fb
FB		 1641 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1642 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598 1643 cpsw_intr_enable(priv);
df828598
M		 1644}
1645#endif
1646
3b72c2fe
M		 1647static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1648 unsigned short vid)
1649{
1650 int ret;
9f6bd8fa
M		 1651 int unreg_mcast_mask = 0;
1652 u32 port_mask;
1e5c4bc4 1653
9f6bd8fa
M		 1654 if (priv->data.dual_emac) {
1655 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1656
9f6bd8fa
M		 1657 if (priv->ndev->flags & IFF_ALLMULTI)
1658 unreg_mcast_mask = port_mask;
1659 } else {
1660 port_mask = ALE_ALL_PORTS;
1661
1662 if (priv->ndev->flags & IFF_ALLMULTI)
1663 unreg_mcast_mask = ALE_ALL_PORTS;
1664 else
1665 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1666 }
3b72c2fe 1667
9f6bd8fa 1668 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
61f1cef9 1669 unreg_mcast_mask);
3b72c2fe
M		 1670 if (ret != 0)
1671 return ret;
1672
1673 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1674 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1675 if (ret != 0)
1676 goto clean_vid;
1677
1678 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1679 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1680 if (ret != 0)
1681 goto clean_vlan_ucast;
1682 return 0;
1683
1684clean_vlan_ucast:
1685 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1686 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1687clean_vid:
1688 cpsw_ale_del_vlan(priv->ale, vid, 0);
1689 return ret;
1690}
1691
1692static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1693 __be16 proto, u16 vid)
3b72c2fe
M		 1694{
1695 struct cpsw_priv *priv = netdev_priv(ndev);
1696
1697 if (vid == priv->data.default_vlan)
1698 return 0;
1699
02a54164
M		 1700 if (priv->data.dual_emac) {
1701 /* In dual EMAC, reserved VLAN id should not be used for
1702 * creating VLAN interfaces as this can break the dual
1703 * EMAC port separation
1704 */
1705 int i;
1706
1707 for (i = 0; i < priv->data.slaves; i++) {
1708 if (vid == priv->slaves[i].port_vlan)
1709 return -EINVAL;
1710 }
1711 }
1712
3b72c2fe
M		 1713 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1714 return cpsw_add_vlan_ale_entry(priv, vid);
1715}
1716
1717static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1718 __be16 proto, u16 vid)
3b72c2fe
M		 1719{
1720 struct cpsw_priv *priv = netdev_priv(ndev);
1721 int ret;
1722
1723 if (vid == priv->data.default_vlan)
1724 return 0;
1725
02a54164
M		 1726 if (priv->data.dual_emac) {
1727 int i;
1728
1729 for (i = 0; i < priv->data.slaves; i++) {
1730 if (vid == priv->slaves[i].port_vlan)
1731 return -EINVAL;
1732 }
1733 }
1734
3b72c2fe
M		 1735 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1736 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1737 if (ret != 0)
1738 return ret;
1739
1740 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
61f1cef9 1741 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1742 if (ret != 0)
1743 return ret;
1744
1745 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1746 0, ALE_VLAN, vid);
1747}
1748
df828598
M		 1749static const struct net_device_ops cpsw_netdev_ops = {
1750 .ndo_open = cpsw_ndo_open,
1751 .ndo_stop = cpsw_ndo_stop,
1752 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1753 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1754 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1755 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1756 .ndo_change_mtu = eth_change_mtu,
df828598 1757 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1758 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1759#ifdef CONFIG_NET_POLL_CONTROLLER
1760 .ndo_poll_controller = cpsw_ndo_poll_controller,
1761#endif
3b72c2fe
M		 1762 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1763 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1764};
1765
52c4f0ec
M		 1766static int cpsw_get_regs_len(struct net_device *ndev)
1767{
1768 struct cpsw_priv *priv = netdev_priv(ndev);
1769
1770 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1771}
1772
1773static void cpsw_get_regs(struct net_device *ndev,
1774 struct ethtool_regs *regs, void *p)
1775{
1776 struct cpsw_priv *priv = netdev_priv(ndev);
1777 u32 *reg = p;
1778
1779 /* update CPSW IP version */
1780 regs->version = priv->version;
1781
1782 cpsw_ale_dump(priv->ale, reg);
1783}
1784
df828598
M		 1785static void cpsw_get_drvinfo(struct net_device *ndev,
1786 struct ethtool_drvinfo *info)
1787{
1788 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f 1789
52c4f0ec 1790 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f
JP		 1791 strlcpy(info->version, "1.0", sizeof(info->version));
1792 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
df828598
M		 1793}
1794
1795static u32 cpsw_get_msglevel(struct net_device *ndev)
1796{
1797 struct cpsw_priv *priv = netdev_priv(ndev);
1798 return priv->msg_enable;
1799}
1800
1801static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1802{
1803 struct cpsw_priv *priv = netdev_priv(ndev);
1804 priv->msg_enable = value;
1805}
1806
2e5b38ab
RC		 1807static int cpsw_get_ts_info(struct net_device *ndev,
1808 struct ethtool_ts_info *info)
1809{
1810#ifdef CONFIG_TI_CPTS
1811 struct cpsw_priv *priv = netdev_priv(ndev);
1812
1813 info->so_timestamping =
1814 SOF_TIMESTAMPING_TX_HARDWARE |
1815 SOF_TIMESTAMPING_TX_SOFTWARE |
1816 SOF_TIMESTAMPING_RX_HARDWARE |
1817 SOF_TIMESTAMPING_RX_SOFTWARE |
1818 SOF_TIMESTAMPING_SOFTWARE |
1819 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1820 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1821 info->tx_types =
1822 (1 << HWTSTAMP_TX_OFF) |
1823 (1 << HWTSTAMP_TX_ON);
1824 info->rx_filters =
1825 (1 << HWTSTAMP_FILTER_NONE) |
1826 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1827#else
1828 info->so_timestamping =
1829 SOF_TIMESTAMPING_TX_SOFTWARE |
1830 SOF_TIMESTAMPING_RX_SOFTWARE |
1831 SOF_TIMESTAMPING_SOFTWARE;
1832 info->phc_index = -1;
1833 info->tx_types = 0;
1834 info->rx_filters = 0;
1835#endif
1836 return 0;
1837}
1838
d3bb9c58
M		 1839static int cpsw_get_settings(struct net_device *ndev,
1840 struct ethtool_cmd *ecmd)
1841{
1842 struct cpsw_priv *priv = netdev_priv(ndev);
1843 int slave_no = cpsw_slave_index(priv);
1844
1845 if (priv->slaves[slave_no].phy)
1846 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1847 else
1848 return -EOPNOTSUPP;
1849}
1850
1851static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1852{
1853 struct cpsw_priv *priv = netdev_priv(ndev);
1854 int slave_no = cpsw_slave_index(priv);
1855
1856 if (priv->slaves[slave_no].phy)
1857 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1858 else
1859 return -EOPNOTSUPP;
1860}
1861
d8a64420
MU		 1862static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1863{
1864 struct cpsw_priv *priv = netdev_priv(ndev);
1865 int slave_no = cpsw_slave_index(priv);
1866
1867 wol->supported = 0;
1868 wol->wolopts = 0;
1869
1870 if (priv->slaves[slave_no].phy)
1871 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1872}
1873
1874static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1875{
1876 struct cpsw_priv *priv = netdev_priv(ndev);
1877 int slave_no = cpsw_slave_index(priv);
1878
1879 if (priv->slaves[slave_no].phy)
1880 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1881 else
1882 return -EOPNOTSUPP;
1883}
1884
1923d6e4
M		 1885static void cpsw_get_pauseparam(struct net_device *ndev,
1886 struct ethtool_pauseparam *pause)
1887{
1888 struct cpsw_priv *priv = netdev_priv(ndev);
1889
1890 pause->autoneg = AUTONEG_DISABLE;
1891 pause->rx_pause = priv->rx_pause ? true : false;
1892 pause->tx_pause = priv->tx_pause ? true : false;
1893}
1894
1895static int cpsw_set_pauseparam(struct net_device *ndev,
1896 struct ethtool_pauseparam *pause)
1897{
1898 struct cpsw_priv *priv = netdev_priv(ndev);
1899 bool link;
1900
1901 priv->rx_pause = pause->rx_pause ? true : false;
1902 priv->tx_pause = pause->tx_pause ? true : false;
1903
1904 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1905
1906 return 0;
1907}
1908
df828598
M		 1909static const struct ethtool_ops cpsw_ethtool_ops = {
1910 .get_drvinfo = cpsw_get_drvinfo,
1911 .get_msglevel = cpsw_get_msglevel,
1912 .set_msglevel = cpsw_set_msglevel,
1913 .get_link = ethtool_op_get_link,
2e5b38ab 1914 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1915 .get_settings = cpsw_get_settings,
1916 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1917 .get_coalesce = cpsw_get_coalesce,
1918 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1919 .get_sset_count = cpsw_get_sset_count,
1920 .get_strings = cpsw_get_strings,
1921 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1922 .get_pauseparam = cpsw_get_pauseparam,
1923 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1924 .get_wol = cpsw_get_wol,
1925 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1926 .get_regs_len = cpsw_get_regs_len,
1927 .get_regs = cpsw_get_regs,
df828598
M		 1928};
1929
549985ee
RC		 1930static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1931 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1932{
1933 void __iomem *regs = priv->regs;
1934 int slave_num = slave->slave_num;
1935 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1936
1937 slave->data = data;
549985ee
RC		 1938 slave->regs = regs + slave_reg_ofs;
1939 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1940 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1941}
1942
552165bc 1943static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 1944 struct platform_device *pdev)
1945{
1946 struct device_node *node = pdev->dev.of_node;
1947 struct device_node *slave_node;
1948 int i = 0, ret;
1949 u32 prop;
1950
1951 if (!node)
1952 return -EINVAL;
1953
1954 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 1955 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 1956 return -EINVAL;
1957 }
1958 data->slaves = prop;
1959
e86ac13b 1960 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 1961 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 1962 return -EINVAL;
78ca0b28 1963 }
e86ac13b 1964 data->active_slave = prop;
78ca0b28 1965
00ab94ee 1966 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 1967 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 1968 return -EINVAL;
00ab94ee
RC		 1969 }
1970 data->cpts_clock_mult = prop;
1971
1972 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 1973 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 1974 return -EINVAL;
00ab94ee
RC		 1975 }
1976 data->cpts_clock_shift = prop;
1977
aa1a15e2
DM		 1978 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1979 * sizeof(struct cpsw_slave_data),
1980 GFP_KERNEL);
b2adaca9 1981 if (!data->slave_data)
aa1a15e2 1982 return -ENOMEM;
2eb32b0a 1983
2eb32b0a 1984 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 1985 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 1986 return -EINVAL;
2eb32b0a
M		 1987 }
1988 data->channels = prop;
1989
2eb32b0a 1990 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 1991 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 1992 return -EINVAL;
2eb32b0a
M		 1993 }
1994 data->ale_entries = prop;
1995
2eb32b0a 1996 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 1997 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 1998 return -EINVAL;
2eb32b0a
M		 1999 }
2000 data->bd_ram_size = prop;
2001
2002 if (of_property_read_u32(node, "rx_descs", &prop)) {
88c99ff6 2003 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
aa1a15e2 2004 return -EINVAL;
2eb32b0a
M		 2005 }
2006 data->rx_descs = prop;
2007
2008 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2009 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2010 return -EINVAL;
2eb32b0a
M		 2011 }
2012 data->mac_control = prop;
2013
281abd96
MP		 2014 if (of_property_read_bool(node, "dual_emac"))
2015 data->dual_emac = 1;
d9ba8f9e 2016
549985ee
RC		 2017 /*
2018 * Populate all the child nodes here...
2019 */
2020 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2021 /* We do not want to force this, as in some cases may not have child */
2022 if (ret)
88c99ff6 2023 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2024
f468b10e 2025 for_each_child_of_node(node, slave_node) {
2eb32b0a 2026 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2027 const void *mac_addr = NULL;
549985ee
RC		 2028 int lenp;
2029 const __be32 *parp;
549985ee 2030
f468b10e
MP		 2031 /* This is no slave child node, continue */
2032 if (strcmp(slave_node->name, "slave"))
2033 continue;
2034
552165bc
DR		 2035 slave_data->phy_node = of_parse_phandle(slave_node,
2036 "phy-handle", 0);
f1eea5c1 2037 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2038 if (slave_data->phy_node) {
2039 dev_dbg(&pdev->dev,
2040 "slave[%d] using phy-handle=\"%s\"\n",
2041 i, slave_data->phy_node->full_name);
2042 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2043 /* In the case of a fixed PHY, the DT node associated
2044 * to the PHY is the Ethernet MAC DT node.
2045 */
1f71e8c9
MB		 2046 ret = of_phy_register_fixed_link(slave_node);
2047 if (ret)
2048 return ret;
06cd6d6e 2049 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2050 } else if (parp) {
2051 u32 phyid;
2052 struct device_node *mdio_node;
2053 struct platform_device *mdio;
2054
2055 if (lenp != (sizeof(__be32) * 2)) {
2056 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2057 goto no_phy_slave;
2058 }
2059 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2060 phyid = be32_to_cpup(parp+1);
2061 mdio = of_find_device_by_node(mdio_node);
2062 of_node_put(mdio_node);
2063 if (!mdio) {
2064 dev_err(&pdev->dev, "Missing mdio platform device\n");
2065 return -EINVAL;
2066 }
2067 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2068 PHY_ID_FMT, mdio->name, phyid);
2069 } else {
ae092b5b
DR		 2070 dev_err(&pdev->dev,
2071 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2072 i);
47276fcc 2073 goto no_phy_slave;
2eb32b0a 2074 }
47276fcc
M		 2075 slave_data->phy_if = of_get_phy_mode(slave_node);
2076 if (slave_data->phy_if < 0) {
2077 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2078 i);
2079 return slave_data->phy_if;
2080 }
2081
2082no_phy_slave:
2eb32b0a 2083 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2084 if (mac_addr) {
2eb32b0a 2085 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2086 } else {
b6745f6e
M		 2087 ret = ti_cm_get_macid(&pdev->dev, i,
2088 slave_data->mac_addr);
2089 if (ret)
2090 return ret;
0ba517b1 2091 }
d9ba8f9e 2092 if (data->dual_emac) {
91c4166c 2093 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2094 &prop)) {
88c99ff6 2095 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2096 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2097 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2098 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2099 } else {
2100 slave_data->dual_emac_res_vlan = prop;
2101 }
2102 }
2103
2eb32b0a 2104 i++;
3a27bfac
M		 2105 if (i == data->slaves)
2106 break;
2eb32b0a
M		 2107 }
2108
2109 return 0;
2eb32b0a
M		 2110}
2111
d9ba8f9e
M		 2112static int cpsw_probe_dual_emac(struct platform_device *pdev,
2113 struct cpsw_priv *priv)
2114{
2115 struct cpsw_platform_data *data = &priv->data;
2116 struct net_device *ndev;
2117 struct cpsw_priv *priv_sl2;
2118 int ret = 0, i;
2119
2120 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2121 if (!ndev) {
88c99ff6 2122 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2123 return -ENOMEM;
2124 }
2125
2126 priv_sl2 = netdev_priv(ndev);
2127 spin_lock_init(&priv_sl2->lock);
2128 priv_sl2->data = *data;
2129 priv_sl2->pdev = pdev;
2130 priv_sl2->ndev = ndev;
2131 priv_sl2->dev = &ndev->dev;
2132 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2133 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2134
2135 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2136 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2137 ETH_ALEN);
88c99ff6 2138 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2139 } else {
2140 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2141 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2142 }
2143 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2144
2145 priv_sl2->slaves = priv->slaves;
2146 priv_sl2->clk = priv->clk;
2147
ff5b8ef2
M		 2148 priv_sl2->coal_intvl = 0;
2149 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2150
d9ba8f9e 2151 priv_sl2->regs = priv->regs;
d9ba8f9e
M		 2152 priv_sl2->host_port_regs = priv->host_port_regs;
2153 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2154 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2155 priv_sl2->dma = priv->dma;
2156 priv_sl2->txch = priv->txch;
2157 priv_sl2->rxch = priv->rxch;
2158 priv_sl2->ale = priv->ale;
2159 priv_sl2->emac_port = 1;
2160 priv->slaves[1].ndev = ndev;
2161 priv_sl2->cpts = priv->cpts;
2162 priv_sl2->version = priv->version;
2163
2164 for (i = 0; i < priv->num_irqs; i++) {
2165 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2166 priv_sl2->num_irqs = priv->num_irqs;
2167 }
f646968f 2168 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2169
2170 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2171 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2172
2173 /* register the network device */
2174 SET_NETDEV_DEV(ndev, &pdev->dev);
2175 ret = register_netdev(ndev);
2176 if (ret) {
88c99ff6 2177 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2178 free_netdev(ndev);
2179 ret = -ENODEV;
2180 }
2181
2182 return ret;
2183}
2184
7da11600
M		 2185#define CPSW_QUIRK_IRQ BIT(0)
2186
2187static struct platform_device_id cpsw_devtype[] = {
2188 {
2189 /* keep it for existing comaptibles */
2190 .name = "cpsw",
2191 .driver_data = CPSW_QUIRK_IRQ,
2192 }, {
2193 .name = "am335x-cpsw",
2194 .driver_data = CPSW_QUIRK_IRQ,
2195 }, {
2196 .name = "am4372-cpsw",
2197 .driver_data = 0,
2198 }, {
2199 .name = "dra7-cpsw",
2200 .driver_data = 0,
2201 }, {
2202 /* sentinel */
2203 }
2204};
2205MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2206
2207enum ti_cpsw_type {
2208 CPSW = 0,
2209 AM335X_CPSW,
2210 AM4372_CPSW,
2211 DRA7_CPSW,
2212};
2213
2214static const struct of_device_id cpsw_of_mtable[] = {
2215 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2216 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2217 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2218 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2219 { /* sentinel */ },
2220};
2221MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2222
663e12e6 2223static int cpsw_probe(struct platform_device *pdev)
df828598 2224{
d1bd9acf 2225 struct cpsw_platform_data *data;
df828598
M		 2226 struct net_device *ndev;
2227 struct cpsw_priv *priv;
2228 struct cpdma_params dma_params;
2229 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2230 void __iomem *ss_regs;
2231 struct resource *res, *ss_res;
7da11600 2232 const struct of_device_id *of_id;
1d147ccb 2233 struct gpio_descs *mode;
549985ee 2234 u32 slave_offset, sliver_offset, slave_size;
5087b915
FB		 2235 int ret = 0, i;
2236 int irq;
df828598 2237
df828598
M		 2238 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2239 if (!ndev) {
88c99ff6 2240 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2241 return -ENOMEM;
2242 }
2243
2244 platform_set_drvdata(pdev, ndev);
2245 priv = netdev_priv(ndev);
2246 spin_lock_init(&priv->lock);
df828598
M		 2247 priv->pdev = pdev;
2248 priv->ndev = ndev;
2249 priv->dev = &ndev->dev;
2250 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2251 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2252 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
ab8e99d2 2253 if (!priv->cpts) {
88c99ff6 2254 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2255 ret = -ENOMEM;
9232b16d
M		 2256 goto clean_ndev_ret;
2257 }
df828598 2258
1d147ccb
M		 2259 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2260 if (IS_ERR(mode)) {
2261 ret = PTR_ERR(mode);
2262 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2263 goto clean_ndev_ret;
2264 }
2265
1fb19aa7
VH		 2266 /*
2267 * This may be required here for child devices.
2268 */
2269 pm_runtime_enable(&pdev->dev);
2270
739683b4
M		 2271 /* Select default pin state */
2272 pinctrl_pm_select_default_state(&pdev->dev);
2273
552165bc 2274 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2275 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2276 ret = -ENODEV;
aa1a15e2 2277 goto clean_runtime_disable_ret;
2eb32b0a
M		 2278 }
2279 data = &priv->data;
2280
df828598
M		 2281 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2282 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2283 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2284 } else {
7efd26d0 2285 eth_random_addr(priv->mac_addr);
88c99ff6 2286 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2287 }
2288
2289 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2290
aa1a15e2
DM		 2291 priv->slaves = devm_kzalloc(&pdev->dev,
2292 sizeof(struct cpsw_slave) * data->slaves,
2293 GFP_KERNEL);
df828598 2294 if (!priv->slaves) {
aa1a15e2
DM		 2295 ret = -ENOMEM;
2296 goto clean_runtime_disable_ret;
df828598
M		 2297 }
2298 for (i = 0; i < data->slaves; i++)
2299 priv->slaves[i].slave_num = i;
2300
d9ba8f9e
M		 2301 priv->slaves[0].ndev = ndev;
2302 priv->emac_port = 0;
2303
aa1a15e2 2304 priv->clk = devm_clk_get(&pdev->dev, "fck");
df828598 2305 if (IS_ERR(priv->clk)) {
aa1a15e2 2306 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2307 ret = -ENODEV;
aa1a15e2 2308 goto clean_runtime_disable_ret;
df828598 2309 }
ff5b8ef2
M		 2310 priv->coal_intvl = 0;
2311 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
df828598 2312
aa1a15e2
DM		 2313 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2314 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2315 if (IS_ERR(ss_regs)) {
2316 ret = PTR_ERR(ss_regs);
2317 goto clean_runtime_disable_ret;
df828598 2318 }
549985ee 2319 priv->regs = ss_regs;
df828598 2320
f280e89a
M		 2321 /* Need to enable clocks with runtime PM api to access module
2322 * registers
2323 */
2324 pm_runtime_get_sync(&pdev->dev);
2325 priv->version = readl(&priv->regs->id_ver);
2326 pm_runtime_put_sync(&pdev->dev);
2327
aa1a15e2
DM		 2328 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2329 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2330 if (IS_ERR(priv->wr_regs)) {
2331 ret = PTR_ERR(priv->wr_regs);
2332 goto clean_runtime_disable_ret;
df828598 2333 }
df828598
M		 2334
2335 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2336 memset(&ale_params, 0, sizeof(ale_params));
2337
2338 switch (priv->version) {
2339 case CPSW_VERSION_1:
2340 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2341 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2342 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2343 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2344 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2345 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2346 slave_offset = CPSW1_SLAVE_OFFSET;
2347 slave_size = CPSW1_SLAVE_SIZE;
2348 sliver_offset = CPSW1_SLIVER_OFFSET;
2349 dma_params.desc_mem_phys = 0;
2350 break;
2351 case CPSW_VERSION_2:
c193f365 2352 case CPSW_VERSION_3:
926489be 2353 case CPSW_VERSION_4:
549985ee 2354 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2355 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2356 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2357 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2358 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2359 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2360 slave_offset = CPSW2_SLAVE_OFFSET;
2361 slave_size = CPSW2_SLAVE_SIZE;
2362 sliver_offset = CPSW2_SLIVER_OFFSET;
2363 dma_params.desc_mem_phys =
aa1a15e2 2364 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2365 break;
2366 default:
2367 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2368 ret = -ENODEV;
aa1a15e2 2369 goto clean_runtime_disable_ret;
549985ee
RC		 2370 }
2371 for (i = 0; i < priv->data.slaves; i++) {
2372 struct cpsw_slave *slave = &priv->slaves[i];
2373 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2374 slave_offset += slave_size;
2375 sliver_offset += SLIVER_SIZE;
2376 }
2377
df828598 2378 dma_params.dev = &pdev->dev;
549985ee
RC		 2379 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2380 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2381 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2382 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2383 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2384
2385 dma_params.num_chan = data->channels;
2386 dma_params.has_soft_reset = true;
2387 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2388 dma_params.desc_mem_size = data->bd_ram_size;
2389 dma_params.desc_align = 16;
2390 dma_params.has_ext_regs = true;
549985ee 2391 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2392
2393 priv->dma = cpdma_ctlr_create(&dma_params);
2394 if (!priv->dma) {
2395 dev_err(priv->dev, "error initializing dma\n");
2396 ret = -ENOMEM;
aa1a15e2 2397 goto clean_runtime_disable_ret;
df828598
M		 2398 }
2399
2400 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2401 cpsw_tx_handler);
2402 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2403 cpsw_rx_handler);
2404
2405 if (WARN_ON(!priv->txch || !priv->rxch)) {
2406 dev_err(priv->dev, "error initializing dma channels\n");
2407 ret = -ENOMEM;
2408 goto clean_dma_ret;
2409 }
2410
df828598 2411 ale_params.dev = &ndev->dev;
df828598
M		 2412 ale_params.ale_ageout = ale_ageout;
2413 ale_params.ale_entries = data->ale_entries;
2414 ale_params.ale_ports = data->slaves;
2415
2416 priv->ale = cpsw_ale_create(&ale_params);
2417 if (!priv->ale) {
2418 dev_err(priv->dev, "error initializing ale engine\n");
2419 ret = -ENODEV;
2420 goto clean_dma_ret;
2421 }
2422
c03abd84 2423 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2424 if (ndev->irq < 0) {
2425 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2426 ret = ndev->irq;
df828598
M		 2427 goto clean_ale_ret;
2428 }
2429
7da11600
M		 2430 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2431 if (of_id) {
2432 pdev->id_entry = of_id->data;
2433 if (pdev->id_entry->driver_data)
2434 priv->quirk_irq = true;
2435 }
2436
c03abd84
FB		 2437 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2438 * MISC IRQs which are always kept disabled with this driver so
2439 * we will not request them.
2440 *
2441 * If anyone wants to implement support for those, make sure to
2442 * first request and append them to irqs_table array.
2443 */
c2b32e58 2444
c03abd84 2445 /* RX IRQ */
5087b915 2446 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2447 if (irq < 0) {
2448 ret = irq;
5087b915 2449 goto clean_ale_ret;
c1e3334f 2450 }
5087b915 2451
c03abd84
FB		 2452 priv->irqs_table[0] = irq;
2453 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2454 0, dev_name(&pdev->dev), priv);
2455 if (ret < 0) {
2456 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2457 goto clean_ale_ret;
2458 }
2459
c03abd84 2460 /* TX IRQ */
5087b915 2461 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2462 if (irq < 0) {
2463 ret = irq;
5087b915 2464 goto clean_ale_ret;
c1e3334f 2465 }
5087b915 2466
c03abd84
FB		 2467 priv->irqs_table[1] = irq;
2468 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2469 0, dev_name(&pdev->dev), priv);
2470 if (ret < 0) {
2471 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2472 goto clean_ale_ret;
df828598 2473 }
c03abd84 2474 priv->num_irqs = 2;
c2b32e58 2475
f646968f 2476 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2477
2478 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2479 ndev->ethtool_ops = &cpsw_ethtool_ops;
32a7432c 2480 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
d64b5e85 2481 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2482
2483 /* register the network device */
2484 SET_NETDEV_DEV(ndev, &pdev->dev);
2485 ret = register_netdev(ndev);
2486 if (ret) {
2487 dev_err(priv->dev, "error registering net device\n");
2488 ret = -ENODEV;
aa1a15e2 2489 goto clean_ale_ret;
df828598
M		 2490 }
2491
1a3b5056
OJ		 2492 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2493 &ss_res->start, ndev->irq);
df828598 2494
d9ba8f9e
M		 2495 if (priv->data.dual_emac) {
2496 ret = cpsw_probe_dual_emac(pdev, priv);
2497 if (ret) {
2498 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2499 goto clean_ale_ret;
d9ba8f9e
M		 2500 }
2501 }
2502
df828598
M		 2503 return 0;
2504
df828598
M		 2505clean_ale_ret:
2506 cpsw_ale_destroy(priv->ale);
2507clean_dma_ret:
df828598 2508 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2509clean_runtime_disable_ret:
f150bd7f 2510 pm_runtime_disable(&pdev->dev);
df828598 2511clean_ndev_ret:
d1bd9acf 2512 free_netdev(priv->ndev);
df828598
M		 2513 return ret;
2514}
2515
030b16a0
M		 2516static int cpsw_remove_child_device(struct device *dev, void *c)
2517{
2518 struct platform_device *pdev = to_platform_device(dev);
2519
2520 of_device_unregister(pdev);
2521
2522 return 0;
2523}
2524
663e12e6 2525static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2526{
2527 struct net_device *ndev = platform_get_drvdata(pdev);
2528 struct cpsw_priv *priv = netdev_priv(ndev);
2529
d1bd9acf
SS		 2530 if (priv->data.dual_emac)
2531 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2532 unregister_netdev(ndev);
df828598 2533
df828598 2534 cpsw_ale_destroy(priv->ale);
df828598 2535 cpdma_ctlr_destroy(priv->dma);
f150bd7f 2536 pm_runtime_disable(&pdev->dev);
030b16a0 2537 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
d1bd9acf
SS		 2538 if (priv->data.dual_emac)
2539 free_netdev(cpsw_get_slave_ndev(priv, 1));
df828598 2540 free_netdev(ndev);
df828598
M		 2541 return 0;
2542}
2543
8963a504 2544#ifdef CONFIG_PM_SLEEP
df828598
M		 2545static int cpsw_suspend(struct device *dev)
2546{
2547 struct platform_device *pdev = to_platform_device(dev);
2548 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2549 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2550
618073e3
M		 2551 if (priv->data.dual_emac) {
2552 int i;
1e7a2e21 2553
618073e3
M		 2554 for (i = 0; i < priv->data.slaves; i++) {
2555 if (netif_running(priv->slaves[i].ndev))
2556 cpsw_ndo_stop(priv->slaves[i].ndev);
2557 soft_reset_slave(priv->slaves + i);
2558 }
2559 } else {
2560 if (netif_running(ndev))
2561 cpsw_ndo_stop(ndev);
2562 for_each_slave(priv, soft_reset_slave);
2563 }
1e7a2e21 2564
f150bd7f
M		 2565 pm_runtime_put_sync(&pdev->dev);
2566
739683b4
M		 2567 /* Select sleep pin state */
2568 pinctrl_pm_select_sleep_state(&pdev->dev);
2569
df828598
M		 2570 return 0;
2571}
2572
2573static int cpsw_resume(struct device *dev)
2574{
2575 struct platform_device *pdev = to_platform_device(dev);
2576 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2577 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2578
f150bd7f 2579 pm_runtime_get_sync(&pdev->dev);
739683b4
M		 2580
2581 /* Select default pin state */
2582 pinctrl_pm_select_default_state(&pdev->dev);
2583
618073e3
M		 2584 if (priv->data.dual_emac) {
2585 int i;
2586
2587 for (i = 0; i < priv->data.slaves; i++) {
2588 if (netif_running(priv->slaves[i].ndev))
2589 cpsw_ndo_open(priv->slaves[i].ndev);
2590 }
2591 } else {
2592 if (netif_running(ndev))
2593 cpsw_ndo_open(ndev);
2594 }
df828598
M		 2595 return 0;
2596}
8963a504 2597#endif
df828598 2598
8963a504 2599static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2600
2601static struct platform_driver cpsw_driver = {
2602 .driver = {
2603 .name = "cpsw",
df828598 2604 .pm = &cpsw_pm_ops,
1e5c76d4 2605 .of_match_table = cpsw_of_mtable,
df828598
M		 2606 },
2607 .probe = cpsw_probe,
663e12e6 2608 .remove = cpsw_remove,
df828598
M		 2609};
2610
6fb3b6b5 2611module_platform_driver(cpsw_driver);
df828598
M		 2612
2613MODULE_LICENSE("GPL");
2614MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2615MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2616MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
This page took 0.4943 seconds and 5 git commands to generate.