projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ef8c2dab CC |
1 | /* |
| 2 | * Texas Instruments CPDMA Driver | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Texas Instruments | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation version 2. | |
| 9 | * | |
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
| 11 | * kind, whether express or implied; without even the implied warranty | |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | */ | |
| 15 | #ifndef __DAVINCI_CPDMA_H__ | |
| 16 | #define __DAVINCI_CPDMA_H__ | |
| 17 | ||
| 18 | #define CPDMA_MAX_CHANNELS BITS_PER_LONG | |
| 19 | ||
| 20 | #define tx_chan_num(chan) (chan) | |
| 21 | #define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS) | |
| 22 | #define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS) | |
| 23 | #define is_tx_chan(chan) (!is_rx_chan(chan)) | |
| 24 | #define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1)) | |
| 25 | #define chan_linear(chan) __chan_linear((chan)->chan_num) | |
| 26 | ||
| f6e135c8 M |
27 | #define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7) |
| 28 | ||
| ef8c2dab CC |
29 | struct cpdma_params { |
| 30 | struct device *dev; | |
| 31 | void __iomem *dmaregs; | |
| 32 | void __iomem *txhdp, *rxhdp, *txcp, *rxcp; | |
| 33 | void __iomem *rxthresh, *rxfree; | |
| 34 | int num_chan; | |
| 35 | bool has_soft_reset; | |
| 36 | int min_packet_size; | |
| 37 | u32 desc_mem_phys; | |
| 6a1fef6d | 38 | u32 desc_hw_addr; |
| ef8c2dab CC |
39 | int desc_mem_size; |
| 40 | int desc_align; | |
| 41 | ||
| 42 | /* | |
| 43 | * Some instances of embedded cpdma controllers have extra control and | |
| 44 | * status registers. The following flag enables access to these | |
| 45 | * "extended" registers. | |
| 46 | */ | |
| 47 | bool has_ext_regs; | |
| 48 | }; | |
| 49 | ||
| 50 | struct cpdma_chan_stats { | |
| 51 | u32 head_enqueue; | |
| 52 | u32 tail_enqueue; | |
| 53 | u32 pad_enqueue; | |
| 54 | u32 misqueued; | |
| 55 | u32 desc_alloc_fail; | |
| 56 | u32 pad_alloc_fail; | |
| 57 | u32 runt_receive_buff; | |
| 58 | u32 runt_transmit_buff; | |
| 59 | u32 empty_dequeue; | |
| 60 | u32 busy_dequeue; | |
| 61 | u32 good_dequeue; | |
| 62 | u32 requeue; | |
| 63 | u32 teardown_dequeue; | |
| 64 | }; | |
| 65 | ||
| 66 | struct cpdma_ctlr; | |
| 67 | struct cpdma_chan; | |
| 68 | ||
| 69 | typedef void (*cpdma_handler_fn)(void *token, int len, int status); | |
| 70 | ||
| 71 | struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params); | |
| 72 | int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr); | |
| 73 | int cpdma_ctlr_start(struct cpdma_ctlr *ctlr); | |
| 74 | int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr); | |
| 75 | int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr); | |
| 76 | ||
| 77 | struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, | |
| 78 | cpdma_handler_fn handler); | |
| 79 | int cpdma_chan_destroy(struct cpdma_chan *chan); | |
| 80 | int cpdma_chan_start(struct cpdma_chan *chan); | |
| 81 | int cpdma_chan_stop(struct cpdma_chan *chan); | |
| 82 | int cpdma_chan_dump(struct cpdma_chan *chan); | |
| 83 | ||
| 84 | int cpdma_chan_get_stats(struct cpdma_chan *chan, | |
| 85 | struct cpdma_chan_stats *stats); | |
| 86 | int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, | |
| f6e135c8 | 87 | int len, int directed, gfp_t gfp_mask); |
| ef8c2dab CC |
88 | int cpdma_chan_process(struct cpdma_chan *chan, int quota); |
| 89 | ||
| 90 | int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable); | |
| 91 | void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr); | |
| 92 | int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable); | |
| fae50823 | 93 | bool cpdma_check_free_tx_desc(struct cpdma_chan *chan); |
| ef8c2dab CC |
94 | |
| 95 | enum cpdma_control { | |
| 96 | CPDMA_CMD_IDLE, /* write-only */ | |
| 97 | CPDMA_COPY_ERROR_FRAMES, /* read-write */ | |
| 98 | CPDMA_RX_OFF_LEN_UPDATE, /* read-write */ | |
| 99 | CPDMA_RX_OWNERSHIP_FLIP, /* read-write */ | |
| 100 | CPDMA_TX_PRIO_FIXED, /* read-write */ | |
| 101 | CPDMA_STAT_IDLE, /* read-only */ | |
| 102 | CPDMA_STAT_TX_ERR_CHAN, /* read-only */ | |
| 103 | CPDMA_STAT_TX_ERR_CODE, /* read-only */ | |
| 104 | CPDMA_STAT_RX_ERR_CHAN, /* read-only */ | |
| 105 | CPDMA_STAT_RX_ERR_CODE, /* read-only */ | |
| 106 | CPDMA_RX_BUFFER_OFFSET, /* read-write */ | |
| 107 | }; | |
| 108 | ||
| 109 | int cpdma_control_get(struct cpdma_ctlr *ctlr, int control); | |
| 110 | int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value); | |
| 111 | ||
| 112 | #endif |