Commit | Line | Data |
---|---|---|
f20136eb CC |
1 | /* |
2 | * DaVinci MDIO Module driver | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments. | |
5 | * | |
6 | * Shamelessly ripped out of davinci_emac.c, original copyrights follow: | |
7 | * | |
8 | * Copyright (C) 2009 Texas Instruments. | |
9 | * | |
10 | * --------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * --------------------------------------------------------------------------- | |
26 | */ | |
27 | #include <linux/module.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/phy.h> | |
34 | #include <linux/clk.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/io.h> | |
8e476d9d | 37 | #include <linux/pm_runtime.h> |
f20136eb CC |
38 | #include <linux/davinci_emac.h> |
39 | ||
40 | /* | |
41 | * This timeout definition is a worst-case ultra defensive measure against | |
42 | * unexpected controller lock ups. Ideally, we should never ever hit this | |
43 | * scenario in practice. | |
44 | */ | |
45 | #define MDIO_TIMEOUT 100 /* msecs */ | |
46 | ||
47 | #define PHY_REG_MASK 0x1f | |
48 | #define PHY_ID_MASK 0x1f | |
49 | ||
50 | #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */ | |
51 | ||
52 | struct davinci_mdio_regs { | |
53 | u32 version; | |
54 | u32 control; | |
55 | #define CONTROL_IDLE BIT(31) | |
56 | #define CONTROL_ENABLE BIT(30) | |
7c3a95a1 | 57 | #define CONTROL_MAX_DIV (0xffff) |
f20136eb CC |
58 | |
59 | u32 alive; | |
60 | u32 link; | |
61 | u32 linkintraw; | |
62 | u32 linkintmasked; | |
63 | u32 __reserved_0[2]; | |
64 | u32 userintraw; | |
65 | u32 userintmasked; | |
66 | u32 userintmaskset; | |
67 | u32 userintmaskclr; | |
68 | u32 __reserved_1[20]; | |
69 | ||
70 | struct { | |
71 | u32 access; | |
72 | #define USERACCESS_GO BIT(31) | |
73 | #define USERACCESS_WRITE BIT(30) | |
74 | #define USERACCESS_ACK BIT(29) | |
75 | #define USERACCESS_READ (0) | |
76 | #define USERACCESS_DATA (0xffff) | |
77 | ||
78 | u32 physel; | |
79 | } user[0]; | |
80 | }; | |
81 | ||
82 | struct mdio_platform_data default_pdata = { | |
83 | .bus_freq = DEF_OUT_FREQ, | |
84 | }; | |
85 | ||
86 | struct davinci_mdio_data { | |
87 | struct mdio_platform_data pdata; | |
88 | struct davinci_mdio_regs __iomem *regs; | |
89 | spinlock_t lock; | |
90 | struct clk *clk; | |
91 | struct device *dev; | |
92 | struct mii_bus *bus; | |
93 | bool suspended; | |
94 | unsigned long access_time; /* jiffies */ | |
95 | }; | |
96 | ||
97 | static void __davinci_mdio_reset(struct davinci_mdio_data *data) | |
98 | { | |
99 | u32 mdio_in, div, mdio_out_khz, access_time; | |
100 | ||
101 | mdio_in = clk_get_rate(data->clk); | |
102 | div = (mdio_in / data->pdata.bus_freq) - 1; | |
103 | if (div > CONTROL_MAX_DIV) | |
104 | div = CONTROL_MAX_DIV; | |
105 | ||
106 | /* set enable and clock divider */ | |
107 | __raw_writel(div | CONTROL_ENABLE, &data->regs->control); | |
108 | ||
109 | /* | |
110 | * One mdio transaction consists of: | |
111 | * 32 bits of preamble | |
112 | * 32 bits of transferred data | |
113 | * 24 bits of bus yield (not needed unless shared?) | |
114 | */ | |
115 | mdio_out_khz = mdio_in / (1000 * (div + 1)); | |
116 | access_time = (88 * 1000) / mdio_out_khz; | |
117 | ||
118 | /* | |
119 | * In the worst case, we could be kicking off a user-access immediately | |
120 | * after the mdio bus scan state-machine triggered its own read. If | |
121 | * so, our request could get deferred by one access cycle. We | |
122 | * defensively allow for 4 access cycles. | |
123 | */ | |
124 | data->access_time = usecs_to_jiffies(access_time * 4); | |
125 | if (!data->access_time) | |
126 | data->access_time = 1; | |
127 | } | |
128 | ||
129 | static int davinci_mdio_reset(struct mii_bus *bus) | |
130 | { | |
131 | struct davinci_mdio_data *data = bus->priv; | |
132 | u32 phy_mask, ver; | |
133 | ||
134 | __davinci_mdio_reset(data); | |
135 | ||
136 | /* wait for scan logic to settle */ | |
137 | msleep(PHY_MAX_ADDR * data->access_time); | |
138 | ||
139 | /* dump hardware version info */ | |
140 | ver = __raw_readl(&data->regs->version); | |
141 | dev_info(data->dev, "davinci mdio revision %d.%d\n", | |
142 | (ver >> 8) & 0xff, ver & 0xff); | |
143 | ||
144 | /* get phy mask from the alive register */ | |
145 | phy_mask = __raw_readl(&data->regs->alive); | |
146 | if (phy_mask) { | |
147 | /* restrict mdio bus to live phys only */ | |
148 | dev_info(data->dev, "detected phy mask %x\n", ~phy_mask); | |
149 | phy_mask = ~phy_mask; | |
150 | } else { | |
151 | /* desperately scan all phys */ | |
152 | dev_warn(data->dev, "no live phy, scanning all\n"); | |
153 | phy_mask = 0; | |
154 | } | |
155 | data->bus->phy_mask = phy_mask; | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | /* wait until hardware is ready for another user access */ | |
161 | static inline int wait_for_user_access(struct davinci_mdio_data *data) | |
162 | { | |
163 | struct davinci_mdio_regs __iomem *regs = data->regs; | |
164 | unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT); | |
165 | u32 reg; | |
166 | ||
167 | while (time_after(timeout, jiffies)) { | |
168 | reg = __raw_readl(®s->user[0].access); | |
169 | if ((reg & USERACCESS_GO) == 0) | |
170 | return 0; | |
171 | ||
172 | reg = __raw_readl(®s->control); | |
173 | if ((reg & CONTROL_IDLE) == 0) | |
174 | continue; | |
175 | ||
176 | /* | |
177 | * An emac soft_reset may have clobbered the mdio controller's | |
178 | * state machine. We need to reset and retry the current | |
179 | * operation | |
180 | */ | |
181 | dev_warn(data->dev, "resetting idled controller\n"); | |
182 | __davinci_mdio_reset(data); | |
183 | return -EAGAIN; | |
184 | } | |
5b76d060 CR |
185 | |
186 | reg = __raw_readl(®s->user[0].access); | |
187 | if ((reg & USERACCESS_GO) == 0) | |
188 | return 0; | |
189 | ||
f20136eb CC |
190 | dev_err(data->dev, "timed out waiting for user access\n"); |
191 | return -ETIMEDOUT; | |
192 | } | |
193 | ||
194 | /* wait until hardware state machine is idle */ | |
195 | static inline int wait_for_idle(struct davinci_mdio_data *data) | |
196 | { | |
197 | struct davinci_mdio_regs __iomem *regs = data->regs; | |
198 | unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT); | |
199 | ||
200 | while (time_after(timeout, jiffies)) { | |
201 | if (__raw_readl(®s->control) & CONTROL_IDLE) | |
202 | return 0; | |
203 | } | |
204 | dev_err(data->dev, "timed out waiting for idle\n"); | |
205 | return -ETIMEDOUT; | |
206 | } | |
207 | ||
208 | static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) | |
209 | { | |
210 | struct davinci_mdio_data *data = bus->priv; | |
211 | u32 reg; | |
212 | int ret; | |
213 | ||
214 | if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) | |
215 | return -EINVAL; | |
216 | ||
217 | spin_lock(&data->lock); | |
218 | ||
219 | if (data->suspended) { | |
220 | spin_unlock(&data->lock); | |
221 | return -ENODEV; | |
222 | } | |
223 | ||
224 | reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | | |
225 | (phy_id << 16)); | |
226 | ||
227 | while (1) { | |
228 | ret = wait_for_user_access(data); | |
229 | if (ret == -EAGAIN) | |
230 | continue; | |
231 | if (ret < 0) | |
232 | break; | |
233 | ||
234 | __raw_writel(reg, &data->regs->user[0].access); | |
235 | ||
236 | ret = wait_for_user_access(data); | |
237 | if (ret == -EAGAIN) | |
238 | continue; | |
239 | if (ret < 0) | |
240 | break; | |
241 | ||
242 | reg = __raw_readl(&data->regs->user[0].access); | |
243 | ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO; | |
244 | break; | |
245 | } | |
246 | ||
247 | spin_unlock(&data->lock); | |
248 | ||
249 | return ret; | |
250 | } | |
251 | ||
252 | static int davinci_mdio_write(struct mii_bus *bus, int phy_id, | |
253 | int phy_reg, u16 phy_data) | |
254 | { | |
255 | struct davinci_mdio_data *data = bus->priv; | |
256 | u32 reg; | |
257 | int ret; | |
258 | ||
259 | if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) | |
260 | return -EINVAL; | |
261 | ||
262 | spin_lock(&data->lock); | |
263 | ||
264 | if (data->suspended) { | |
265 | spin_unlock(&data->lock); | |
266 | return -ENODEV; | |
267 | } | |
268 | ||
269 | reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | | |
270 | (phy_id << 16) | (phy_data & USERACCESS_DATA)); | |
271 | ||
272 | while (1) { | |
273 | ret = wait_for_user_access(data); | |
274 | if (ret == -EAGAIN) | |
275 | continue; | |
276 | if (ret < 0) | |
277 | break; | |
278 | ||
279 | __raw_writel(reg, &data->regs->user[0].access); | |
280 | ||
281 | ret = wait_for_user_access(data); | |
282 | if (ret == -EAGAIN) | |
283 | continue; | |
284 | break; | |
285 | } | |
286 | ||
287 | spin_unlock(&data->lock); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static int __devinit davinci_mdio_probe(struct platform_device *pdev) | |
293 | { | |
294 | struct mdio_platform_data *pdata = pdev->dev.platform_data; | |
295 | struct device *dev = &pdev->dev; | |
296 | struct davinci_mdio_data *data; | |
297 | struct resource *res; | |
298 | struct phy_device *phy; | |
299 | int ret, addr; | |
300 | ||
301 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
302 | if (!data) { | |
303 | dev_err(dev, "failed to alloc device data\n"); | |
304 | return -ENOMEM; | |
305 | } | |
306 | ||
307 | data->pdata = pdata ? (*pdata) : default_pdata; | |
308 | ||
309 | data->bus = mdiobus_alloc(); | |
310 | if (!data->bus) { | |
311 | dev_err(dev, "failed to alloc mii bus\n"); | |
312 | ret = -ENOMEM; | |
313 | goto bail_out; | |
314 | } | |
315 | ||
316 | data->bus->name = dev_name(dev); | |
317 | data->bus->read = davinci_mdio_read, | |
318 | data->bus->write = davinci_mdio_write, | |
319 | data->bus->reset = davinci_mdio_reset, | |
320 | data->bus->parent = dev; | |
321 | data->bus->priv = data; | |
5a05a820 FF |
322 | snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x", |
323 | pdev->name, pdev->id); | |
f20136eb | 324 | |
8e476d9d M |
325 | pm_runtime_enable(&pdev->dev); |
326 | pm_runtime_get_sync(&pdev->dev); | |
327 | data->clk = clk_get(&pdev->dev, "fck"); | |
f20136eb | 328 | if (IS_ERR(data->clk)) { |
f20136eb CC |
329 | dev_err(dev, "failed to get device clock\n"); |
330 | ret = PTR_ERR(data->clk); | |
cb0a178c | 331 | data->clk = NULL; |
f20136eb CC |
332 | goto bail_out; |
333 | } | |
334 | ||
f20136eb CC |
335 | dev_set_drvdata(dev, data); |
336 | data->dev = dev; | |
337 | spin_lock_init(&data->lock); | |
338 | ||
339 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
340 | if (!res) { | |
341 | dev_err(dev, "could not find register map resource\n"); | |
342 | ret = -ENOENT; | |
343 | goto bail_out; | |
344 | } | |
345 | ||
346 | res = devm_request_mem_region(dev, res->start, resource_size(res), | |
347 | dev_name(dev)); | |
348 | if (!res) { | |
349 | dev_err(dev, "could not allocate register map resource\n"); | |
350 | ret = -ENXIO; | |
351 | goto bail_out; | |
352 | } | |
353 | ||
354 | data->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
355 | if (!data->regs) { | |
356 | dev_err(dev, "could not map mdio registers\n"); | |
357 | ret = -ENOMEM; | |
358 | goto bail_out; | |
359 | } | |
360 | ||
361 | /* register the mii bus */ | |
362 | ret = mdiobus_register(data->bus); | |
363 | if (ret) | |
364 | goto bail_out; | |
365 | ||
366 | /* scan and dump the bus */ | |
367 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { | |
368 | phy = data->bus->phy_map[addr]; | |
369 | if (phy) { | |
370 | dev_info(dev, "phy[%d]: device %s, driver %s\n", | |
371 | phy->addr, dev_name(&phy->dev), | |
372 | phy->drv ? phy->drv->name : "unknown"); | |
373 | } | |
374 | } | |
375 | ||
376 | return 0; | |
377 | ||
378 | bail_out: | |
379 | if (data->bus) | |
380 | mdiobus_free(data->bus); | |
381 | ||
8e476d9d | 382 | if (data->clk) |
f20136eb | 383 | clk_put(data->clk); |
8e476d9d M |
384 | pm_runtime_put_sync(&pdev->dev); |
385 | pm_runtime_disable(&pdev->dev); | |
f20136eb CC |
386 | |
387 | kfree(data); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | static int __devexit davinci_mdio_remove(struct platform_device *pdev) | |
393 | { | |
394 | struct device *dev = &pdev->dev; | |
395 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
396 | ||
397 | if (data->bus) | |
398 | mdiobus_free(data->bus); | |
399 | ||
8e476d9d | 400 | if (data->clk) |
f20136eb | 401 | clk_put(data->clk); |
8e476d9d M |
402 | pm_runtime_put_sync(&pdev->dev); |
403 | pm_runtime_disable(&pdev->dev); | |
f20136eb CC |
404 | |
405 | dev_set_drvdata(dev, NULL); | |
406 | ||
407 | kfree(data); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
412 | static int davinci_mdio_suspend(struct device *dev) | |
413 | { | |
414 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
415 | u32 ctrl; | |
416 | ||
417 | spin_lock(&data->lock); | |
418 | ||
419 | /* shutdown the scan state machine */ | |
420 | ctrl = __raw_readl(&data->regs->control); | |
421 | ctrl &= ~CONTROL_ENABLE; | |
422 | __raw_writel(ctrl, &data->regs->control); | |
423 | wait_for_idle(data); | |
424 | ||
8e476d9d | 425 | pm_runtime_put_sync(data->dev); |
f20136eb CC |
426 | |
427 | data->suspended = true; | |
428 | spin_unlock(&data->lock); | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | static int davinci_mdio_resume(struct device *dev) | |
434 | { | |
435 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
436 | u32 ctrl; | |
437 | ||
438 | spin_lock(&data->lock); | |
8e476d9d | 439 | pm_runtime_put_sync(data->dev); |
f20136eb CC |
440 | |
441 | /* restart the scan state machine */ | |
442 | ctrl = __raw_readl(&data->regs->control); | |
443 | ctrl |= CONTROL_ENABLE; | |
444 | __raw_writel(ctrl, &data->regs->control); | |
445 | ||
446 | data->suspended = false; | |
447 | spin_unlock(&data->lock); | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | static const struct dev_pm_ops davinci_mdio_pm_ops = { | |
453 | .suspend = davinci_mdio_suspend, | |
454 | .resume = davinci_mdio_resume, | |
455 | }; | |
456 | ||
457 | static struct platform_driver davinci_mdio_driver = { | |
458 | .driver = { | |
459 | .name = "davinci_mdio", | |
460 | .owner = THIS_MODULE, | |
461 | .pm = &davinci_mdio_pm_ops, | |
462 | }, | |
463 | .probe = davinci_mdio_probe, | |
464 | .remove = __devexit_p(davinci_mdio_remove), | |
465 | }; | |
466 | ||
467 | static int __init davinci_mdio_init(void) | |
468 | { | |
469 | return platform_driver_register(&davinci_mdio_driver); | |
470 | } | |
471 | device_initcall(davinci_mdio_init); | |
472 | ||
473 | static void __exit davinci_mdio_exit(void) | |
474 | { | |
475 | platform_driver_unregister(&davinci_mdio_driver); | |
476 | } | |
477 | module_exit(davinci_mdio_exit); | |
478 | ||
479 | MODULE_LICENSE("GPL"); | |
480 | MODULE_DESCRIPTION("DaVinci MDIO driver"); |