[deliverable/linux.git] / drivers / net / ethernet / ti / davinci_mdio.c

/*
 * DaVinci MDIO Module driver
 *
 * Copyright (C) 2010 Texas Instruments.
 *
 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
 *
 * Copyright (C) 2009 Texas Instruments.
 *
 * ---------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ---------------------------------------------------------------------------
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/phy.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/davinci_emac.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/pinctrl/consumer.h>

/*
 * This timeout definition is a worst-case ultra defensive measure against
 * unexpected controller lock ups.  Ideally, we should never ever hit this
 * scenario in practice.
 */
#define MDIO_TIMEOUT		100 /* msecs */

#define PHY_REG_MASK		0x1f
#define PHY_ID_MASK		0x1f

#define DEF_OUT_FREQ		2200000		/* 2.2 MHz */

struct davinci_mdio_regs {
	u32	version;
	u32	control;
#define CONTROL_IDLE		BIT(31)
#define CONTROL_ENABLE		BIT(30)
#define CONTROL_MAX_DIV		(0xffff)

	u32	alive;
	u32	link;
	u32	linkintraw;
	u32	linkintmasked;
	u32	__reserved_0[2];
	u32	userintraw;
	u32	userintmasked;
	u32	userintmaskset;
	u32	userintmaskclr;
	u32	__reserved_1[20];

	struct {
		u32	access;
#define USERACCESS_GO		BIT(31)
#define USERACCESS_WRITE	BIT(30)
#define USERACCESS_ACK		BIT(29)
#define USERACCESS_READ		(0)
#define USERACCESS_DATA		(0xffff)

		u32	physel;
	}	user[0];
};

static const struct mdio_platform_data default_pdata = {
	.bus_freq = DEF_OUT_FREQ,
};

struct davinci_mdio_data {
	struct mdio_platform_data pdata;
	struct davinci_mdio_regs __iomem *regs;
	struct clk	*clk;
	struct device	*dev;
	struct mii_bus	*bus;
	unsigned long	access_time; /* jiffies */
	/* Indicates that driver shouldn't modify phy_mask in case
	 * if MDIO bus is registered from DT.
	 */
	bool		skip_scan;
	u32		clk_div;
};

static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
{
	u32 mdio_in, div, mdio_out_khz, access_time;

	mdio_in = clk_get_rate(data->clk);
	div = (mdio_in / data->pdata.bus_freq) - 1;
	if (div > CONTROL_MAX_DIV)
		div = CONTROL_MAX_DIV;

	data->clk_div = div;
	/*
	 * One mdio transaction consists of:
	 *	32 bits of preamble
	 *	32 bits of transferred data
	 *	24 bits of bus yield (not needed unless shared?)
	 */
	mdio_out_khz = mdio_in / (1000 * (div + 1));
	access_time  = (88 * 1000) / mdio_out_khz;

	/*
	 * In the worst case, we could be kicking off a user-access immediately
	 * after the mdio bus scan state-machine triggered its own read.  If
	 * so, our request could get deferred by one access cycle.  We
	 * defensively allow for 4 access cycles.
	 */
	data->access_time = usecs_to_jiffies(access_time * 4);
	if (!data->access_time)
		data->access_time = 1;
}

static void davinci_mdio_enable(struct davinci_mdio_data *data)
{
	/* set enable and clock divider */
	__raw_writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
}

static int davinci_mdio_reset(struct mii_bus *bus)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 phy_mask, ver;

	davinci_mdio_enable(data);

	/* wait for scan logic to settle */
	msleep(PHY_MAX_ADDR * data->access_time);

	/* dump hardware version info */
	ver = __raw_readl(&data->regs->version);
	dev_info(data->dev, "davinci mdio revision %d.%d\n",
		 (ver >> 8) & 0xff, ver & 0xff);

	if (data->skip_scan)
		return 0;

	/* get phy mask from the alive register */
	phy_mask = __raw_readl(&data->regs->alive);
	if (phy_mask) {
		/* restrict mdio bus to live phys only */
		dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
		phy_mask = ~phy_mask;
	} else {
		/* desperately scan all phys */
		dev_warn(data->dev, "no live phy, scanning all\n");
		phy_mask = 0;
	}
	data->bus->phy_mask = phy_mask;

	return 0;
}

/* wait until hardware is ready for another user access */
static inline int wait_for_user_access(struct davinci_mdio_data *data)
{
	struct davinci_mdio_regs __iomem *regs = data->regs;
	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	u32 reg;

	while (time_after(timeout, jiffies)) {
		reg = __raw_readl(&regs->user[0].access);
		if ((reg & USERACCESS_GO) == 0)
			return 0;

		reg = __raw_readl(&regs->control);
		if ((reg & CONTROL_IDLE) == 0)
			continue;

		/*
		 * An emac soft_reset may have clobbered the mdio controller's
		 * state machine.  We need to reset and retry the current
		 * operation
		 */
		dev_warn(data->dev, "resetting idled controller\n");
		davinci_mdio_enable(data);
		return -EAGAIN;
	}

	reg = __raw_readl(&regs->user[0].access);
	if ((reg & USERACCESS_GO) == 0)
		return 0;

	dev_err(data->dev, "timed out waiting for user access\n");
	return -ETIMEDOUT;
}

/* wait until hardware state machine is idle */
static inline int wait_for_idle(struct davinci_mdio_data *data)
{
	struct davinci_mdio_regs __iomem *regs = data->regs;
	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);

	while (time_after(timeout, jiffies)) {
		if (__raw_readl(&regs->control) & CONTROL_IDLE)
			return 0;
	}
	dev_err(data->dev, "timed out waiting for idle\n");
	return -ETIMEDOUT;
}

static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 reg;
	int ret;

	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
		return -EINVAL;

	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
	       (phy_id << 16));

	while (1) {
		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		__raw_writel(reg, &data->regs->user[0].access);

		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		reg = __raw_readl(&data->regs->user[0].access);
		ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
		break;
	}

	return ret;
}

static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
			      int phy_reg, u16 phy_data)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 reg;
	int ret;

	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
		return -EINVAL;

	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
		   (phy_id << 16) | (phy_data & USERACCESS_DATA));

	while (1) {
		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		__raw_writel(reg, &data->regs->user[0].access);

		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		break;
	}

	return 0;
}

#if IS_ENABLED(CONFIG_OF)
static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
			 struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	u32 prop;

	if (!node)
		return -EINVAL;

	if (of_property_read_u32(node, "bus_freq", &prop)) {
		dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
		return -EINVAL;
	}
	data->bus_freq = prop;

	return 0;
}
#endif

static int davinci_mdio_probe(struct platform_device *pdev)
{
	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct device *dev = &pdev->dev;
	struct davinci_mdio_data *data;
	struct resource *res;
	struct phy_device *phy;
	int ret, addr;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->bus = devm_mdiobus_alloc(dev);
	if (!data->bus) {
		dev_err(dev, "failed to alloc mii bus\n");
		return -ENOMEM;
	}

	if (dev->of_node) {
		if (davinci_mdio_probe_dt(&data->pdata, pdev))
			data->pdata = default_pdata;
		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
	} else {
		data->pdata = pdata ? (*pdata) : default_pdata;
		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
			 pdev->name, pdev->id);
	}

	data->bus->name		= dev_name(dev);
	data->bus->read		= davinci_mdio_read,
	data->bus->write	= davinci_mdio_write,
	data->bus->reset	= davinci_mdio_reset,
	data->bus->parent	= dev;
	data->bus->priv		= data;

	data->clk = devm_clk_get(dev, "fck");
	if (IS_ERR(data->clk)) {
		dev_err(dev, "failed to get device clock\n");
		return PTR_ERR(data->clk);
	}

	dev_set_drvdata(dev, data);
	data->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(data->regs))
		return PTR_ERR(data->regs);

	davinci_mdio_init_clk(data);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/* register the mii bus
	 * Create PHYs from DT only in case if PHY child nodes are explicitly
	 * defined to support backward compatibility with DTs which assume that
	 * Davinci MDIO will always scan the bus for PHYs detection.
	 */
	if (dev->of_node && of_get_child_count(dev->of_node)) {
		data->skip_scan = true;
		ret = of_mdiobus_register(data->bus, dev->of_node);
	} else {
		ret = mdiobus_register(data->bus);
	}
	if (ret)
		goto bail_out;

	/* scan and dump the bus */
	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
		phy = mdiobus_get_phy(data->bus, addr);
		if (phy) {
			dev_info(dev, "phy[%d]: device %s, driver %s\n",
				 phy->mdio.addr, phydev_name(phy),
				 phy->drv ? phy->drv->name : "unknown");
		}
	}

	return 0;

bail_out:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int davinci_mdio_remove(struct platform_device *pdev)
{
	struct davinci_mdio_data *data = platform_get_drvdata(pdev);

	if (data->bus)
		mdiobus_unregister(data->bus);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int davinci_mdio_suspend(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	u32 ctrl;

	/* shutdown the scan state machine */
	ctrl = __raw_readl(&data->regs->control);
	ctrl &= ~CONTROL_ENABLE;
	__raw_writel(ctrl, &data->regs->control);
	wait_for_idle(data);

	/* Select sleep pin state */
	pinctrl_pm_select_sleep_state(dev);

	return 0;
}

static int davinci_mdio_resume(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);

	/* Select default pin state */
	pinctrl_pm_select_default_state(dev);

	/* restart the scan state machine */
	davinci_mdio_enable(data);

	return 0;
}
#endif

static const struct dev_pm_ops davinci_mdio_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
};

#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id davinci_mdio_of_mtable[] = {
	{ .compatible = "ti,davinci_mdio", },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
#endif

static struct platform_driver davinci_mdio_driver = {
	.driver = {
		.name	 = "davinci_mdio",
		.pm	 = &davinci_mdio_pm_ops,
		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
	},
	.probe = davinci_mdio_probe,
	.remove = davinci_mdio_remove,
};

static int __init davinci_mdio_init(void)
{
	return platform_driver_register(&davinci_mdio_driver);
}
device_initcall(davinci_mdio_init);

static void __exit davinci_mdio_exit(void)
{
	platform_driver_unregister(&davinci_mdio_driver);
}
module_exit(davinci_mdio_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DaVinci MDIO driver");
Commit	Line	Data
f20136eb CC	1	/*
	2	* DaVinci MDIO Module driver
	3	*
	4	* Copyright (C) 2010 Texas Instruments.
	5	*
	6	* Shamelessly ripped out of davinci_emac.c, original copyrights follow:
	7	*
	8	* Copyright (C) 2009 Texas Instruments.
	9	*
	10	* ---------------------------------------------------------------------------
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	* ---------------------------------------------------------------------------
	26	*/
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/delay.h>
	31	#include <linux/sched.h>
	32	#include <linux/slab.h>
	33	#include <linux/phy.h>
	34	#include <linux/clk.h>
	35	#include <linux/err.h>
	36	#include <linux/io.h>
8e476d9d	37	#include <linux/pm_runtime.h>
f20136eb	38	#include <linux/davinci_emac.h>
ec03e6a8 M	39	#include <linux/of.h>
ec03e6a8 M	40	#include <linux/of_device.h>
0a0ea068	41	#include <linux/of_mdio.h>
5c0e3580	42	#include <linux/pinctrl/consumer.h>
f20136eb CC	43
	44	/*
	45	* This timeout definition is a worst-case ultra defensive measure against
	46	* unexpected controller lock ups. Ideally, we should never ever hit this
	47	* scenario in practice.
	48	*/
	49	#define MDIO_TIMEOUT 100 /* msecs */
	50
	51	#define PHY_REG_MASK 0x1f
	52	#define PHY_ID_MASK 0x1f
	53
	54	#define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
	55
	56	struct davinci_mdio_regs {
	57	u32 version;
	58	u32 control;
	59	#define CONTROL_IDLE BIT(31)
	60	#define CONTROL_ENABLE BIT(30)
7c3a95a1	61	#define CONTROL_MAX_DIV (0xffff)
f20136eb CC	62
	63	u32 alive;
	64	u32 link;
	65	u32 linkintraw;
	66	u32 linkintmasked;
	67	u32 __reserved_0[2];
	68	u32 userintraw;
	69	u32 userintmasked;
	70	u32 userintmaskset;
	71	u32 userintmaskclr;
	72	u32 __reserved_1[20];
	73
	74	struct {
	75	u32 access;
	76	#define USERACCESS_GO BIT(31)
	77	#define USERACCESS_WRITE BIT(30)
	78	#define USERACCESS_ACK BIT(29)
	79	#define USERACCESS_READ (0)
	80	#define USERACCESS_DATA (0xffff)
	81
	82	u32 physel;
	83	} user[0];
	84	};
	85
9b05f462	86	static const struct mdio_platform_data default_pdata = {
f20136eb CC	87	.bus_freq = DEF_OUT_FREQ,
	88	};
	89
	90	struct davinci_mdio_data {
	91	struct mdio_platform_data pdata;
	92	struct davinci_mdio_regs __iomem *regs;
f20136eb CC	93	struct clk *clk;
	94	struct device *dev;
	95	struct mii_bus *bus;
f20136eb	96	unsigned long access_time; /* jiffies */
0a0ea068 GS	97	/* Indicates that driver shouldn't modify phy_mask in case
	98	* if MDIO bus is registered from DT.
	99	*/
	100	bool skip_scan;
28f0ccb9	101	u32 clk_div;
f20136eb CC	102	};
f20136eb CC	103
28f0ccb9	104	static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
f20136eb CC	105	{
	106	u32 mdio_in, div, mdio_out_khz, access_time;
	107
	108	mdio_in = clk_get_rate(data->clk);
	109	div = (mdio_in / data->pdata.bus_freq) - 1;
	110	if (div > CONTROL_MAX_DIV)
	111	div = CONTROL_MAX_DIV;
	112
28f0ccb9	113	data->clk_div = div;
f20136eb CC	114	/*
	115	* One mdio transaction consists of:
	116	* 32 bits of preamble
	117	* 32 bits of transferred data
	118	* 24 bits of bus yield (not needed unless shared?)
	119	*/
	120	mdio_out_khz = mdio_in / (1000 * (div + 1));
	121	access_time = (88 * 1000) / mdio_out_khz;
	122
	123	/*
	124	* In the worst case, we could be kicking off a user-access immediately
	125	* after the mdio bus scan state-machine triggered its own read. If
	126	* so, our request could get deferred by one access cycle. We
	127	* defensively allow for 4 access cycles.
	128	*/
	129	data->access_time = usecs_to_jiffies(access_time * 4);
	130	if (!data->access_time)
	131	data->access_time = 1;
	132	}
	133
28f0ccb9 GS	134	static void davinci_mdio_enable(struct davinci_mdio_data *data)
	135	{
	136	/* set enable and clock divider */
	137	__raw_writel(data->clk_div \| CONTROL_ENABLE, &data->regs->control);
	138	}
	139
f20136eb CC	140	static int davinci_mdio_reset(struct mii_bus *bus)
	141	{
	142	struct davinci_mdio_data *data = bus->priv;
	143	u32 phy_mask, ver;
	144
28f0ccb9	145	davinci_mdio_enable(data);
f20136eb CC	146
	147	/* wait for scan logic to settle */
	148	msleep(PHY_MAX_ADDR * data->access_time);
	149
	150	/* dump hardware version info */
	151	ver = __raw_readl(&data->regs->version);
	152	dev_info(data->dev, "davinci mdio revision %d.%d\n",
	153	(ver >> 8) & 0xff, ver & 0xff);
	154
0a0ea068 GS	155	if (data->skip_scan)
	156	return 0;
	157
f20136eb CC	158	/* get phy mask from the alive register */
	159	phy_mask = __raw_readl(&data->regs->alive);
	160	if (phy_mask) {
	161	/* restrict mdio bus to live phys only */
	162	dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
	163	phy_mask = ~phy_mask;
	164	} else {
	165	/* desperately scan all phys */
	166	dev_warn(data->dev, "no live phy, scanning all\n");
	167	phy_mask = 0;
	168	}
	169	data->bus->phy_mask = phy_mask;
	170
	171	return 0;
	172	}
	173
	174	/* wait until hardware is ready for another user access */
	175	static inline int wait_for_user_access(struct davinci_mdio_data *data)
	176	{
	177	struct davinci_mdio_regs __iomem *regs = data->regs;
	178	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	179	u32 reg;
	180
	181	while (time_after(timeout, jiffies)) {
	182	reg = __raw_readl(&regs->user[0].access);
	183	if ((reg & USERACCESS_GO) == 0)
	184	return 0;
	185
	186	reg = __raw_readl(&regs->control);
	187	if ((reg & CONTROL_IDLE) == 0)
	188	continue;
	189
	190	/*
	191	* An emac soft_reset may have clobbered the mdio controller's
	192	* state machine. We need to reset and retry the current
	193	* operation
	194	*/
	195	dev_warn(data->dev, "resetting idled controller\n");
28f0ccb9	196	davinci_mdio_enable(data);
f20136eb CC	197	return -EAGAIN;
f20136eb CC	198	}
5b76d060 CR	199
	200	reg = __raw_readl(&regs->user[0].access);
	201	if ((reg & USERACCESS_GO) == 0)
	202	return 0;
	203
f20136eb CC	204	dev_err(data->dev, "timed out waiting for user access\n");
	205	return -ETIMEDOUT;
	206	}
	207
	208	/* wait until hardware state machine is idle */
	209	static inline int wait_for_idle(struct davinci_mdio_data *data)
	210	{
	211	struct davinci_mdio_regs __iomem *regs = data->regs;
	212	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	213
	214	while (time_after(timeout, jiffies)) {
	215	if (__raw_readl(&regs->control) & CONTROL_IDLE)
	216	return 0;
	217	}
	218	dev_err(data->dev, "timed out waiting for idle\n");
	219	return -ETIMEDOUT;
	220	}
	221
	222	static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
	223	{
	224	struct davinci_mdio_data *data = bus->priv;
	225	u32 reg;
	226	int ret;
	227
	228	if (phy_reg & ~PHY_REG_MASK \|\| phy_id & ~PHY_ID_MASK)
	229	return -EINVAL;
	230
f20136eb CC	231	reg = (USERACCESS_GO \| USERACCESS_READ \| (phy_reg << 21) \|
	232	(phy_id << 16));
	233
	234	while (1) {
	235	ret = wait_for_user_access(data);
	236	if (ret == -EAGAIN)
	237	continue;
	238	if (ret < 0)
	239	break;
	240
	241	__raw_writel(reg, &data->regs->user[0].access);
	242
	243	ret = wait_for_user_access(data);
	244	if (ret == -EAGAIN)
	245	continue;
	246	if (ret < 0)
	247	break;
	248
	249	reg = __raw_readl(&data->regs->user[0].access);
	250	ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
	251	break;
	252	}
	253
f20136eb CC	254	return ret;
	255	}
	256
	257	static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
	258	int phy_reg, u16 phy_data)
	259	{
	260	struct davinci_mdio_data *data = bus->priv;
	261	u32 reg;
	262	int ret;
	263
	264	if (phy_reg & ~PHY_REG_MASK \|\| phy_id & ~PHY_ID_MASK)
	265	return -EINVAL;
	266
f20136eb CC	267	reg = (USERACCESS_GO \| USERACCESS_WRITE \| (phy_reg << 21) \|
	268	(phy_id << 16) \| (phy_data & USERACCESS_DATA));
	269
	270	while (1) {
	271	ret = wait_for_user_access(data);
	272	if (ret == -EAGAIN)
	273	continue;
	274	if (ret < 0)
	275	break;
	276
	277	__raw_writel(reg, &data->regs->user[0].access);
	278
	279	ret = wait_for_user_access(data);
	280	if (ret == -EAGAIN)
	281	continue;
	282	break;
	283	}
	284
f20136eb CC	285	return 0;
	286	}
	287
277e2a84	288	#if IS_ENABLED(CONFIG_OF)
ec03e6a8 M	289	static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
	290	struct platform_device *pdev)
	291	{
	292	struct device_node *node = pdev->dev.of_node;
	293	u32 prop;
	294
	295	if (!node)
	296	return -EINVAL;
	297
	298	if (of_property_read_u32(node, "bus_freq", &prop)) {
a92f40a9	299	dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
ec03e6a8 M	300	return -EINVAL;
	301	}
	302	data->bus_freq = prop;
	303
	304	return 0;
	305	}
277e2a84	306	#endif
ec03e6a8	307
e38921d4	308	static int davinci_mdio_probe(struct platform_device *pdev)
f20136eb	309	{
894cdbb0	310	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
f20136eb CC	311	struct device *dev = &pdev->dev;
	312	struct davinci_mdio_data *data;
	313	struct resource *res;
	314	struct phy_device *phy;
	315	int ret, addr;
	316
50d0636e	317	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
b2adaca9	318	if (!data)
f20136eb	319	return -ENOMEM;
f20136eb	320
50d0636e	321	data->bus = devm_mdiobus_alloc(dev);
f20136eb CC	322	if (!data->bus) {
f20136eb CC	323	dev_err(dev, "failed to alloc mii bus\n");
50d0636e	324	return -ENOMEM;
f20136eb CC	325	}
f20136eb CC	326
ec03e6a8 M	327	if (dev->of_node) {
	328	if (davinci_mdio_probe_dt(&data->pdata, pdev))
	329	data->pdata = default_pdata;
	330	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
	331	} else {
	332	data->pdata = pdata ? (*pdata) : default_pdata;
	333	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
	334	pdev->name, pdev->id);
	335	}
	336
f20136eb CC	337	data->bus->name = dev_name(dev);
	338	data->bus->read = davinci_mdio_read,
	339	data->bus->write = davinci_mdio_write,
	340	data->bus->reset = davinci_mdio_reset,
	341	data->bus->parent = dev;
	342	data->bus->priv = data;
f20136eb	343
50d0636e	344	data->clk = devm_clk_get(dev, "fck");
f20136eb	345	if (IS_ERR(data->clk)) {
f20136eb	346	dev_err(dev, "failed to get device clock\n");
909892a6	347	return PTR_ERR(data->clk);
f20136eb CC	348	}
f20136eb CC	349
f20136eb CC	350	dev_set_drvdata(dev, data);
f20136eb CC	351	data->dev = dev;
f20136eb CC	352
f20136eb CC	353	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9728e1a7	354	data->regs = devm_ioremap_resource(dev, res);
909892a6 GS	355	if (IS_ERR(data->regs))
	356	return PTR_ERR(data->regs);
	357
28f0ccb9 GS	358	davinci_mdio_init_clk(data);
28f0ccb9 GS	359
909892a6 GS	360	pm_runtime_enable(&pdev->dev);
909892a6 GS	361	pm_runtime_get_sync(&pdev->dev);
f20136eb	362
0a0ea068 GS	363	/* register the mii bus
	364	* Create PHYs from DT only in case if PHY child nodes are explicitly
	365	* defined to support backward compatibility with DTs which assume that
	366	* Davinci MDIO will always scan the bus for PHYs detection.
	367	*/
	368	if (dev->of_node && of_get_child_count(dev->of_node)) {
	369	data->skip_scan = true;
	370	ret = of_mdiobus_register(data->bus, dev->of_node);
	371	} else {
	372	ret = mdiobus_register(data->bus);
	373	}
f20136eb CC	374	if (ret)
	375	goto bail_out;
	376
	377	/* scan and dump the bus */
	378	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
7f854420	379	phy = mdiobus_get_phy(data->bus, addr);
f20136eb CC	380	if (phy) {
f20136eb CC	381	dev_info(dev, "phy[%d]: device %s, driver %s\n",
e5a03bfd	382	phy->mdio.addr, phydev_name(phy),
f20136eb CC	383	phy->drv ? phy->drv->name : "unknown");
	384	}
	385	}
	386
	387	return 0;
	388
	389	bail_out:
8e476d9d M	390	pm_runtime_put_sync(&pdev->dev);
8e476d9d M	391	pm_runtime_disable(&pdev->dev);
f20136eb	392
f20136eb CC	393	return ret;
	394	}
	395
e38921d4	396	static int davinci_mdio_remove(struct platform_device *pdev)
f20136eb	397	{
84ce22df	398	struct davinci_mdio_data *data = platform_get_drvdata(pdev);
f20136eb	399
50d0636e	400	if (data->bus)
b27393ae	401	mdiobus_unregister(data->bus);
f20136eb	402
8e476d9d M	403	pm_runtime_put_sync(&pdev->dev);
8e476d9d M	404	pm_runtime_disable(&pdev->dev);
f20136eb	405
f20136eb CC	406	return 0;
	407	}
	408
2f5c54ce	409	#ifdef CONFIG_PM_SLEEP
f20136eb CC	410	static int davinci_mdio_suspend(struct device *dev)
	411	{
	412	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	413	u32 ctrl;
	414
f20136eb CC	415	/* shutdown the scan state machine */
	416	ctrl = __raw_readl(&data->regs->control);
	417	ctrl &= ~CONTROL_ENABLE;
	418	__raw_writel(ctrl, &data->regs->control);
	419	wait_for_idle(data);
	420
5c0e3580 M	421	/* Select sleep pin state */
	422	pinctrl_pm_select_sleep_state(dev);
	423
f20136eb CC	424	return 0;
	425	}
	426
	427	static int davinci_mdio_resume(struct device *dev)
	428	{
	429	struct davinci_mdio_data *data = dev_get_drvdata(dev);
f20136eb	430
5c0e3580 M	431	/* Select default pin state */
	432	pinctrl_pm_select_default_state(dev);
	433
f20136eb	434	/* restart the scan state machine */
28f0ccb9	435	davinci_mdio_enable(data);
f20136eb	436
f20136eb CC	437	return 0;
f20136eb CC	438	}
2f5c54ce	439	#endif
f20136eb CC	440
f20136eb CC	441	static const struct dev_pm_ops davinci_mdio_pm_ops = {
2f5c54ce	442	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
f20136eb CC	443	};
f20136eb CC	444
277e2a84	445	#if IS_ENABLED(CONFIG_OF)
ec03e6a8 M	446	static const struct of_device_id davinci_mdio_of_mtable[] = {
	447	{ .compatible = "ti,davinci_mdio", },
	448	{ /* sentinel */ },
	449	};
4bc21d41	450	MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
277e2a84	451	#endif
ec03e6a8	452
f20136eb CC	453	static struct platform_driver davinci_mdio_driver = {
	454	.driver = {
	455	.name = "davinci_mdio",
f20136eb	456	.pm = &davinci_mdio_pm_ops,
ec03e6a8	457	.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
f20136eb CC	458	},
f20136eb CC	459	.probe = davinci_mdio_probe,
e38921d4	460	.remove = davinci_mdio_remove,
f20136eb CC	461	};
	462
	463	static int __init davinci_mdio_init(void)
	464	{
	465	return platform_driver_register(&davinci_mdio_driver);
	466	}
	467	device_initcall(davinci_mdio_init);
	468
	469	static void __exit davinci_mdio_exit(void)
	470	{
	471	platform_driver_unregister(&davinci_mdio_driver);
	472	}
	473	module_exit(davinci_mdio_exit);
	474
	475	MODULE_LICENSE("GPL");
	476	MODULE_DESCRIPTION("DaVinci MDIO driver");