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f20136eb CC |
1 | /* |
2 | * DaVinci MDIO Module driver | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments. | |
5 | * | |
6 | * Shamelessly ripped out of davinci_emac.c, original copyrights follow: | |
7 | * | |
8 | * Copyright (C) 2009 Texas Instruments. | |
9 | * | |
10 | * --------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * --------------------------------------------------------------------------- | |
26 | */ | |
27 | #include <linux/module.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/phy.h> | |
34 | #include <linux/clk.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/io.h> | |
8e476d9d | 37 | #include <linux/pm_runtime.h> |
f20136eb | 38 | #include <linux/davinci_emac.h> |
ec03e6a8 M |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
0a0ea068 | 41 | #include <linux/of_mdio.h> |
5c0e3580 | 42 | #include <linux/pinctrl/consumer.h> |
f20136eb CC |
43 | |
44 | /* | |
45 | * This timeout definition is a worst-case ultra defensive measure against | |
46 | * unexpected controller lock ups. Ideally, we should never ever hit this | |
47 | * scenario in practice. | |
48 | */ | |
49 | #define MDIO_TIMEOUT 100 /* msecs */ | |
50 | ||
51 | #define PHY_REG_MASK 0x1f | |
52 | #define PHY_ID_MASK 0x1f | |
53 | ||
54 | #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */ | |
55 | ||
56 | struct davinci_mdio_regs { | |
57 | u32 version; | |
58 | u32 control; | |
59 | #define CONTROL_IDLE BIT(31) | |
60 | #define CONTROL_ENABLE BIT(30) | |
7c3a95a1 | 61 | #define CONTROL_MAX_DIV (0xffff) |
f20136eb CC |
62 | |
63 | u32 alive; | |
64 | u32 link; | |
65 | u32 linkintraw; | |
66 | u32 linkintmasked; | |
67 | u32 __reserved_0[2]; | |
68 | u32 userintraw; | |
69 | u32 userintmasked; | |
70 | u32 userintmaskset; | |
71 | u32 userintmaskclr; | |
72 | u32 __reserved_1[20]; | |
73 | ||
74 | struct { | |
75 | u32 access; | |
76 | #define USERACCESS_GO BIT(31) | |
77 | #define USERACCESS_WRITE BIT(30) | |
78 | #define USERACCESS_ACK BIT(29) | |
79 | #define USERACCESS_READ (0) | |
80 | #define USERACCESS_DATA (0xffff) | |
81 | ||
82 | u32 physel; | |
83 | } user[0]; | |
84 | }; | |
85 | ||
9b05f462 | 86 | static const struct mdio_platform_data default_pdata = { |
f20136eb CC |
87 | .bus_freq = DEF_OUT_FREQ, |
88 | }; | |
89 | ||
90 | struct davinci_mdio_data { | |
91 | struct mdio_platform_data pdata; | |
92 | struct davinci_mdio_regs __iomem *regs; | |
f20136eb CC |
93 | struct clk *clk; |
94 | struct device *dev; | |
95 | struct mii_bus *bus; | |
f20136eb | 96 | unsigned long access_time; /* jiffies */ |
0a0ea068 GS |
97 | /* Indicates that driver shouldn't modify phy_mask in case |
98 | * if MDIO bus is registered from DT. | |
99 | */ | |
100 | bool skip_scan; | |
28f0ccb9 | 101 | u32 clk_div; |
f20136eb CC |
102 | }; |
103 | ||
28f0ccb9 | 104 | static void davinci_mdio_init_clk(struct davinci_mdio_data *data) |
f20136eb CC |
105 | { |
106 | u32 mdio_in, div, mdio_out_khz, access_time; | |
107 | ||
108 | mdio_in = clk_get_rate(data->clk); | |
109 | div = (mdio_in / data->pdata.bus_freq) - 1; | |
110 | if (div > CONTROL_MAX_DIV) | |
111 | div = CONTROL_MAX_DIV; | |
112 | ||
28f0ccb9 | 113 | data->clk_div = div; |
f20136eb CC |
114 | /* |
115 | * One mdio transaction consists of: | |
116 | * 32 bits of preamble | |
117 | * 32 bits of transferred data | |
118 | * 24 bits of bus yield (not needed unless shared?) | |
119 | */ | |
120 | mdio_out_khz = mdio_in / (1000 * (div + 1)); | |
121 | access_time = (88 * 1000) / mdio_out_khz; | |
122 | ||
123 | /* | |
124 | * In the worst case, we could be kicking off a user-access immediately | |
125 | * after the mdio bus scan state-machine triggered its own read. If | |
126 | * so, our request could get deferred by one access cycle. We | |
127 | * defensively allow for 4 access cycles. | |
128 | */ | |
129 | data->access_time = usecs_to_jiffies(access_time * 4); | |
130 | if (!data->access_time) | |
131 | data->access_time = 1; | |
132 | } | |
133 | ||
28f0ccb9 GS |
134 | static void davinci_mdio_enable(struct davinci_mdio_data *data) |
135 | { | |
136 | /* set enable and clock divider */ | |
137 | __raw_writel(data->clk_div | CONTROL_ENABLE, &data->regs->control); | |
138 | } | |
139 | ||
f20136eb CC |
140 | static int davinci_mdio_reset(struct mii_bus *bus) |
141 | { | |
142 | struct davinci_mdio_data *data = bus->priv; | |
143 | u32 phy_mask, ver; | |
144 | ||
28f0ccb9 | 145 | davinci_mdio_enable(data); |
f20136eb CC |
146 | |
147 | /* wait for scan logic to settle */ | |
148 | msleep(PHY_MAX_ADDR * data->access_time); | |
149 | ||
150 | /* dump hardware version info */ | |
151 | ver = __raw_readl(&data->regs->version); | |
152 | dev_info(data->dev, "davinci mdio revision %d.%d\n", | |
153 | (ver >> 8) & 0xff, ver & 0xff); | |
154 | ||
0a0ea068 GS |
155 | if (data->skip_scan) |
156 | return 0; | |
157 | ||
f20136eb CC |
158 | /* get phy mask from the alive register */ |
159 | phy_mask = __raw_readl(&data->regs->alive); | |
160 | if (phy_mask) { | |
161 | /* restrict mdio bus to live phys only */ | |
162 | dev_info(data->dev, "detected phy mask %x\n", ~phy_mask); | |
163 | phy_mask = ~phy_mask; | |
164 | } else { | |
165 | /* desperately scan all phys */ | |
166 | dev_warn(data->dev, "no live phy, scanning all\n"); | |
167 | phy_mask = 0; | |
168 | } | |
169 | data->bus->phy_mask = phy_mask; | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | /* wait until hardware is ready for another user access */ | |
175 | static inline int wait_for_user_access(struct davinci_mdio_data *data) | |
176 | { | |
177 | struct davinci_mdio_regs __iomem *regs = data->regs; | |
178 | unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT); | |
179 | u32 reg; | |
180 | ||
181 | while (time_after(timeout, jiffies)) { | |
182 | reg = __raw_readl(®s->user[0].access); | |
183 | if ((reg & USERACCESS_GO) == 0) | |
184 | return 0; | |
185 | ||
186 | reg = __raw_readl(®s->control); | |
187 | if ((reg & CONTROL_IDLE) == 0) | |
188 | continue; | |
189 | ||
190 | /* | |
191 | * An emac soft_reset may have clobbered the mdio controller's | |
192 | * state machine. We need to reset and retry the current | |
193 | * operation | |
194 | */ | |
195 | dev_warn(data->dev, "resetting idled controller\n"); | |
28f0ccb9 | 196 | davinci_mdio_enable(data); |
f20136eb CC |
197 | return -EAGAIN; |
198 | } | |
5b76d060 CR |
199 | |
200 | reg = __raw_readl(®s->user[0].access); | |
201 | if ((reg & USERACCESS_GO) == 0) | |
202 | return 0; | |
203 | ||
f20136eb CC |
204 | dev_err(data->dev, "timed out waiting for user access\n"); |
205 | return -ETIMEDOUT; | |
206 | } | |
207 | ||
208 | /* wait until hardware state machine is idle */ | |
209 | static inline int wait_for_idle(struct davinci_mdio_data *data) | |
210 | { | |
211 | struct davinci_mdio_regs __iomem *regs = data->regs; | |
212 | unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT); | |
213 | ||
214 | while (time_after(timeout, jiffies)) { | |
215 | if (__raw_readl(®s->control) & CONTROL_IDLE) | |
216 | return 0; | |
217 | } | |
218 | dev_err(data->dev, "timed out waiting for idle\n"); | |
219 | return -ETIMEDOUT; | |
220 | } | |
221 | ||
222 | static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) | |
223 | { | |
224 | struct davinci_mdio_data *data = bus->priv; | |
225 | u32 reg; | |
226 | int ret; | |
227 | ||
228 | if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) | |
229 | return -EINVAL; | |
230 | ||
f20136eb CC |
231 | reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | |
232 | (phy_id << 16)); | |
233 | ||
234 | while (1) { | |
235 | ret = wait_for_user_access(data); | |
236 | if (ret == -EAGAIN) | |
237 | continue; | |
238 | if (ret < 0) | |
239 | break; | |
240 | ||
241 | __raw_writel(reg, &data->regs->user[0].access); | |
242 | ||
243 | ret = wait_for_user_access(data); | |
244 | if (ret == -EAGAIN) | |
245 | continue; | |
246 | if (ret < 0) | |
247 | break; | |
248 | ||
249 | reg = __raw_readl(&data->regs->user[0].access); | |
250 | ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO; | |
251 | break; | |
252 | } | |
253 | ||
f20136eb CC |
254 | return ret; |
255 | } | |
256 | ||
257 | static int davinci_mdio_write(struct mii_bus *bus, int phy_id, | |
258 | int phy_reg, u16 phy_data) | |
259 | { | |
260 | struct davinci_mdio_data *data = bus->priv; | |
261 | u32 reg; | |
262 | int ret; | |
263 | ||
264 | if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) | |
265 | return -EINVAL; | |
266 | ||
f20136eb CC |
267 | reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | |
268 | (phy_id << 16) | (phy_data & USERACCESS_DATA)); | |
269 | ||
270 | while (1) { | |
271 | ret = wait_for_user_access(data); | |
272 | if (ret == -EAGAIN) | |
273 | continue; | |
274 | if (ret < 0) | |
275 | break; | |
276 | ||
277 | __raw_writel(reg, &data->regs->user[0].access); | |
278 | ||
279 | ret = wait_for_user_access(data); | |
280 | if (ret == -EAGAIN) | |
281 | continue; | |
282 | break; | |
283 | } | |
284 | ||
f20136eb CC |
285 | return 0; |
286 | } | |
287 | ||
277e2a84 | 288 | #if IS_ENABLED(CONFIG_OF) |
ec03e6a8 M |
289 | static int davinci_mdio_probe_dt(struct mdio_platform_data *data, |
290 | struct platform_device *pdev) | |
291 | { | |
292 | struct device_node *node = pdev->dev.of_node; | |
293 | u32 prop; | |
294 | ||
295 | if (!node) | |
296 | return -EINVAL; | |
297 | ||
298 | if (of_property_read_u32(node, "bus_freq", &prop)) { | |
a92f40a9 | 299 | dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n"); |
ec03e6a8 M |
300 | return -EINVAL; |
301 | } | |
302 | data->bus_freq = prop; | |
303 | ||
304 | return 0; | |
305 | } | |
277e2a84 | 306 | #endif |
ec03e6a8 | 307 | |
e38921d4 | 308 | static int davinci_mdio_probe(struct platform_device *pdev) |
f20136eb | 309 | { |
894cdbb0 | 310 | struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev); |
f20136eb CC |
311 | struct device *dev = &pdev->dev; |
312 | struct davinci_mdio_data *data; | |
313 | struct resource *res; | |
314 | struct phy_device *phy; | |
315 | int ret, addr; | |
316 | ||
50d0636e | 317 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
b2adaca9 | 318 | if (!data) |
f20136eb | 319 | return -ENOMEM; |
f20136eb | 320 | |
50d0636e | 321 | data->bus = devm_mdiobus_alloc(dev); |
f20136eb CC |
322 | if (!data->bus) { |
323 | dev_err(dev, "failed to alloc mii bus\n"); | |
50d0636e | 324 | return -ENOMEM; |
f20136eb CC |
325 | } |
326 | ||
ec03e6a8 M |
327 | if (dev->of_node) { |
328 | if (davinci_mdio_probe_dt(&data->pdata, pdev)) | |
329 | data->pdata = default_pdata; | |
330 | snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name); | |
331 | } else { | |
332 | data->pdata = pdata ? (*pdata) : default_pdata; | |
333 | snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x", | |
334 | pdev->name, pdev->id); | |
335 | } | |
336 | ||
f20136eb CC |
337 | data->bus->name = dev_name(dev); |
338 | data->bus->read = davinci_mdio_read, | |
339 | data->bus->write = davinci_mdio_write, | |
340 | data->bus->reset = davinci_mdio_reset, | |
341 | data->bus->parent = dev; | |
342 | data->bus->priv = data; | |
f20136eb | 343 | |
50d0636e | 344 | data->clk = devm_clk_get(dev, "fck"); |
f20136eb | 345 | if (IS_ERR(data->clk)) { |
f20136eb | 346 | dev_err(dev, "failed to get device clock\n"); |
909892a6 | 347 | return PTR_ERR(data->clk); |
f20136eb CC |
348 | } |
349 | ||
f20136eb CC |
350 | dev_set_drvdata(dev, data); |
351 | data->dev = dev; | |
f20136eb CC |
352 | |
353 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
9728e1a7 | 354 | data->regs = devm_ioremap_resource(dev, res); |
909892a6 GS |
355 | if (IS_ERR(data->regs)) |
356 | return PTR_ERR(data->regs); | |
357 | ||
28f0ccb9 GS |
358 | davinci_mdio_init_clk(data); |
359 | ||
909892a6 GS |
360 | pm_runtime_enable(&pdev->dev); |
361 | pm_runtime_get_sync(&pdev->dev); | |
f20136eb | 362 | |
0a0ea068 GS |
363 | /* register the mii bus |
364 | * Create PHYs from DT only in case if PHY child nodes are explicitly | |
365 | * defined to support backward compatibility with DTs which assume that | |
366 | * Davinci MDIO will always scan the bus for PHYs detection. | |
367 | */ | |
368 | if (dev->of_node && of_get_child_count(dev->of_node)) { | |
369 | data->skip_scan = true; | |
370 | ret = of_mdiobus_register(data->bus, dev->of_node); | |
371 | } else { | |
372 | ret = mdiobus_register(data->bus); | |
373 | } | |
f20136eb CC |
374 | if (ret) |
375 | goto bail_out; | |
376 | ||
377 | /* scan and dump the bus */ | |
378 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { | |
7f854420 | 379 | phy = mdiobus_get_phy(data->bus, addr); |
f20136eb CC |
380 | if (phy) { |
381 | dev_info(dev, "phy[%d]: device %s, driver %s\n", | |
e5a03bfd | 382 | phy->mdio.addr, phydev_name(phy), |
f20136eb CC |
383 | phy->drv ? phy->drv->name : "unknown"); |
384 | } | |
385 | } | |
386 | ||
387 | return 0; | |
388 | ||
389 | bail_out: | |
8e476d9d M |
390 | pm_runtime_put_sync(&pdev->dev); |
391 | pm_runtime_disable(&pdev->dev); | |
f20136eb | 392 | |
f20136eb CC |
393 | return ret; |
394 | } | |
395 | ||
e38921d4 | 396 | static int davinci_mdio_remove(struct platform_device *pdev) |
f20136eb | 397 | { |
84ce22df | 398 | struct davinci_mdio_data *data = platform_get_drvdata(pdev); |
f20136eb | 399 | |
50d0636e | 400 | if (data->bus) |
b27393ae | 401 | mdiobus_unregister(data->bus); |
f20136eb | 402 | |
8e476d9d M |
403 | pm_runtime_put_sync(&pdev->dev); |
404 | pm_runtime_disable(&pdev->dev); | |
f20136eb | 405 | |
f20136eb CC |
406 | return 0; |
407 | } | |
408 | ||
651652aa GS |
409 | #ifdef CONFIG_PM |
410 | static int davinci_mdio_runtime_suspend(struct device *dev) | |
f20136eb CC |
411 | { |
412 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
413 | u32 ctrl; | |
414 | ||
f20136eb CC |
415 | /* shutdown the scan state machine */ |
416 | ctrl = __raw_readl(&data->regs->control); | |
417 | ctrl &= ~CONTROL_ENABLE; | |
418 | __raw_writel(ctrl, &data->regs->control); | |
419 | wait_for_idle(data); | |
420 | ||
651652aa GS |
421 | return 0; |
422 | } | |
423 | ||
424 | static int davinci_mdio_runtime_resume(struct device *dev) | |
425 | { | |
426 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
427 | ||
428 | davinci_mdio_enable(data); | |
429 | return 0; | |
430 | } | |
431 | #endif | |
432 | ||
433 | #ifdef CONFIG_PM_SLEEP | |
434 | static int davinci_mdio_suspend(struct device *dev) | |
435 | { | |
436 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
437 | int ret = 0; | |
438 | ||
439 | ret = pm_runtime_force_suspend(dev); | |
440 | if (ret < 0) | |
441 | return ret; | |
442 | ||
5c0e3580 M |
443 | /* Select sleep pin state */ |
444 | pinctrl_pm_select_sleep_state(dev); | |
445 | ||
f20136eb CC |
446 | return 0; |
447 | } | |
448 | ||
449 | static int davinci_mdio_resume(struct device *dev) | |
450 | { | |
451 | struct davinci_mdio_data *data = dev_get_drvdata(dev); | |
f20136eb | 452 | |
5c0e3580 M |
453 | /* Select default pin state */ |
454 | pinctrl_pm_select_default_state(dev); | |
455 | ||
651652aa | 456 | pm_runtime_force_resume(dev); |
f20136eb | 457 | |
f20136eb CC |
458 | return 0; |
459 | } | |
2f5c54ce | 460 | #endif |
f20136eb CC |
461 | |
462 | static const struct dev_pm_ops davinci_mdio_pm_ops = { | |
651652aa GS |
463 | SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend, |
464 | davinci_mdio_runtime_resume, NULL) | |
2f5c54ce | 465 | SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume) |
f20136eb CC |
466 | }; |
467 | ||
277e2a84 | 468 | #if IS_ENABLED(CONFIG_OF) |
ec03e6a8 M |
469 | static const struct of_device_id davinci_mdio_of_mtable[] = { |
470 | { .compatible = "ti,davinci_mdio", }, | |
471 | { /* sentinel */ }, | |
472 | }; | |
4bc21d41 | 473 | MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable); |
277e2a84 | 474 | #endif |
ec03e6a8 | 475 | |
f20136eb CC |
476 | static struct platform_driver davinci_mdio_driver = { |
477 | .driver = { | |
478 | .name = "davinci_mdio", | |
f20136eb | 479 | .pm = &davinci_mdio_pm_ops, |
ec03e6a8 | 480 | .of_match_table = of_match_ptr(davinci_mdio_of_mtable), |
f20136eb CC |
481 | }, |
482 | .probe = davinci_mdio_probe, | |
e38921d4 | 483 | .remove = davinci_mdio_remove, |
f20136eb CC |
484 | }; |
485 | ||
486 | static int __init davinci_mdio_init(void) | |
487 | { | |
488 | return platform_driver_register(&davinci_mdio_driver); | |
489 | } | |
490 | device_initcall(davinci_mdio_init); | |
491 | ||
492 | static void __exit davinci_mdio_exit(void) | |
493 | { | |
494 | platform_driver_unregister(&davinci_mdio_driver); | |
495 | } | |
496 | module_exit(davinci_mdio_exit); | |
497 | ||
498 | MODULE_LICENSE("GPL"); | |
499 | MODULE_DESCRIPTION("DaVinci MDIO driver"); |