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phy: Centralise print about attached phy
[deliverable/linux.git] / drivers / net / ethernet / toshiba / tc35815.c
CommitLineData
eea221ce
AN		 1/*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
1da177e4
LT		 3 *
4 * Based on skelton.c by Donald Becker.
1da177e4 5 *
eea221ce
AN		 6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
1da177e4 16 *
eea221ce
AN		 17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
1da177e4 20 *
eea221ce
AN		 21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
1da177e4
LT		 23 */
24
c6a2dbba 25#define DRV_VERSION "1.39"
eea221ce
AN		 26static const char *version = "tc35815.c:v" DRV_VERSION "\n";
27#define MODNAME "tc35815"
1da177e4
LT		 28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/fcntl.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/in.h>
82a9928d 36#include <linux/if_vlan.h>
1da177e4
LT		 37#include <linux/slab.h>
38#include <linux/string.h>
eea221ce 39#include <linux/spinlock.h>
1da177e4 40#include <linux/errno.h>
1da177e4
LT		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/skbuff.h>
44#include <linux/delay.h>
45#include <linux/pci.h>
c6686fe3
AN		 46#include <linux/phy.h>
47#include <linux/workqueue.h>
bd43da8f 48#include <linux/platform_device.h>
70c71606 49#include <linux/prefetch.h>
1da177e4 50#include <asm/io.h>
1da177e4
LT		 51#include <asm/byteorder.h>
52
c6686fe3 53enum tc35815_chiptype {
eea221ce
AN		 54 TC35815CF = 0,
55 TC35815_NWU,
56 TC35815_TX4939,
c6686fe3 57};
eea221ce 58
c6686fe3 59/* indexed by tc35815_chiptype, above */
eea221ce
AN		 60static const struct {
61 const char *name;
b38d1306 62} chip_info[] = {
eea221ce
AN		 63 { "TOSHIBA TC35815CF 10/100BaseTX" },
64 { "TOSHIBA TC35815 with Wake on LAN" },
65 { "TOSHIBA TC35815/TX4939" },
66};
67
9baa3c34 68static const struct pci_device_id tc35815_pci_tbl[] = {
eea221ce
AN		 69 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
72 {0,}
73};
7f225b42 74MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
1da177e4 75
eea221ce
AN		 76/* see MODULE_PARM_DESC */
77static struct tc35815_options {
78 int speed;
79 int duplex;
eea221ce 80} options;
1da177e4
LT		 81
82/*
83 * Registers
84 */
85struct tc35815_regs {
22adf7e5
AN		 86 __u32 DMA_Ctl; /* 0x00 */
87 __u32 TxFrmPtr;
88 __u32 TxThrsh;
89 __u32 TxPollCtr;
90 __u32 BLFrmPtr;
91 __u32 RxFragSize;
92 __u32 Int_En;
93 __u32 FDA_Bas;
94 __u32 FDA_Lim; /* 0x20 */
95 __u32 Int_Src;
96 __u32 unused0[2];
97 __u32 PauseCnt;
98 __u32 RemPauCnt;
99 __u32 TxCtlFrmStat;
100 __u32 unused1;
101 __u32 MAC_Ctl; /* 0x40 */
102 __u32 CAM_Ctl;
103 __u32 Tx_Ctl;
104 __u32 Tx_Stat;
105 __u32 Rx_Ctl;
106 __u32 Rx_Stat;
107 __u32 MD_Data;
108 __u32 MD_CA;
109 __u32 CAM_Adr; /* 0x60 */
110 __u32 CAM_Data;
111 __u32 CAM_Ena;
112 __u32 PROM_Ctl;
113 __u32 PROM_Data;
114 __u32 Algn_Cnt;
115 __u32 CRC_Cnt;
116 __u32 Miss_Cnt;
1da177e4
LT		 117};
118
119/*
120 * Bit assignments
121 */
25985edc 122/* DMA_Ctl bit assign ------------------------------------------------------- */
7f225b42
AN		 123#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
124#define DMA_RxAlign_1 0x00400000
125#define DMA_RxAlign_2 0x00800000
126#define DMA_RxAlign_3 0x00c00000
127#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
25985edc 128#define DMA_IntMask 0x00040000 /* 1:Interrupt mask */
7f225b42
AN		 129#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
130#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
131#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
132#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
133#define DMA_TestMode 0x00002000 /* 1:Test Mode */
134#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
135#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
1da177e4 136
25985edc 137/* RxFragSize bit assign ---------------------------------------------------- */
7f225b42
AN		 138#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
139#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
1da177e4 140
25985edc 141/* MAC_Ctl bit assign ------------------------------------------------------- */
7f225b42
AN		 142#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
143#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
144#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
145#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
146#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
147#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
148#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
149#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
150#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
151#define MAC_Reset 0x00000004 /* 1:Software Reset */
152#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
153#define MAC_HaltReq 0x00000001 /* 1:Halt request */
1da177e4 154
25985edc 155/* PROM_Ctl bit assign ------------------------------------------------------ */
7f225b42
AN		 156#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
157#define PROM_Read 0x00004000 /*10:Read operation */
158#define PROM_Write 0x00002000 /*01:Write operation */
159#define PROM_Erase 0x00006000 /*11:Erase operation */
160 /*00:Enable or Disable Writting, */
161 /* as specified in PROM_Addr. */
162#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
163 /*00xxxx: disable */
1da177e4 164
25985edc 165/* CAM_Ctl bit assign ------------------------------------------------------- */
7f225b42
AN		 166#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
167#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
168 /* accept other */
169#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
170#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
171#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
1da177e4 172
25985edc 173/* CAM_Ena bit assign ------------------------------------------------------- */
7f225b42 174#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
1da177e4 175#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
7f225b42 176#define CAM_Ena_Bit(index) (1 << (index))
1da177e4
LT		 177#define CAM_ENTRY_DESTINATION 0
178#define CAM_ENTRY_SOURCE 1
179#define CAM_ENTRY_MACCTL 20
180
25985edc 181/* Tx_Ctl bit assign -------------------------------------------------------- */
7f225b42
AN		 182#define Tx_En 0x00000001 /* 1:Transmit enable */
183#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
184#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
185#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
186#define Tx_FBack 0x00000010 /* 1:Fast Back-off */
187#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
188#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
189#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
190#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
191#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
192#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
193#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
1da177e4 194
25985edc 195/* Tx_Stat bit assign ------------------------------------------------------- */
7f225b42
AN		 196#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
197#define Tx_ExColl 0x00000010 /* Excessive Collision */
198#define Tx_TXDefer 0x00000020 /* Transmit Defered */
199#define Tx_Paused 0x00000040 /* Transmit Paused */
200#define Tx_IntTx 0x00000080 /* Interrupt on Tx */
201#define Tx_Under 0x00000100 /* Underrun */
202#define Tx_Defer 0x00000200 /* Deferral */
203#define Tx_NCarr 0x00000400 /* No Carrier */
204#define Tx_10Stat 0x00000800 /* 10Mbps Status */
205#define Tx_LateColl 0x00001000 /* Late Collision */
206#define Tx_TxPar 0x00002000 /* Tx Parity Error */
207#define Tx_Comp 0x00004000 /* Completion */
208#define Tx_Halted 0x00008000 /* Tx Halted */
209#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
1da177e4 210
25985edc 211/* Rx_Ctl bit assign -------------------------------------------------------- */
7f225b42
AN		 212#define Rx_EnGood 0x00004000 /* 1:Enable Good */
213#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
214#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
215#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
216#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
217#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
218#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
219#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
220#define Rx_ShortEn 0x00000008 /* 1:Short Enable */
221#define Rx_LongEn 0x00000004 /* 1:Long Enable */
222#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
223#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
1da177e4 224
25985edc 225/* Rx_Stat bit assign ------------------------------------------------------- */
7f225b42
AN		 226#define Rx_Halted 0x00008000 /* Rx Halted */
227#define Rx_Good 0x00004000 /* Rx Good */
228#define Rx_RxPar 0x00002000 /* Rx Parity Error */
842e08bd 229#define Rx_TypePkt 0x00001000 /* Rx Type Packet */
7f225b42
AN		 230#define Rx_LongErr 0x00000800 /* Rx Long Error */
231#define Rx_Over 0x00000400 /* Rx Overflow */
232#define Rx_CRCErr 0x00000200 /* Rx CRC Error */
233#define Rx_Align 0x00000100 /* Rx Alignment Error */
234#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
235#define Rx_IntRx 0x00000040 /* Rx Interrupt */
236#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
842e08bd 237#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
7f225b42 238
842e08bd 239#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
1da177e4 240
25985edc 241/* Int_En bit assign -------------------------------------------------------- */
7f225b42
AN		 242#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
243#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
244#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
245#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
246#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
247#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
248#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
249#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
250#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
251#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
252#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
253#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
254 /* Exhausted Enable */
1da177e4 255
25985edc 256/* Int_Src bit assign ------------------------------------------------------- */
7f225b42
AN		 257#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
258#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
259#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
260#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
261#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
262#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
263#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
264#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
265#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
266#define Int_SWInt 0x00000020 /* 1:Software request & Clear */
267#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
268#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
269#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
270#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
271#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
1da177e4 272
25985edc
LDM		 273/* MD_CA bit assign --------------------------------------------------------- */
274#define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */
7f225b42
AN		 275#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
276#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
1da177e4
LT		 277
278
1da177e4
LT		 279/*
280 * Descriptors
281 */
282
283/* Frame descripter */
284struct FDesc {
285 volatile __u32 FDNext;
286 volatile __u32 FDSystem;
287 volatile __u32 FDStat;
288 volatile __u32 FDCtl;
289};
290
291/* Buffer descripter */
292struct BDesc {
293 volatile __u32 BuffData;
294 volatile __u32 BDCtl;
295};
296
297#define FD_ALIGN 16
298
25985edc 299/* Frame Descripter bit assign ---------------------------------------------- */
7f225b42
AN		 300#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
301#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
302#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
1da177e4 303#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
7f225b42
AN		 304#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
305#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
1da177e4
LT		 306#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
307#define FD_FrmOpt_Packing 0x04000000 /* Rx only */
7f225b42
AN		 308#define FD_CownsFD 0x80000000 /* FD Controller owner bit */
309#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
310#define FD_BDCnt_SHIFT 16
1da177e4 311
25985edc
LDM		 312/* Buffer Descripter bit assign --------------------------------------------- */
313#define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */
7f225b42
AN		 314#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
315#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
316#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
317#define BD_RxBDID_SHIFT 16
1da177e4
LT		 318#define BD_RxBDSeqN_SHIFT 24
319
320
321/* Some useful constants. */
1da177e4 322
a02b7b7a 323#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
eea221ce
AN		 324 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
325 Tx_En) /* maybe 0x7b01 */
297713de 326/* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
1da177e4 327#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
297713de 328 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
1da177e4 329#define INT_EN_CMD (Int_NRAbtEn | \
eea221ce 330 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
1da177e4
LT		 331 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
332 Int_STargAbtEn | \
333 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
eea221ce 334#define DMA_CTL_CMD DMA_BURST_SIZE
c6686fe3 335#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
1da177e4
LT		 336
337/* Tuning parameters */
338#define DMA_BURST_SIZE 32
339#define TX_THRESHOLD 1024
7f225b42
AN		 340/* used threshold with packet max byte for low pci transfer ability.*/
341#define TX_THRESHOLD_MAX 1536
25985edc 342/* setting threshold max value when overrun error occurred this count. */
7f225b42 343#define TX_THRESHOLD_KEEP_LIMIT 10
1da177e4 344
eea221ce 345/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
eea221ce
AN		 346#define FD_PAGE_NUM 4
347#define RX_BUF_NUM 128 /* < 256 */
348#define RX_FD_NUM 256 /* >= 32 */
349#define TX_FD_NUM 128
350#if RX_CTL_CMD & Rx_LongEn
351#define RX_BUF_SIZE PAGE_SIZE
352#elif RX_CTL_CMD & Rx_StripCRC
82a9928d
AN		 353#define RX_BUF_SIZE \
354 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
eea221ce 355#else
82a9928d
AN		 356#define RX_BUF_SIZE \
357 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
eea221ce 358#endif
eea221ce
AN		 359#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
360#define NAPI_WEIGHT 16
1da177e4
LT		 361
362struct TxFD {
363 struct FDesc fd;
364 struct BDesc bd;
365 struct BDesc unused;
366};
367
368struct RxFD {
369 struct FDesc fd;
370 struct BDesc bd[0]; /* variable length */
371};
372
373struct FrFD {
374 struct FDesc fd;
eea221ce 375 struct BDesc bd[RX_BUF_NUM];
1da177e4
LT		 376};
377
378
22adf7e5
AN		 379#define tc_readl(addr) ioread32(addr)
380#define tc_writel(d, addr) iowrite32(d, addr)
1da177e4 381
eea221ce
AN		 382#define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
383
c6686fe3 384/* Information that need to be kept for each controller. */
1da177e4 385struct tc35815_local {
eea221ce 386 struct pci_dev *pci_dev;
1da177e4 387
bea3348e
SH		 388 struct net_device *dev;
389 struct napi_struct napi;
390
1da177e4 391 /* statistics */
1da177e4
LT		 392 struct {
393 int max_tx_qlen;
394 int tx_ints;
395 int rx_ints;
7f225b42 396 int tx_underrun;
1da177e4
LT		 397 } lstats;
398
eea221ce
AN		 399 /* Tx control lock. This protects the transmit buffer ring
400 * state along with the "tx full" state of the driver. This
401 * means all netif_queue flow control actions are protected
402 * by this lock as well.
403 */
404 spinlock_t lock;
dee7399c 405 spinlock_t rx_lock;
eea221ce 406
298cf9be 407 struct mii_bus *mii_bus;
c6686fe3
AN		 408 struct phy_device *phy_dev;
409 int duplex;
410 int speed;
411 int link;
412 struct work_struct restart_work;
1da177e4
LT		 413
414 /*
415 * Transmitting: Batch Mode.
416 * 1 BD in 1 TxFD.
a02b7b7a 417 * Receiving: Non-Packing Mode.
eea221ce
AN		 418 * 1 circular FD for Free Buffer List.
419 * RX_BUF_NUM BD in Free Buffer FD.
420 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
1da177e4 421 */
7f225b42 422 void *fd_buf; /* for TxFD, RxFD, FrFD */
eea221ce 423 dma_addr_t fd_buf_dma;
1da177e4 424 struct TxFD *tfd_base;
eea221ce
AN		 425 unsigned int tfd_start;
426 unsigned int tfd_end;
1da177e4
LT		 427 struct RxFD *rfd_base;
428 struct RxFD *rfd_limit;
429 struct RxFD *rfd_cur;
430 struct FrFD *fbl_ptr;
eea221ce
AN		 431 unsigned int fbl_count;
432 struct {
433 struct sk_buff *skb;
434 dma_addr_t skb_dma;
435 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
eea221ce 436 u32 msg_enable;
c6686fe3 437 enum tc35815_chiptype chiptype;
1da177e4
LT		 438};
439
eea221ce
AN		 440static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
441{
442 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
443}
444#ifdef DEBUG
445static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
446{
447 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
448}
449#endif
eea221ce
AN		 450static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
451 struct pci_dev *hwdev,
452 dma_addr_t *dma_handle)
453{
454 struct sk_buff *skb;
dae2e9f4 455 skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
eea221ce
AN		 456 if (!skb)
457 return NULL;
eea221ce
AN		 458 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
459 PCI_DMA_FROMDEVICE);
8d8bb39b 460 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
eea221ce
AN		 461 dev_kfree_skb_any(skb);
462 return NULL;
463 }
464 skb_reserve(skb, 2); /* make IP header 4byte aligned */
465 return skb;
466}
467
468static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
469{
470 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
471 PCI_DMA_FROMDEVICE);
472 dev_kfree_skb_any(skb);
473}
1da177e4 474
eea221ce 475/* Index to functions, as function prototypes. */
1da177e4
LT		 476
477static int tc35815_open(struct net_device *dev);
478static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
eea221ce 479static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
eea221ce 480static int tc35815_rx(struct net_device *dev, int limit);
bea3348e 481static int tc35815_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 482static void tc35815_txdone(struct net_device *dev);
483static int tc35815_close(struct net_device *dev);
484static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
485static void tc35815_set_multicast_list(struct net_device *dev);
7f225b42 486static void tc35815_tx_timeout(struct net_device *dev);
eea221ce
AN		 487static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
488#ifdef CONFIG_NET_POLL_CONTROLLER
489static void tc35815_poll_controller(struct net_device *dev);
490#endif
491static const struct ethtool_ops tc35815_ethtool_ops;
1da177e4 492
eea221ce 493/* Example routines you must write ;->. */
7f225b42
AN		 494static void tc35815_chip_reset(struct net_device *dev);
495static void tc35815_chip_init(struct net_device *dev);
1da177e4 496
eea221ce
AN		 497#ifdef DEBUG
498static void panic_queues(struct net_device *dev);
499#endif
1da177e4 500
c6686fe3
AN		 501static void tc35815_restart_work(struct work_struct *work);
502
503static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
504{
505 struct net_device *dev = bus->priv;
506 struct tc35815_regs __iomem *tr =
507 (struct tc35815_regs __iomem *)dev->base_addr;
c60a5cf7 508 unsigned long timeout = jiffies + HZ;
c6686fe3
AN		 509
510 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
c60a5cf7 511 udelay(12); /* it takes 32 x 400ns at least */
c6686fe3
AN		 512 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
513 if (time_after(jiffies, timeout))
514 return -EIO;
515 cpu_relax();
516 }
517 return tc_readl(&tr->MD_Data) & 0xffff;
518}
519
520static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
521{
522 struct net_device *dev = bus->priv;
523 struct tc35815_regs __iomem *tr =
524 (struct tc35815_regs __iomem *)dev->base_addr;
c60a5cf7 525 unsigned long timeout = jiffies + HZ;
c6686fe3
AN		 526
527 tc_writel(val, &tr->MD_Data);
528 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
529 &tr->MD_CA);
c60a5cf7 530 udelay(12); /* it takes 32 x 400ns at least */
c6686fe3
AN		 531 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
532 if (time_after(jiffies, timeout))
533 return -EIO;
534 cpu_relax();
535 }
536 return 0;
537}
538
539static void tc_handle_link_change(struct net_device *dev)
540{
541 struct tc35815_local *lp = netdev_priv(dev);
542 struct phy_device *phydev = lp->phy_dev;
543 unsigned long flags;
544 int status_change = 0;
545
546 spin_lock_irqsave(&lp->lock, flags);
547 if (phydev->link &&
548 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
549 struct tc35815_regs __iomem *tr =
550 (struct tc35815_regs __iomem *)dev->base_addr;
551 u32 reg;
552
553 reg = tc_readl(&tr->MAC_Ctl);
554 reg |= MAC_HaltReq;
555 tc_writel(reg, &tr->MAC_Ctl);
556 if (phydev->duplex == DUPLEX_FULL)
557 reg |= MAC_FullDup;
558 else
559 reg &= ~MAC_FullDup;
560 tc_writel(reg, &tr->MAC_Ctl);
561 reg &= ~MAC_HaltReq;
562 tc_writel(reg, &tr->MAC_Ctl);
563
564 /*
565 * TX4939 PCFG.SPEEDn bit will be changed on
566 * NETDEV_CHANGE event.
567 */
c6686fe3
AN		 568 /*
569 * WORKAROUND: enable LostCrS only if half duplex
570 * operation.
571 * (TX4939 does not have EnLCarr)
572 */
573 if (phydev->duplex == DUPLEX_HALF &&
574 lp->chiptype != TC35815_TX4939)
575 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
576 &tr->Tx_Ctl);
c6686fe3
AN		 577
578 lp->speed = phydev->speed;
579 lp->duplex = phydev->duplex;
580 status_change = 1;
581 }
582
583 if (phydev->link != lp->link) {
584 if (phydev->link) {
c6686fe3
AN		 585 /* delayed promiscuous enabling */
586 if (dev->flags & IFF_PROMISC)
587 tc35815_set_multicast_list(dev);
c6686fe3
AN		 588 } else {
589 lp->speed = 0;
590 lp->duplex = -1;
591 }
592 lp->link = phydev->link;
593
594 status_change = 1;
595 }
596 spin_unlock_irqrestore(&lp->lock, flags);
597
598 if (status_change && netif_msg_link(lp)) {
599 phy_print_status(phydev);
72903831
JP		 600 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
601 dev->name,
602 phy_read(phydev, MII_BMCR),
603 phy_read(phydev, MII_BMSR),
604 phy_read(phydev, MII_LPA));
c6686fe3
AN		 605 }
606}
607
608static int tc_mii_probe(struct net_device *dev)
609{
610 struct tc35815_local *lp = netdev_priv(dev);
611 struct phy_device *phydev = NULL;
612 int phy_addr;
613 u32 dropmask;
614
615 /* find the first phy */
616 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
298cf9be 617 if (lp->mii_bus->phy_map[phy_addr]) {
c6686fe3
AN		 618 if (phydev) {
619 printk(KERN_ERR "%s: multiple PHYs found\n",
620 dev->name);
621 return -EINVAL;
622 }
298cf9be 623 phydev = lp->mii_bus->phy_map[phy_addr];
c6686fe3
AN		 624 break;
625 }
626 }
627
628 if (!phydev) {
629 printk(KERN_ERR "%s: no PHY found\n", dev->name);
630 return -ENODEV;
631 }
632
633 /* attach the mac to the phy */
84eff6d1 634 phydev = phy_connect(dev, phydev_name(phydev),
f9a8f83b
FF		 635 &tc_handle_link_change,
636 lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
c6686fe3
AN		 637 if (IS_ERR(phydev)) {
638 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
639 return PTR_ERR(phydev);
640 }
2220943a
AL		 641
642 phy_attached_info(phydev);
c6686fe3
AN		 643
644 /* mask with MAC supported features */
645 phydev->supported &= PHY_BASIC_FEATURES;
646 dropmask = 0;
647 if (options.speed == 10)
648 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
649 else if (options.speed == 100)
650 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
651 if (options.duplex == 1)
652 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
653 else if (options.duplex == 2)
654 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
655 phydev->supported &= ~dropmask;
656 phydev->advertising = phydev->supported;
657
658 lp->link = 0;
659 lp->speed = 0;
660 lp->duplex = -1;
661 lp->phy_dev = phydev;
662
663 return 0;
664}
665
666static int tc_mii_init(struct net_device *dev)
667{
668 struct tc35815_local *lp = netdev_priv(dev);
669 int err;
670 int i;
671
298cf9be
LB		 672 lp->mii_bus = mdiobus_alloc();
673 if (lp->mii_bus == NULL) {
c6686fe3
AN		 674 err = -ENOMEM;
675 goto err_out;
676 }
677
298cf9be
LB		 678 lp->mii_bus->name = "tc35815_mii_bus";
679 lp->mii_bus->read = tc_mdio_read;
680 lp->mii_bus->write = tc_mdio_write;
681 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
682 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
683 lp->mii_bus->priv = dev;
684 lp->mii_bus->parent = &lp->pci_dev->dev;
685 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
686 if (!lp->mii_bus->irq) {
687 err = -ENOMEM;
688 goto err_out_free_mii_bus;
689 }
690
c6686fe3 691 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 692 lp->mii_bus->irq[i] = PHY_POLL;
c6686fe3 693
298cf9be 694 err = mdiobus_register(lp->mii_bus);
c6686fe3
AN		 695 if (err)
696 goto err_out_free_mdio_irq;
697 err = tc_mii_probe(dev);
698 if (err)
699 goto err_out_unregister_bus;
700 return 0;
701
702err_out_unregister_bus:
298cf9be 703 mdiobus_unregister(lp->mii_bus);
c6686fe3 704err_out_free_mdio_irq:
298cf9be 705 kfree(lp->mii_bus->irq);
51cf756c 706err_out_free_mii_bus:
298cf9be 707 mdiobus_free(lp->mii_bus);
c6686fe3
AN		 708err_out:
709 return err;
710}
1da177e4 711
bd43da8f
AN		 712#ifdef CONFIG_CPU_TX49XX
713/*
714 * Find a platform_device providing a MAC address. The platform code
715 * should provide a "tc35815-mac" device with a MAC address in its
716 * platform_data.
717 */
b38d1306 718static int tc35815_mac_match(struct device *dev, void *data)
bd43da8f
AN		 719{
720 struct platform_device *plat_dev = to_platform_device(dev);
721 struct pci_dev *pci_dev = data;
06675e6f 722 unsigned int id = pci_dev->irq;
bd43da8f
AN		 723 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
724}
725
b38d1306 726static int tc35815_read_plat_dev_addr(struct net_device *dev)
bd43da8f 727{
ee79b7fb 728 struct tc35815_local *lp = netdev_priv(dev);
bd43da8f
AN		 729 struct device *pd = bus_find_device(&platform_bus_type, NULL,
730 lp->pci_dev, tc35815_mac_match);
731 if (pd) {
732 if (pd->platform_data)
733 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
734 put_device(pd);
735 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
736 }
737 return -ENODEV;
738}
739#else
b38d1306 740static int tc35815_read_plat_dev_addr(struct net_device *dev)
bd43da8f
AN		 741{
742 return -ENODEV;
743}
744#endif
745
b38d1306 746static int tc35815_init_dev_addr(struct net_device *dev)
eea221ce
AN		 747{
748 struct tc35815_regs __iomem *tr =
749 (struct tc35815_regs __iomem *)dev->base_addr;
750 int i;
751
eea221ce
AN		 752 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
753 ;
754 for (i = 0; i < 6; i += 2) {
755 unsigned short data;
756 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
757 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
758 ;
759 data = tc_readl(&tr->PROM_Data);
760 dev->dev_addr[i] = data & 0xff;
761 dev->dev_addr[i+1] = data >> 8;
762 }
bd43da8f
AN		 763 if (!is_valid_ether_addr(dev->dev_addr))
764 return tc35815_read_plat_dev_addr(dev);
765 return 0;
eea221ce 766}
1da177e4 767
5a1c28b3
AB		 768static const struct net_device_ops tc35815_netdev_ops = {
769 .ndo_open = tc35815_open,
770 .ndo_stop = tc35815_close,
771 .ndo_start_xmit = tc35815_send_packet,
772 .ndo_get_stats = tc35815_get_stats,
afc4b13d 773 .ndo_set_rx_mode = tc35815_set_multicast_list,
5a1c28b3
AB		 774 .ndo_tx_timeout = tc35815_tx_timeout,
775 .ndo_do_ioctl = tc35815_ioctl,
776 .ndo_validate_addr = eth_validate_addr,
777 .ndo_change_mtu = eth_change_mtu,
778 .ndo_set_mac_address = eth_mac_addr,
779#ifdef CONFIG_NET_POLL_CONTROLLER
780 .ndo_poll_controller = tc35815_poll_controller,
781#endif
782};
783
b38d1306 784static int tc35815_init_one(struct pci_dev *pdev,
1dd06ae8 785 const struct pci_device_id *ent)
1da177e4 786{
eea221ce
AN		 787 void __iomem *ioaddr = NULL;
788 struct net_device *dev;
789 struct tc35815_local *lp;
790 int rc;
eea221ce
AN		 791
792 static int printed_version;
793 if (!printed_version++) {
794 printk(version);
795 dev_printk(KERN_DEBUG, &pdev->dev,
c6686fe3
AN		 796 "speed:%d duplex:%d\n",
797 options.speed, options.duplex);
eea221ce
AN		 798 }
799
800 if (!pdev->irq) {
801 dev_warn(&pdev->dev, "no IRQ assigned.\n");
802 return -ENODEV;
803 }
1da177e4 804
eea221ce 805 /* dev zeroed in alloc_etherdev */
7f225b42 806 dev = alloc_etherdev(sizeof(*lp));
41de8d4c 807 if (dev == NULL)
eea221ce 808 return -ENOMEM;
41de8d4c 809
eea221ce 810 SET_NETDEV_DEV(dev, &pdev->dev);
ee79b7fb 811 lp = netdev_priv(dev);
bea3348e 812 lp->dev = dev;
1da177e4 813
eea221ce 814 /* enable device (incl. PCI PM wakeup), and bus-mastering */
22adf7e5 815 rc = pcim_enable_device(pdev);
eea221ce
AN		 816 if (rc)
817 goto err_out;
22adf7e5 818 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
eea221ce 819 if (rc)
1da177e4 820 goto err_out;
22adf7e5
AN		 821 pci_set_master(pdev);
822 ioaddr = pcim_iomap_table(pdev)[1];
1da177e4 823
eea221ce 824 /* Initialize the device structure. */
5a1c28b3 825 dev->netdev_ops = &tc35815_netdev_ops;
eea221ce 826 dev->ethtool_ops = &tc35815_ethtool_ops;
eea221ce 827 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
bea3348e 828 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
1da177e4 829
eea221ce 830 dev->irq = pdev->irq;
7f225b42 831 dev->base_addr = (unsigned long)ioaddr;
1da177e4 832
c6686fe3 833 INIT_WORK(&lp->restart_work, tc35815_restart_work);
eea221ce 834 spin_lock_init(&lp->lock);
dee7399c 835 spin_lock_init(&lp->rx_lock);
eea221ce 836 lp->pci_dev = pdev;
c6686fe3 837 lp->chiptype = ent->driver_data;
1da177e4 838
eea221ce
AN		 839 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
840 pci_set_drvdata(pdev, dev);
1da177e4 841
eea221ce 842 /* Soft reset the chip. */
1da177e4
LT		 843 tc35815_chip_reset(dev);
844
eea221ce 845 /* Retrieve the ethernet address. */
bd43da8f
AN		 846 if (tc35815_init_dev_addr(dev)) {
847 dev_warn(&pdev->dev, "not valid ether addr\n");
f2cedb63 848 eth_hw_addr_random(dev);
bd43da8f 849 }
eea221ce 850
7f225b42 851 rc = register_netdev(dev);
eea221ce 852 if (rc)
1e2cfeef 853 goto err_out;
eea221ce 854
e174961c 855 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
eea221ce 856 dev->name,
c6686fe3 857 chip_info[ent->driver_data].name,
eea221ce 858 dev->base_addr,
e174961c 859 dev->dev_addr,
eea221ce
AN		 860 dev->irq);
861
c6686fe3
AN		 862 rc = tc_mii_init(dev);
863 if (rc)
864 goto err_out_unregister;
1da177e4 865
eea221ce 866 return 0;
1da177e4 867
c6686fe3
AN		 868err_out_unregister:
869 unregister_netdev(dev);
eea221ce 870err_out:
7f225b42 871 free_netdev(dev);
eea221ce
AN		 872 return rc;
873}
1da177e4 874
1da177e4 875
b38d1306 876static void tc35815_remove_one(struct pci_dev *pdev)
eea221ce 877{
7f225b42 878 struct net_device *dev = pci_get_drvdata(pdev);
c6686fe3 879 struct tc35815_local *lp = netdev_priv(dev);
1da177e4 880
c6686fe3 881 phy_disconnect(lp->phy_dev);
298cf9be
LB		 882 mdiobus_unregister(lp->mii_bus);
883 kfree(lp->mii_bus->irq);
884 mdiobus_free(lp->mii_bus);
7f225b42
AN		 885 unregister_netdev(dev);
886 free_netdev(dev);
1da177e4
LT		 887}
888
1da177e4
LT		 889static int
890tc35815_init_queues(struct net_device *dev)
891{
ee79b7fb 892 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 893 int i;
894 unsigned long fd_addr;
895
896 if (!lp->fd_buf) {
eea221ce
AN		 897 BUG_ON(sizeof(struct FDesc) +
898 sizeof(struct BDesc) * RX_BUF_NUM +
899 sizeof(struct FDesc) * RX_FD_NUM +
900 sizeof(struct TxFD) * TX_FD_NUM >
901 PAGE_SIZE * FD_PAGE_NUM);
1da177e4 902
7f225b42
AN		 903 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
904 PAGE_SIZE * FD_PAGE_NUM,
905 &lp->fd_buf_dma);
906 if (!lp->fd_buf)
1da177e4 907 return -ENOMEM;
eea221ce 908 for (i = 0; i < RX_BUF_NUM; i++) {
eea221ce
AN		 909 lp->rx_skbs[i].skb =
910 alloc_rxbuf_skb(dev, lp->pci_dev,
911 &lp->rx_skbs[i].skb_dma);
912 if (!lp->rx_skbs[i].skb) {
913 while (--i >= 0) {
914 free_rxbuf_skb(lp->pci_dev,
915 lp->rx_skbs[i].skb,
916 lp->rx_skbs[i].skb_dma);
917 lp->rx_skbs[i].skb = NULL;
918 }
919 pci_free_consistent(lp->pci_dev,
920 PAGE_SIZE * FD_PAGE_NUM,
921 lp->fd_buf,
922 lp->fd_buf_dma);
923 lp->fd_buf = NULL;
1da177e4
LT		 924 return -ENOMEM;
925 }
1da177e4 926 }
eea221ce
AN		 927 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
928 dev->name, lp->fd_buf);
eea221ce 929 printk("\n");
1da177e4 930 } else {
7f225b42
AN		 931 for (i = 0; i < FD_PAGE_NUM; i++)
932 clear_page((void *)((unsigned long)lp->fd_buf +
933 i * PAGE_SIZE));
1da177e4 934 }
1da177e4 935 fd_addr = (unsigned long)lp->fd_buf;
1da177e4
LT		 936
937 /* Free Descriptors (for Receive) */
938 lp->rfd_base = (struct RxFD *)fd_addr;
939 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
7f225b42 940 for (i = 0; i < RX_FD_NUM; i++)
1da177e4 941 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1da177e4 942 lp->rfd_cur = lp->rfd_base;
eea221ce 943 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1da177e4
LT		 944
945 /* Transmit Descriptors */
946 lp->tfd_base = (struct TxFD *)fd_addr;
947 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
948 for (i = 0; i < TX_FD_NUM; i++) {
eea221ce
AN		 949 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
950 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4
LT		 951 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
952 }
eea221ce 953 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1da177e4
LT		 954 lp->tfd_start = 0;
955 lp->tfd_end = 0;
956
957 /* Buffer List (for Receive) */
958 lp->fbl_ptr = (struct FrFD *)fd_addr;
eea221ce
AN		 959 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
960 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
eea221ce
AN		 961 /*
962 * move all allocated skbs to head of rx_skbs[] array.
963 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
964 * tc35815_rx() had failed.
965 */
966 lp->fbl_count = 0;
967 for (i = 0; i < RX_BUF_NUM; i++) {
968 if (lp->rx_skbs[i].skb) {
969 if (i != lp->fbl_count) {
970 lp->rx_skbs[lp->fbl_count].skb =
971 lp->rx_skbs[i].skb;
972 lp->rx_skbs[lp->fbl_count].skb_dma =
973 lp->rx_skbs[i].skb_dma;
974 }
975 lp->fbl_count++;
976 }
977 }
eea221ce 978 for (i = 0; i < RX_BUF_NUM; i++) {
eea221ce
AN		 979 if (i >= lp->fbl_count) {
980 lp->fbl_ptr->bd[i].BuffData = 0;
981 lp->fbl_ptr->bd[i].BDCtl = 0;
982 continue;
983 }
984 lp->fbl_ptr->bd[i].BuffData =
985 cpu_to_le32(lp->rx_skbs[i].skb_dma);
1da177e4
LT		 986 /* BDID is index of FrFD.bd[] */
987 lp->fbl_ptr->bd[i].BDCtl =
eea221ce
AN		 988 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
989 RX_BUF_SIZE);
1da177e4 990 }
1da177e4 991
eea221ce
AN		 992 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
993 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1da177e4
LT		 994 return 0;
995}
996
997static void
998tc35815_clear_queues(struct net_device *dev)
999{
ee79b7fb 1000 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 1001 int i;
1002
1003 for (i = 0; i < TX_FD_NUM; i++) {
eea221ce
AN		 1004 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1005 struct sk_buff *skb =
1006 fdsystem != 0xffffffff ?
1007 lp->tx_skbs[fdsystem].skb : NULL;
1008#ifdef DEBUG
1009 if (lp->tx_skbs[i].skb != skb) {
1010 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1011 panic_queues(dev);
1012 }
1013#else
1014 BUG_ON(lp->tx_skbs[i].skb != skb);
1015#endif
1016 if (skb) {
1017 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1018 lp->tx_skbs[i].skb = NULL;
1019 lp->tx_skbs[i].skb_dma = 0;
1da177e4 1020 dev_kfree_skb_any(skb);
eea221ce
AN		 1021 }
1022 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4
LT		 1023 }
1024
1025 tc35815_init_queues(dev);
1026}
1027
1028static void
1029tc35815_free_queues(struct net_device *dev)
1030{
ee79b7fb 1031 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 1032 int i;
1033
1034 if (lp->tfd_base) {
1035 for (i = 0; i < TX_FD_NUM; i++) {
eea221ce
AN		 1036 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1037 struct sk_buff *skb =
1038 fdsystem != 0xffffffff ?
1039 lp->tx_skbs[fdsystem].skb : NULL;
1040#ifdef DEBUG
1041 if (lp->tx_skbs[i].skb != skb) {
1042 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1043 panic_queues(dev);
1044 }
1045#else
1046 BUG_ON(lp->tx_skbs[i].skb != skb);
1047#endif
1048 if (skb) {
1049 dev_kfree_skb(skb);
1050 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1051 lp->tx_skbs[i].skb = NULL;
1052 lp->tx_skbs[i].skb_dma = 0;
1053 }
1054 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4
LT		 1055 }
1056 }
1057
1da177e4
LT		 1058 lp->rfd_base = NULL;
1059 lp->rfd_limit = NULL;
1060 lp->rfd_cur = NULL;
1061 lp->fbl_ptr = NULL;
1062
eea221ce 1063 for (i = 0; i < RX_BUF_NUM; i++) {
eea221ce
AN		 1064 if (lp->rx_skbs[i].skb) {
1065 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1066 lp->rx_skbs[i].skb_dma);
1067 lp->rx_skbs[i].skb = NULL;
1068 }
eea221ce
AN		 1069 }
1070 if (lp->fd_buf) {
1071 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1072 lp->fd_buf, lp->fd_buf_dma);
1073 lp->fd_buf = NULL;
1da177e4 1074 }
1da177e4
LT		 1075}
1076
1077static void
1078dump_txfd(struct TxFD *fd)
1079{
1080 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1081 le32_to_cpu(fd->fd.FDNext),
1082 le32_to_cpu(fd->fd.FDSystem),
1083 le32_to_cpu(fd->fd.FDStat),
1084 le32_to_cpu(fd->fd.FDCtl));
1085 printk("BD: ");
1086 printk(" %08x %08x",
1087 le32_to_cpu(fd->bd.BuffData),
1088 le32_to_cpu(fd->bd.BDCtl));
1089 printk("\n");
1090}
1091
1092static int
1093dump_rxfd(struct RxFD *fd)
1094{
1095 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1096 if (bd_count > 8)
1097 bd_count = 8;
1098 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1099 le32_to_cpu(fd->fd.FDNext),
1100 le32_to_cpu(fd->fd.FDSystem),
1101 le32_to_cpu(fd->fd.FDStat),
1102 le32_to_cpu(fd->fd.FDCtl));
1103 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
7f225b42 1104 return 0;
1da177e4
LT		 1105 printk("BD: ");
1106 for (i = 0; i < bd_count; i++)
1107 printk(" %08x %08x",
1108 le32_to_cpu(fd->bd[i].BuffData),
1109 le32_to_cpu(fd->bd[i].BDCtl));
1110 printk("\n");
1111 return bd_count;
1112}
1113
a02b7b7a 1114#ifdef DEBUG
1da177e4
LT		 1115static void
1116dump_frfd(struct FrFD *fd)
1117{
1118 int i;
1119 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1120 le32_to_cpu(fd->fd.FDNext),
1121 le32_to_cpu(fd->fd.FDSystem),
1122 le32_to_cpu(fd->fd.FDStat),
1123 le32_to_cpu(fd->fd.FDCtl));
1124 printk("BD: ");
eea221ce 1125 for (i = 0; i < RX_BUF_NUM; i++)
1da177e4
LT		 1126 printk(" %08x %08x",
1127 le32_to_cpu(fd->bd[i].BuffData),
1128 le32_to_cpu(fd->bd[i].BDCtl));
1129 printk("\n");
1130}
1131
1132static void
1133panic_queues(struct net_device *dev)
1134{
ee79b7fb 1135 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 1136 int i;
1137
eea221ce 1138 printk("TxFD base %p, start %u, end %u\n",
1da177e4
LT		 1139 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1140 printk("RxFD base %p limit %p cur %p\n",
1141 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1142 printk("FrFD %p\n", lp->fbl_ptr);
1143 for (i = 0; i < TX_FD_NUM; i++)
1144 dump_txfd(&lp->tfd_base[i]);
1145 for (i = 0; i < RX_FD_NUM; i++) {
1146 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1147 i += (bd_count + 1) / 2; /* skip BDs */
1148 }
1149 dump_frfd(lp->fbl_ptr);
1150 panic("%s: Illegal queue state.", dev->name);
1151}
1da177e4
LT		 1152#endif
1153
958eb80b 1154static void print_eth(const u8 *add)
1da177e4 1155{
958eb80b 1156 printk(KERN_DEBUG "print_eth(%p)\n", add);
e174961c
JB		 1157 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1158 add + 6, add, add[12], add[13]);
1da177e4
LT		 1159}
1160
eea221ce
AN		 1161static int tc35815_tx_full(struct net_device *dev)
1162{
ee79b7fb 1163 struct tc35815_local *lp = netdev_priv(dev);
807540ba 1164 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
eea221ce
AN		 1165}
1166
1167static void tc35815_restart(struct net_device *dev)
1168{
ee79b7fb 1169 struct tc35815_local *lp = netdev_priv(dev);
01b0114e 1170 int ret;
eea221ce 1171
c6686fe3 1172 if (lp->phy_dev) {
01b0114e
FF		 1173 ret = phy_init_hw(lp->phy_dev);
1174 if (ret)
1175 printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
eea221ce
AN		 1176 }
1177
dee7399c 1178 spin_lock_bh(&lp->rx_lock);
c6686fe3 1179 spin_lock_irq(&lp->lock);
eea221ce
AN		 1180 tc35815_chip_reset(dev);
1181 tc35815_clear_queues(dev);
1182 tc35815_chip_init(dev);
1183 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1184 tc35815_set_multicast_list(dev);
c6686fe3 1185 spin_unlock_irq(&lp->lock);
dee7399c 1186 spin_unlock_bh(&lp->rx_lock);
c6686fe3
AN		 1187
1188 netif_wake_queue(dev);
eea221ce
AN		 1189}
1190
c6686fe3
AN		 1191static void tc35815_restart_work(struct work_struct *work)
1192{
1193 struct tc35815_local *lp =
1194 container_of(work, struct tc35815_local, restart_work);
1195 struct net_device *dev = lp->dev;
1196
1197 tc35815_restart(dev);
1198}
1199
1200static void tc35815_schedule_restart(struct net_device *dev)
eea221ce 1201{
ee79b7fb 1202 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 1203 struct tc35815_regs __iomem *tr =
1204 (struct tc35815_regs __iomem *)dev->base_addr;
dee7399c 1205 unsigned long flags;
eea221ce 1206
c6686fe3 1207 /* disable interrupts */
dee7399c 1208 spin_lock_irqsave(&lp->lock, flags);
c6686fe3
AN		 1209 tc_writel(0, &tr->Int_En);
1210 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1211 schedule_work(&lp->restart_work);
dee7399c 1212 spin_unlock_irqrestore(&lp->lock, flags);
c6686fe3
AN		 1213}
1214
1215static void tc35815_tx_timeout(struct net_device *dev)
1216{
1217 struct tc35815_regs __iomem *tr =
1218 (struct tc35815_regs __iomem *)dev->base_addr;
1219
eea221ce
AN		 1220 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1221 dev->name, tc_readl(&tr->Tx_Stat));
1222
1223 /* Try to restart the adaptor. */
c6686fe3 1224 tc35815_schedule_restart(dev);
c201abd9 1225 dev->stats.tx_errors++;
eea221ce
AN		 1226}
1227
1da177e4 1228/*
c6686fe3 1229 * Open/initialize the controller. This is called (in the current kernel)
1da177e4
LT		 1230 * sometime after booting when the 'ifconfig' program is run.
1231 *
1232 * This routine should set everything up anew at each open, even
1233 * registers that "should" only need to be set once at boot, so that
1234 * there is non-reboot way to recover if something goes wrong.
1235 */
1236static int
1237tc35815_open(struct net_device *dev)
1238{
ee79b7fb 1239 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1240
1da177e4
LT		 1241 /*
1242 * This is used if the interrupt line can turned off (shared).
1243 * See 3c503.c for an example of selecting the IRQ at config-time.
1244 */
a0607fd3 1245 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
7f225b42 1246 dev->name, dev))
1da177e4 1247 return -EAGAIN;
1da177e4
LT		 1248
1249 tc35815_chip_reset(dev);
1250
1251 if (tc35815_init_queues(dev) != 0) {
1252 free_irq(dev->irq, dev);
1253 return -EAGAIN;
1254 }
1255
bea3348e 1256 napi_enable(&lp->napi);
bea3348e 1257
1da177e4 1258 /* Reset the hardware here. Don't forget to set the station address. */
eea221ce 1259 spin_lock_irq(&lp->lock);
1da177e4 1260 tc35815_chip_init(dev);
eea221ce 1261 spin_unlock_irq(&lp->lock);
1da177e4 1262
59524a37 1263 netif_carrier_off(dev);
c6686fe3
AN		 1264 /* schedule a link state check */
1265 phy_start(lp->phy_dev);
1266
eea221ce
AN		 1267 /* We are now ready to accept transmit requeusts from
1268 * the queueing layer of the networking.
1269 */
1da177e4
LT		 1270 netif_start_queue(dev);
1271
1272 return 0;
1273}
1274
eea221ce
AN		 1275/* This will only be invoked if your driver is _not_ in XOFF state.
1276 * What this means is that you need not check it, and that this
1277 * invariant will hold if you make sure that the netif_*_queue()
1278 * calls are done at the proper times.
1279 */
1280static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1da177e4 1281{
ee79b7fb 1282 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1283 struct TxFD *txfd;
1da177e4
LT		 1284 unsigned long flags;
1285
eea221ce
AN		 1286 /* If some error occurs while trying to transmit this
1287 * packet, you should return '1' from this function.
1288 * In such a case you _may not_ do anything to the
1289 * SKB, it is still owned by the network queueing
1290 * layer when an error is returned. This means you
1291 * may not modify any SKB fields, you may not free
1292 * the SKB, etc.
1293 */
1294
1295 /* This is the most common case for modern hardware.
1296 * The spinlock protects this code from the TX complete
1297 * hardware interrupt handler. Queue flow control is
1298 * thus managed under this lock as well.
1299 */
1da177e4 1300 spin_lock_irqsave(&lp->lock, flags);
1da177e4 1301
eea221ce
AN		 1302 /* failsafe... (handle txdone now if half of FDs are used) */
1303 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1304 TX_FD_NUM / 2)
1305 tc35815_txdone(dev);
1306
1307 if (netif_msg_pktdata(lp))
1308 print_eth(skb->data);
1309#ifdef DEBUG
1310 if (lp->tx_skbs[lp->tfd_start].skb) {
1311 printk("%s: tx_skbs conflict.\n", dev->name);
1312 panic_queues(dev);
1da177e4 1313 }
eea221ce
AN		 1314#else
1315 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1da177e4 1316#endif
eea221ce
AN		 1317 lp->tx_skbs[lp->tfd_start].skb = skb;
1318 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1319
1320 /*add to ring */
1321 txfd = &lp->tfd_base[lp->tfd_start];
1322 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1323 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1324 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1325 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1326
1327 if (lp->tfd_start == lp->tfd_end) {
1328 struct tc35815_regs __iomem *tr =
1329 (struct tc35815_regs __iomem *)dev->base_addr;
1330 /* Start DMA Transmitter. */
1331 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
eea221ce 1332 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
eea221ce
AN		 1333 if (netif_msg_tx_queued(lp)) {
1334 printk("%s: starting TxFD.\n", dev->name);
1335 dump_txfd(txfd);
1336 }
1337 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1338 } else {
1339 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1340 if (netif_msg_tx_queued(lp)) {
1341 printk("%s: queueing TxFD.\n", dev->name);
1342 dump_txfd(txfd);
1da177e4 1343 }
eea221ce
AN		 1344 }
1345 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1da177e4 1346
eea221ce
AN		 1347 /* If we just used up the very last entry in the
1348 * TX ring on this device, tell the queueing
1349 * layer to send no more.
1350 */
1351 if (tc35815_tx_full(dev)) {
1352 if (netif_msg_tx_queued(lp))
1353 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1354 netif_stop_queue(dev);
1da177e4
LT		 1355 }
1356
eea221ce
AN		 1357 /* When the TX completion hw interrupt arrives, this
1358 * is when the transmit statistics are updated.
1359 */
1360
1361 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 1362 return NETDEV_TX_OK;
1da177e4
LT		 1363}
1364
1365#define FATAL_ERROR_INT \
1366 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
eea221ce 1367static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1da177e4
LT		 1368{
1369 static int count;
1370 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1371 dev->name, status);
1da177e4
LT		 1372 if (status & Int_IntPCI)
1373 printk(" IntPCI");
1374 if (status & Int_DmParErr)
1375 printk(" DmParErr");
1376 if (status & Int_IntNRAbt)
1377 printk(" IntNRAbt");
1378 printk("\n");
1379 if (count++ > 100)
1380 panic("%s: Too many fatal errors.", dev->name);
eea221ce 1381 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1da177e4 1382 /* Try to restart the adaptor. */
c6686fe3 1383 tc35815_schedule_restart(dev);
eea221ce
AN		 1384}
1385
eea221ce 1386static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
eea221ce 1387{
ee79b7fb 1388 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 1389 int ret = -1;
1390
1391 /* Fatal errors... */
1392 if (status & FATAL_ERROR_INT) {
1393 tc35815_fatal_error_interrupt(dev, status);
1394 return 0;
1395 }
1396 /* recoverable errors */
1397 if (status & Int_IntFDAEx) {
db30f5ef
AN		 1398 if (netif_msg_rx_err(lp))
1399 dev_warn(&dev->dev,
1400 "Free Descriptor Area Exhausted (%#x).\n",
1401 status);
c201abd9 1402 dev->stats.rx_dropped++;
eea221ce
AN		 1403 ret = 0;
1404 }
1405 if (status & Int_IntBLEx) {
db30f5ef
AN		 1406 if (netif_msg_rx_err(lp))
1407 dev_warn(&dev->dev,
1408 "Buffer List Exhausted (%#x).\n",
1409 status);
c201abd9 1410 dev->stats.rx_dropped++;
eea221ce
AN		 1411 ret = 0;
1412 }
1413 if (status & Int_IntExBD) {
db30f5ef
AN		 1414 if (netif_msg_rx_err(lp))
1415 dev_warn(&dev->dev,
1416 "Excessive Buffer Descriptiors (%#x).\n",
1417 status);
c201abd9 1418 dev->stats.rx_length_errors++;
eea221ce
AN		 1419 ret = 0;
1420 }
1421
1422 /* normal notification */
1423 if (status & Int_IntMacRx) {
1424 /* Got a packet(s). */
eea221ce 1425 ret = tc35815_rx(dev, limit);
eea221ce
AN		 1426 lp->lstats.rx_ints++;
1427 }
1428 if (status & Int_IntMacTx) {
1429 /* Transmit complete. */
1430 lp->lstats.tx_ints++;
dee7399c 1431 spin_lock_irq(&lp->lock);
eea221ce 1432 tc35815_txdone(dev);
dee7399c 1433 spin_unlock_irq(&lp->lock);
02c5c8ec
AN		 1434 if (ret < 0)
1435 ret = 0;
eea221ce
AN		 1436 }
1437 return ret;
1da177e4
LT		 1438}
1439
1440/*
1441 * The typical workload of the driver:
eea221ce 1442 * Handle the network interface interrupts.
1da177e4 1443 */
7d12e780 1444static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1da177e4
LT		 1445{
1446 struct net_device *dev = dev_id;
bea3348e 1447 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 1448 struct tc35815_regs __iomem *tr =
1449 (struct tc35815_regs __iomem *)dev->base_addr;
eea221ce
AN		 1450 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1451
1452 if (!(dmactl & DMA_IntMask)) {
1453 /* disable interrupts */
1454 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
288379f0
BH		 1455 if (napi_schedule_prep(&lp->napi))
1456 __napi_schedule(&lp->napi);
eea221ce
AN		 1457 else {
1458 printk(KERN_ERR "%s: interrupt taken in poll\n",
1459 dev->name);
1460 BUG();
1da177e4 1461 }
eea221ce
AN		 1462 (void)tc_readl(&tr->Int_Src); /* flush */
1463 return IRQ_HANDLED;
1464 }
1465 return IRQ_NONE;
eea221ce 1466}
1da177e4 1467
eea221ce
AN		 1468#ifdef CONFIG_NET_POLL_CONTROLLER
1469static void tc35815_poll_controller(struct net_device *dev)
1470{
1471 disable_irq(dev->irq);
1472 tc35815_interrupt(dev->irq, dev);
1473 enable_irq(dev->irq);
1da177e4 1474}
eea221ce 1475#endif
1da177e4
LT		 1476
1477/* We have a good packet(s), get it/them out of the buffers. */
eea221ce
AN		 1478static int
1479tc35815_rx(struct net_device *dev, int limit)
1da177e4 1480{
ee79b7fb 1481 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 1482 unsigned int fdctl;
1483 int i;
eea221ce 1484 int received = 0;
1da177e4
LT		 1485
1486 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1487 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1488 int pkt_len = fdctl & FD_FDLength_MASK;
1da177e4 1489 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
eea221ce
AN		 1490#ifdef DEBUG
1491 struct RxFD *next_rfd;
1492#endif
1493#if (RX_CTL_CMD & Rx_StripCRC) == 0
82a9928d 1494 pkt_len -= ETH_FCS_LEN;
eea221ce 1495#endif
1da177e4 1496
eea221ce 1497 if (netif_msg_rx_status(lp))
1da177e4
LT		 1498 dump_rxfd(lp->rfd_cur);
1499 if (status & Rx_Good) {
1da177e4
LT		 1500 struct sk_buff *skb;
1501 unsigned char *data;
eea221ce 1502 int cur_bd;
6aa20a22 1503
eea221ce
AN		 1504 if (--limit < 0)
1505 break;
eea221ce
AN		 1506 BUG_ON(bd_count > 1);
1507 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1508 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1509#ifdef DEBUG
1510 if (cur_bd >= RX_BUF_NUM) {
1511 printk("%s: invalid BDID.\n", dev->name);
1512 panic_queues(dev);
1513 }
1514 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1515 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1516 if (!lp->rx_skbs[cur_bd].skb) {
1517 printk("%s: NULL skb.\n", dev->name);
1518 panic_queues(dev);
1519 }
1520#else
1521 BUG_ON(cur_bd >= RX_BUF_NUM);
1da177e4 1522#endif
eea221ce
AN		 1523 skb = lp->rx_skbs[cur_bd].skb;
1524 prefetch(skb->data);
1525 lp->rx_skbs[cur_bd].skb = NULL;
eea221ce
AN		 1526 pci_unmap_single(lp->pci_dev,
1527 lp->rx_skbs[cur_bd].skb_dma,
1528 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
82a9928d
AN		 1529 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1530 memmove(skb->data, skb->data - NET_IP_ALIGN,
1531 pkt_len);
eea221ce 1532 data = skb_put(skb, pkt_len);
eea221ce 1533 if (netif_msg_pktdata(lp))
1da177e4
LT		 1534 print_eth(data);
1535 skb->protocol = eth_type_trans(skb, dev);
eea221ce
AN		 1536 netif_receive_skb(skb);
1537 received++;
c201abd9
AN		 1538 dev->stats.rx_packets++;
1539 dev->stats.rx_bytes += pkt_len;
1da177e4 1540 } else {
c201abd9 1541 dev->stats.rx_errors++;
db30f5ef
AN		 1542 if (netif_msg_rx_err(lp))
1543 dev_info(&dev->dev, "Rx error (status %x)\n",
1544 status & Rx_Stat_Mask);
1da177e4
LT		 1545 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1546 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1547 status &= ~(Rx_LongErr|Rx_CRCErr);
1548 status |= Rx_Over;
1549 }
c201abd9
AN		 1550 if (status & Rx_LongErr)
1551 dev->stats.rx_length_errors++;
1552 if (status & Rx_Over)
1553 dev->stats.rx_fifo_errors++;
1554 if (status & Rx_CRCErr)
1555 dev->stats.rx_crc_errors++;
1556 if (status & Rx_Align)
1557 dev->stats.rx_frame_errors++;
1da177e4
LT		 1558 }
1559
1560 if (bd_count > 0) {
1561 /* put Free Buffer back to controller */
1562 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1563 unsigned char id =
1564 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
eea221ce
AN		 1565#ifdef DEBUG
1566 if (id >= RX_BUF_NUM) {
1da177e4
LT		 1567 printk("%s: invalid BDID.\n", dev->name);
1568 panic_queues(dev);
1569 }
eea221ce
AN		 1570#else
1571 BUG_ON(id >= RX_BUF_NUM);
1572#endif
1da177e4 1573 /* free old buffers */
ccc57aac 1574 lp->fbl_count--;
eea221ce 1575 while (lp->fbl_count < RX_BUF_NUM)
eea221ce 1576 {
eea221ce
AN		 1577 unsigned char curid =
1578 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
eea221ce
AN		 1579 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1580#ifdef DEBUG
1581 bdctl = le32_to_cpu(bd->BDCtl);
1da177e4
LT		 1582 if (bdctl & BD_CownsBD) {
1583 printk("%s: Freeing invalid BD.\n",
1584 dev->name);
1585 panic_queues(dev);
1586 }
eea221ce 1587#endif
3a4fa0a2 1588 /* pass BD to controller */
eea221ce
AN		 1589 if (!lp->rx_skbs[curid].skb) {
1590 lp->rx_skbs[curid].skb =
1591 alloc_rxbuf_skb(dev,
1592 lp->pci_dev,
1593 &lp->rx_skbs[curid].skb_dma);
1594 if (!lp->rx_skbs[curid].skb)
1595 break; /* try on next reception */
1596 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1597 }
1da177e4 1598 /* Note: BDLength was modified by chip. */
eea221ce
AN		 1599 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1600 (curid << BD_RxBDID_SHIFT) |
1601 RX_BUF_SIZE);
eea221ce 1602 lp->fbl_count++;
1da177e4
LT		 1603 }
1604 }
1605
1606 /* put RxFD back to controller */
eea221ce
AN		 1607#ifdef DEBUG
1608 next_rfd = fd_bus_to_virt(lp,
1609 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1da177e4
LT		 1610 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1611 printk("%s: RxFD FDNext invalid.\n", dev->name);
1612 panic_queues(dev);
1613 }
eea221ce 1614#endif
1da177e4 1615 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
3a4fa0a2 1616 /* pass FD to controller */
eea221ce
AN		 1617#ifdef DEBUG
1618 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1619#else
1620 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1621#endif
1da177e4
LT		 1622 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1623 lp->rfd_cur++;
1da177e4 1624 }
eea221ce
AN		 1625 if (lp->rfd_cur > lp->rfd_limit)
1626 lp->rfd_cur = lp->rfd_base;
1627#ifdef DEBUG
1628 if (lp->rfd_cur != next_rfd)
1629 printk("rfd_cur = %p, next_rfd %p\n",
1630 lp->rfd_cur, next_rfd);
1631#endif
1da177e4
LT		 1632 }
1633
eea221ce 1634 return received;
1da177e4
LT		 1635}
1636
bea3348e 1637static int tc35815_poll(struct napi_struct *napi, int budget)
eea221ce 1638{
bea3348e
SH		 1639 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1640 struct net_device *dev = lp->dev;
eea221ce
AN		 1641 struct tc35815_regs __iomem *tr =
1642 (struct tc35815_regs __iomem *)dev->base_addr;
eea221ce
AN		 1643 int received = 0, handled;
1644 u32 status;
1645
176f792f
EB		 1646 if (budget <= 0)
1647 return received;
1648
dee7399c 1649 spin_lock(&lp->rx_lock);
eea221ce
AN		 1650 status = tc_readl(&tr->Int_Src);
1651 do {
db30f5ef
AN		 1652 /* BLEx, FDAEx will be cleared later */
1653 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1654 &tr->Int_Src); /* write to clear */
eea221ce 1655
a2c465db 1656 handled = tc35815_do_interrupt(dev, status, budget - received);
db30f5ef
AN		 1657 if (status & (Int_BLEx | Int_FDAEx))
1658 tc_writel(status & (Int_BLEx | Int_FDAEx),
1659 &tr->Int_Src);
eea221ce
AN		 1660 if (handled >= 0) {
1661 received += handled;
bea3348e 1662 if (received >= budget)
eea221ce
AN		 1663 break;
1664 }
1665 status = tc_readl(&tr->Int_Src);
1666 } while (status);
dee7399c 1667 spin_unlock(&lp->rx_lock);
eea221ce 1668
bea3348e 1669 if (received < budget) {
288379f0 1670 napi_complete(napi);
bea3348e
SH		 1671 /* enable interrupts */
1672 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1673 }
1674 return received;
eea221ce 1675}
eea221ce 1676
1da177e4 1677#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1da177e4
LT		 1678
1679static void
1680tc35815_check_tx_stat(struct net_device *dev, int status)
1681{
ee79b7fb 1682 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 1683 const char *msg = NULL;
1684
1685 /* count collisions */
1686 if (status & Tx_ExColl)
c201abd9 1687 dev->stats.collisions += 16;
1da177e4 1688 if (status & Tx_TxColl_MASK)
c201abd9 1689 dev->stats.collisions += status & Tx_TxColl_MASK;
1da177e4 1690
eea221ce 1691 /* TX4939 does not have NCarr */
c6686fe3 1692 if (lp->chiptype == TC35815_TX4939)
eea221ce 1693 status &= ~Tx_NCarr;
1da177e4 1694 /* WORKAROUND: ignore LostCrS in full duplex operation */
c6686fe3 1695 if (!lp->link || lp->duplex == DUPLEX_FULL)
1da177e4
LT		 1696 status &= ~Tx_NCarr;
1697
1698 if (!(status & TX_STA_ERR)) {
1699 /* no error. */
c201abd9 1700 dev->stats.tx_packets++;
1da177e4
LT		 1701 return;
1702 }
1703
c201abd9 1704 dev->stats.tx_errors++;
1da177e4 1705 if (status & Tx_ExColl) {
c201abd9 1706 dev->stats.tx_aborted_errors++;
1da177e4
LT		 1707 msg = "Excessive Collision.";
1708 }
1709 if (status & Tx_Under) {
c201abd9 1710 dev->stats.tx_fifo_errors++;
1da177e4 1711 msg = "Tx FIFO Underrun.";
eea221ce
AN		 1712 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1713 lp->lstats.tx_underrun++;
1714 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1715 struct tc35815_regs __iomem *tr =
1716 (struct tc35815_regs __iomem *)dev->base_addr;
1717 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1718 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1719 }
1720 }
1da177e4
LT		 1721 }
1722 if (status & Tx_Defer) {
c201abd9 1723 dev->stats.tx_fifo_errors++;
1da177e4
LT		 1724 msg = "Excessive Deferral.";
1725 }
1da177e4 1726 if (status & Tx_NCarr) {
c201abd9 1727 dev->stats.tx_carrier_errors++;
1da177e4
LT		 1728 msg = "Lost Carrier Sense.";
1729 }
1da177e4 1730 if (status & Tx_LateColl) {
c201abd9 1731 dev->stats.tx_aborted_errors++;
1da177e4
LT		 1732 msg = "Late Collision.";
1733 }
1734 if (status & Tx_TxPar) {
c201abd9 1735 dev->stats.tx_fifo_errors++;
1da177e4
LT		 1736 msg = "Transmit Parity Error.";
1737 }
1738 if (status & Tx_SQErr) {
c201abd9 1739 dev->stats.tx_heartbeat_errors++;
1da177e4
LT		 1740 msg = "Signal Quality Error.";
1741 }
eea221ce 1742 if (msg && netif_msg_tx_err(lp))
1da177e4
LT		 1743 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1744}
1745
eea221ce
AN		 1746/* This handles TX complete events posted by the device
1747 * via interrupts.
1748 */
1da177e4
LT		 1749static void
1750tc35815_txdone(struct net_device *dev)
1751{
ee79b7fb 1752 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT		 1753 struct TxFD *txfd;
1754 unsigned int fdctl;
1da177e4
LT		 1755
1756 txfd = &lp->tfd_base[lp->tfd_end];
1757 while (lp->tfd_start != lp->tfd_end &&
1758 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1759 int status = le32_to_cpu(txfd->fd.FDStat);
1760 struct sk_buff *skb;
1761 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
eea221ce 1762 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1da177e4 1763
eea221ce 1764 if (netif_msg_tx_done(lp)) {
1da177e4
LT		 1765 printk("%s: complete TxFD.\n", dev->name);
1766 dump_txfd(txfd);
1767 }
1768 tc35815_check_tx_stat(dev, status);
1769
eea221ce
AN		 1770 skb = fdsystem != 0xffffffff ?
1771 lp->tx_skbs[fdsystem].skb : NULL;
1772#ifdef DEBUG
1773 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1774 printk("%s: tx_skbs mismatch.\n", dev->name);
1775 panic_queues(dev);
1776 }
1777#else
1778 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1779#endif
1da177e4 1780 if (skb) {
c201abd9 1781 dev->stats.tx_bytes += skb->len;
eea221ce
AN		 1782 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1783 lp->tx_skbs[lp->tfd_end].skb = NULL;
1784 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1da177e4
LT		 1785 dev_kfree_skb_any(skb);
1786 }
eea221ce 1787 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4 1788
1da177e4
LT		 1789 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1790 txfd = &lp->tfd_base[lp->tfd_end];
eea221ce
AN		 1791#ifdef DEBUG
1792 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1da177e4
LT		 1793 printk("%s: TxFD FDNext invalid.\n", dev->name);
1794 panic_queues(dev);
1795 }
eea221ce 1796#endif
1da177e4
LT		 1797 if (fdnext & FD_Next_EOL) {
1798 /* DMA Transmitter has been stopping... */
1799 if (lp->tfd_end != lp->tfd_start) {
eea221ce
AN		 1800 struct tc35815_regs __iomem *tr =
1801 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4 1802 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
7f225b42 1803 struct TxFD *txhead = &lp->tfd_base[head];
1da177e4
LT		 1804 int qlen = (lp->tfd_start + TX_FD_NUM
1805 - lp->tfd_end) % TX_FD_NUM;
1806
eea221ce 1807#ifdef DEBUG
1da177e4
LT		 1808 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1809 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1810 panic_queues(dev);
1811 }
eea221ce 1812#endif
1da177e4
LT		 1813 /* log max queue length */
1814 if (lp->lstats.max_tx_qlen < qlen)
1815 lp->lstats.max_tx_qlen = qlen;
1816
1817
1818 /* start DMA Transmitter again */
1819 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1da177e4 1820 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
eea221ce 1821 if (netif_msg_tx_queued(lp)) {
1da177e4
LT		 1822 printk("%s: start TxFD on queue.\n",
1823 dev->name);
1824 dump_txfd(txfd);
1825 }
eea221ce 1826 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1da177e4
LT		 1827 }
1828 break;
1829 }
1830 }
1831
eea221ce
AN		 1832 /* If we had stopped the queue due to a "tx full"
1833 * condition, and space has now been made available,
1834 * wake up the queue.
1835 */
7f225b42 1836 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
eea221ce 1837 netif_wake_queue(dev);
1da177e4
LT		 1838}
1839
1840/* The inverse routine to tc35815_open(). */
1841static int
1842tc35815_close(struct net_device *dev)
1843{
ee79b7fb 1844 struct tc35815_local *lp = netdev_priv(dev);
bea3348e 1845
1da177e4 1846 netif_stop_queue(dev);
bea3348e 1847 napi_disable(&lp->napi);
c6686fe3
AN		 1848 if (lp->phy_dev)
1849 phy_stop(lp->phy_dev);
1850 cancel_work_sync(&lp->restart_work);
1da177e4
LT		 1851
1852 /* Flush the Tx and disable Rx here. */
1da177e4
LT		 1853 tc35815_chip_reset(dev);
1854 free_irq(dev->irq, dev);
1855
1856 tc35815_free_queues(dev);
1857
1858 return 0;
eea221ce 1859
1da177e4
LT		 1860}
1861
1862/*
1863 * Get the current statistics.
1864 * This may be called with the card open or closed.
1865 */
1866static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1867{
eea221ce
AN		 1868 struct tc35815_regs __iomem *tr =
1869 (struct tc35815_regs __iomem *)dev->base_addr;
c201abd9 1870 if (netif_running(dev))
1da177e4 1871 /* Update the statistics from the device registers. */
7bb82e83 1872 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1da177e4 1873
c201abd9 1874 return &dev->stats;
1da177e4
LT		 1875}
1876
eea221ce 1877static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1da177e4 1878{
ee79b7fb 1879 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 1880 struct tc35815_regs __iomem *tr =
1881 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4 1882 int cam_index = index * 6;
eea221ce
AN		 1883 u32 cam_data;
1884 u32 saved_addr;
958eb80b 1885
1da177e4
LT		 1886 saved_addr = tc_readl(&tr->CAM_Adr);
1887
958eb80b 1888 if (netif_msg_hw(lp))
e174961c
JB		 1889 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1890 dev->name, index, addr);
1da177e4
LT		 1891 if (index & 1) {
1892 /* read modify write */
1893 tc_writel(cam_index - 2, &tr->CAM_Adr);
1894 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1895 cam_data |= addr[0] << 8 | addr[1];
1896 tc_writel(cam_data, &tr->CAM_Data);
1897 /* write whole word */
1898 tc_writel(cam_index + 2, &tr->CAM_Adr);
1899 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1900 tc_writel(cam_data, &tr->CAM_Data);
1901 } else {
1902 /* write whole word */
1903 tc_writel(cam_index, &tr->CAM_Adr);
1904 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1905 tc_writel(cam_data, &tr->CAM_Data);
1906 /* read modify write */
1907 tc_writel(cam_index + 4, &tr->CAM_Adr);
1908 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1909 cam_data |= addr[4] << 24 | (addr[5] << 16);
1910 tc_writel(cam_data, &tr->CAM_Data);
1911 }
1912
1da177e4
LT		 1913 tc_writel(saved_addr, &tr->CAM_Adr);
1914}
1915
1916
1917/*
1918 * Set or clear the multicast filter for this adaptor.
1919 * num_addrs == -1 Promiscuous mode, receive all packets
1920 * num_addrs == 0 Normal mode, clear multicast list
1921 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1922 * and do best-effort filtering.
1923 */
1924static void
1925tc35815_set_multicast_list(struct net_device *dev)
1926{
eea221ce
AN		 1927 struct tc35815_regs __iomem *tr =
1928 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4 1929
7f225b42 1930 if (dev->flags & IFF_PROMISC) {
eea221ce
AN		 1931 /* With some (all?) 100MHalf HUB, controller will hang
1932 * if we enabled promiscuous mode before linkup... */
ee79b7fb 1933 struct tc35815_local *lp = netdev_priv(dev);
c6686fe3
AN		 1934
1935 if (!lp->link)
eea221ce 1936 return;
1da177e4
LT		 1937 /* Enable promiscuous mode */
1938 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
7f225b42 1939 } else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 1940 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1da177e4
LT		 1941 /* CAM 0, 1, 20 are reserved. */
1942 /* Disable promiscuous mode, use normal mode. */
1943 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
4cd24eaf 1944 } else if (!netdev_mc_empty(dev)) {
22bedad3 1945 struct netdev_hw_addr *ha;
1da177e4
LT		 1946 int i;
1947 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1948
1949 tc_writel(0, &tr->CAM_Ctl);
1950 /* Walk the address list, and load the filter */
567ec874 1951 i = 0;
22bedad3 1952 netdev_for_each_mc_addr(ha, dev) {
1da177e4 1953 /* entry 0,1 is reserved. */
22bedad3 1954 tc35815_set_cam_entry(dev, i + 2, ha->addr);
1da177e4 1955 ena_bits |= CAM_Ena_Bit(i + 2);
567ec874 1956 i++;
1da177e4
LT		 1957 }
1958 tc_writel(ena_bits, &tr->CAM_Ena);
1959 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
7f225b42 1960 } else {
1da177e4
LT		 1961 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1962 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1963 }
1964}
1965
eea221ce 1966static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1da177e4 1967{
ee79b7fb 1968 struct tc35815_local *lp = netdev_priv(dev);
7826d43f
JP		 1969
1970 strlcpy(info->driver, MODNAME, sizeof(info->driver));
1971 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1972 strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
eea221ce 1973}
6aa20a22 1974
eea221ce
AN		 1975static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1976{
ee79b7fb 1977 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1978
c6686fe3
AN		 1979 if (!lp->phy_dev)
1980 return -ENODEV;
1981 return phy_ethtool_gset(lp->phy_dev, cmd);
eea221ce
AN		 1982}
1983
c6686fe3 1984static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
eea221ce 1985{
ee79b7fb 1986 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1987
c6686fe3
AN		 1988 if (!lp->phy_dev)
1989 return -ENODEV;
1990 return phy_ethtool_sset(lp->phy_dev, cmd);
eea221ce
AN		 1991}
1992
1993static u32 tc35815_get_msglevel(struct net_device *dev)
1994{
ee79b7fb 1995 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 1996 return lp->msg_enable;
1997}
1998
1999static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2000{
ee79b7fb 2001 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 2002 lp->msg_enable = datum;
2003}
2004
b9f2c044 2005static int tc35815_get_sset_count(struct net_device *dev, int sset)
eea221ce 2006{
ee79b7fb 2007 struct tc35815_local *lp = netdev_priv(dev);
b9f2c044
JG		 2008
2009 switch (sset) {
2010 case ETH_SS_STATS:
2011 return sizeof(lp->lstats) / sizeof(int);
2012 default:
2013 return -EOPNOTSUPP;
2014 }
eea221ce 2015}
1da177e4 2016
eea221ce
AN		 2017static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2018{
ee79b7fb 2019 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 2020 data[0] = lp->lstats.max_tx_qlen;
2021 data[1] = lp->lstats.tx_ints;
2022 data[2] = lp->lstats.rx_ints;
2023 data[3] = lp->lstats.tx_underrun;
2024}
2025
2026static struct {
2027 const char str[ETH_GSTRING_LEN];
2028} ethtool_stats_keys[] = {
2029 { "max_tx_qlen" },
2030 { "tx_ints" },
2031 { "rx_ints" },
2032 { "tx_underrun" },
2033};
2034
2035static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2036{
2037 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2038}
2039
2040static const struct ethtool_ops tc35815_ethtool_ops = {
2041 .get_drvinfo = tc35815_get_drvinfo,
2042 .get_settings = tc35815_get_settings,
2043 .set_settings = tc35815_set_settings,
c6686fe3 2044 .get_link = ethtool_op_get_link,
eea221ce
AN		 2045 .get_msglevel = tc35815_get_msglevel,
2046 .set_msglevel = tc35815_set_msglevel,
2047 .get_strings = tc35815_get_strings,
b9f2c044 2048 .get_sset_count = tc35815_get_sset_count,
eea221ce 2049 .get_ethtool_stats = tc35815_get_ethtool_stats,
eea221ce
AN		 2050};
2051
2052static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2053{
ee79b7fb 2054 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 2055
2056 if (!netif_running(dev))
2057 return -EINVAL;
c6686fe3
AN		 2058 if (!lp->phy_dev)
2059 return -ENODEV;
28b04113 2060 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
eea221ce
AN		 2061}
2062
2063static void tc35815_chip_reset(struct net_device *dev)
2064{
2065 struct tc35815_regs __iomem *tr =
2066 (struct tc35815_regs __iomem *)dev->base_addr;
2067 int i;
1da177e4
LT		 2068 /* reset the controller */
2069 tc_writel(MAC_Reset, &tr->MAC_Ctl);
eea221ce
AN		 2070 udelay(4); /* 3200ns */
2071 i = 0;
2072 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2073 if (i++ > 100) {
2074 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2075 break;
2076 }
2077 mdelay(1);
2078 }
1da177e4
LT		 2079 tc_writel(0, &tr->MAC_Ctl);
2080
2081 /* initialize registers to default value */
2082 tc_writel(0, &tr->DMA_Ctl);
2083 tc_writel(0, &tr->TxThrsh);
2084 tc_writel(0, &tr->TxPollCtr);
2085 tc_writel(0, &tr->RxFragSize);
2086 tc_writel(0, &tr->Int_En);
2087 tc_writel(0, &tr->FDA_Bas);
2088 tc_writel(0, &tr->FDA_Lim);
2089 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2090 tc_writel(0, &tr->CAM_Ctl);
2091 tc_writel(0, &tr->Tx_Ctl);
2092 tc_writel(0, &tr->Rx_Ctl);
2093 tc_writel(0, &tr->CAM_Ena);
2094 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2095
eea221ce
AN		 2096 /* initialize internal SRAM */
2097 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2098 for (i = 0; i < 0x1000; i += 4) {
2099 tc_writel(i, &tr->CAM_Adr);
2100 tc_writel(0, &tr->CAM_Data);
2101 }
2102 tc_writel(0, &tr->DMA_Ctl);
1da177e4
LT		 2103}
2104
2105static void tc35815_chip_init(struct net_device *dev)
2106{
ee79b7fb 2107 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 2108 struct tc35815_regs __iomem *tr =
2109 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4
LT		 2110 unsigned long txctl = TX_CTL_CMD;
2111
1da177e4 2112 /* load station address to CAM */
eea221ce 2113 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
1da177e4
LT		 2114
2115 /* Enable CAM (broadcast and unicast) */
2116 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2117 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2118
eea221ce
AN		 2119 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2120 if (HAVE_DMA_RXALIGN(lp))
2121 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2122 else
2123 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
1da177e4
LT		 2124 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2125 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2126 tc_writel(INT_EN_CMD, &tr->Int_En);
2127
2128 /* set queues */
eea221ce 2129 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
1da177e4
LT		 2130 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2131 &tr->FDA_Lim);
2132 /*
2133 * Activation method:
eea221ce 2134 * First, enable the MAC Transmitter and the DMA Receive circuits.
1da177e4
LT		 2135 * Then enable the DMA Transmitter and the MAC Receive circuits.
2136 */
eea221ce 2137 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
1da177e4 2138 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
eea221ce 2139
1da177e4 2140 /* start MAC transmitter */
eea221ce 2141 /* TX4939 does not have EnLCarr */
c6686fe3 2142 if (lp->chiptype == TC35815_TX4939)
eea221ce 2143 txctl &= ~Tx_EnLCarr;
1da177e4 2144 /* WORKAROUND: ignore LostCrS in full duplex operation */
c6686fe3 2145 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
eea221ce 2146 txctl &= ~Tx_EnLCarr;
1da177e4 2147 tc_writel(txctl, &tr->Tx_Ctl);
eea221ce
AN		 2148}
2149
2150#ifdef CONFIG_PM
2151static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2152{
2153 struct net_device *dev = pci_get_drvdata(pdev);
ee79b7fb 2154 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 2155 unsigned long flags;
2156
2157 pci_save_state(pdev);
2158 if (!netif_running(dev))
2159 return 0;
2160 netif_device_detach(dev);
c6686fe3
AN		 2161 if (lp->phy_dev)
2162 phy_stop(lp->phy_dev);
eea221ce 2163 spin_lock_irqsave(&lp->lock, flags);
eea221ce 2164 tc35815_chip_reset(dev);
1da177e4 2165 spin_unlock_irqrestore(&lp->lock, flags);
eea221ce
AN		 2166 pci_set_power_state(pdev, PCI_D3hot);
2167 return 0;
1da177e4
LT		 2168}
2169
eea221ce
AN		 2170static int tc35815_resume(struct pci_dev *pdev)
2171{
2172 struct net_device *dev = pci_get_drvdata(pdev);
ee79b7fb 2173 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN		 2174
2175 pci_restore_state(pdev);
2176 if (!netif_running(dev))
2177 return 0;
2178 pci_set_power_state(pdev, PCI_D0);
eea221ce 2179 tc35815_restart(dev);
59524a37 2180 netif_carrier_off(dev);
c6686fe3
AN		 2181 if (lp->phy_dev)
2182 phy_start(lp->phy_dev);
eea221ce
AN		 2183 netif_device_attach(dev);
2184 return 0;
2185}
2186#endif /* CONFIG_PM */
2187
2188static struct pci_driver tc35815_pci_driver = {
2189 .name = MODNAME,
2190 .id_table = tc35815_pci_tbl,
2191 .probe = tc35815_init_one,
b38d1306 2192 .remove = tc35815_remove_one,
eea221ce
AN		 2193#ifdef CONFIG_PM
2194 .suspend = tc35815_suspend,
2195 .resume = tc35815_resume,
2196#endif
1da177e4
LT		 2197};
2198
eea221ce
AN		 2199module_param_named(speed, options.speed, int, 0);
2200MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2201module_param_named(duplex, options.duplex, int, 0);
2202MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
eea221ce 2203
b6f57210 2204module_pci_driver(tc35815_pci_driver);
eea221ce
AN		 2205MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2206MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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