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net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*
[deliverable/linux.git] / drivers / net / ethernet / xilinx / ll_temac_main.c
CommitLineData
92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/init.h>
33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
9f1a1fca 41#include <linux/of_address.h>
92744989
GL		 42#include <linux/skbuff.h>
43#include <linux/spinlock.h>
44#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45#include <linux/udp.h> /* needed for sizeof(udphdr) */
46#include <linux/phy.h>
47#include <linux/in.h>
48#include <linux/io.h>
49#include <linux/ip.h>
5a0e3ad6 50#include <linux/slab.h>
ffbc03bc 51#include <linux/interrupt.h>
84cac398 52#include <linux/dma-mapping.h>
92744989
GL		 53
54#include "ll_temac.h"
55
56#define TX_BD_NUM 64
57#define RX_BD_NUM 128
58
59/* ---------------------------------------------------------------------
60 * Low level register access functions
61 */
62
63u32 temac_ior(struct temac_local *lp, int offset)
64{
65 return in_be32((u32 *)(lp->regs + offset));
66}
67
68void temac_iow(struct temac_local *lp, int offset, u32 value)
69{
70 out_be32((u32 *) (lp->regs + offset), value);
71}
72
73int temac_indirect_busywait(struct temac_local *lp)
74{
75 long end = jiffies + 2;
76
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
79 WARN_ON(1);
80 return -ETIMEDOUT;
81 }
82 msleep(1);
83 }
84 return 0;
85}
86
87/**
88 * temac_indirect_in32
89 *
90 * lp->indirect_mutex must be held when calling this function
91 */
92u32 temac_indirect_in32(struct temac_local *lp, int reg)
93{
94 u32 val;
95
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
100 return -ETIMEDOUT;
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
102
103 return val;
104}
105
106/**
107 * temac_indirect_out32
108 *
109 * lp->indirect_mutex must be held when calling this function
110 */
111void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112{
113 if (temac_indirect_busywait(lp))
114 return;
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
f79d7e6f 117 temac_indirect_busywait(lp);
92744989
GL		 118}
119
e44171f1
JL		 120/**
121 * temac_dma_in32 - Memory mapped DMA read, this function expects a
122 * register input that is based on DCR word addresses which
123 * are then converted to memory mapped byte addresses
124 */
92744989
GL		 125static u32 temac_dma_in32(struct temac_local *lp, int reg)
126{
e44171f1 127 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
92744989
GL		 128}
129
e44171f1
JL		 130/**
131 * temac_dma_out32 - Memory mapped DMA read, this function expects a
132 * register input that is based on DCR word addresses which
133 * are then converted to memory mapped byte addresses
134 */
92744989 135static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
e44171f1
JL		 136{
137 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
138}
139
140/* DMA register access functions can be DCR based or memory mapped.
141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
142 * memory mapped.
143 */
144#ifdef CONFIG_PPC_DCR
145
146/**
147 * temac_dma_dcr_in32 - DCR based DMA read
148 */
149static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
150{
151 return dcr_read(lp->sdma_dcrs, reg);
152}
153
154/**
155 * temac_dma_dcr_out32 - DCR based DMA write
156 */
157static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 158{
159 dcr_write(lp->sdma_dcrs, reg, value);
160}
161
e44171f1
JL		 162/**
163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
164 * I/O functions
165 */
2dc11581 166static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 167 struct device_node *np)
168{
169 unsigned int dcrs;
170
171 /* setup the dcr address mapping if it's in the device tree */
172
173 dcrs = dcr_resource_start(np, 0);
174 if (dcrs != 0) {
175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176 lp->dma_in = temac_dma_dcr_in;
177 lp->dma_out = temac_dma_dcr_out;
178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
179 return 0;
180 }
181 /* no DCR in the device tree, indicate a failure */
182 return -1;
183}
184
185#else
186
187/*
188 * temac_dcr_setup - This is a stub for when DCR is not supported,
189 * such as with MicroBlaze
190 */
2dc11581 191static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 192 struct device_node *np)
193{
194 return -1;
195}
196
197#endif
198
301e9d96 199/**
49ce9c2c 200 * temac_dma_bd_release - Release buffer descriptor rings
301e9d96
DK		 201 */
202static void temac_dma_bd_release(struct net_device *ndev)
203{
204 struct temac_local *lp = netdev_priv(ndev);
205 int i;
206
50ec1538
RR		 207 /* Reset Local Link (DMA) */
208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
209
301e9d96
DK		 210 for (i = 0; i < RX_BD_NUM; i++) {
211 if (!lp->rx_skb[i])
212 break;
213 else {
214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216 dev_kfree_skb(lp->rx_skb[i]);
217 }
218 }
219 if (lp->rx_bd_v)
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 lp->rx_bd_v, lp->rx_bd_p);
223 if (lp->tx_bd_v)
224 dma_free_coherent(ndev->dev.parent,
225 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226 lp->tx_bd_v, lp->tx_bd_p);
227 if (lp->rx_skb)
228 kfree(lp->rx_skb);
229}
230
92744989
GL		 231/**
232 * temac_dma_bd_init - Setup buffer descriptor rings
233 */
234static int temac_dma_bd_init(struct net_device *ndev)
235{
236 struct temac_local *lp = netdev_priv(ndev);
237 struct sk_buff *skb;
238 int i;
239
ddf98e6d 240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
b2adaca9 241 if (!lp->rx_skb)
fe62c298 242 goto out;
b2adaca9 243
92744989 244 /* allocate the tx and rx ring buffer descriptors. */
b595076a 245 /* returns a virtual address and a physical address. */
92744989
GL		 246 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
247 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
1f9061d2 248 &lp->tx_bd_p, GFP_KERNEL | __GFP_ZERO);
d0320f75 249 if (!lp->tx_bd_v)
fe62c298 250 goto out;
d0320f75 251
92744989
GL		 252 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
253 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
1f9061d2 254 &lp->rx_bd_p, GFP_KERNEL | __GFP_ZERO);
d0320f75 255 if (!lp->rx_bd_v)
fe62c298 256 goto out;
92744989 257
92744989
GL		 258 for (i = 0; i < TX_BD_NUM; i++) {
259 lp->tx_bd_v[i].next = lp->tx_bd_p +
260 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
261 }
262
92744989
GL		 263 for (i = 0; i < RX_BD_NUM; i++) {
264 lp->rx_bd_v[i].next = lp->rx_bd_p +
265 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
266
e44171f1
JL		 267 skb = netdev_alloc_skb_ip_align(ndev,
268 XTE_MAX_JUMBO_FRAME_SIZE);
720a43ef 269 if (!skb)
fe62c298 270 goto out;
720a43ef 271
92744989 272 lp->rx_skb[i] = skb;
92744989
GL		 273 /* returns physical address of skb->data */
274 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
275 skb->data,
276 XTE_MAX_JUMBO_FRAME_SIZE,
277 DMA_FROM_DEVICE);
278 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
279 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
280 }
281
e44171f1 282 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
92744989
GL		 283 CHNL_CTRL_IRQ_EN |
284 CHNL_CTRL_IRQ_DLY_EN |
285 CHNL_CTRL_IRQ_COAL_EN);
286 /* 0x10220483 */
287 /* 0x00100483 */
23ecc4bd 288 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
92744989
GL		 289 CHNL_CTRL_IRQ_EN |
290 CHNL_CTRL_IRQ_DLY_EN |
291 CHNL_CTRL_IRQ_COAL_EN |
292 CHNL_CTRL_IRQ_IOE);
293 /* 0xff010283 */
294
e44171f1
JL		 295 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
296 lp->dma_out(lp, RX_TAILDESC_PTR,
92744989 297 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
e44171f1 298 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
92744989
GL		 299
300 return 0;
fe62c298
DK		 301
302out:
301e9d96 303 temac_dma_bd_release(ndev);
fe62c298 304 return -ENOMEM;
92744989
GL		 305}
306
307/* ---------------------------------------------------------------------
308 * net_device_ops
309 */
310
04e406dc 311static void temac_do_set_mac_address(struct net_device *ndev)
92744989
GL		 312{
313 struct temac_local *lp = netdev_priv(ndev);
314
92744989
GL		 315 /* set up unicast MAC address filter set its mac address */
316 mutex_lock(&lp->indirect_mutex);
317 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
318 (ndev->dev_addr[0]) |
319 (ndev->dev_addr[1] << 8) |
320 (ndev->dev_addr[2] << 16) |
321 (ndev->dev_addr[3] << 24));
322 /* There are reserved bits in EUAW1
323 * so don't affect them Set MAC bits [47:32] in EUAW1 */
324 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
325 (ndev->dev_addr[4] & 0x000000ff) |
326 (ndev->dev_addr[5] << 8));
327 mutex_unlock(&lp->indirect_mutex);
04e406dc 328}
92744989 329
04e406dc
JP		 330static int temac_init_mac_address(struct net_device *ndev, void *address)
331{
332 memcpy(ndev->dev_addr, address, ETH_ALEN);
333 if (!is_valid_ether_addr(ndev->dev_addr))
334 eth_hw_addr_random(ndev);
335 temac_do_set_mac_address(ndev);
92744989
GL		 336 return 0;
337}
338
04e406dc 339static int temac_set_mac_address(struct net_device *ndev, void *p)
8ea7a37c
SM		 340{
341 struct sockaddr *addr = p;
342
04e406dc
JP		 343 if (!is_valid_ether_addr(addr->sa_data))
344 return -EADDRNOTAVAIL;
345 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
346 temac_do_set_mac_address(ndev);
347 return 0;
8ea7a37c
SM		 348}
349
92744989
GL		 350static void temac_set_multicast_list(struct net_device *ndev)
351{
352 struct temac_local *lp = netdev_priv(ndev);
353 u32 multi_addr_msw, multi_addr_lsw, val;
354 int i;
355
356 mutex_lock(&lp->indirect_mutex);
8e95a202 357 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 358 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 359 /*
360 * We must make the kernel realise we had to move
361 * into promisc mode or we start all out war on
362 * the cable. If it was a promisc request the
363 * flag is already set. If not we assert it.
364 */
365 ndev->flags |= IFF_PROMISC;
366 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
367 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 368 } else if (!netdev_mc_empty(ndev)) {
22bedad3 369 struct netdev_hw_addr *ha;
92744989 370
f9dcbcc9 371 i = 0;
22bedad3 372 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 373 if (i >= MULTICAST_CAM_TABLE_NUM)
374 break;
22bedad3
JP		 375 multi_addr_msw = ((ha->addr[3] << 24) |
376 (ha->addr[2] << 16) |
377 (ha->addr[1] << 8) |
378 (ha->addr[0]));
92744989
GL		 379 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
380 multi_addr_msw);
22bedad3
JP		 381 multi_addr_lsw = ((ha->addr[5] << 8) |
382 (ha->addr[4]) | (i << 16));
92744989
GL		 383 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
384 multi_addr_lsw);
f9dcbcc9 385 i++;
92744989
GL		 386 }
387 } else {
388 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
389 temac_indirect_out32(lp, XTE_AFM_OFFSET,
390 val & ~XTE_AFM_EPPRM_MASK);
391 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
392 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
393 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
394 }
395 mutex_unlock(&lp->indirect_mutex);
396}
397
398struct temac_option {
399 int flg;
400 u32 opt;
401 u32 reg;
402 u32 m_or;
403 u32 m_and;
404} temac_options[] = {
405 /* Turn on jumbo packet support for both Rx and Tx */
406 {
407 .opt = XTE_OPTION_JUMBO,
408 .reg = XTE_TXC_OFFSET,
409 .m_or = XTE_TXC_TXJMBO_MASK,
410 },
411 {
412 .opt = XTE_OPTION_JUMBO,
413 .reg = XTE_RXC1_OFFSET,
414 .m_or =XTE_RXC1_RXJMBO_MASK,
415 },
416 /* Turn on VLAN packet support for both Rx and Tx */
417 {
418 .opt = XTE_OPTION_VLAN,
419 .reg = XTE_TXC_OFFSET,
420 .m_or =XTE_TXC_TXVLAN_MASK,
421 },
422 {
423 .opt = XTE_OPTION_VLAN,
424 .reg = XTE_RXC1_OFFSET,
425 .m_or =XTE_RXC1_RXVLAN_MASK,
426 },
427 /* Turn on FCS stripping on receive packets */
428 {
429 .opt = XTE_OPTION_FCS_STRIP,
430 .reg = XTE_RXC1_OFFSET,
431 .m_or =XTE_RXC1_RXFCS_MASK,
432 },
433 /* Turn on FCS insertion on transmit packets */
434 {
435 .opt = XTE_OPTION_FCS_INSERT,
436 .reg = XTE_TXC_OFFSET,
437 .m_or =XTE_TXC_TXFCS_MASK,
438 },
439 /* Turn on length/type field checking on receive packets */
440 {
441 .opt = XTE_OPTION_LENTYPE_ERR,
442 .reg = XTE_RXC1_OFFSET,
443 .m_or =XTE_RXC1_RXLT_MASK,
444 },
445 /* Turn on flow control */
446 {
447 .opt = XTE_OPTION_FLOW_CONTROL,
448 .reg = XTE_FCC_OFFSET,
449 .m_or =XTE_FCC_RXFLO_MASK,
450 },
451 /* Turn on flow control */
452 {
453 .opt = XTE_OPTION_FLOW_CONTROL,
454 .reg = XTE_FCC_OFFSET,
455 .m_or =XTE_FCC_TXFLO_MASK,
456 },
457 /* Turn on promiscuous frame filtering (all frames are received ) */
458 {
459 .opt = XTE_OPTION_PROMISC,
460 .reg = XTE_AFM_OFFSET,
461 .m_or =XTE_AFM_EPPRM_MASK,
462 },
463 /* Enable transmitter if not already enabled */
464 {
465 .opt = XTE_OPTION_TXEN,
466 .reg = XTE_TXC_OFFSET,
467 .m_or =XTE_TXC_TXEN_MASK,
468 },
469 /* Enable receiver? */
470 {
471 .opt = XTE_OPTION_RXEN,
472 .reg = XTE_RXC1_OFFSET,
473 .m_or =XTE_RXC1_RXEN_MASK,
474 },
475 {}
476};
477
478/**
479 * temac_setoptions
480 */
481static u32 temac_setoptions(struct net_device *ndev, u32 options)
482{
483 struct temac_local *lp = netdev_priv(ndev);
484 struct temac_option *tp = &temac_options[0];
485 int reg;
486
487 mutex_lock(&lp->indirect_mutex);
488 while (tp->opt) {
489 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
490 if (options & tp->opt)
491 reg |= tp->m_or;
492 temac_indirect_out32(lp, tp->reg, reg);
493 tp++;
494 }
495 lp->options |= options;
496 mutex_unlock(&lp->indirect_mutex);
497
807540ba 498 return 0;
92744989
GL		 499}
500
421f91d2 501/* Initialize temac */
92744989
GL		 502static void temac_device_reset(struct net_device *ndev)
503{
504 struct temac_local *lp = netdev_priv(ndev);
505 u32 timeout;
506 u32 val;
507
508 /* Perform a software reset */
509
510 /* 0x300 host enable bit ? */
511 /* reset PHY through control register ?:1 */
512
513 dev_dbg(&ndev->dev, "%s()\n", __func__);
514
515 mutex_lock(&lp->indirect_mutex);
516 /* Reset the receiver and wait for it to finish reset */
517 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
518 timeout = 1000;
519 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
520 udelay(1);
521 if (--timeout == 0) {
522 dev_err(&ndev->dev,
523 "temac_device_reset RX reset timeout!!\n");
524 break;
525 }
526 }
527
528 /* Reset the transmitter and wait for it to finish reset */
529 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
530 timeout = 1000;
531 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
532 udelay(1);
533 if (--timeout == 0) {
534 dev_err(&ndev->dev,
535 "temac_device_reset TX reset timeout!!\n");
536 break;
537 }
538 }
539
540 /* Disable the receiver */
541 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
542 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
543
544 /* Reset Local Link (DMA) */
e44171f1 545 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 546 timeout = 1000;
e44171f1 547 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 548 udelay(1);
549 if (--timeout == 0) {
550 dev_err(&ndev->dev,
551 "temac_device_reset DMA reset timeout!!\n");
552 break;
553 }
554 }
e44171f1 555 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 556
fe62c298
DK		 557 if (temac_dma_bd_init(ndev)) {
558 dev_err(&ndev->dev,
559 "temac_device_reset descriptor allocation failed\n");
560 }
92744989
GL		 561
562 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
563 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
564 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
565 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
566
567 mutex_unlock(&lp->indirect_mutex);
568
569 /* Sync default options with HW
570 * but leave receiver and transmitter disabled. */
571 temac_setoptions(ndev,
572 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
573
04e406dc 574 temac_do_set_mac_address(ndev);
92744989
GL		 575
576 /* Set address filter table */
577 temac_set_multicast_list(ndev);
578 if (temac_setoptions(ndev, lp->options))
579 dev_err(&ndev->dev, "Error setting TEMAC options\n");
580
581 /* Init Driver variable */
1ae5dc34 582 ndev->trans_start = jiffies; /* prevent tx timeout */
92744989
GL		 583}
584
585void temac_adjust_link(struct net_device *ndev)
586{
587 struct temac_local *lp = netdev_priv(ndev);
588 struct phy_device *phy = lp->phy_dev;
589 u32 mii_speed;
590 int link_state;
591
592 /* hash together the state values to decide if something has changed */
593 link_state = phy->speed | (phy->duplex << 1) | phy->link;
594
595 mutex_lock(&lp->indirect_mutex);
596 if (lp->last_link != link_state) {
597 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
598 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
599
600 switch (phy->speed) {
601 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
602 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
603 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
604 }
605
606 /* Write new speed setting out to TEMAC */
607 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
608 lp->last_link = link_state;
609 phy_print_status(phy);
610 }
611 mutex_unlock(&lp->indirect_mutex);
612}
613
614static void temac_start_xmit_done(struct net_device *ndev)
615{
616 struct temac_local *lp = netdev_priv(ndev);
617 struct cdmac_bd *cur_p;
618 unsigned int stat = 0;
619
620 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
621 stat = cur_p->app0;
622
623 while (stat & STS_CTRL_APP0_CMPLT) {
624 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
625 DMA_TO_DEVICE);
626 if (cur_p->app4)
627 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
628 cur_p->app0 = 0;
23ecc4bd
BH		 629 cur_p->app1 = 0;
630 cur_p->app2 = 0;
631 cur_p->app3 = 0;
632 cur_p->app4 = 0;
92744989
GL		 633
634 ndev->stats.tx_packets++;
635 ndev->stats.tx_bytes += cur_p->len;
636
637 lp->tx_bd_ci++;
638 if (lp->tx_bd_ci >= TX_BD_NUM)
639 lp->tx_bd_ci = 0;
640
641 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
642 stat = cur_p->app0;
643 }
644
645 netif_wake_queue(ndev);
646}
647
23ecc4bd
BH		 648static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
649{
650 struct cdmac_bd *cur_p;
651 int tail;
652
653 tail = lp->tx_bd_tail;
654 cur_p = &lp->tx_bd_v[tail];
655
656 do {
657 if (cur_p->app0)
658 return NETDEV_TX_BUSY;
659
660 tail++;
661 if (tail >= TX_BD_NUM)
662 tail = 0;
663
664 cur_p = &lp->tx_bd_v[tail];
665 num_frag--;
666 } while (num_frag >= 0);
667
668 return 0;
669}
670
92744989
GL		 671static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
672{
673 struct temac_local *lp = netdev_priv(ndev);
674 struct cdmac_bd *cur_p;
675 dma_addr_t start_p, tail_p;
676 int ii;
677 unsigned long num_frag;
678 skb_frag_t *frag;
679
680 num_frag = skb_shinfo(skb)->nr_frags;
681 frag = &skb_shinfo(skb)->frags[0];
682 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
683 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
684
23ecc4bd 685 if (temac_check_tx_bd_space(lp, num_frag)) {
92744989
GL		 686 if (!netif_queue_stopped(ndev)) {
687 netif_stop_queue(ndev);
688 return NETDEV_TX_BUSY;
689 }
690 return NETDEV_TX_BUSY;
691 }
692
693 cur_p->app0 = 0;
694 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 695 unsigned int csum_start_off = skb_checksum_start_offset(skb);
23ecc4bd
BH		 696 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
697
698 cur_p->app0 |= 1; /* TX Checksum Enabled */
699 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
700 cur_p->app2 = 0; /* initial checksum seed */
92744989 701 }
23ecc4bd 702
92744989
GL		 703 cur_p->app0 |= STS_CTRL_APP0_SOP;
704 cur_p->len = skb_headlen(skb);
705 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
706 DMA_TO_DEVICE);
707 cur_p->app4 = (unsigned long)skb;
708
709 for (ii = 0; ii < num_frag; ii++) {
710 lp->tx_bd_tail++;
711 if (lp->tx_bd_tail >= TX_BD_NUM)
712 lp->tx_bd_tail = 0;
713
714 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
715 cur_p->phys = dma_map_single(ndev->dev.parent,
3ed6f695 716 skb_frag_address(frag),
2edcd4ca
SR		 717 skb_frag_size(frag), DMA_TO_DEVICE);
718 cur_p->len = skb_frag_size(frag);
92744989
GL		 719 cur_p->app0 = 0;
720 frag++;
721 }
722 cur_p->app0 |= STS_CTRL_APP0_EOP;
723
724 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
725 lp->tx_bd_tail++;
726 if (lp->tx_bd_tail >= TX_BD_NUM)
727 lp->tx_bd_tail = 0;
728
93e0ed15
RC		 729 skb_tx_timestamp(skb);
730
92744989 731 /* Kick off the transfer */
e44171f1 732 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 733
6ed10654 734 return NETDEV_TX_OK;
92744989
GL		 735}
736
737
738static void ll_temac_recv(struct net_device *ndev)
739{
740 struct temac_local *lp = netdev_priv(ndev);
741 struct sk_buff *skb, *new_skb;
742 unsigned int bdstat;
743 struct cdmac_bd *cur_p;
744 dma_addr_t tail_p;
745 int length;
92744989
GL		 746 unsigned long flags;
747
748 spin_lock_irqsave(&lp->rx_lock, flags);
749
750 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
751 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
752
753 bdstat = cur_p->app0;
754 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
755
756 skb = lp->rx_skb[lp->rx_bd_ci];
c3b7c12c 757 length = cur_p->app4 & 0x3FFF;
92744989 758
33646d7f 759 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
92744989
GL		 760 DMA_FROM_DEVICE);
761
762 skb_put(skb, length);
92744989 763 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 764 skb_checksum_none_assert(skb);
92744989 765
23ecc4bd
BH		 766 /* if we're doing rx csum offload, set it up */
767 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
768 (skb->protocol == __constant_htons(ETH_P_IP)) &&
769 (skb->len > 64)) {
770
771 skb->csum = cur_p->app3 & 0xFFFF;
772 skb->ip_summed = CHECKSUM_COMPLETE;
773 }
774
93e0ed15
RC		 775 if (!skb_defer_rx_timestamp(skb))
776 netif_rx(skb);
92744989
GL		 777
778 ndev->stats.rx_packets++;
779 ndev->stats.rx_bytes += length;
780
e44171f1
JL		 781 new_skb = netdev_alloc_skb_ip_align(ndev,
782 XTE_MAX_JUMBO_FRAME_SIZE);
720a43ef 783 if (!new_skb) {
92744989
GL		 784 spin_unlock_irqrestore(&lp->rx_lock, flags);
785 return;
786 }
787
92744989
GL		 788 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
789 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
790 XTE_MAX_JUMBO_FRAME_SIZE,
791 DMA_FROM_DEVICE);
792 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
793 lp->rx_skb[lp->rx_bd_ci] = new_skb;
794
795 lp->rx_bd_ci++;
796 if (lp->rx_bd_ci >= RX_BD_NUM)
797 lp->rx_bd_ci = 0;
798
799 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
800 bdstat = cur_p->app0;
801 }
e44171f1 802 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 803
804 spin_unlock_irqrestore(&lp->rx_lock, flags);
805}
806
807static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
808{
809 struct net_device *ndev = _ndev;
810 struct temac_local *lp = netdev_priv(ndev);
811 unsigned int status;
812
e44171f1
JL		 813 status = lp->dma_in(lp, TX_IRQ_REG);
814 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 815
816 if (status & (IRQ_COAL | IRQ_DLY))
817 temac_start_xmit_done(lp->ndev);
818 if (status & 0x080)
819 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
820
821 return IRQ_HANDLED;
822}
823
824static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
825{
826 struct net_device *ndev = _ndev;
827 struct temac_local *lp = netdev_priv(ndev);
828 unsigned int status;
829
830 /* Read and clear the status registers */
e44171f1
JL		 831 status = lp->dma_in(lp, RX_IRQ_REG);
832 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 833
834 if (status & (IRQ_COAL | IRQ_DLY))
835 ll_temac_recv(lp->ndev);
836
837 return IRQ_HANDLED;
838}
839
840static int temac_open(struct net_device *ndev)
841{
842 struct temac_local *lp = netdev_priv(ndev);
843 int rc;
844
845 dev_dbg(&ndev->dev, "temac_open()\n");
846
847 if (lp->phy_node) {
848 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
849 temac_adjust_link, 0, 0);
850 if (!lp->phy_dev) {
851 dev_err(lp->dev, "of_phy_connect() failed\n");
852 return -ENODEV;
853 }
854
855 phy_start(lp->phy_dev);
856 }
857
50ec1538
RR		 858 temac_device_reset(ndev);
859
92744989
GL		 860 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
861 if (rc)
862 goto err_tx_irq;
863 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
864 if (rc)
865 goto err_rx_irq;
866
92744989
GL		 867 return 0;
868
869 err_rx_irq:
870 free_irq(lp->tx_irq, ndev);
871 err_tx_irq:
872 if (lp->phy_dev)
873 phy_disconnect(lp->phy_dev);
874 lp->phy_dev = NULL;
875 dev_err(lp->dev, "request_irq() failed\n");
876 return rc;
877}
878
879static int temac_stop(struct net_device *ndev)
880{
881 struct temac_local *lp = netdev_priv(ndev);
882
883 dev_dbg(&ndev->dev, "temac_close()\n");
884
885 free_irq(lp->tx_irq, ndev);
886 free_irq(lp->rx_irq, ndev);
887
888 if (lp->phy_dev)
889 phy_disconnect(lp->phy_dev);
890 lp->phy_dev = NULL;
891
301e9d96
DK		 892 temac_dma_bd_release(ndev);
893
92744989
GL		 894 return 0;
895}
896
897#ifdef CONFIG_NET_POLL_CONTROLLER
898static void
899temac_poll_controller(struct net_device *ndev)
900{
901 struct temac_local *lp = netdev_priv(ndev);
902
903 disable_irq(lp->tx_irq);
904 disable_irq(lp->rx_irq);
905
8539992f
MS		 906 ll_temac_rx_irq(lp->tx_irq, ndev);
907 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 908
909 enable_irq(lp->tx_irq);
910 enable_irq(lp->rx_irq);
911}
912#endif
913
8d8bdfe8
RR		 914static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
915{
916 struct temac_local *lp = netdev_priv(ndev);
917
918 if (!netif_running(ndev))
919 return -EINVAL;
920
921 if (!lp->phy_dev)
922 return -EINVAL;
923
924 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
925}
926
92744989
GL		 927static const struct net_device_ops temac_netdev_ops = {
928 .ndo_open = temac_open,
929 .ndo_stop = temac_stop,
930 .ndo_start_xmit = temac_start_xmit,
04e406dc 931 .ndo_set_mac_address = temac_set_mac_address,
60eb5fd1 932 .ndo_validate_addr = eth_validate_addr,
8d8bdfe8 933 .ndo_do_ioctl = temac_ioctl,
92744989
GL		 934#ifdef CONFIG_NET_POLL_CONTROLLER
935 .ndo_poll_controller = temac_poll_controller,
936#endif
937};
938
939/* ---------------------------------------------------------------------
940 * SYSFS device attributes
941 */
942static ssize_t temac_show_llink_regs(struct device *dev,
943 struct device_attribute *attr, char *buf)
944{
945 struct net_device *ndev = dev_get_drvdata(dev);
946 struct temac_local *lp = netdev_priv(ndev);
947 int i, len = 0;
948
949 for (i = 0; i < 0x11; i++)
e44171f1 950 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 951 (i % 8) == 7 ? "\n" : " ");
952 len += sprintf(buf + len, "\n");
953
954 return len;
955}
956
957static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
958
959static struct attribute *temac_device_attrs[] = {
960 &dev_attr_llink_regs.attr,
961 NULL,
962};
963
964static const struct attribute_group temac_attr_group = {
965 .attrs = temac_device_attrs,
966};
967
9eac2d4d
R		 968/* ethtool support */
969static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
970{
971 struct temac_local *lp = netdev_priv(ndev);
972 return phy_ethtool_gset(lp->phy_dev, cmd);
973}
974
975static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
976{
977 struct temac_local *lp = netdev_priv(ndev);
978 return phy_ethtool_sset(lp->phy_dev, cmd);
979}
980
981static int temac_nway_reset(struct net_device *ndev)
982{
983 struct temac_local *lp = netdev_priv(ndev);
984 return phy_start_aneg(lp->phy_dev);
985}
986
987static const struct ethtool_ops temac_ethtool_ops = {
988 .get_settings = temac_get_settings,
989 .set_settings = temac_set_settings,
990 .nway_reset = temac_nway_reset,
991 .get_link = ethtool_op_get_link,
f85e5ea2 992 .get_ts_info = ethtool_op_get_ts_info,
9eac2d4d
R		 993};
994
06b0e683 995static int temac_of_probe(struct platform_device *op)
92744989
GL		 996{
997 struct device_node *np;
998 struct temac_local *lp;
999 struct net_device *ndev;
1000 const void *addr;
23ecc4bd 1001 __be32 *p;
92744989 1002 int size, rc = 0;
92744989
GL		 1003
1004 /* Init network device structure */
1005 ndev = alloc_etherdev(sizeof(*lp));
41de8d4c 1006 if (!ndev)
92744989 1007 return -ENOMEM;
41de8d4c 1008
92744989
GL		 1009 ether_setup(ndev);
1010 dev_set_drvdata(&op->dev, ndev);
1011 SET_NETDEV_DEV(ndev, &op->dev);
1012 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1013 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
1014 ndev->netdev_ops = &temac_netdev_ops;
9eac2d4d 1015 ndev->ethtool_ops = &temac_ethtool_ops;
92744989
GL		 1016#if 0
1017 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1018 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1019 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1020 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
f646968f
PM		 1021 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1022 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1023 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
92744989
GL		 1024 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1025 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1026 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1027 ndev->features |= NETIF_F_LRO; /* large receive offload */
1028#endif
1029
1030 /* setup temac private info structure */
1031 lp = netdev_priv(ndev);
1032 lp->ndev = ndev;
1033 lp->dev = &op->dev;
1034 lp->options = XTE_OPTION_DEFAULTS;
1035 spin_lock_init(&lp->rx_lock);
1036 mutex_init(&lp->indirect_mutex);
1037
1038 /* map device registers */
61c7a080 1039 lp->regs = of_iomap(op->dev.of_node, 0);
92744989
GL		 1040 if (!lp->regs) {
1041 dev_err(&op->dev, "could not map temac regs.\n");
1042 goto nodev;
1043 }
1044
23ecc4bd
BH		 1045 /* Setup checksum offload, but default to off if not specified */
1046 lp->temac_features = 0;
1047 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1048 if (p && be32_to_cpu(*p)) {
1049 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1050 /* Can checksum TCP/UDP over IPv4. */
1051 ndev->features |= NETIF_F_IP_CSUM;
1052 }
1053 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1054 if (p && be32_to_cpu(*p))
1055 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1056
92744989 1057 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
61c7a080 1058 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
92744989
GL		 1059 if (!np) {
1060 dev_err(&op->dev, "could not find DMA node\n");
dfe1e8ed 1061 goto err_iounmap;
92744989
GL		 1062 }
1063
e44171f1
JL		 1064 /* Setup the DMA register accesses, could be DCR or memory mapped */
1065 if (temac_dcr_setup(lp, op, np)) {
1066
1067 /* no DCR in the device tree, try non-DCR */
1068 lp->sdma_regs = of_iomap(np, 0);
1069 if (lp->sdma_regs) {
1070 lp->dma_in = temac_dma_in32;
1071 lp->dma_out = temac_dma_out32;
1072 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1073 } else {
1074 dev_err(&op->dev, "unable to map DMA registers\n");
7cc36f6f 1075 of_node_put(np);
dfe1e8ed 1076 goto err_iounmap;
e44171f1 1077 }
92744989 1078 }
92744989
GL		 1079
1080 lp->rx_irq = irq_of_parse_and_map(np, 0);
1081 lp->tx_irq = irq_of_parse_and_map(np, 1);
7cc36f6f
KV		 1082
1083 of_node_put(np); /* Finished with the DMA node; drop the reference */
1084
4e68ea26 1085 if (!lp->rx_irq || !lp->tx_irq) {
92744989
GL		 1086 dev_err(&op->dev, "could not determine irqs\n");
1087 rc = -ENOMEM;
dfe1e8ed 1088 goto err_iounmap_2;
92744989
GL		 1089 }
1090
92744989
GL		 1091
1092 /* Retrieve the MAC address */
61c7a080 1093 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
92744989
GL		 1094 if ((!addr) || (size != 6)) {
1095 dev_err(&op->dev, "could not find MAC address\n");
1096 rc = -ENODEV;
dfe1e8ed 1097 goto err_iounmap_2;
92744989 1098 }
04e406dc 1099 temac_init_mac_address(ndev, (void *)addr);
92744989 1100
61c7a080 1101 rc = temac_mdio_setup(lp, op->dev.of_node);
92744989
GL		 1102 if (rc)
1103 dev_warn(&op->dev, "error registering MDIO bus\n");
1104
61c7a080 1105 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
92744989
GL		 1106 if (lp->phy_node)
1107 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1108
1109 /* Add the device attributes */
1110 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1111 if (rc) {
1112 dev_err(lp->dev, "Error creating sysfs files\n");
dfe1e8ed 1113 goto err_iounmap_2;
92744989
GL		 1114 }
1115
1116 rc = register_netdev(lp->ndev);
1117 if (rc) {
1118 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1119 goto err_register_ndev;
1120 }
1121
1122 return 0;
1123
1124 err_register_ndev:
1125 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
dfe1e8ed
DK		 1126 err_iounmap_2:
1127 if (lp->sdma_regs)
1128 iounmap(lp->sdma_regs);
1129 err_iounmap:
1130 iounmap(lp->regs);
92744989
GL		 1131 nodev:
1132 free_netdev(ndev);
1133 ndev = NULL;
1134 return rc;
1135}
1136
06b0e683 1137static int temac_of_remove(struct platform_device *op)
92744989
GL		 1138{
1139 struct net_device *ndev = dev_get_drvdata(&op->dev);
1140 struct temac_local *lp = netdev_priv(ndev);
1141
1142 temac_mdio_teardown(lp);
1143 unregister_netdev(ndev);
1144 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1145 if (lp->phy_node)
1146 of_node_put(lp->phy_node);
1147 lp->phy_node = NULL;
1148 dev_set_drvdata(&op->dev, NULL);
dfe1e8ed
DK		 1149 iounmap(lp->regs);
1150 if (lp->sdma_regs)
1151 iounmap(lp->sdma_regs);
92744989
GL		 1152 free_netdev(ndev);
1153 return 0;
1154}
1155
06b0e683 1156static struct of_device_id temac_of_match[] = {
92744989 1157 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1158 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1159 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1160 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1161 {},
1162};
1163MODULE_DEVICE_TABLE(of, temac_of_match);
1164
74888760 1165static struct platform_driver temac_of_driver = {
92744989 1166 .probe = temac_of_probe,
06b0e683 1167 .remove = temac_of_remove,
92744989
GL		 1168 .driver = {
1169 .owner = THIS_MODULE,
1170 .name = "xilinx_temac",
4018294b 1171 .of_match_table = temac_of_match,
92744989
GL		 1172 },
1173};
1174
db62f684 1175module_platform_driver(temac_of_driver);
92744989
GL		 1176
1177MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1178MODULE_AUTHOR("Yoshio Kashiwagi");
1179MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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