Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / ethernet / xilinx / ll_temac_mdio.c
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1/*
2 * MDIO bus driver for the Xilinx TEMAC device
3 *
4 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
5 */
6
7#include <linux/io.h>
8#include <linux/netdevice.h>
9#include <linux/mutex.h>
10#include <linux/phy.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
9f1a1fca 13#include <linux/of_address.h>
5a0e3ad6 14#include <linux/slab.h>
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15#include <linux/of_mdio.h>
16
17#include "ll_temac.h"
18
19/* ---------------------------------------------------------------------
20 * MDIO Bus functions
21 */
22static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
23{
24 struct temac_local *lp = bus->priv;
25 u32 rc;
26
27 /* Write the PHY address to the MIIM Access Initiator register.
28 * When the transfer completes, the PHY register value will appear
29 * in the LSW0 register */
30 mutex_lock(&lp->indirect_mutex);
31 temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
32 rc = temac_indirect_in32(lp, XTE_MIIMAI_OFFSET);
33 mutex_unlock(&lp->indirect_mutex);
34
35 dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n",
36 phy_id, reg, rc);
37
38 return rc;
39}
40
41static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
42{
43 struct temac_local *lp = bus->priv;
44
45 dev_dbg(lp->dev, "temac_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
46 phy_id, reg, val);
47
48 /* First write the desired value into the write data register
49 * and then write the address into the access initiator register
50 */
51 mutex_lock(&lp->indirect_mutex);
52 temac_indirect_out32(lp, XTE_MGTDR_OFFSET, val);
53 temac_indirect_out32(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg);
54 mutex_unlock(&lp->indirect_mutex);
55
56 return 0;
57}
58
59int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
60{
61 struct mii_bus *bus;
e734a42f 62 u32 bus_hz;
92744989 63 int clk_div;
e734a42f 64 int rc;
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65 struct resource res;
66
67 /* Calculate a reasonable divisor for the clock rate */
68 clk_div = 0x3f; /* worst-case default setting */
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69 if (of_property_read_u32(np, "clock-frequency", &bus_hz) == 0) {
70 clk_div = bus_hz / (2500 * 1000 * 2) - 1;
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71 if (clk_div < 1)
72 clk_div = 1;
73 if (clk_div > 0x3f)
74 clk_div = 0x3f;
75 }
76
77 /* Enable the MDIO bus by asserting the enable bit and writing
78 * in the clock config */
79 mutex_lock(&lp->indirect_mutex);
80 temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
81 mutex_unlock(&lp->indirect_mutex);
82
83 bus = mdiobus_alloc();
84 if (!bus)
85 return -ENOMEM;
86
87 of_address_to_resource(np, 0, &res);
88 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
89 (unsigned long long)res.start);
90 bus->priv = lp;
91 bus->name = "Xilinx TEMAC MDIO";
92 bus->read = temac_mdio_read;
93 bus->write = temac_mdio_write;
94 bus->parent = lp->dev;
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95
96 lp->mii_bus = bus;
97
98 rc = of_mdiobus_register(bus, np);
99 if (rc)
100 goto err_register;
101
102 mutex_lock(&lp->indirect_mutex);
103 dev_dbg(lp->dev, "MDIO bus registered; MC:%x\n",
104 temac_indirect_in32(lp, XTE_MC_OFFSET));
105 mutex_unlock(&lp->indirect_mutex);
106 return 0;
107
108 err_register:
109 mdiobus_free(bus);
110 return rc;
111}
112
113void temac_mdio_teardown(struct temac_local *lp)
114{
115 mdiobus_unregister(lp->mii_bus);
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116 mdiobus_free(lp->mii_bus);
117 lp->mii_bus = NULL;
118}
119
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