| 8a3b7a25 |
1 | /* |
| 2 | * Definitions for Xilinx Axi Ethernet device driver. |
| 3 | * |
| 4 | * Copyright (c) 2009 Secret Lab Technologies, Ltd. |
| 59a54f30 |
5 | * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. |
| 8a3b7a25 |
6 | */ |
| 7 | |
| 8 | #ifndef XILINX_AXIENET_H |
| 9 | #define XILINX_AXIENET_H |
| 10 | |
| 11 | #include <linux/netdevice.h> |
| 12 | #include <linux/spinlock.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | |
| 15 | /* Packet size info */ |
| 16 | #define XAE_HDR_SIZE 14 /* Size of Ethernet header */ |
| 17 | #define XAE_HDR_VLAN_SIZE 18 /* Size of an Ethernet hdr + VLAN */ |
| 18 | #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */ |
| 19 | #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */ |
| 20 | #define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */ |
| 21 | |
| 22 | #define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) |
| 23 | #define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + XAE_HDR_VLAN_SIZE + XAE_TRL_SIZE) |
| 24 | #define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) |
| 25 | |
| 26 | /* Configuration options */ |
| 27 | |
| 28 | /* Accept all incoming packets. Default: disabled (cleared) */ |
| 29 | #define XAE_OPTION_PROMISC (1 << 0) |
| 30 | |
| 31 | /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */ |
| 32 | #define XAE_OPTION_JUMBO (1 << 1) |
| 33 | |
| 34 | /* VLAN Rx & Tx frame support. Default: disabled (cleared) */ |
| 35 | #define XAE_OPTION_VLAN (1 << 2) |
| 36 | |
| 37 | /* Enable recognition of flow control frames on Rx. Default: enabled (set) */ |
| 38 | #define XAE_OPTION_FLOW_CONTROL (1 << 4) |
| 39 | |
| 40 | /* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not |
| 41 | * stripped. Default: disabled (set) */ |
| 42 | #define XAE_OPTION_FCS_STRIP (1 << 5) |
| 43 | |
| 44 | /* Generate FCS field and add PAD automatically for outgoing frames. |
| 45 | * Default: enabled (set) */ |
| 46 | #define XAE_OPTION_FCS_INSERT (1 << 6) |
| 47 | |
| 48 | /* Enable Length/Type error checking for incoming frames. When this option is |
| 49 | * set, the MAC will filter frames that have a mismatched type/length field |
| 50 | * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these |
| 51 | * types of frames are encountered. When this option is cleared, the MAC will |
| 52 | * allow these types of frames to be received. Default: enabled (set) */ |
| 53 | #define XAE_OPTION_LENTYPE_ERR (1 << 7) |
| 54 | |
| 55 | /* Enable the transmitter. Default: enabled (set) */ |
| 56 | #define XAE_OPTION_TXEN (1 << 11) |
| 57 | |
| 58 | /* Enable the receiver. Default: enabled (set) */ |
| 59 | #define XAE_OPTION_RXEN (1 << 12) |
| 60 | |
| 61 | /* Default options set when device is initialized or reset */ |
| 62 | #define XAE_OPTION_DEFAULTS \ |
| 63 | (XAE_OPTION_TXEN | \ |
| 64 | XAE_OPTION_FLOW_CONTROL | \ |
| 65 | XAE_OPTION_RXEN) |
| 66 | |
| 67 | /* Axi DMA Register definitions */ |
| 68 | |
| 69 | #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ |
| 70 | #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */ |
| 71 | #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */ |
| 72 | #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */ |
| 73 | |
| 74 | #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */ |
| 75 | #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */ |
| 76 | #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */ |
| 77 | #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */ |
| 78 | |
| 79 | #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ |
| 80 | #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ |
| 81 | |
| 82 | #define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */ |
| 83 | #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */ |
| 84 | #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */ |
| 85 | #define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */ |
| 86 | #define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */ |
| 87 | #define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */ |
| 88 | #define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */ |
| 89 | #define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */ |
| 90 | #define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */ |
| 91 | #define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */ |
| 92 | #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */ |
| 93 | #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */ |
| 94 | |
| 95 | #define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */ |
| 96 | #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */ |
| 97 | #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */ |
| 98 | |
| 99 | #define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */ |
| 100 | #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
| 101 | #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
| 102 | #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ |
| 103 | |
| 104 | #define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */ |
| 105 | #define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */ |
| 106 | |
| 107 | #define XAXIDMA_DELAY_SHIFT 24 |
| 108 | #define XAXIDMA_COALESCE_SHIFT 16 |
| 109 | |
| 110 | #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ |
| 111 | #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ |
| 112 | #define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */ |
| 113 | #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ |
| 114 | |
| 115 | /* Default TX/RX Threshold and waitbound values for SGDMA mode */ |
| 116 | #define XAXIDMA_DFT_TX_THRESHOLD 24 |
| 117 | #define XAXIDMA_DFT_TX_WAITBOUND 254 |
| 118 | #define XAXIDMA_DFT_RX_THRESHOLD 24 |
| 119 | #define XAXIDMA_DFT_RX_WAITBOUND 254 |
| 120 | |
| 121 | #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
| 122 | #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
| 123 | #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ |
| 124 | |
| 125 | #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */ |
| 126 | #define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */ |
| 127 | #define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */ |
| 128 | #define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */ |
| 129 | #define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */ |
| 130 | #define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */ |
| 131 | #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */ |
| 132 | #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */ |
| 133 | #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */ |
| 134 | |
| 135 | #define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 |
| 136 | |
| 137 | /* Axi Ethernet registers definition */ |
| 138 | #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */ |
| 139 | #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */ |
| 140 | #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/ |
| 141 | #define XAE_IS_OFFSET 0x0000000C /* Interrupt status */ |
| 142 | #define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */ |
| 143 | #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */ |
| 144 | #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */ |
| 145 | #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */ |
| 146 | #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */ |
| 147 | #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */ |
| 148 | #define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */ |
| 149 | #define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */ |
| 150 | #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */ |
| 151 | #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */ |
| 152 | #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */ |
| 153 | #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */ |
| 154 | #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ |
| 155 | #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ |
| 156 | #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ |
| 157 | #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ |
| 158 | #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ |
| 159 | #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ |
| 160 | #define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */ |
| 161 | #define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */ |
| 162 | #define XAE_MDIO_MIP_OFFSET 0x00000620 /* MII Mgmt Interrupt Pending |
| 163 | * register offset */ |
| 164 | #define XAE_MDIO_MIE_OFFSET 0x00000640 /* MII Management Interrupt Enable |
| 165 | * register offset */ |
| 166 | #define XAE_MDIO_MIC_OFFSET 0x00000660 /* MII Management Interrupt Clear |
| 167 | * register offset. */ |
| 168 | #define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */ |
| 169 | #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */ |
| 170 | #define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */ |
| 171 | #define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */ |
| 172 | #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */ |
| 173 | |
| 174 | #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */ |
| 175 | #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */ |
| 176 | #define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */ |
| 177 | |
| 178 | /* Bit Masks for Axi Ethernet RAF register */ |
| 179 | #define XAE_RAF_MCSTREJ_MASK 0x00000002 /* Reject receive multicast |
| 180 | * destination address */ |
| 181 | #define XAE_RAF_BCSTREJ_MASK 0x00000004 /* Reject receive broadcast |
| 182 | * destination address */ |
| 183 | #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */ |
| 184 | #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */ |
| 185 | #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */ |
| 186 | #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */ |
| 187 | #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */ |
| 188 | #define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000 /* Exteneded Multicast |
| 189 | * Filtering mode |
| 190 | */ |
| 191 | #define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */ |
| 192 | #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */ |
| 193 | #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */ |
| 194 | #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */ |
| 195 | #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/ |
| 196 | #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/ |
| 197 | |
| 198 | /* Bit Masks for Axi Ethernet TPF and IFGP registers */ |
| 199 | #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */ |
| 200 | #define XAE_IFGP0_IFGP_MASK 0x0000007F /* Transmit inter-frame |
| 201 | * gap adjustment value */ |
| 202 | |
| 203 | /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply |
| 204 | * for all 3 registers. */ |
| 205 | #define XAE_INT_HARDACSCMPLT_MASK 0x00000001 /* Hard register access |
| 206 | * complete */ |
| 207 | #define XAE_INT_AUTONEG_MASK 0x00000002 /* Auto negotiation |
| 208 | * complete */ |
| 209 | #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */ |
| 210 | #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ |
| 211 | #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */ |
| 212 | #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */ |
| 213 | #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */ |
| 214 | #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ |
| 215 | #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */ |
| 216 | #define XAE_INT_ALL_MASK 0x0000003F /* All the ints */ |
| 217 | |
| 218 | #define XAE_INT_RECV_ERROR_MASK \ |
| 219 | (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK) /* INT bits that |
| 220 | * indicate receive |
| 221 | * errors */ |
| 222 | |
| 223 | /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */ |
| 224 | #define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */ |
| 225 | #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */ |
| 226 | |
| 227 | /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */ |
| 228 | #define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */ |
| 229 | #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */ |
| 230 | |
| 231 | /* Bit masks for Axi Ethernet RCW1 register */ |
| 232 | #define XAE_RCW1_RST_MASK 0x80000000 /* Reset */ |
| 233 | #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */ |
| 234 | #define XAE_RCW1_FCS_MASK 0x20000000 /* In-Band FCS enable |
| 235 | * (FCS not stripped) */ |
| 236 | #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ |
| 237 | #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */ |
| 238 | #define XAE_RCW1_LT_DIS_MASK 0x02000000 /* Length/type field valid check |
| 239 | * disable */ |
| 240 | #define XAE_RCW1_CL_DIS_MASK 0x01000000 /* Control frame Length check |
| 241 | * disable */ |
| 242 | #define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF /* Pause frame source address |
| 243 | * bits [47:32]. Bits [31:0] are |
| 244 | * stored in register RCW0 */ |
| 245 | |
| 246 | /* Bit masks for Axi Ethernet TC register */ |
| 247 | #define XAE_TC_RST_MASK 0x80000000 /* Reset */ |
| 248 | #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */ |
| 249 | #define XAE_TC_FCS_MASK 0x20000000 /* In-Band FCS enable |
| 250 | * (FCS not generated) */ |
| 251 | #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ |
| 252 | #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */ |
| 253 | #define XAE_TC_IFG_MASK 0x02000000 /* Inter-frame gap adjustment |
| 254 | * enable */ |
| 255 | |
| 256 | /* Bit masks for Axi Ethernet FCC register */ |
| 257 | #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */ |
| 258 | #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */ |
| 259 | |
| 260 | /* Bit masks for Axi Ethernet EMMC register */ |
| 261 | #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ |
| 262 | #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */ |
| 263 | #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */ |
| 264 | #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */ |
| 265 | #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */ |
| 266 | #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */ |
| 267 | #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */ |
| 268 | #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ |
| 269 | #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ |
| 270 | #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ |
| 271 | |
| 272 | /* Bit masks for Axi Ethernet PHYC register */ |
| 273 | #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/ |
| 274 | #define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */ |
| 275 | #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */ |
| 276 | #define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */ |
| 277 | #define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */ |
| 278 | #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */ |
| 279 | #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */ |
| 280 | #define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */ |
| 281 | #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */ |
| 282 | #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */ |
| 283 | |
| 284 | /* Bit masks for Axi Ethernet MDIO interface MC register */ |
| 285 | #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */ |
| 286 | #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */ |
| 287 | |
| 288 | /* Bit masks for Axi Ethernet MDIO interface MCR register */ |
| 289 | #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ |
| 290 | #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ |
| 291 | #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ |
| 292 | #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ |
| 293 | #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */ |
| 294 | #define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */ |
| 295 | #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ |
| 296 | #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ |
| 297 | #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ |
| 298 | #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ |
| 299 | |
| 300 | /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */ |
| 301 | #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */ |
| 302 | |
| 303 | /* Bit masks for Axi Ethernet UAW1 register */ |
| 304 | #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF /* Station address bits |
| 305 | * [47:32]; Station address |
| 306 | * bits [31:0] are stored in |
| 307 | * register UAW0 */ |
| 308 | |
| 309 | /* Bit masks for Axi Ethernet FMI register */ |
| 310 | #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */ |
| 311 | #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */ |
| 312 | |
| 313 | #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ |
| 314 | |
| 315 | /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */ |
| 316 | #define XAE_PHY_TYPE_MII 0 |
| 317 | #define XAE_PHY_TYPE_GMII 1 |
| 318 | #define XAE_PHY_TYPE_RGMII_1_3 2 |
| 319 | #define XAE_PHY_TYPE_RGMII_2_0 3 |
| 320 | #define XAE_PHY_TYPE_SGMII 4 |
| 321 | #define XAE_PHY_TYPE_1000BASE_X 5 |
| 322 | |
| 323 | #define XAE_MULTICAST_CAM_TABLE_NUM 4 /* Total number of entries in the |
| 324 | * hardware multicast table. */ |
| 325 | |
| 326 | /* Axi Ethernet Synthesis features */ |
| 327 | #define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0) |
| 328 | #define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1) |
| 329 | #define XAE_FEATURE_FULL_RX_CSUM (1 << 2) |
| 330 | #define XAE_FEATURE_FULL_TX_CSUM (1 << 3) |
| 331 | |
| 332 | #define XAE_NO_CSUM_OFFLOAD 0 |
| 333 | |
| 334 | #define XAE_FULL_CSUM_STATUS_MASK 0x00000038 |
| 335 | #define XAE_IP_UDP_CSUM_VALIDATED 0x00000003 |
| 336 | #define XAE_IP_TCP_CSUM_VALIDATED 0x00000002 |
| 337 | |
| 338 | #define DELAY_OF_ONE_MILLISEC 1000 |
| 339 | |
| 340 | /** |
| 341 | * struct axidma_bd - Axi Dma buffer descriptor layout |
| 342 | * @next: MM2S/S2MM Next Descriptor Pointer |
| 343 | * @reserved1: Reserved and not used |
| 344 | * @phys: MM2S/S2MM Buffer Address |
| 345 | * @reserved2: Reserved and not used |
| 346 | * @reserved3: Reserved and not used |
| 347 | * @reserved4: Reserved and not used |
| 348 | * @cntrl: MM2S/S2MM Control value |
| 349 | * @status: MM2S/S2MM Status value |
| 350 | * @app0: MM2S/S2MM User Application Field 0. |
| 351 | * @app1: MM2S/S2MM User Application Field 1. |
| 352 | * @app2: MM2S/S2MM User Application Field 2. |
| 353 | * @app3: MM2S/S2MM User Application Field 3. |
| 354 | * @app4: MM2S/S2MM User Application Field 4. |
| 355 | * @sw_id_offset: MM2S/S2MM Sw ID |
| 356 | * @reserved5: Reserved and not used |
| 357 | * @reserved6: Reserved and not used |
| 358 | */ |
| 359 | struct axidma_bd { |
| 360 | u32 next; /* Physical address of next buffer descriptor */ |
| 361 | u32 reserved1; |
| 362 | u32 phys; |
| 363 | u32 reserved2; |
| 364 | u32 reserved3; |
| 365 | u32 reserved4; |
| 366 | u32 cntrl; |
| 367 | u32 status; |
| 368 | u32 app0; |
| 369 | u32 app1; /* TX start << 16 | insert */ |
| 370 | u32 app2; /* TX csum seed */ |
| 371 | u32 app3; |
| 372 | u32 app4; |
| 373 | u32 sw_id_offset; |
| 374 | u32 reserved5; |
| 375 | u32 reserved6; |
| 376 | }; |
| 377 | |
| 378 | /** |
| 379 | * struct axienet_local - axienet private per device data |
| 380 | * @ndev: Pointer for net_device to which it will be attached. |
| 381 | * @dev: Pointer to device structure |
| 382 | * @phy_dev: Pointer to PHY device structure attached to the axienet_local |
| 383 | * @phy_node: Pointer to device node structure |
| 384 | * @mii_bus: Pointer to MII bus structure |
| 385 | * @mdio_irqs: IRQs table for MDIO bus required in mii_bus structure |
| 386 | * @regs: Base address for the axienet_local device address space |
| 387 | * @dma_regs: Base address for the axidma device address space |
| 388 | * @dma_err_tasklet: Tasklet structure to process Axi DMA errors |
| 389 | * @tx_irq: Axidma TX IRQ number |
| 390 | * @rx_irq: Axidma RX IRQ number |
| 391 | * @temac_type: axienet type to identify between soft and hard temac |
| 392 | * @phy_type: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X |
| 393 | * @options: AxiEthernet option word |
| 394 | * @last_link: Phy link state in which the PHY was negotiated earlier |
| 395 | * @features: Stores the extended features supported by the axienet hw |
| 396 | * @tx_bd_v: Virtual address of the TX buffer descriptor ring |
| 397 | * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring |
| 398 | * @rx_bd_v: Virtual address of the RX buffer descriptor ring |
| 399 | * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring |
| 400 | * @tx_bd_ci: Stores the index of the Tx buffer descriptor in the ring being |
| 401 | * accessed currently. Used while alloc. BDs before a TX starts |
| 402 | * @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being |
| 403 | * accessed currently. Used while processing BDs after the TX |
| 404 | * completed. |
| 405 | * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being |
| 406 | * accessed currently. |
| 407 | * @max_frm_size: Stores the maximum size of the frame that can be that |
| 408 | * Txed/Rxed in the existing hardware. If jumbo option is |
| 409 | * supported, the maximum frame size would be 9k. Else it is |
| 410 | * 1522 bytes (assuming support for basic VLAN) |
| 411 | * @jumbo_support: Stores hardware configuration for jumbo support. If hardware |
| 412 | * can handle jumbo packets, this entry will be 1, else 0. |
| 413 | */ |
| 414 | struct axienet_local { |
| 415 | struct net_device *ndev; |
| 416 | struct device *dev; |
| 417 | |
| 418 | /* Connection to PHY device */ |
| 419 | struct phy_device *phy_dev; /* Pointer to PHY device */ |
| 420 | struct device_node *phy_node; |
| 421 | |
| 422 | /* MDIO bus data */ |
| 423 | struct mii_bus *mii_bus; /* MII bus reference */ |
| 424 | int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */ |
| 425 | |
| 426 | /* IO registers, dma functions and IRQs */ |
| 427 | void __iomem *regs; |
| 428 | void __iomem *dma_regs; |
| 429 | |
| 430 | struct tasklet_struct dma_err_tasklet; |
| 431 | |
| 432 | int tx_irq; |
| 433 | int rx_irq; |
| 434 | u32 temac_type; |
| 435 | u32 phy_type; |
| 436 | |
| 437 | u32 options; /* Current options word */ |
| 438 | u32 last_link; |
| 439 | u32 features; |
| 440 | |
| 441 | /* Buffer descriptors */ |
| 442 | struct axidma_bd *tx_bd_v; |
| 443 | dma_addr_t tx_bd_p; |
| 444 | struct axidma_bd *rx_bd_v; |
| 445 | dma_addr_t rx_bd_p; |
| 446 | u32 tx_bd_ci; |
| 447 | u32 tx_bd_tail; |
| 448 | u32 rx_bd_ci; |
| 449 | |
| 450 | u32 max_frm_size; |
| 451 | u32 jumbo_support; |
| 452 | |
| 453 | int csum_offload_on_tx_path; |
| 454 | int csum_offload_on_rx_path; |
| 455 | |
| 456 | u32 coalesce_count_rx; |
| 457 | u32 coalesce_count_tx; |
| 458 | }; |
| 459 | |
| 460 | /** |
| 461 | * struct axiethernet_option - Used to set axi ethernet hardware options |
| 462 | * @opt: Option to be set. |
| 463 | * @reg: Register offset to be written for setting the option |
| 464 | * @m_or: Mask to be ORed for setting the option in the register |
| 465 | */ |
| 466 | struct axienet_option { |
| 467 | u32 opt; |
| 468 | u32 reg; |
| 469 | u32 m_or; |
| 470 | }; |
| 471 | |
| 472 | /** |
| 473 | * axienet_ior - Memory mapped Axi Ethernet register read |
| 474 | * @lp: Pointer to axienet local structure |
| 475 | * @offset: Address offset from the base address of Axi Ethernet core |
| 476 | * |
| 477 | * returns: The contents of the Axi Ethernet register |
| 478 | * |
| 479 | * This function returns the contents of the corresponding register. |
| 480 | */ |
| 481 | static inline u32 axienet_ior(struct axienet_local *lp, off_t offset) |
| 482 | { |
| 483 | return in_be32(lp->regs + offset); |
| 484 | } |
| 485 | |
| 486 | /** |
| 487 | * axienet_iow - Memory mapped Axi Ethernet register write |
| 488 | * @lp: Pointer to axienet local structure |
| 489 | * @offset: Address offset from the base address of Axi Ethernet core |
| 490 | * @value: Value to be written into the Axi Ethernet register |
| 491 | * |
| 492 | * This function writes the desired value into the corresponding Axi Ethernet |
| 493 | * register. |
| 494 | */ |
| 495 | static inline void axienet_iow(struct axienet_local *lp, off_t offset, |
| 496 | u32 value) |
| 497 | { |
| 498 | out_be32((lp->regs + offset), value); |
| 499 | } |
| 500 | |
| 501 | /* Function prototypes visible in xilinx_axienet_mdio.c for other files */ |
| 502 | int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np); |
| 503 | int axienet_mdio_wait_until_ready(struct axienet_local *lp); |
| 504 | void axienet_mdio_teardown(struct axienet_local *lp); |
| 505 | |
| 506 | #endif /* XILINX_AXI_ENET_H */ |
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