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dac2f83f KH |
1 | /* |
2 | * Intel IXP4xx Ethernet driver for Linux | |
3 | * | |
4 | * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of version 2 of the GNU General Public License | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * Ethernet port config (0x00 is not present on IXP42X): | |
11 | * | |
12 | * logical port 0x00 0x10 0x20 | |
13 | * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) | |
14 | * physical PortId 2 0 1 | |
15 | * TX queue 23 24 25 | |
16 | * RX-free queue 26 27 28 | |
17 | * TX-done queue is always 31, per-port RX and TX-ready queues are configurable | |
18 | * | |
19 | * | |
20 | * Queue entries: | |
21 | * bits 0 -> 1 - NPE ID (RX and TX-done) | |
22 | * bits 0 -> 2 - priority (TX, per 802.1D) | |
23 | * bits 3 -> 4 - port ID (user-set?) | |
24 | * bits 5 -> 31 - physical descriptor address | |
25 | */ | |
26 | ||
27 | #include <linux/delay.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/dmapool.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/kernel.h> | |
32bd93e8 | 33 | #include <linux/net_tstamp.h> |
2098c18d | 34 | #include <linux/phy.h> |
dac2f83f | 35 | #include <linux/platform_device.h> |
32bd93e8 | 36 | #include <linux/ptp_classify.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
9d9779e7 | 38 | #include <linux/module.h> |
32bd93e8 | 39 | #include <mach/ixp46x_ts.h> |
a09e64fb RK |
40 | #include <mach/npe.h> |
41 | #include <mach/qmgr.h> | |
dac2f83f | 42 | |
dac2f83f KH |
43 | #define DEBUG_DESC 0 |
44 | #define DEBUG_RX 0 | |
45 | #define DEBUG_TX 0 | |
46 | #define DEBUG_PKT_BYTES 0 | |
47 | #define DEBUG_MDIO 0 | |
48 | #define DEBUG_CLOSE 0 | |
49 | ||
50 | #define DRV_NAME "ixp4xx_eth" | |
51 | ||
52 | #define MAX_NPES 3 | |
53 | ||
54 | #define RX_DESCS 64 /* also length of all RX queues */ | |
55 | #define TX_DESCS 16 /* also length of all TX queues */ | |
56 | #define TXDONE_QUEUE_LEN 64 /* dwords */ | |
57 | ||
58 | #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) | |
59 | #define REGS_SIZE 0x1000 | |
60 | #define MAX_MRU 1536 /* 0x600 */ | |
61 | #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) | |
62 | ||
63 | #define NAPI_WEIGHT 16 | |
64 | #define MDIO_INTERVAL (3 * HZ) | |
65 | #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ | |
dac2f83f KH |
66 | #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ |
67 | ||
68 | #define NPE_ID(port_id) ((port_id) >> 4) | |
69 | #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) | |
70 | #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) | |
71 | #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) | |
72 | #define TXDONE_QUEUE 31 | |
73 | ||
32bd93e8 RC |
74 | #define PTP_SLAVE_MODE 1 |
75 | #define PTP_MASTER_MODE 2 | |
76 | #define PORT2CHANNEL(p) NPE_ID(p->id) | |
77 | ||
dac2f83f KH |
78 | /* TX Control Registers */ |
79 | #define TX_CNTRL0_TX_EN 0x01 | |
80 | #define TX_CNTRL0_HALFDUPLEX 0x02 | |
81 | #define TX_CNTRL0_RETRY 0x04 | |
82 | #define TX_CNTRL0_PAD_EN 0x08 | |
83 | #define TX_CNTRL0_APPEND_FCS 0x10 | |
84 | #define TX_CNTRL0_2DEFER 0x20 | |
85 | #define TX_CNTRL0_RMII 0x40 /* reduced MII */ | |
86 | #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ | |
87 | ||
88 | /* RX Control Registers */ | |
89 | #define RX_CNTRL0_RX_EN 0x01 | |
90 | #define RX_CNTRL0_PADSTRIP_EN 0x02 | |
91 | #define RX_CNTRL0_SEND_FCS 0x04 | |
92 | #define RX_CNTRL0_PAUSE_EN 0x08 | |
93 | #define RX_CNTRL0_LOOP_EN 0x10 | |
94 | #define RX_CNTRL0_ADDR_FLTR_EN 0x20 | |
95 | #define RX_CNTRL0_RX_RUNT_EN 0x40 | |
96 | #define RX_CNTRL0_BCAST_DIS 0x80 | |
97 | #define RX_CNTRL1_DEFER_EN 0x01 | |
98 | ||
99 | /* Core Control Register */ | |
100 | #define CORE_RESET 0x01 | |
101 | #define CORE_RX_FIFO_FLUSH 0x02 | |
102 | #define CORE_TX_FIFO_FLUSH 0x04 | |
103 | #define CORE_SEND_JAM 0x08 | |
104 | #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ | |
105 | ||
106 | #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ | |
107 | TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ | |
108 | TX_CNTRL0_2DEFER) | |
109 | #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN | |
110 | #define DEFAULT_CORE_CNTRL CORE_MDC_EN | |
111 | ||
112 | ||
113 | /* NPE message codes */ | |
114 | #define NPE_GETSTATUS 0x00 | |
115 | #define NPE_EDB_SETPORTADDRESS 0x01 | |
116 | #define NPE_EDB_GETMACADDRESSDATABASE 0x02 | |
117 | #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 | |
118 | #define NPE_GETSTATS 0x04 | |
119 | #define NPE_RESETSTATS 0x05 | |
120 | #define NPE_SETMAXFRAMELENGTHS 0x06 | |
121 | #define NPE_VLAN_SETRXTAGMODE 0x07 | |
122 | #define NPE_VLAN_SETDEFAULTRXVID 0x08 | |
123 | #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 | |
124 | #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A | |
125 | #define NPE_VLAN_SETRXQOSENTRY 0x0B | |
126 | #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C | |
127 | #define NPE_STP_SETBLOCKINGSTATE 0x0D | |
128 | #define NPE_FW_SETFIREWALLMODE 0x0E | |
129 | #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F | |
130 | #define NPE_PC_SETAPMACTABLE 0x11 | |
131 | #define NPE_SETLOOPBACK_MODE 0x12 | |
132 | #define NPE_PC_SETBSSIDTABLE 0x13 | |
133 | #define NPE_ADDRESS_FILTER_CONFIG 0x14 | |
134 | #define NPE_APPENDFCSCONFIG 0x15 | |
135 | #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 | |
136 | #define NPE_MAC_RECOVERY_START 0x17 | |
137 | ||
138 | ||
139 | #ifdef __ARMEB__ | |
140 | typedef struct sk_buff buffer_t; | |
141 | #define free_buffer dev_kfree_skb | |
142 | #define free_buffer_irq dev_kfree_skb_irq | |
143 | #else | |
144 | typedef void buffer_t; | |
145 | #define free_buffer kfree | |
146 | #define free_buffer_irq kfree | |
147 | #endif | |
148 | ||
149 | struct eth_regs { | |
150 | u32 tx_control[2], __res1[2]; /* 000 */ | |
151 | u32 rx_control[2], __res2[2]; /* 010 */ | |
152 | u32 random_seed, __res3[3]; /* 020 */ | |
153 | u32 partial_empty_threshold, __res4; /* 030 */ | |
154 | u32 partial_full_threshold, __res5; /* 038 */ | |
155 | u32 tx_start_bytes, __res6[3]; /* 040 */ | |
156 | u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ | |
157 | u32 tx_2part_deferral[2], __res8[2]; /* 060 */ | |
158 | u32 slot_time, __res9[3]; /* 070 */ | |
159 | u32 mdio_command[4]; /* 080 */ | |
160 | u32 mdio_status[4]; /* 090 */ | |
161 | u32 mcast_mask[6], __res10[2]; /* 0A0 */ | |
162 | u32 mcast_addr[6], __res11[2]; /* 0C0 */ | |
163 | u32 int_clock_threshold, __res12[3]; /* 0E0 */ | |
164 | u32 hw_addr[6], __res13[61]; /* 0F0 */ | |
165 | u32 core_control; /* 1FC */ | |
166 | }; | |
167 | ||
168 | struct port { | |
169 | struct resource *mem_res; | |
170 | struct eth_regs __iomem *regs; | |
171 | struct npe *npe; | |
172 | struct net_device *netdev; | |
173 | struct napi_struct napi; | |
2098c18d | 174 | struct phy_device *phydev; |
dac2f83f KH |
175 | struct eth_plat_info *plat; |
176 | buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; | |
177 | struct desc *desc_tab; /* coherent */ | |
178 | u32 desc_tab_phys; | |
179 | int id; /* logical port ID */ | |
2098c18d | 180 | int speed, duplex; |
490b7722 | 181 | u8 firmware[4]; |
32bd93e8 RC |
182 | int hwts_tx_en; |
183 | int hwts_rx_en; | |
dac2f83f KH |
184 | }; |
185 | ||
186 | /* NPE message structure */ | |
187 | struct msg { | |
188 | #ifdef __ARMEB__ | |
189 | u8 cmd, eth_id, byte2, byte3; | |
190 | u8 byte4, byte5, byte6, byte7; | |
191 | #else | |
192 | u8 byte3, byte2, eth_id, cmd; | |
193 | u8 byte7, byte6, byte5, byte4; | |
194 | #endif | |
195 | }; | |
196 | ||
197 | /* Ethernet packet descriptor */ | |
198 | struct desc { | |
199 | u32 next; /* pointer to next buffer, unused */ | |
200 | ||
201 | #ifdef __ARMEB__ | |
202 | u16 buf_len; /* buffer length */ | |
203 | u16 pkt_len; /* packet length */ | |
204 | u32 data; /* pointer to data buffer in RAM */ | |
205 | u8 dest_id; | |
206 | u8 src_id; | |
207 | u16 flags; | |
208 | u8 qos; | |
209 | u8 padlen; | |
210 | u16 vlan_tci; | |
211 | #else | |
212 | u16 pkt_len; /* packet length */ | |
213 | u16 buf_len; /* buffer length */ | |
214 | u32 data; /* pointer to data buffer in RAM */ | |
215 | u16 flags; | |
216 | u8 src_id; | |
217 | u8 dest_id; | |
218 | u16 vlan_tci; | |
219 | u8 padlen; | |
220 | u8 qos; | |
221 | #endif | |
222 | ||
223 | #ifdef __ARMEB__ | |
224 | u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; | |
225 | u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; | |
226 | u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; | |
227 | #else | |
228 | u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; | |
229 | u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; | |
230 | u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; | |
231 | #endif | |
232 | }; | |
233 | ||
234 | ||
235 | #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ | |
236 | (n) * sizeof(struct desc)) | |
237 | #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) | |
238 | ||
239 | #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ | |
240 | ((n) + RX_DESCS) * sizeof(struct desc)) | |
241 | #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) | |
242 | ||
243 | #ifndef __ARMEB__ | |
244 | static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) | |
245 | { | |
246 | int i; | |
247 | for (i = 0; i < cnt; i++) | |
248 | dest[i] = swab32(src[i]); | |
249 | } | |
250 | #endif | |
251 | ||
252 | static spinlock_t mdio_lock; | |
253 | static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ | |
0409cb0d | 254 | static struct mii_bus *mdio_bus; |
dac2f83f KH |
255 | static int ports_open; |
256 | static struct port *npe_port_tab[MAX_NPES]; | |
257 | static struct dma_pool *dma_pool; | |
258 | ||
32bd93e8 RC |
259 | static struct sock_filter ptp_filter[] = { |
260 | PTP_FILTER | |
261 | }; | |
262 | ||
263 | static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) | |
264 | { | |
265 | u8 *data = skb->data; | |
266 | unsigned int offset; | |
267 | u16 *hi, *id; | |
268 | u32 lo; | |
269 | ||
270 | if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4) | |
271 | return 0; | |
272 | ||
273 | offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; | |
274 | ||
275 | if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) | |
276 | return 0; | |
277 | ||
278 | hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); | |
279 | id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); | |
280 | ||
281 | memcpy(&lo, &hi[1], sizeof(lo)); | |
282 | ||
283 | return (uid_hi == ntohs(*hi) && | |
284 | uid_lo == ntohl(lo) && | |
285 | seqid == ntohs(*id)); | |
286 | } | |
287 | ||
288 | static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) | |
289 | { | |
290 | struct skb_shared_hwtstamps *shhwtstamps; | |
291 | struct ixp46x_ts_regs *regs; | |
292 | u64 ns; | |
293 | u32 ch, hi, lo, val; | |
294 | u16 uid, seq; | |
295 | ||
296 | if (!port->hwts_rx_en) | |
297 | return; | |
298 | ||
299 | ch = PORT2CHANNEL(port); | |
300 | ||
301 | regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; | |
302 | ||
303 | val = __raw_readl(®s->channel[ch].ch_event); | |
304 | ||
305 | if (!(val & RX_SNAPSHOT_LOCKED)) | |
306 | return; | |
307 | ||
308 | lo = __raw_readl(®s->channel[ch].src_uuid_lo); | |
309 | hi = __raw_readl(®s->channel[ch].src_uuid_hi); | |
310 | ||
311 | uid = hi & 0xffff; | |
312 | seq = (hi >> 16) & 0xffff; | |
313 | ||
314 | if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) | |
315 | goto out; | |
316 | ||
317 | lo = __raw_readl(®s->channel[ch].rx_snap_lo); | |
318 | hi = __raw_readl(®s->channel[ch].rx_snap_hi); | |
319 | ns = ((u64) hi) << 32; | |
320 | ns |= lo; | |
321 | ns <<= TICKS_NS_SHIFT; | |
322 | ||
323 | shhwtstamps = skb_hwtstamps(skb); | |
324 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
325 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
326 | out: | |
327 | __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); | |
328 | } | |
329 | ||
330 | static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) | |
331 | { | |
332 | struct skb_shared_hwtstamps shhwtstamps; | |
333 | struct ixp46x_ts_regs *regs; | |
334 | struct skb_shared_info *shtx; | |
335 | u64 ns; | |
336 | u32 ch, cnt, hi, lo, val; | |
337 | ||
338 | shtx = skb_shinfo(skb); | |
339 | if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) | |
340 | shtx->tx_flags |= SKBTX_IN_PROGRESS; | |
341 | else | |
342 | return; | |
343 | ||
344 | ch = PORT2CHANNEL(port); | |
345 | ||
346 | regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; | |
347 | ||
348 | /* | |
349 | * This really stinks, but we have to poll for the Tx time stamp. | |
350 | * Usually, the time stamp is ready after 4 to 6 microseconds. | |
351 | */ | |
352 | for (cnt = 0; cnt < 100; cnt++) { | |
353 | val = __raw_readl(®s->channel[ch].ch_event); | |
354 | if (val & TX_SNAPSHOT_LOCKED) | |
355 | break; | |
356 | udelay(1); | |
357 | } | |
358 | if (!(val & TX_SNAPSHOT_LOCKED)) { | |
359 | shtx->tx_flags &= ~SKBTX_IN_PROGRESS; | |
360 | return; | |
361 | } | |
362 | ||
363 | lo = __raw_readl(®s->channel[ch].tx_snap_lo); | |
364 | hi = __raw_readl(®s->channel[ch].tx_snap_hi); | |
365 | ns = ((u64) hi) << 32; | |
366 | ns |= lo; | |
367 | ns <<= TICKS_NS_SHIFT; | |
368 | ||
369 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
370 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
371 | skb_tstamp_tx(skb, &shhwtstamps); | |
372 | ||
373 | __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); | |
374 | } | |
375 | ||
376 | static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
377 | { | |
378 | struct hwtstamp_config cfg; | |
379 | struct ixp46x_ts_regs *regs; | |
380 | struct port *port = netdev_priv(netdev); | |
381 | int ch; | |
382 | ||
383 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
384 | return -EFAULT; | |
385 | ||
386 | if (cfg.flags) /* reserved for future extensions */ | |
387 | return -EINVAL; | |
388 | ||
389 | ch = PORT2CHANNEL(port); | |
390 | regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; | |
391 | ||
392 | switch (cfg.tx_type) { | |
393 | case HWTSTAMP_TX_OFF: | |
394 | port->hwts_tx_en = 0; | |
395 | break; | |
396 | case HWTSTAMP_TX_ON: | |
397 | port->hwts_tx_en = 1; | |
398 | break; | |
399 | default: | |
400 | return -ERANGE; | |
401 | } | |
402 | ||
403 | switch (cfg.rx_filter) { | |
404 | case HWTSTAMP_FILTER_NONE: | |
405 | port->hwts_rx_en = 0; | |
406 | break; | |
407 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
408 | port->hwts_rx_en = PTP_SLAVE_MODE; | |
409 | __raw_writel(0, ®s->channel[ch].ch_control); | |
410 | break; | |
411 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
412 | port->hwts_rx_en = PTP_MASTER_MODE; | |
413 | __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); | |
414 | break; | |
415 | default: | |
416 | return -ERANGE; | |
417 | } | |
418 | ||
419 | /* Clear out any old time stamps. */ | |
420 | __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, | |
421 | ®s->channel[ch].ch_event); | |
422 | ||
423 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
424 | } | |
dac2f83f | 425 | |
2098c18d KH |
426 | static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, |
427 | int write, u16 cmd) | |
dac2f83f KH |
428 | { |
429 | int cycles = 0; | |
430 | ||
431 | if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { | |
2098c18d KH |
432 | printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); |
433 | return -1; | |
dac2f83f KH |
434 | } |
435 | ||
436 | if (write) { | |
437 | __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); | |
438 | __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); | |
439 | } | |
440 | __raw_writel(((phy_id << 5) | location) & 0xFF, | |
441 | &mdio_regs->mdio_command[2]); | |
442 | __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, | |
443 | &mdio_regs->mdio_command[3]); | |
444 | ||
445 | while ((cycles < MAX_MDIO_RETRIES) && | |
446 | (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { | |
447 | udelay(1); | |
448 | cycles++; | |
449 | } | |
450 | ||
451 | if (cycles == MAX_MDIO_RETRIES) { | |
2098c18d KH |
452 | printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, |
453 | phy_id); | |
454 | return -1; | |
dac2f83f KH |
455 | } |
456 | ||
457 | #if DEBUG_MDIO | |
2098c18d KH |
458 | printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, |
459 | phy_id, write ? "write" : "read", cycles); | |
dac2f83f KH |
460 | #endif |
461 | ||
462 | if (write) | |
463 | return 0; | |
464 | ||
465 | if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { | |
2098c18d KH |
466 | #if DEBUG_MDIO |
467 | printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, | |
468 | phy_id); | |
469 | #endif | |
470 | return 0xFFFF; /* don't return error */ | |
dac2f83f KH |
471 | } |
472 | ||
473 | return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | | |
2098c18d | 474 | ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); |
dac2f83f KH |
475 | } |
476 | ||
2098c18d | 477 | static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) |
dac2f83f KH |
478 | { |
479 | unsigned long flags; | |
2098c18d | 480 | int ret; |
dac2f83f KH |
481 | |
482 | spin_lock_irqsave(&mdio_lock, flags); | |
2098c18d | 483 | ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); |
dac2f83f | 484 | spin_unlock_irqrestore(&mdio_lock, flags); |
2098c18d KH |
485 | #if DEBUG_MDIO |
486 | printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, | |
487 | phy_id, location, ret); | |
488 | #endif | |
489 | return ret; | |
dac2f83f KH |
490 | } |
491 | ||
2098c18d KH |
492 | static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, |
493 | u16 val) | |
dac2f83f KH |
494 | { |
495 | unsigned long flags; | |
2098c18d | 496 | int ret; |
dac2f83f KH |
497 | |
498 | spin_lock_irqsave(&mdio_lock, flags); | |
2098c18d | 499 | ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); |
dac2f83f | 500 | spin_unlock_irqrestore(&mdio_lock, flags); |
2098c18d | 501 | #if DEBUG_MDIO |
8ae45a53 | 502 | printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", |
2098c18d KH |
503 | bus->name, phy_id, location, val, ret); |
504 | #endif | |
505 | return ret; | |
dac2f83f KH |
506 | } |
507 | ||
2098c18d | 508 | static int ixp4xx_mdio_register(void) |
dac2f83f | 509 | { |
2098c18d | 510 | int err; |
dac2f83f | 511 | |
2098c18d KH |
512 | if (!(mdio_bus = mdiobus_alloc())) |
513 | return -ENOMEM; | |
dac2f83f | 514 | |
5ca328d2 KH |
515 | if (cpu_is_ixp43x()) { |
516 | /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */ | |
517 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH)) | |
3ba8c792 | 518 | return -ENODEV; |
5ca328d2 KH |
519 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; |
520 | } else { | |
521 | /* All MII PHY accesses use NPE-B Ethernet registers */ | |
522 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) | |
3ba8c792 | 523 | return -ENODEV; |
5ca328d2 KH |
524 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; |
525 | } | |
dac2f83f | 526 | |
5ca328d2 KH |
527 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); |
528 | spin_lock_init(&mdio_lock); | |
2098c18d KH |
529 | mdio_bus->name = "IXP4xx MII Bus"; |
530 | mdio_bus->read = &ixp4xx_mdio_read; | |
531 | mdio_bus->write = &ixp4xx_mdio_write; | |
0869b3a4 | 532 | snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); |
dac2f83f | 533 | |
2098c18d KH |
534 | if ((err = mdiobus_register(mdio_bus))) |
535 | mdiobus_free(mdio_bus); | |
536 | return err; | |
dac2f83f KH |
537 | } |
538 | ||
2098c18d | 539 | static void ixp4xx_mdio_remove(void) |
dac2f83f | 540 | { |
2098c18d KH |
541 | mdiobus_unregister(mdio_bus); |
542 | mdiobus_free(mdio_bus); | |
dac2f83f KH |
543 | } |
544 | ||
545 | ||
2098c18d | 546 | static void ixp4xx_adjust_link(struct net_device *dev) |
dac2f83f | 547 | { |
2098c18d KH |
548 | struct port *port = netdev_priv(dev); |
549 | struct phy_device *phydev = port->phydev; | |
550 | ||
551 | if (!phydev->link) { | |
552 | if (port->speed) { | |
553 | port->speed = 0; | |
dac2f83f | 554 | printk(KERN_INFO "%s: link down\n", dev->name); |
dac2f83f | 555 | } |
2098c18d | 556 | return; |
dac2f83f | 557 | } |
dac2f83f | 558 | |
2098c18d KH |
559 | if (port->speed == phydev->speed && port->duplex == phydev->duplex) |
560 | return; | |
dac2f83f | 561 | |
2098c18d KH |
562 | port->speed = phydev->speed; |
563 | port->duplex = phydev->duplex; | |
dac2f83f | 564 | |
2098c18d KH |
565 | if (port->duplex) |
566 | __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, | |
567 | &port->regs->tx_control[0]); | |
568 | else | |
569 | __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, | |
570 | &port->regs->tx_control[0]); | |
dac2f83f | 571 | |
2098c18d KH |
572 | printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", |
573 | dev->name, port->speed, port->duplex ? "full" : "half"); | |
dac2f83f KH |
574 | } |
575 | ||
576 | ||
577 | static inline void debug_pkt(struct net_device *dev, const char *func, | |
578 | u8 *data, int len) | |
579 | { | |
580 | #if DEBUG_PKT_BYTES | |
581 | int i; | |
582 | ||
583 | printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); | |
584 | for (i = 0; i < len; i++) { | |
585 | if (i >= DEBUG_PKT_BYTES) | |
586 | break; | |
587 | printk("%s%02X", | |
588 | ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", | |
589 | data[i]); | |
590 | } | |
591 | printk("\n"); | |
592 | #endif | |
593 | } | |
594 | ||
595 | ||
596 | static inline void debug_desc(u32 phys, struct desc *desc) | |
597 | { | |
598 | #if DEBUG_DESC | |
599 | printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" | |
600 | " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", | |
601 | phys, desc->next, desc->buf_len, desc->pkt_len, | |
602 | desc->data, desc->dest_id, desc->src_id, desc->flags, | |
603 | desc->qos, desc->padlen, desc->vlan_tci, | |
604 | desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, | |
605 | desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, | |
606 | desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, | |
607 | desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); | |
608 | #endif | |
609 | } | |
610 | ||
dac2f83f KH |
611 | static inline int queue_get_desc(unsigned int queue, struct port *port, |
612 | int is_tx) | |
613 | { | |
614 | u32 phys, tab_phys, n_desc; | |
615 | struct desc *tab; | |
616 | ||
e6da96ac | 617 | if (!(phys = qmgr_get_entry(queue))) |
dac2f83f KH |
618 | return -1; |
619 | ||
620 | phys &= ~0x1F; /* mask out non-address bits */ | |
621 | tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); | |
622 | tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); | |
623 | n_desc = (phys - tab_phys) / sizeof(struct desc); | |
624 | BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); | |
625 | debug_desc(phys, &tab[n_desc]); | |
626 | BUG_ON(tab[n_desc].next); | |
627 | return n_desc; | |
628 | } | |
629 | ||
630 | static inline void queue_put_desc(unsigned int queue, u32 phys, | |
631 | struct desc *desc) | |
632 | { | |
dac2f83f KH |
633 | debug_desc(phys, desc); |
634 | BUG_ON(phys & 0x1F); | |
635 | qmgr_put_entry(queue, phys); | |
6a68afe3 KH |
636 | /* Don't check for queue overflow here, we've allocated sufficient |
637 | length and queues >= 32 don't support this check anyway. */ | |
dac2f83f KH |
638 | } |
639 | ||
640 | ||
641 | static inline void dma_unmap_tx(struct port *port, struct desc *desc) | |
642 | { | |
643 | #ifdef __ARMEB__ | |
644 | dma_unmap_single(&port->netdev->dev, desc->data, | |
645 | desc->buf_len, DMA_TO_DEVICE); | |
646 | #else | |
647 | dma_unmap_single(&port->netdev->dev, desc->data & ~3, | |
648 | ALIGN((desc->data & 3) + desc->buf_len, 4), | |
649 | DMA_TO_DEVICE); | |
650 | #endif | |
651 | } | |
652 | ||
653 | ||
654 | static void eth_rx_irq(void *pdev) | |
655 | { | |
656 | struct net_device *dev = pdev; | |
657 | struct port *port = netdev_priv(dev); | |
658 | ||
659 | #if DEBUG_RX | |
660 | printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); | |
661 | #endif | |
662 | qmgr_disable_irq(port->plat->rxq); | |
288379f0 | 663 | napi_schedule(&port->napi); |
dac2f83f KH |
664 | } |
665 | ||
666 | static int eth_poll(struct napi_struct *napi, int budget) | |
667 | { | |
668 | struct port *port = container_of(napi, struct port, napi); | |
669 | struct net_device *dev = port->netdev; | |
670 | unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); | |
671 | int received = 0; | |
672 | ||
673 | #if DEBUG_RX | |
674 | printk(KERN_DEBUG "%s: eth_poll\n", dev->name); | |
675 | #endif | |
676 | ||
677 | while (received < budget) { | |
678 | struct sk_buff *skb; | |
679 | struct desc *desc; | |
680 | int n; | |
681 | #ifdef __ARMEB__ | |
682 | struct sk_buff *temp; | |
683 | u32 phys; | |
684 | #endif | |
685 | ||
686 | if ((n = queue_get_desc(rxq, port, 0)) < 0) { | |
dac2f83f | 687 | #if DEBUG_RX |
288379f0 | 688 | printk(KERN_DEBUG "%s: eth_poll napi_complete\n", |
dac2f83f KH |
689 | dev->name); |
690 | #endif | |
288379f0 | 691 | napi_complete(napi); |
dac2f83f | 692 | qmgr_enable_irq(rxq); |
9733bb8e KH |
693 | if (!qmgr_stat_below_low_watermark(rxq) && |
694 | napi_reschedule(napi)) { /* not empty again */ | |
dac2f83f KH |
695 | #if DEBUG_RX |
696 | printk(KERN_DEBUG "%s: eth_poll" | |
288379f0 | 697 | " napi_reschedule successed\n", |
dac2f83f KH |
698 | dev->name); |
699 | #endif | |
700 | qmgr_disable_irq(rxq); | |
701 | continue; | |
702 | } | |
703 | #if DEBUG_RX | |
704 | printk(KERN_DEBUG "%s: eth_poll all done\n", | |
705 | dev->name); | |
706 | #endif | |
9076689a | 707 | return received; /* all work done */ |
dac2f83f KH |
708 | } |
709 | ||
710 | desc = rx_desc_ptr(port, n); | |
711 | ||
712 | #ifdef __ARMEB__ | |
713 | if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { | |
714 | phys = dma_map_single(&dev->dev, skb->data, | |
715 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
7144decb | 716 | if (dma_mapping_error(&dev->dev, phys)) { |
dac2f83f KH |
717 | dev_kfree_skb(skb); |
718 | skb = NULL; | |
719 | } | |
720 | } | |
721 | #else | |
722 | skb = netdev_alloc_skb(dev, | |
723 | ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); | |
724 | #endif | |
725 | ||
726 | if (!skb) { | |
b4c7d3b0 | 727 | dev->stats.rx_dropped++; |
dac2f83f KH |
728 | /* put the desc back on RX-ready queue */ |
729 | desc->buf_len = MAX_MRU; | |
730 | desc->pkt_len = 0; | |
731 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); | |
732 | continue; | |
733 | } | |
734 | ||
735 | /* process received frame */ | |
736 | #ifdef __ARMEB__ | |
737 | temp = skb; | |
738 | skb = port->rx_buff_tab[n]; | |
739 | dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, | |
740 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
741 | #else | |
5d23a1d2 FT |
742 | dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, |
743 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
dac2f83f KH |
744 | memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], |
745 | ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); | |
746 | #endif | |
747 | skb_reserve(skb, NET_IP_ALIGN); | |
748 | skb_put(skb, desc->pkt_len); | |
749 | ||
750 | debug_pkt(dev, "eth_poll", skb->data, skb->len); | |
751 | ||
32bd93e8 | 752 | ixp_rx_timestamp(port, skb); |
dac2f83f | 753 | skb->protocol = eth_type_trans(skb, dev); |
b4c7d3b0 KH |
754 | dev->stats.rx_packets++; |
755 | dev->stats.rx_bytes += skb->len; | |
dac2f83f KH |
756 | netif_receive_skb(skb); |
757 | ||
758 | /* put the new buffer on RX-free queue */ | |
759 | #ifdef __ARMEB__ | |
760 | port->rx_buff_tab[n] = temp; | |
761 | desc->data = phys + NET_IP_ALIGN; | |
762 | #endif | |
763 | desc->buf_len = MAX_MRU; | |
764 | desc->pkt_len = 0; | |
765 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); | |
766 | received++; | |
767 | } | |
768 | ||
769 | #if DEBUG_RX | |
770 | printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); | |
771 | #endif | |
772 | return received; /* not all work done */ | |
773 | } | |
774 | ||
775 | ||
776 | static void eth_txdone_irq(void *unused) | |
777 | { | |
778 | u32 phys; | |
779 | ||
780 | #if DEBUG_TX | |
781 | printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); | |
782 | #endif | |
e6da96ac | 783 | while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { |
dac2f83f KH |
784 | u32 npe_id, n_desc; |
785 | struct port *port; | |
786 | struct desc *desc; | |
787 | int start; | |
788 | ||
789 | npe_id = phys & 3; | |
790 | BUG_ON(npe_id >= MAX_NPES); | |
791 | port = npe_port_tab[npe_id]; | |
792 | BUG_ON(!port); | |
793 | phys &= ~0x1F; /* mask out non-address bits */ | |
794 | n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); | |
795 | BUG_ON(n_desc >= TX_DESCS); | |
796 | desc = tx_desc_ptr(port, n_desc); | |
797 | debug_desc(phys, desc); | |
798 | ||
799 | if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ | |
b4c7d3b0 KH |
800 | port->netdev->stats.tx_packets++; |
801 | port->netdev->stats.tx_bytes += desc->pkt_len; | |
dac2f83f KH |
802 | |
803 | dma_unmap_tx(port, desc); | |
804 | #if DEBUG_TX | |
805 | printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", | |
806 | port->netdev->name, port->tx_buff_tab[n_desc]); | |
807 | #endif | |
808 | free_buffer_irq(port->tx_buff_tab[n_desc]); | |
809 | port->tx_buff_tab[n_desc] = NULL; | |
810 | } | |
811 | ||
9733bb8e | 812 | start = qmgr_stat_below_low_watermark(port->plat->txreadyq); |
dac2f83f | 813 | queue_put_desc(port->plat->txreadyq, phys, desc); |
9733bb8e | 814 | if (start) { /* TX-ready queue was empty */ |
dac2f83f KH |
815 | #if DEBUG_TX |
816 | printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", | |
817 | port->netdev->name); | |
818 | #endif | |
819 | netif_wake_queue(port->netdev); | |
820 | } | |
821 | } | |
822 | } | |
823 | ||
824 | static int eth_xmit(struct sk_buff *skb, struct net_device *dev) | |
825 | { | |
826 | struct port *port = netdev_priv(dev); | |
827 | unsigned int txreadyq = port->plat->txreadyq; | |
828 | int len, offset, bytes, n; | |
829 | void *mem; | |
830 | u32 phys; | |
831 | struct desc *desc; | |
832 | ||
833 | #if DEBUG_TX | |
834 | printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); | |
835 | #endif | |
836 | ||
837 | if (unlikely(skb->len > MAX_MRU)) { | |
838 | dev_kfree_skb(skb); | |
b4c7d3b0 | 839 | dev->stats.tx_errors++; |
dac2f83f KH |
840 | return NETDEV_TX_OK; |
841 | } | |
842 | ||
843 | debug_pkt(dev, "eth_xmit", skb->data, skb->len); | |
844 | ||
845 | len = skb->len; | |
846 | #ifdef __ARMEB__ | |
847 | offset = 0; /* no need to keep alignment */ | |
848 | bytes = len; | |
849 | mem = skb->data; | |
850 | #else | |
851 | offset = (int)skb->data & 3; /* keep 32-bit alignment */ | |
852 | bytes = ALIGN(offset + len, 4); | |
853 | if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { | |
854 | dev_kfree_skb(skb); | |
b4c7d3b0 | 855 | dev->stats.tx_dropped++; |
dac2f83f KH |
856 | return NETDEV_TX_OK; |
857 | } | |
858 | memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); | |
dac2f83f KH |
859 | #endif |
860 | ||
861 | phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); | |
7144decb | 862 | if (dma_mapping_error(&dev->dev, phys)) { |
dac2f83f | 863 | dev_kfree_skb(skb); |
32bd93e8 | 864 | #ifndef __ARMEB__ |
dac2f83f KH |
865 | kfree(mem); |
866 | #endif | |
b4c7d3b0 | 867 | dev->stats.tx_dropped++; |
dac2f83f KH |
868 | return NETDEV_TX_OK; |
869 | } | |
870 | ||
871 | n = queue_get_desc(txreadyq, port, 1); | |
872 | BUG_ON(n < 0); | |
873 | desc = tx_desc_ptr(port, n); | |
874 | ||
875 | #ifdef __ARMEB__ | |
876 | port->tx_buff_tab[n] = skb; | |
877 | #else | |
878 | port->tx_buff_tab[n] = mem; | |
879 | #endif | |
880 | desc->data = phys + offset; | |
881 | desc->buf_len = desc->pkt_len = len; | |
882 | ||
883 | /* NPE firmware pads short frames with zeros internally */ | |
884 | wmb(); | |
885 | queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); | |
dac2f83f | 886 | |
9733bb8e | 887 | if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ |
dac2f83f KH |
888 | #if DEBUG_TX |
889 | printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); | |
890 | #endif | |
891 | netif_stop_queue(dev); | |
892 | /* we could miss TX ready interrupt */ | |
6a68afe3 | 893 | /* really empty in fact */ |
9733bb8e | 894 | if (!qmgr_stat_below_low_watermark(txreadyq)) { |
dac2f83f KH |
895 | #if DEBUG_TX |
896 | printk(KERN_DEBUG "%s: eth_xmit ready again\n", | |
897 | dev->name); | |
898 | #endif | |
899 | netif_wake_queue(dev); | |
900 | } | |
901 | } | |
902 | ||
903 | #if DEBUG_TX | |
904 | printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); | |
905 | #endif | |
32bd93e8 RC |
906 | |
907 | ixp_tx_timestamp(port, skb); | |
908 | skb_tx_timestamp(skb); | |
909 | ||
910 | #ifndef __ARMEB__ | |
911 | dev_kfree_skb(skb); | |
912 | #endif | |
dac2f83f KH |
913 | return NETDEV_TX_OK; |
914 | } | |
915 | ||
916 | ||
dac2f83f KH |
917 | static void eth_set_mcast_list(struct net_device *dev) |
918 | { | |
919 | struct port *port = netdev_priv(dev); | |
22bedad3 | 920 | struct netdev_hw_addr *ha; |
dac2f83f | 921 | u8 diffs[ETH_ALEN], *addr; |
3b9a7728 | 922 | int i; |
95e3bb7a RC |
923 | static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; |
924 | ||
925 | if (dev->flags & IFF_ALLMULTI) { | |
926 | for (i = 0; i < ETH_ALEN; i++) { | |
927 | __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); | |
928 | __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); | |
929 | } | |
930 | __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, | |
931 | &port->regs->rx_control[0]); | |
932 | return; | |
933 | } | |
dac2f83f | 934 | |
3b9a7728 | 935 | if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { |
dac2f83f KH |
936 | __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, |
937 | &port->regs->rx_control[0]); | |
938 | return; | |
939 | } | |
940 | ||
941 | memset(diffs, 0, ETH_ALEN); | |
dac2f83f | 942 | |
3b9a7728 | 943 | addr = NULL; |
22bedad3 | 944 | netdev_for_each_mc_addr(ha, dev) { |
3b9a7728 | 945 | if (!addr) |
22bedad3 | 946 | addr = ha->addr; /* first MAC address */ |
dac2f83f | 947 | for (i = 0; i < ETH_ALEN; i++) |
22bedad3 | 948 | diffs[i] |= addr[i] ^ ha->addr[i]; |
3b9a7728 | 949 | } |
dac2f83f KH |
950 | |
951 | for (i = 0; i < ETH_ALEN; i++) { | |
952 | __raw_writel(addr[i], &port->regs->mcast_addr[i]); | |
953 | __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); | |
954 | } | |
955 | ||
956 | __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, | |
957 | &port->regs->rx_control[0]); | |
958 | } | |
959 | ||
960 | ||
961 | static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
962 | { | |
963 | struct port *port = netdev_priv(dev); | |
dac2f83f KH |
964 | |
965 | if (!netif_running(dev)) | |
966 | return -EINVAL; | |
28b04113 | 967 | |
32bd93e8 RC |
968 | if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP) |
969 | return hwtstamp_ioctl(dev, req, cmd); | |
970 | ||
28b04113 | 971 | return phy_mii_ioctl(port->phydev, req, cmd); |
dac2f83f KH |
972 | } |
973 | ||
490b7722 KH |
974 | /* ethtool support */ |
975 | ||
976 | static void ixp4xx_get_drvinfo(struct net_device *dev, | |
977 | struct ethtool_drvinfo *info) | |
978 | { | |
979 | struct port *port = netdev_priv(dev); | |
7826d43f JP |
980 | |
981 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); | |
490b7722 KH |
982 | snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", |
983 | port->firmware[0], port->firmware[1], | |
984 | port->firmware[2], port->firmware[3]); | |
7826d43f | 985 | strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); |
dac2f83f KH |
986 | } |
987 | ||
490b7722 KH |
988 | static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
989 | { | |
990 | struct port *port = netdev_priv(dev); | |
991 | return phy_ethtool_gset(port->phydev, cmd); | |
992 | } | |
993 | ||
994 | static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
995 | { | |
996 | struct port *port = netdev_priv(dev); | |
997 | return phy_ethtool_sset(port->phydev, cmd); | |
998 | } | |
999 | ||
1000 | static int ixp4xx_nway_reset(struct net_device *dev) | |
1001 | { | |
1002 | struct port *port = netdev_priv(dev); | |
1003 | return phy_start_aneg(port->phydev); | |
1004 | } | |
1005 | ||
509a7c25 | 1006 | int ixp46x_phc_index = -1; |
8b82f7c3 | 1007 | EXPORT_SYMBOL_GPL(ixp46x_phc_index); |
509a7c25 RC |
1008 | |
1009 | static int ixp4xx_get_ts_info(struct net_device *dev, | |
1010 | struct ethtool_ts_info *info) | |
1011 | { | |
1012 | if (!cpu_is_ixp46x()) { | |
1013 | info->so_timestamping = | |
1014 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1015 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1016 | SOF_TIMESTAMPING_SOFTWARE; | |
1017 | info->phc_index = -1; | |
1018 | return 0; | |
1019 | } | |
1020 | info->so_timestamping = | |
1021 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1022 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1023 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1024 | info->phc_index = ixp46x_phc_index; | |
1025 | info->tx_types = | |
1026 | (1 << HWTSTAMP_TX_OFF) | | |
1027 | (1 << HWTSTAMP_TX_ON); | |
1028 | info->rx_filters = | |
1029 | (1 << HWTSTAMP_FILTER_NONE) | | |
1030 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | | |
1031 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); | |
1032 | return 0; | |
1033 | } | |
1034 | ||
0fc0b732 | 1035 | static const struct ethtool_ops ixp4xx_ethtool_ops = { |
490b7722 KH |
1036 | .get_drvinfo = ixp4xx_get_drvinfo, |
1037 | .get_settings = ixp4xx_get_settings, | |
1038 | .set_settings = ixp4xx_set_settings, | |
1039 | .nway_reset = ixp4xx_nway_reset, | |
1040 | .get_link = ethtool_op_get_link, | |
509a7c25 | 1041 | .get_ts_info = ixp4xx_get_ts_info, |
490b7722 KH |
1042 | }; |
1043 | ||
dac2f83f KH |
1044 | |
1045 | static int request_queues(struct port *port) | |
1046 | { | |
1047 | int err; | |
1048 | ||
e6da96ac | 1049 | err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, |
2e418400 | 1050 | "%s:RX-free", port->netdev->name); |
dac2f83f KH |
1051 | if (err) |
1052 | return err; | |
1053 | ||
e6da96ac | 1054 | err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, |
2e418400 | 1055 | "%s:RX", port->netdev->name); |
dac2f83f KH |
1056 | if (err) |
1057 | goto rel_rxfree; | |
1058 | ||
e6da96ac | 1059 | err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, |
2e418400 | 1060 | "%s:TX", port->netdev->name); |
dac2f83f KH |
1061 | if (err) |
1062 | goto rel_rx; | |
1063 | ||
e6da96ac | 1064 | err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, |
2e418400 | 1065 | "%s:TX-ready", port->netdev->name); |
dac2f83f KH |
1066 | if (err) |
1067 | goto rel_tx; | |
1068 | ||
1069 | /* TX-done queue handles skbs sent out by the NPEs */ | |
1070 | if (!ports_open) { | |
e6da96ac | 1071 | err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, |
2e418400 | 1072 | "%s:TX-done", DRV_NAME); |
dac2f83f KH |
1073 | if (err) |
1074 | goto rel_txready; | |
1075 | } | |
1076 | return 0; | |
1077 | ||
1078 | rel_txready: | |
1079 | qmgr_release_queue(port->plat->txreadyq); | |
1080 | rel_tx: | |
1081 | qmgr_release_queue(TX_QUEUE(port->id)); | |
1082 | rel_rx: | |
1083 | qmgr_release_queue(port->plat->rxq); | |
1084 | rel_rxfree: | |
1085 | qmgr_release_queue(RXFREE_QUEUE(port->id)); | |
1086 | printk(KERN_DEBUG "%s: unable to request hardware queues\n", | |
1087 | port->netdev->name); | |
1088 | return err; | |
1089 | } | |
1090 | ||
1091 | static void release_queues(struct port *port) | |
1092 | { | |
1093 | qmgr_release_queue(RXFREE_QUEUE(port->id)); | |
1094 | qmgr_release_queue(port->plat->rxq); | |
1095 | qmgr_release_queue(TX_QUEUE(port->id)); | |
1096 | qmgr_release_queue(port->plat->txreadyq); | |
1097 | ||
1098 | if (!ports_open) | |
1099 | qmgr_release_queue(TXDONE_QUEUE); | |
1100 | } | |
1101 | ||
1102 | static int init_queues(struct port *port) | |
1103 | { | |
1104 | int i; | |
1105 | ||
1a490117 XW |
1106 | if (!ports_open) { |
1107 | dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, | |
1108 | POOL_ALLOC_SIZE, 32, 0); | |
1109 | if (!dma_pool) | |
dac2f83f | 1110 | return -ENOMEM; |
1a490117 | 1111 | } |
dac2f83f KH |
1112 | |
1113 | if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, | |
1114 | &port->desc_tab_phys))) | |
1115 | return -ENOMEM; | |
1116 | memset(port->desc_tab, 0, POOL_ALLOC_SIZE); | |
1117 | memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ | |
1118 | memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); | |
1119 | ||
1120 | /* Setup RX buffers */ | |
1121 | for (i = 0; i < RX_DESCS; i++) { | |
1122 | struct desc *desc = rx_desc_ptr(port, i); | |
1123 | buffer_t *buff; /* skb or kmalloc()ated memory */ | |
1124 | void *data; | |
1125 | #ifdef __ARMEB__ | |
1126 | if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) | |
1127 | return -ENOMEM; | |
1128 | data = buff->data; | |
1129 | #else | |
1130 | if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) | |
1131 | return -ENOMEM; | |
1132 | data = buff; | |
1133 | #endif | |
1134 | desc->buf_len = MAX_MRU; | |
1135 | desc->data = dma_map_single(&port->netdev->dev, data, | |
1136 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
7144decb | 1137 | if (dma_mapping_error(&port->netdev->dev, desc->data)) { |
dac2f83f KH |
1138 | free_buffer(buff); |
1139 | return -EIO; | |
1140 | } | |
1141 | desc->data += NET_IP_ALIGN; | |
1142 | port->rx_buff_tab[i] = buff; | |
1143 | } | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | static void destroy_queues(struct port *port) | |
1149 | { | |
1150 | int i; | |
1151 | ||
1152 | if (port->desc_tab) { | |
1153 | for (i = 0; i < RX_DESCS; i++) { | |
1154 | struct desc *desc = rx_desc_ptr(port, i); | |
1155 | buffer_t *buff = port->rx_buff_tab[i]; | |
1156 | if (buff) { | |
1157 | dma_unmap_single(&port->netdev->dev, | |
1158 | desc->data - NET_IP_ALIGN, | |
1159 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
1160 | free_buffer(buff); | |
1161 | } | |
1162 | } | |
1163 | for (i = 0; i < TX_DESCS; i++) { | |
1164 | struct desc *desc = tx_desc_ptr(port, i); | |
1165 | buffer_t *buff = port->tx_buff_tab[i]; | |
1166 | if (buff) { | |
1167 | dma_unmap_tx(port, desc); | |
1168 | free_buffer(buff); | |
1169 | } | |
1170 | } | |
1171 | dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); | |
1172 | port->desc_tab = NULL; | |
1173 | } | |
1174 | ||
1175 | if (!ports_open && dma_pool) { | |
1176 | dma_pool_destroy(dma_pool); | |
1177 | dma_pool = NULL; | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | static int eth_open(struct net_device *dev) | |
1182 | { | |
1183 | struct port *port = netdev_priv(dev); | |
1184 | struct npe *npe = port->npe; | |
1185 | struct msg msg; | |
1186 | int i, err; | |
1187 | ||
1188 | if (!npe_running(npe)) { | |
1189 | err = npe_load_firmware(npe, npe_name(npe), &dev->dev); | |
1190 | if (err) | |
1191 | return err; | |
1192 | ||
1193 | if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { | |
1194 | printk(KERN_ERR "%s: %s not responding\n", dev->name, | |
1195 | npe_name(npe)); | |
1196 | return -EIO; | |
1197 | } | |
490b7722 KH |
1198 | port->firmware[0] = msg.byte4; |
1199 | port->firmware[1] = msg.byte5; | |
1200 | port->firmware[2] = msg.byte6; | |
1201 | port->firmware[3] = msg.byte7; | |
dac2f83f KH |
1202 | } |
1203 | ||
dac2f83f KH |
1204 | memset(&msg, 0, sizeof(msg)); |
1205 | msg.cmd = NPE_VLAN_SETRXQOSENTRY; | |
1206 | msg.eth_id = port->id; | |
1207 | msg.byte5 = port->plat->rxq | 0x80; | |
1208 | msg.byte7 = port->plat->rxq << 4; | |
1209 | for (i = 0; i < 8; i++) { | |
1210 | msg.byte3 = i; | |
1211 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) | |
1212 | return -EIO; | |
1213 | } | |
1214 | ||
1215 | msg.cmd = NPE_EDB_SETPORTADDRESS; | |
1216 | msg.eth_id = PHYSICAL_ID(port->id); | |
1217 | msg.byte2 = dev->dev_addr[0]; | |
1218 | msg.byte3 = dev->dev_addr[1]; | |
1219 | msg.byte4 = dev->dev_addr[2]; | |
1220 | msg.byte5 = dev->dev_addr[3]; | |
1221 | msg.byte6 = dev->dev_addr[4]; | |
1222 | msg.byte7 = dev->dev_addr[5]; | |
1223 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) | |
1224 | return -EIO; | |
1225 | ||
1226 | memset(&msg, 0, sizeof(msg)); | |
1227 | msg.cmd = NPE_FW_SETFIREWALLMODE; | |
1228 | msg.eth_id = port->id; | |
1229 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) | |
1230 | return -EIO; | |
1231 | ||
1232 | if ((err = request_queues(port)) != 0) | |
1233 | return err; | |
1234 | ||
1235 | if ((err = init_queues(port)) != 0) { | |
1236 | destroy_queues(port); | |
1237 | release_queues(port); | |
1238 | return err; | |
1239 | } | |
1240 | ||
2098c18d KH |
1241 | port->speed = 0; /* force "link up" message */ |
1242 | phy_start(port->phydev); | |
1243 | ||
dac2f83f KH |
1244 | for (i = 0; i < ETH_ALEN; i++) |
1245 | __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); | |
1246 | __raw_writel(0x08, &port->regs->random_seed); | |
1247 | __raw_writel(0x12, &port->regs->partial_empty_threshold); | |
1248 | __raw_writel(0x30, &port->regs->partial_full_threshold); | |
1249 | __raw_writel(0x08, &port->regs->tx_start_bytes); | |
1250 | __raw_writel(0x15, &port->regs->tx_deferral); | |
1251 | __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); | |
1252 | __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); | |
1253 | __raw_writel(0x80, &port->regs->slot_time); | |
1254 | __raw_writel(0x01, &port->regs->int_clock_threshold); | |
1255 | ||
1256 | /* Populate queues with buffers, no failure after this point */ | |
1257 | for (i = 0; i < TX_DESCS; i++) | |
1258 | queue_put_desc(port->plat->txreadyq, | |
1259 | tx_desc_phys(port, i), tx_desc_ptr(port, i)); | |
1260 | ||
1261 | for (i = 0; i < RX_DESCS; i++) | |
1262 | queue_put_desc(RXFREE_QUEUE(port->id), | |
1263 | rx_desc_phys(port, i), rx_desc_ptr(port, i)); | |
1264 | ||
1265 | __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); | |
1266 | __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); | |
1267 | __raw_writel(0, &port->regs->rx_control[1]); | |
1268 | __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); | |
1269 | ||
1270 | napi_enable(&port->napi); | |
dac2f83f KH |
1271 | eth_set_mcast_list(dev); |
1272 | netif_start_queue(dev); | |
dac2f83f KH |
1273 | |
1274 | qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, | |
1275 | eth_rx_irq, dev); | |
1276 | if (!ports_open) { | |
1277 | qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, | |
1278 | eth_txdone_irq, NULL); | |
1279 | qmgr_enable_irq(TXDONE_QUEUE); | |
1280 | } | |
1281 | ports_open++; | |
1282 | /* we may already have RX data, enables IRQ */ | |
288379f0 | 1283 | napi_schedule(&port->napi); |
dac2f83f KH |
1284 | return 0; |
1285 | } | |
1286 | ||
1287 | static int eth_close(struct net_device *dev) | |
1288 | { | |
1289 | struct port *port = netdev_priv(dev); | |
1290 | struct msg msg; | |
1291 | int buffs = RX_DESCS; /* allocated RX buffers */ | |
1292 | int i; | |
1293 | ||
1294 | ports_open--; | |
1295 | qmgr_disable_irq(port->plat->rxq); | |
1296 | napi_disable(&port->napi); | |
1297 | netif_stop_queue(dev); | |
1298 | ||
1299 | while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) | |
1300 | buffs--; | |
1301 | ||
1302 | memset(&msg, 0, sizeof(msg)); | |
1303 | msg.cmd = NPE_SETLOOPBACK_MODE; | |
1304 | msg.eth_id = port->id; | |
1305 | msg.byte3 = 1; | |
1306 | if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) | |
1307 | printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); | |
1308 | ||
1309 | i = 0; | |
1310 | do { /* drain RX buffers */ | |
1311 | while (queue_get_desc(port->plat->rxq, port, 0) >= 0) | |
1312 | buffs--; | |
1313 | if (!buffs) | |
1314 | break; | |
1315 | if (qmgr_stat_empty(TX_QUEUE(port->id))) { | |
1316 | /* we have to inject some packet */ | |
1317 | struct desc *desc; | |
1318 | u32 phys; | |
1319 | int n = queue_get_desc(port->plat->txreadyq, port, 1); | |
1320 | BUG_ON(n < 0); | |
1321 | desc = tx_desc_ptr(port, n); | |
1322 | phys = tx_desc_phys(port, n); | |
1323 | desc->buf_len = desc->pkt_len = 1; | |
1324 | wmb(); | |
1325 | queue_put_desc(TX_QUEUE(port->id), phys, desc); | |
1326 | } | |
1327 | udelay(1); | |
1328 | } while (++i < MAX_CLOSE_WAIT); | |
1329 | ||
1330 | if (buffs) | |
1331 | printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" | |
1332 | " left in NPE\n", dev->name, buffs); | |
1333 | #if DEBUG_CLOSE | |
1334 | if (!buffs) | |
1335 | printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); | |
1336 | #endif | |
1337 | ||
1338 | buffs = TX_DESCS; | |
1339 | while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) | |
1340 | buffs--; /* cancel TX */ | |
1341 | ||
1342 | i = 0; | |
1343 | do { | |
1344 | while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) | |
1345 | buffs--; | |
1346 | if (!buffs) | |
1347 | break; | |
1348 | } while (++i < MAX_CLOSE_WAIT); | |
1349 | ||
1350 | if (buffs) | |
1351 | printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " | |
1352 | "left in NPE\n", dev->name, buffs); | |
1353 | #if DEBUG_CLOSE | |
1354 | if (!buffs) | |
1355 | printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); | |
1356 | #endif | |
1357 | ||
1358 | msg.byte3 = 0; | |
1359 | if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) | |
1360 | printk(KERN_CRIT "%s: unable to disable loopback\n", | |
1361 | dev->name); | |
1362 | ||
2098c18d | 1363 | phy_stop(port->phydev); |
dac2f83f KH |
1364 | |
1365 | if (!ports_open) | |
1366 | qmgr_disable_irq(TXDONE_QUEUE); | |
dac2f83f KH |
1367 | destroy_queues(port); |
1368 | release_queues(port); | |
1369 | return 0; | |
1370 | } | |
1371 | ||
59f8500e KH |
1372 | static const struct net_device_ops ixp4xx_netdev_ops = { |
1373 | .ndo_open = eth_open, | |
1374 | .ndo_stop = eth_close, | |
1375 | .ndo_start_xmit = eth_xmit, | |
afc4b13d | 1376 | .ndo_set_rx_mode = eth_set_mcast_list, |
59f8500e | 1377 | .ndo_do_ioctl = eth_ioctl, |
635ecaa7 | 1378 | .ndo_change_mtu = eth_change_mtu, |
240c102d BH |
1379 | .ndo_set_mac_address = eth_mac_addr, |
1380 | .ndo_validate_addr = eth_validate_addr, | |
59f8500e KH |
1381 | }; |
1382 | ||
9871b639 | 1383 | static int eth_init_one(struct platform_device *pdev) |
dac2f83f KH |
1384 | { |
1385 | struct port *port; | |
1386 | struct net_device *dev; | |
1387 | struct eth_plat_info *plat = pdev->dev.platform_data; | |
1388 | u32 regs_phys; | |
0e53c7f9 | 1389 | char phy_id[MII_BUS_ID_SIZE + 3]; |
dac2f83f KH |
1390 | int err; |
1391 | ||
32bd93e8 RC |
1392 | if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) { |
1393 | pr_err("ixp4xx_eth: bad ptp filter\n"); | |
1394 | return -EINVAL; | |
1395 | } | |
1396 | ||
dac2f83f KH |
1397 | if (!(dev = alloc_etherdev(sizeof(struct port)))) |
1398 | return -ENOMEM; | |
1399 | ||
1400 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1401 | port = netdev_priv(dev); | |
1402 | port->netdev = dev; | |
1403 | port->id = pdev->id; | |
1404 | ||
1405 | switch (port->id) { | |
1406 | case IXP4XX_ETH_NPEA: | |
1407 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; | |
1408 | regs_phys = IXP4XX_EthA_BASE_PHYS; | |
1409 | break; | |
1410 | case IXP4XX_ETH_NPEB: | |
1411 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; | |
1412 | regs_phys = IXP4XX_EthB_BASE_PHYS; | |
1413 | break; | |
1414 | case IXP4XX_ETH_NPEC: | |
1415 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; | |
1416 | regs_phys = IXP4XX_EthC_BASE_PHYS; | |
1417 | break; | |
1418 | default: | |
3ba8c792 | 1419 | err = -ENODEV; |
dac2f83f KH |
1420 | goto err_free; |
1421 | } | |
1422 | ||
59f8500e | 1423 | dev->netdev_ops = &ixp4xx_netdev_ops; |
490b7722 | 1424 | dev->ethtool_ops = &ixp4xx_ethtool_ops; |
dac2f83f KH |
1425 | dev->tx_queue_len = 100; |
1426 | ||
1427 | netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); | |
1428 | ||
1429 | if (!(port->npe = npe_request(NPE_ID(port->id)))) { | |
1430 | err = -EIO; | |
1431 | goto err_free; | |
1432 | } | |
1433 | ||
dac2f83f KH |
1434 | port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); |
1435 | if (!port->mem_res) { | |
1436 | err = -EBUSY; | |
7aa6a478 | 1437 | goto err_npe_rel; |
dac2f83f KH |
1438 | } |
1439 | ||
1440 | port->plat = plat; | |
1441 | npe_port_tab[NPE_ID(port->id)] = port; | |
1442 | memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); | |
1443 | ||
1444 | platform_set_drvdata(pdev, dev); | |
1445 | ||
1446 | __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, | |
1447 | &port->regs->core_control); | |
1448 | udelay(50); | |
1449 | __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); | |
1450 | udelay(50); | |
1451 | ||
7465ac3c FF |
1452 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, |
1453 | mdio_bus->id, plat->phy); | |
2098c18d KH |
1454 | port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0, |
1455 | PHY_INTERFACE_MODE_MII); | |
0c661001 AL |
1456 | if (IS_ERR(port->phydev)) { |
1457 | err = PTR_ERR(port->phydev); | |
7aa6a478 | 1458 | goto err_free_mem; |
0c661001 | 1459 | } |
2098c18d KH |
1460 | |
1461 | port->phydev->irq = PHY_POLL; | |
dac2f83f | 1462 | |
7aa6a478 KH |
1463 | if ((err = register_netdev(dev))) |
1464 | goto err_phy_dis; | |
1465 | ||
dac2f83f KH |
1466 | printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, |
1467 | npe_name(port->npe)); | |
1468 | ||
dac2f83f KH |
1469 | return 0; |
1470 | ||
7aa6a478 KH |
1471 | err_phy_dis: |
1472 | phy_disconnect(port->phydev); | |
1473 | err_free_mem: | |
1474 | npe_port_tab[NPE_ID(port->id)] = NULL; | |
1475 | platform_set_drvdata(pdev, NULL); | |
1476 | release_resource(port->mem_res); | |
dac2f83f KH |
1477 | err_npe_rel: |
1478 | npe_release(port->npe); | |
1479 | err_free: | |
1480 | free_netdev(dev); | |
1481 | return err; | |
1482 | } | |
1483 | ||
9871b639 | 1484 | static int eth_remove_one(struct platform_device *pdev) |
dac2f83f KH |
1485 | { |
1486 | struct net_device *dev = platform_get_drvdata(pdev); | |
1487 | struct port *port = netdev_priv(dev); | |
1488 | ||
1489 | unregister_netdev(dev); | |
7aa6a478 | 1490 | phy_disconnect(port->phydev); |
dac2f83f KH |
1491 | npe_port_tab[NPE_ID(port->id)] = NULL; |
1492 | platform_set_drvdata(pdev, NULL); | |
1493 | npe_release(port->npe); | |
1494 | release_resource(port->mem_res); | |
1495 | free_netdev(dev); | |
1496 | return 0; | |
1497 | } | |
1498 | ||
3c36a837 | 1499 | static struct platform_driver ixp4xx_eth_driver = { |
dac2f83f KH |
1500 | .driver.name = DRV_NAME, |
1501 | .probe = eth_init_one, | |
1502 | .remove = eth_remove_one, | |
1503 | }; | |
1504 | ||
1505 | static int __init eth_init_module(void) | |
1506 | { | |
2098c18d | 1507 | int err; |
2098c18d KH |
1508 | if ((err = ixp4xx_mdio_register())) |
1509 | return err; | |
3c36a837 | 1510 | return platform_driver_register(&ixp4xx_eth_driver); |
dac2f83f KH |
1511 | } |
1512 | ||
1513 | static void __exit eth_cleanup_module(void) | |
1514 | { | |
3c36a837 | 1515 | platform_driver_unregister(&ixp4xx_eth_driver); |
2098c18d | 1516 | ixp4xx_mdio_remove(); |
dac2f83f KH |
1517 | } |
1518 | ||
1519 | MODULE_AUTHOR("Krzysztof Halasa"); | |
1520 | MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); | |
1521 | MODULE_LICENSE("GPL v2"); | |
1522 | MODULE_ALIAS("platform:ixp4xx_eth"); | |
1523 | module_init(eth_init_module); | |
1524 | module_exit(eth_cleanup_module); |