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ethoc: write number of TX buffers in init_ring
[deliverable/linux.git] / drivers / net / ethoc.c
CommitLineData
a1702857
TR		 1/*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14#include <linux/etherdevice.h>
15#include <linux/crc32.h>
16#include <linux/io.h>
17#include <linux/mii.h>
18#include <linux/phy.h>
19#include <linux/platform_device.h>
d43c36dc 20#include <linux/sched.h>
5a0e3ad6 21#include <linux/slab.h>
a1702857
TR		 22#include <net/ethoc.h>
23
0baa080c
TC		 24static int buffer_size = 0x8000; /* 32 KBytes */
25module_param(buffer_size, int, 0);
26MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
27
a1702857
TR		 28/* register offsets */
29#define MODER 0x00
30#define INT_SOURCE 0x04
31#define INT_MASK 0x08
32#define IPGT 0x0c
33#define IPGR1 0x10
34#define IPGR2 0x14
35#define PACKETLEN 0x18
36#define COLLCONF 0x1c
37#define TX_BD_NUM 0x20
38#define CTRLMODER 0x24
39#define MIIMODER 0x28
40#define MIICOMMAND 0x2c
41#define MIIADDRESS 0x30
42#define MIITX_DATA 0x34
43#define MIIRX_DATA 0x38
44#define MIISTATUS 0x3c
45#define MAC_ADDR0 0x40
46#define MAC_ADDR1 0x44
47#define ETH_HASH0 0x48
48#define ETH_HASH1 0x4c
49#define ETH_TXCTRL 0x50
50
51/* mode register */
52#define MODER_RXEN (1 << 0) /* receive enable */
53#define MODER_TXEN (1 << 1) /* transmit enable */
54#define MODER_NOPRE (1 << 2) /* no preamble */
55#define MODER_BRO (1 << 3) /* broadcast address */
56#define MODER_IAM (1 << 4) /* individual address mode */
57#define MODER_PRO (1 << 5) /* promiscuous mode */
58#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59#define MODER_LOOP (1 << 7) /* loopback */
60#define MODER_NBO (1 << 8) /* no back-off */
61#define MODER_EDE (1 << 9) /* excess defer enable */
62#define MODER_FULLD (1 << 10) /* full duplex */
63#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64#define MODER_DCRC (1 << 12) /* delayed CRC enable */
65#define MODER_CRC (1 << 13) /* CRC enable */
66#define MODER_HUGE (1 << 14) /* huge packets enable */
67#define MODER_PAD (1 << 15) /* padding enabled */
68#define MODER_RSM (1 << 16) /* receive small packets */
69
70/* interrupt source and mask registers */
71#define INT_MASK_TXF (1 << 0) /* transmit frame */
72#define INT_MASK_TXE (1 << 1) /* transmit error */
73#define INT_MASK_RXF (1 << 2) /* receive frame */
74#define INT_MASK_RXE (1 << 3) /* receive error */
75#define INT_MASK_BUSY (1 << 4)
76#define INT_MASK_TXC (1 << 5) /* transmit control frame */
77#define INT_MASK_RXC (1 << 6) /* receive control frame */
78
79#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
81
82#define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
86 INT_MASK_BUSY \
87 )
88
89/* packet length register */
90#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
93 PACKETLEN_MAX(max))
94
95/* transmit buffer number register */
96#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
97
98/* control module mode register */
99#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
102
103/* MII mode register */
104#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105#define MIIMODER_NOPRE (1 << 8) /* no preamble */
106
107/* MII command register */
108#define MIICOMMAND_SCAN (1 << 0) /* scan status */
109#define MIICOMMAND_READ (1 << 1) /* read status */
110#define MIICOMMAND_WRITE (1 << 2) /* write control data */
111
112/* MII address register */
113#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
117
118/* MII transmit data register */
119#define MIITX_DATA_VAL(x) ((x) & 0xffff)
120
121/* MII receive data register */
122#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
123
124/* MII status register */
125#define MIISTATUS_LINKFAIL (1 << 0)
126#define MIISTATUS_BUSY (1 << 1)
127#define MIISTATUS_INVALID (1 << 2)
128
129/* TX buffer descriptor */
130#define TX_BD_CS (1 << 0) /* carrier sense lost */
131#define TX_BD_DF (1 << 1) /* defer indication */
132#define TX_BD_LC (1 << 2) /* late collision */
133#define TX_BD_RL (1 << 3) /* retransmission limit */
134#define TX_BD_RETRY_MASK (0x00f0)
135#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136#define TX_BD_UR (1 << 8) /* transmitter underrun */
137#define TX_BD_CRC (1 << 11) /* TX CRC enable */
138#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139#define TX_BD_WRAP (1 << 13)
140#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141#define TX_BD_READY (1 << 15) /* TX buffer ready */
142#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143#define TX_BD_LEN_MASK (0xffff << 16)
144
145#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
147
148/* RX buffer descriptor */
149#define RX_BD_LC (1 << 0) /* late collision */
150#define RX_BD_CRC (1 << 1) /* RX CRC error */
151#define RX_BD_SF (1 << 2) /* short frame */
152#define RX_BD_TL (1 << 3) /* too long */
153#define RX_BD_DN (1 << 4) /* dribble nibble */
154#define RX_BD_IS (1 << 5) /* invalid symbol */
155#define RX_BD_OR (1 << 6) /* receiver overrun */
156#define RX_BD_MISS (1 << 7)
157#define RX_BD_CF (1 << 8) /* control frame */
158#define RX_BD_WRAP (1 << 13)
159#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160#define RX_BD_EMPTY (1 << 15)
161#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
162
163#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
165
166#define ETHOC_BUFSIZ 1536
167#define ETHOC_ZLEN 64
168#define ETHOC_BD_BASE 0x400
169#define ETHOC_TIMEOUT (HZ / 2)
170#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
171
172/**
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
0baa080c 176 * @dma_alloc: dma allocated buffer size
ee02a4ef 177 * @io_region_size: I/O memory region size
a1702857
TR		 178 * @num_tx: number of send buffers
179 * @cur_tx: last send buffer written
180 * @dty_tx: last buffer actually sent
181 * @num_rx: number of receive buffers
182 * @cur_rx: current receive buffer
f8555ad0 183 * @vma: pointer to array of virtual memory addresses for buffers
a1702857
TR		 184 * @netdev: pointer to network device structure
185 * @napi: NAPI structure
186 * @stats: network device statistics
187 * @msg_enable: device state flags
188 * @rx_lock: receive lock
189 * @lock: device lock
190 * @phy: attached PHY
191 * @mdio: MDIO bus for PHY access
192 * @phy_id: address of attached PHY
193 */
194struct ethoc {
195 void __iomem *iobase;
196 void __iomem *membase;
0baa080c 197 int dma_alloc;
ee02a4ef 198 resource_size_t io_region_size;
a1702857
TR		 199
200 unsigned int num_tx;
201 unsigned int cur_tx;
202 unsigned int dty_tx;
203
204 unsigned int num_rx;
205 unsigned int cur_rx;
206
f8555ad0
JB		 207 void** vma;
208
a1702857
TR		 209 struct net_device *netdev;
210 struct napi_struct napi;
211 struct net_device_stats stats;
212 u32 msg_enable;
213
214 spinlock_t rx_lock;
215 spinlock_t lock;
216
217 struct phy_device *phy;
218 struct mii_bus *mdio;
219 s8 phy_id;
220};
221
222/**
223 * struct ethoc_bd - buffer descriptor
224 * @stat: buffer statistics
225 * @addr: physical memory address
226 */
227struct ethoc_bd {
228 u32 stat;
229 u32 addr;
230};
231
16dd18b0 232static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
a1702857
TR		 233{
234 return ioread32(dev->iobase + offset);
235}
236
16dd18b0 237static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
a1702857
TR		 238{
239 iowrite32(data, dev->iobase + offset);
240}
241
16dd18b0
TC		 242static inline void ethoc_read_bd(struct ethoc *dev, int index,
243 struct ethoc_bd *bd)
a1702857
TR		 244{
245 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
246 bd->stat = ethoc_read(dev, offset + 0);
247 bd->addr = ethoc_read(dev, offset + 4);
248}
249
16dd18b0 250static inline void ethoc_write_bd(struct ethoc *dev, int index,
a1702857
TR		 251 const struct ethoc_bd *bd)
252{
253 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
254 ethoc_write(dev, offset + 0, bd->stat);
255 ethoc_write(dev, offset + 4, bd->addr);
256}
257
16dd18b0 258static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
a1702857
TR		 259{
260 u32 imask = ethoc_read(dev, INT_MASK);
261 imask |= mask;
262 ethoc_write(dev, INT_MASK, imask);
263}
264
16dd18b0 265static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
a1702857
TR		 266{
267 u32 imask = ethoc_read(dev, INT_MASK);
268 imask &= ~mask;
269 ethoc_write(dev, INT_MASK, imask);
270}
271
16dd18b0 272static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
a1702857
TR		 273{
274 ethoc_write(dev, INT_SOURCE, mask);
275}
276
16dd18b0 277static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
a1702857
TR		 278{
279 u32 mode = ethoc_read(dev, MODER);
280 mode |= MODER_RXEN | MODER_TXEN;
281 ethoc_write(dev, MODER, mode);
282}
283
16dd18b0 284static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
a1702857
TR		 285{
286 u32 mode = ethoc_read(dev, MODER);
287 mode &= ~(MODER_RXEN | MODER_TXEN);
288 ethoc_write(dev, MODER, mode);
289}
290
f8555ad0 291static int ethoc_init_ring(struct ethoc *dev, void* mem_start)
a1702857
TR		 292{
293 struct ethoc_bd bd;
294 int i;
f8555ad0 295 void* vma;
a1702857
TR		 296
297 dev->cur_tx = 0;
298 dev->dty_tx = 0;
299 dev->cur_rx = 0;
300
ee4f56b9
JB		 301 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
302
a1702857 303 /* setup transmission buffers */
f8555ad0 304 bd.addr = mem_start;
a1702857 305 bd.stat = TX_BD_IRQ | TX_BD_CRC;
f8555ad0 306 vma = dev->membase;
a1702857
TR		 307
308 for (i = 0; i < dev->num_tx; i++) {
309 if (i == dev->num_tx - 1)
310 bd.stat |= TX_BD_WRAP;
311
312 ethoc_write_bd(dev, i, &bd);
313 bd.addr += ETHOC_BUFSIZ;
f8555ad0
JB		 314
315 dev->vma[i] = vma;
316 vma += ETHOC_BUFSIZ;
a1702857
TR		 317 }
318
a1702857
TR		 319 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
320
321 for (i = 0; i < dev->num_rx; i++) {
322 if (i == dev->num_rx - 1)
323 bd.stat |= RX_BD_WRAP;
324
325 ethoc_write_bd(dev, dev->num_tx + i, &bd);
326 bd.addr += ETHOC_BUFSIZ;
f8555ad0
JB		 327
328 dev->vma[dev->num_tx + i] = vma;
329 vma += ETHOC_BUFSIZ;
a1702857
TR		 330 }
331
332 return 0;
333}
334
335static int ethoc_reset(struct ethoc *dev)
336{
337 u32 mode;
338
339 /* TODO: reset controller? */
340
341 ethoc_disable_rx_and_tx(dev);
342
343 /* TODO: setup registers */
344
345 /* enable FCS generation and automatic padding */
346 mode = ethoc_read(dev, MODER);
347 mode |= MODER_CRC | MODER_PAD;
348 ethoc_write(dev, MODER, mode);
349
350 /* set full-duplex mode */
351 mode = ethoc_read(dev, MODER);
352 mode |= MODER_FULLD;
353 ethoc_write(dev, MODER, mode);
354 ethoc_write(dev, IPGT, 0x15);
355
356 ethoc_ack_irq(dev, INT_MASK_ALL);
357 ethoc_enable_irq(dev, INT_MASK_ALL);
358 ethoc_enable_rx_and_tx(dev);
359 return 0;
360}
361
362static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
363 struct ethoc_bd *bd)
364{
365 struct net_device *netdev = dev->netdev;
366 unsigned int ret = 0;
367
368 if (bd->stat & RX_BD_TL) {
369 dev_err(&netdev->dev, "RX: frame too long\n");
370 dev->stats.rx_length_errors++;
371 ret++;
372 }
373
374 if (bd->stat & RX_BD_SF) {
375 dev_err(&netdev->dev, "RX: frame too short\n");
376 dev->stats.rx_length_errors++;
377 ret++;
378 }
379
380 if (bd->stat & RX_BD_DN) {
381 dev_err(&netdev->dev, "RX: dribble nibble\n");
382 dev->stats.rx_frame_errors++;
383 }
384
385 if (bd->stat & RX_BD_CRC) {
386 dev_err(&netdev->dev, "RX: wrong CRC\n");
387 dev->stats.rx_crc_errors++;
388 ret++;
389 }
390
391 if (bd->stat & RX_BD_OR) {
392 dev_err(&netdev->dev, "RX: overrun\n");
393 dev->stats.rx_over_errors++;
394 ret++;
395 }
396
397 if (bd->stat & RX_BD_MISS)
398 dev->stats.rx_missed_errors++;
399
400 if (bd->stat & RX_BD_LC) {
401 dev_err(&netdev->dev, "RX: late collision\n");
402 dev->stats.collisions++;
403 ret++;
404 }
405
406 return ret;
407}
408
409static int ethoc_rx(struct net_device *dev, int limit)
410{
411 struct ethoc *priv = netdev_priv(dev);
412 int count;
413
414 for (count = 0; count < limit; ++count) {
415 unsigned int entry;
416 struct ethoc_bd bd;
417
418 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
419 ethoc_read_bd(priv, entry, &bd);
420 if (bd.stat & RX_BD_EMPTY)
421 break;
422
423 if (ethoc_update_rx_stats(priv, &bd) == 0) {
424 int size = bd.stat >> 16;
89d71a66 425 struct sk_buff *skb;
050f91dc
TC		 426
427 size -= 4; /* strip the CRC */
89d71a66 428 skb = netdev_alloc_skb_ip_align(dev, size);
050f91dc 429
a1702857 430 if (likely(skb)) {
f8555ad0 431 void *src = priv->vma[entry];
a1702857
TR		 432 memcpy_fromio(skb_put(skb, size), src, size);
433 skb->protocol = eth_type_trans(skb, dev);
a1702857
TR		 434 priv->stats.rx_packets++;
435 priv->stats.rx_bytes += size;
436 netif_receive_skb(skb);
437 } else {
438 if (net_ratelimit())
439 dev_warn(&dev->dev, "low on memory - "
440 "packet dropped\n");
441
442 priv->stats.rx_dropped++;
443 break;
444 }
445 }
446
447 /* clear the buffer descriptor so it can be reused */
448 bd.stat &= ~RX_BD_STATS;
449 bd.stat |= RX_BD_EMPTY;
450 ethoc_write_bd(priv, entry, &bd);
451 priv->cur_rx++;
452 }
453
454 return count;
455}
456
457static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
458{
459 struct net_device *netdev = dev->netdev;
460
461 if (bd->stat & TX_BD_LC) {
462 dev_err(&netdev->dev, "TX: late collision\n");
463 dev->stats.tx_window_errors++;
464 }
465
466 if (bd->stat & TX_BD_RL) {
467 dev_err(&netdev->dev, "TX: retransmit limit\n");
468 dev->stats.tx_aborted_errors++;
469 }
470
471 if (bd->stat & TX_BD_UR) {
472 dev_err(&netdev->dev, "TX: underrun\n");
473 dev->stats.tx_fifo_errors++;
474 }
475
476 if (bd->stat & TX_BD_CS) {
477 dev_err(&netdev->dev, "TX: carrier sense lost\n");
478 dev->stats.tx_carrier_errors++;
479 }
480
481 if (bd->stat & TX_BD_STATS)
482 dev->stats.tx_errors++;
483
484 dev->stats.collisions += (bd->stat >> 4) & 0xf;
485 dev->stats.tx_bytes += bd->stat >> 16;
486 dev->stats.tx_packets++;
487 return 0;
488}
489
490static void ethoc_tx(struct net_device *dev)
491{
492 struct ethoc *priv = netdev_priv(dev);
493
494 spin_lock(&priv->lock);
495
496 while (priv->dty_tx != priv->cur_tx) {
497 unsigned int entry = priv->dty_tx % priv->num_tx;
498 struct ethoc_bd bd;
499
500 ethoc_read_bd(priv, entry, &bd);
501 if (bd.stat & TX_BD_READY)
502 break;
503
504 entry = (++priv->dty_tx) % priv->num_tx;
505 (void)ethoc_update_tx_stats(priv, &bd);
506 }
507
508 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
509 netif_wake_queue(dev);
510
511 ethoc_ack_irq(priv, INT_MASK_TX);
512 spin_unlock(&priv->lock);
513}
514
515static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
516{
517 struct net_device *dev = (struct net_device *)dev_id;
518 struct ethoc *priv = netdev_priv(dev);
519 u32 pending;
520
521 ethoc_disable_irq(priv, INT_MASK_ALL);
522 pending = ethoc_read(priv, INT_SOURCE);
523 if (unlikely(pending == 0)) {
524 ethoc_enable_irq(priv, INT_MASK_ALL);
525 return IRQ_NONE;
526 }
527
50c54a57 528 ethoc_ack_irq(priv, pending);
a1702857
TR		 529
530 if (pending & INT_MASK_BUSY) {
531 dev_err(&dev->dev, "packet dropped\n");
532 priv->stats.rx_dropped++;
533 }
534
535 if (pending & INT_MASK_RX) {
536 if (napi_schedule_prep(&priv->napi))
537 __napi_schedule(&priv->napi);
538 } else {
539 ethoc_enable_irq(priv, INT_MASK_RX);
540 }
541
542 if (pending & INT_MASK_TX)
543 ethoc_tx(dev);
544
545 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
546 return IRQ_HANDLED;
547}
548
549static int ethoc_get_mac_address(struct net_device *dev, void *addr)
550{
551 struct ethoc *priv = netdev_priv(dev);
552 u8 *mac = (u8 *)addr;
553 u32 reg;
554
555 reg = ethoc_read(priv, MAC_ADDR0);
556 mac[2] = (reg >> 24) & 0xff;
557 mac[3] = (reg >> 16) & 0xff;
558 mac[4] = (reg >> 8) & 0xff;
559 mac[5] = (reg >> 0) & 0xff;
560
561 reg = ethoc_read(priv, MAC_ADDR1);
562 mac[0] = (reg >> 8) & 0xff;
563 mac[1] = (reg >> 0) & 0xff;
564
565 return 0;
566}
567
568static int ethoc_poll(struct napi_struct *napi, int budget)
569{
570 struct ethoc *priv = container_of(napi, struct ethoc, napi);
571 int work_done = 0;
572
573 work_done = ethoc_rx(priv->netdev, budget);
574 if (work_done < budget) {
575 ethoc_enable_irq(priv, INT_MASK_RX);
576 napi_complete(napi);
577 }
578
579 return work_done;
580}
581
582static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
583{
584 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
585 struct ethoc *priv = bus->priv;
586
587 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
588 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
589
590 while (time_before(jiffies, timeout)) {
591 u32 status = ethoc_read(priv, MIISTATUS);
592 if (!(status & MIISTATUS_BUSY)) {
593 u32 data = ethoc_read(priv, MIIRX_DATA);
594 /* reset MII command register */
595 ethoc_write(priv, MIICOMMAND, 0);
596 return data;
597 }
598
599 schedule();
600 }
601
602 return -EBUSY;
603}
604
605static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
606{
607 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
608 struct ethoc *priv = bus->priv;
609
610 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
611 ethoc_write(priv, MIITX_DATA, val);
612 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
613
614 while (time_before(jiffies, timeout)) {
615 u32 stat = ethoc_read(priv, MIISTATUS);
616 if (!(stat & MIISTATUS_BUSY))
617 return 0;
618
619 schedule();
620 }
621
622 return -EBUSY;
623}
624
625static int ethoc_mdio_reset(struct mii_bus *bus)
626{
627 return 0;
628}
629
630static void ethoc_mdio_poll(struct net_device *dev)
631{
632}
633
634static int ethoc_mdio_probe(struct net_device *dev)
635{
636 struct ethoc *priv = netdev_priv(dev);
637 struct phy_device *phy;
638 int i;
639
640 for (i = 0; i < PHY_MAX_ADDR; i++) {
641 phy = priv->mdio->phy_map[i];
642 if (phy) {
643 if (priv->phy_id != -1) {
644 /* attach to specified PHY */
645 if (priv->phy_id == phy->addr)
646 break;
647 } else {
648 /* autoselect PHY if none was specified */
649 if (phy->addr != 0)
650 break;
651 }
652 }
653 }
654
655 if (!phy) {
656 dev_err(&dev->dev, "no PHY found\n");
657 return -ENXIO;
658 }
659
dddcb445 660 phy = phy_connect(dev, dev_name(&phy->dev), ethoc_mdio_poll, 0,
a1702857
TR		 661 PHY_INTERFACE_MODE_GMII);
662 if (IS_ERR(phy)) {
663 dev_err(&dev->dev, "could not attach to PHY\n");
664 return PTR_ERR(phy);
665 }
666
667 priv->phy = phy;
668 return 0;
669}
670
671static int ethoc_open(struct net_device *dev)
672{
673 struct ethoc *priv = netdev_priv(dev);
a1702857
TR		 674 int ret;
675
676 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
677 dev->name, dev);
678 if (ret)
679 return ret;
680
f8555ad0 681 ethoc_init_ring(priv, (void*)dev->mem_start);
a1702857
TR		 682 ethoc_reset(priv);
683
684 if (netif_queue_stopped(dev)) {
685 dev_dbg(&dev->dev, " resuming queue\n");
686 netif_wake_queue(dev);
687 } else {
688 dev_dbg(&dev->dev, " starting queue\n");
689 netif_start_queue(dev);
690 }
691
692 phy_start(priv->phy);
693 napi_enable(&priv->napi);
694
695 if (netif_msg_ifup(priv)) {
696 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
697 dev->base_addr, dev->mem_start, dev->mem_end);
698 }
699
700 return 0;
701}
702
703static int ethoc_stop(struct net_device *dev)
704{
705 struct ethoc *priv = netdev_priv(dev);
706
707 napi_disable(&priv->napi);
708
709 if (priv->phy)
710 phy_stop(priv->phy);
711
712 ethoc_disable_rx_and_tx(priv);
713 free_irq(dev->irq, dev);
714
715 if (!netif_queue_stopped(dev))
716 netif_stop_queue(dev);
717
718 return 0;
719}
720
721static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
722{
723 struct ethoc *priv = netdev_priv(dev);
724 struct mii_ioctl_data *mdio = if_mii(ifr);
725 struct phy_device *phy = NULL;
726
727 if (!netif_running(dev))
728 return -EINVAL;
729
730 if (cmd != SIOCGMIIPHY) {
731 if (mdio->phy_id >= PHY_MAX_ADDR)
732 return -ERANGE;
733
734 phy = priv->mdio->phy_map[mdio->phy_id];
735 if (!phy)
736 return -ENODEV;
737 } else {
738 phy = priv->phy;
739 }
740
741 return phy_mii_ioctl(phy, mdio, cmd);
742}
743
744static int ethoc_config(struct net_device *dev, struct ifmap *map)
745{
746 return -ENOSYS;
747}
748
749static int ethoc_set_mac_address(struct net_device *dev, void *addr)
750{
751 struct ethoc *priv = netdev_priv(dev);
752 u8 *mac = (u8 *)addr;
753
754 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
755 (mac[4] << 8) | (mac[5] << 0));
756 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
757
758 return 0;
759}
760
761static void ethoc_set_multicast_list(struct net_device *dev)
762{
763 struct ethoc *priv = netdev_priv(dev);
764 u32 mode = ethoc_read(priv, MODER);
22bedad3 765 struct netdev_hw_addr *ha;
a1702857
TR		 766 u32 hash[2] = { 0, 0 };
767
768 /* set loopback mode if requested */
769 if (dev->flags & IFF_LOOPBACK)
770 mode |= MODER_LOOP;
771 else
772 mode &= ~MODER_LOOP;
773
774 /* receive broadcast frames if requested */
775 if (dev->flags & IFF_BROADCAST)
776 mode &= ~MODER_BRO;
777 else
778 mode |= MODER_BRO;
779
780 /* enable promiscuous mode if requested */
781 if (dev->flags & IFF_PROMISC)
782 mode |= MODER_PRO;
783 else
784 mode &= ~MODER_PRO;
785
786 ethoc_write(priv, MODER, mode);
787
788 /* receive multicast frames */
789 if (dev->flags & IFF_ALLMULTI) {
790 hash[0] = 0xffffffff;
791 hash[1] = 0xffffffff;
792 } else {
22bedad3
JP		 793 netdev_for_each_mc_addr(ha, dev) {
794 u32 crc = ether_crc(ETH_ALEN, ha->addr);
a1702857
TR		 795 int bit = (crc >> 26) & 0x3f;
796 hash[bit >> 5] |= 1 << (bit & 0x1f);
797 }
798 }
799
800 ethoc_write(priv, ETH_HASH0, hash[0]);
801 ethoc_write(priv, ETH_HASH1, hash[1]);
802}
803
804static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
805{
806 return -ENOSYS;
807}
808
809static void ethoc_tx_timeout(struct net_device *dev)
810{
811 struct ethoc *priv = netdev_priv(dev);
812 u32 pending = ethoc_read(priv, INT_SOURCE);
813 if (likely(pending))
814 ethoc_interrupt(dev->irq, dev);
815}
816
817static struct net_device_stats *ethoc_stats(struct net_device *dev)
818{
819 struct ethoc *priv = netdev_priv(dev);
820 return &priv->stats;
821}
822
61357325 823static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
a1702857
TR		 824{
825 struct ethoc *priv = netdev_priv(dev);
826 struct ethoc_bd bd;
827 unsigned int entry;
828 void *dest;
829
830 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
831 priv->stats.tx_errors++;
3790c8cd 832 goto out;
a1702857
TR		 833 }
834
835 entry = priv->cur_tx % priv->num_tx;
836 spin_lock_irq(&priv->lock);
837 priv->cur_tx++;
838
839 ethoc_read_bd(priv, entry, &bd);
840 if (unlikely(skb->len < ETHOC_ZLEN))
841 bd.stat |= TX_BD_PAD;
842 else
843 bd.stat &= ~TX_BD_PAD;
844
f8555ad0 845 dest = priv->vma[entry];
a1702857
TR		 846 memcpy_toio(dest, skb->data, skb->len);
847
848 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
849 bd.stat |= TX_BD_LEN(skb->len);
850 ethoc_write_bd(priv, entry, &bd);
851
852 bd.stat |= TX_BD_READY;
853 ethoc_write_bd(priv, entry, &bd);
854
855 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
856 dev_dbg(&dev->dev, "stopping queue\n");
857 netif_stop_queue(dev);
858 }
859
a1702857 860 spin_unlock_irq(&priv->lock);
3790c8cd
PM		 861out:
862 dev_kfree_skb(skb);
a1702857
TR		 863 return NETDEV_TX_OK;
864}
865
866static const struct net_device_ops ethoc_netdev_ops = {
867 .ndo_open = ethoc_open,
868 .ndo_stop = ethoc_stop,
869 .ndo_do_ioctl = ethoc_ioctl,
870 .ndo_set_config = ethoc_config,
871 .ndo_set_mac_address = ethoc_set_mac_address,
872 .ndo_set_multicast_list = ethoc_set_multicast_list,
873 .ndo_change_mtu = ethoc_change_mtu,
874 .ndo_tx_timeout = ethoc_tx_timeout,
875 .ndo_get_stats = ethoc_stats,
876 .ndo_start_xmit = ethoc_start_xmit,
877};
878
879/**
880 * ethoc_probe() - initialize OpenCores ethernet MAC
881 * pdev: platform device
882 */
883static int ethoc_probe(struct platform_device *pdev)
884{
885 struct net_device *netdev = NULL;
886 struct resource *res = NULL;
887 struct resource *mmio = NULL;
888 struct resource *mem = NULL;
889 struct ethoc *priv = NULL;
890 unsigned int phy;
c527f814 891 int num_bd;
a1702857
TR		 892 int ret = 0;
893
894 /* allocate networking device */
895 netdev = alloc_etherdev(sizeof(struct ethoc));
896 if (!netdev) {
897 dev_err(&pdev->dev, "cannot allocate network device\n");
898 ret = -ENOMEM;
899 goto out;
900 }
901
902 SET_NETDEV_DEV(netdev, &pdev->dev);
903 platform_set_drvdata(pdev, netdev);
904
905 /* obtain I/O memory space */
906 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
907 if (!res) {
908 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
909 ret = -ENXIO;
910 goto free;
911 }
912
913 mmio = devm_request_mem_region(&pdev->dev, res->start,
d8645847 914 resource_size(res), res->name);
463889e2 915 if (!mmio) {
a1702857
TR		 916 dev_err(&pdev->dev, "cannot request I/O memory space\n");
917 ret = -ENXIO;
918 goto free;
919 }
920
921 netdev->base_addr = mmio->start;
922
923 /* obtain buffer memory space */
924 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0baa080c
TC		 925 if (res) {
926 mem = devm_request_mem_region(&pdev->dev, res->start,
d8645847 927 resource_size(res), res->name);
0baa080c
TC		 928 if (!mem) {
929 dev_err(&pdev->dev, "cannot request memory space\n");
930 ret = -ENXIO;
931 goto free;
932 }
933
934 netdev->mem_start = mem->start;
935 netdev->mem_end = mem->end;
a1702857
TR		 936 }
937
a1702857
TR		 938
939 /* obtain device IRQ number */
940 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
941 if (!res) {
942 dev_err(&pdev->dev, "cannot obtain IRQ\n");
943 ret = -ENXIO;
944 goto free;
945 }
946
947 netdev->irq = res->start;
948
949 /* setup driver-private data */
950 priv = netdev_priv(netdev);
951 priv->netdev = netdev;
0baa080c 952 priv->dma_alloc = 0;
ee02a4ef 953 priv->io_region_size = mmio->end - mmio->start + 1;
a1702857
TR		 954
955 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
d8645847 956 resource_size(mmio));
a1702857
TR		 957 if (!priv->iobase) {
958 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
959 ret = -ENXIO;
960 goto error;
961 }
962
0baa080c
TC		 963 if (netdev->mem_end) {
964 priv->membase = devm_ioremap_nocache(&pdev->dev,
d8645847 965 netdev->mem_start, resource_size(mem));
0baa080c
TC		 966 if (!priv->membase) {
967 dev_err(&pdev->dev, "cannot remap memory space\n");
968 ret = -ENXIO;
969 goto error;
970 }
971 } else {
972 /* Allocate buffer memory */
973 priv->membase = dma_alloc_coherent(NULL,
974 buffer_size, (void *)&netdev->mem_start,
975 GFP_KERNEL);
976 if (!priv->membase) {
977 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
978 buffer_size);
979 ret = -ENOMEM;
980 goto error;
981 }
982 netdev->mem_end = netdev->mem_start + buffer_size;
983 priv->dma_alloc = buffer_size;
a1702857
TR		 984 }
985
c527f814
JB		 986 /* calculate the number of TX/RX buffers, maximum 128 supported */
987 num_bd = min_t(unsigned int,
988 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
989 priv->num_tx = max(2, num_bd / 4);
990 priv->num_rx = num_bd - priv->num_tx;
991
f8555ad0
JB		 992 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL);
993 if (!priv->vma) {
994 ret = -ENOMEM;
995 goto error;
996 }
997
a1702857
TR		 998 /* Allow the platform setup code to pass in a MAC address. */
999 if (pdev->dev.platform_data) {
1000 struct ethoc_platform_data *pdata =
1001 (struct ethoc_platform_data *)pdev->dev.platform_data;
1002 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
1003 priv->phy_id = pdata->phy_id;
1004 }
1005
1006 /* Check that the given MAC address is valid. If it isn't, read the
1007 * current MAC from the controller. */
1008 if (!is_valid_ether_addr(netdev->dev_addr))
1009 ethoc_get_mac_address(netdev, netdev->dev_addr);
1010
1011 /* Check the MAC again for validity, if it still isn't choose and
1012 * program a random one. */
1013 if (!is_valid_ether_addr(netdev->dev_addr))
1014 random_ether_addr(netdev->dev_addr);
1015
1016 ethoc_set_mac_address(netdev, netdev->dev_addr);
1017
1018 /* register MII bus */
1019 priv->mdio = mdiobus_alloc();
1020 if (!priv->mdio) {
1021 ret = -ENOMEM;
1022 goto free;
1023 }
1024
1025 priv->mdio->name = "ethoc-mdio";
1026 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1027 priv->mdio->name, pdev->id);
1028 priv->mdio->read = ethoc_mdio_read;
1029 priv->mdio->write = ethoc_mdio_write;
1030 priv->mdio->reset = ethoc_mdio_reset;
1031 priv->mdio->priv = priv;
1032
1033 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1034 if (!priv->mdio->irq) {
1035 ret = -ENOMEM;
1036 goto free_mdio;
1037 }
1038
1039 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1040 priv->mdio->irq[phy] = PHY_POLL;
1041
1042 ret = mdiobus_register(priv->mdio);
1043 if (ret) {
1044 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1045 goto free_mdio;
1046 }
1047
1048 ret = ethoc_mdio_probe(netdev);
1049 if (ret) {
1050 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1051 goto error;
1052 }
1053
1054 ether_setup(netdev);
1055
1056 /* setup the net_device structure */
1057 netdev->netdev_ops = &ethoc_netdev_ops;
1058 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1059 netdev->features |= 0;
1060
1061 /* setup NAPI */
a1702857
TR		 1062 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1063
1064 spin_lock_init(&priv->rx_lock);
1065 spin_lock_init(&priv->lock);
1066
1067 ret = register_netdev(netdev);
1068 if (ret < 0) {
1069 dev_err(&netdev->dev, "failed to register interface\n");
ee02a4ef 1070 goto error2;
a1702857
TR		 1071 }
1072
1073 goto out;
1074
ee02a4ef
TC		 1075error2:
1076 netif_napi_del(&priv->napi);
a1702857
TR		 1077error:
1078 mdiobus_unregister(priv->mdio);
1079free_mdio:
1080 kfree(priv->mdio->irq);
1081 mdiobus_free(priv->mdio);
1082free:
ee02a4ef
TC		 1083 if (priv) {
1084 if (priv->dma_alloc)
1085 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1086 netdev->mem_start);
1087 else if (priv->membase)
1088 devm_iounmap(&pdev->dev, priv->membase);
1089 if (priv->iobase)
1090 devm_iounmap(&pdev->dev, priv->iobase);
1091 }
1092 if (mem)
1093 devm_release_mem_region(&pdev->dev, mem->start,
1094 mem->end - mem->start + 1);
1095 if (mmio)
1096 devm_release_mem_region(&pdev->dev, mmio->start,
1097 mmio->end - mmio->start + 1);
a1702857
TR		 1098 free_netdev(netdev);
1099out:
1100 return ret;
1101}
1102
1103/**
1104 * ethoc_remove() - shutdown OpenCores ethernet MAC
1105 * @pdev: platform device
1106 */
1107static int ethoc_remove(struct platform_device *pdev)
1108{
1109 struct net_device *netdev = platform_get_drvdata(pdev);
1110 struct ethoc *priv = netdev_priv(netdev);
1111
1112 platform_set_drvdata(pdev, NULL);
1113
1114 if (netdev) {
ee02a4ef 1115 netif_napi_del(&priv->napi);
a1702857
TR		 1116 phy_disconnect(priv->phy);
1117 priv->phy = NULL;
1118
1119 if (priv->mdio) {
1120 mdiobus_unregister(priv->mdio);
1121 kfree(priv->mdio->irq);
1122 mdiobus_free(priv->mdio);
1123 }
0baa080c
TC		 1124 if (priv->dma_alloc)
1125 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1126 netdev->mem_start);
ee02a4ef
TC		 1127 else {
1128 devm_iounmap(&pdev->dev, priv->membase);
1129 devm_release_mem_region(&pdev->dev, netdev->mem_start,
1130 netdev->mem_end - netdev->mem_start + 1);
1131 }
1132 devm_iounmap(&pdev->dev, priv->iobase);
1133 devm_release_mem_region(&pdev->dev, netdev->base_addr,
1134 priv->io_region_size);
a1702857
TR		 1135 unregister_netdev(netdev);
1136 free_netdev(netdev);
1137 }
1138
1139 return 0;
1140}
1141
1142#ifdef CONFIG_PM
1143static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1144{
1145 return -ENOSYS;
1146}
1147
1148static int ethoc_resume(struct platform_device *pdev)
1149{
1150 return -ENOSYS;
1151}
1152#else
1153# define ethoc_suspend NULL
1154# define ethoc_resume NULL
1155#endif
1156
1157static struct platform_driver ethoc_driver = {
1158 .probe = ethoc_probe,
1159 .remove = ethoc_remove,
1160 .suspend = ethoc_suspend,
1161 .resume = ethoc_resume,
1162 .driver = {
1163 .name = "ethoc",
1164 },
1165};
1166
1167static int __init ethoc_init(void)
1168{
1169 return platform_driver_register(&ethoc_driver);
1170}
1171
1172static void __exit ethoc_exit(void)
1173{
1174 platform_driver_unregister(&ethoc_driver);
1175}
1176
1177module_init(ethoc_init);
1178module_exit(ethoc_exit);
1179
1180MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1181MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1182MODULE_LICENSE("GPL v2");
1183
Linux kernel - Deliverables
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