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1da177e4 LT |
1 | /* |
2 | * File Name: | |
3 | * defxx.c | |
4 | * | |
5 | * Copyright Information: | |
6 | * Copyright Digital Equipment Corporation 1996. | |
7 | * | |
8 | * This software may be used and distributed according to the terms of | |
9 | * the GNU General Public License, incorporated herein by reference. | |
10 | * | |
11 | * Abstract: | |
12 | * A Linux device driver supporting the Digital Equipment Corporation | |
e89a2cfb MR |
13 | * FDDI TURBOchannel, EISA and PCI controller families. Supported |
14 | * adapters include: | |
1da177e4 | 15 | * |
e89a2cfb MR |
16 | * DEC FDDIcontroller/TURBOchannel (DEFTA) |
17 | * DEC FDDIcontroller/EISA (DEFEA) | |
18 | * DEC FDDIcontroller/PCI (DEFPA) | |
1da177e4 LT |
19 | * |
20 | * The original author: | |
21 | * LVS Lawrence V. Stefani <lstefani@yahoo.com> | |
22 | * | |
23 | * Maintainers: | |
24 | * macro Maciej W. Rozycki <macro@linux-mips.org> | |
25 | * | |
26 | * Credits: | |
27 | * I'd like to thank Patricia Cross for helping me get started with | |
28 | * Linux, David Davies for a lot of help upgrading and configuring | |
29 | * my development system and for answering many OS and driver | |
30 | * development questions, and Alan Cox for recommendations and | |
31 | * integration help on getting FDDI support into Linux. LVS | |
32 | * | |
33 | * Driver Architecture: | |
34 | * The driver architecture is largely based on previous driver work | |
35 | * for other operating systems. The upper edge interface and | |
36 | * functions were largely taken from existing Linux device drivers | |
37 | * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C | |
38 | * driver. | |
39 | * | |
40 | * Adapter Probe - | |
41 | * The driver scans for supported EISA adapters by reading the | |
42 | * SLOT ID register for each EISA slot and making a match | |
43 | * against the expected value. | |
44 | * | |
45 | * Bus-Specific Initialization - | |
46 | * This driver currently supports both EISA and PCI controller | |
47 | * families. While the custom DMA chip and FDDI logic is similar | |
48 | * or identical, the bus logic is very different. After | |
49 | * initialization, the only bus-specific differences is in how the | |
50 | * driver enables and disables interrupts. Other than that, the | |
51 | * run-time critical code behaves the same on both families. | |
52 | * It's important to note that both adapter families are configured | |
53 | * to I/O map, rather than memory map, the adapter registers. | |
54 | * | |
55 | * Driver Open/Close - | |
56 | * In the driver open routine, the driver ISR (interrupt service | |
57 | * routine) is registered and the adapter is brought to an | |
58 | * operational state. In the driver close routine, the opposite | |
59 | * occurs; the driver ISR is deregistered and the adapter is | |
60 | * brought to a safe, but closed state. Users may use consecutive | |
61 | * commands to bring the adapter up and down as in the following | |
62 | * example: | |
63 | * ifconfig fddi0 up | |
64 | * ifconfig fddi0 down | |
65 | * ifconfig fddi0 up | |
66 | * | |
67 | * Driver Shutdown - | |
68 | * Apparently, there is no shutdown or halt routine support under | |
69 | * Linux. This routine would be called during "reboot" or | |
70 | * "shutdown" to allow the driver to place the adapter in a safe | |
71 | * state before a warm reboot occurs. To be really safe, the user | |
72 | * should close the adapter before shutdown (eg. ifconfig fddi0 down) | |
73 | * to ensure that the adapter DMA engine is taken off-line. However, | |
74 | * the current driver code anticipates this problem and always issues | |
75 | * a soft reset of the adapter at the beginning of driver initialization. | |
76 | * A future driver enhancement in this area may occur in 2.1.X where | |
77 | * Alan indicated that a shutdown handler may be implemented. | |
78 | * | |
79 | * Interrupt Service Routine - | |
80 | * The driver supports shared interrupts, so the ISR is registered for | |
81 | * each board with the appropriate flag and the pointer to that board's | |
82 | * device structure. This provides the context during interrupt | |
83 | * processing to support shared interrupts and multiple boards. | |
84 | * | |
85 | * Interrupt enabling/disabling can occur at many levels. At the host | |
86 | * end, you can disable system interrupts, or disable interrupts at the | |
87 | * PIC (on Intel systems). Across the bus, both EISA and PCI adapters | |
88 | * have a bus-logic chip interrupt enable/disable as well as a DMA | |
89 | * controller interrupt enable/disable. | |
90 | * | |
91 | * The driver currently enables and disables adapter interrupts at the | |
92 | * bus-logic chip and assumes that Linux will take care of clearing or | |
93 | * acknowledging any host-based interrupt chips. | |
94 | * | |
95 | * Control Functions - | |
96 | * Control functions are those used to support functions such as adding | |
97 | * or deleting multicast addresses, enabling or disabling packet | |
98 | * reception filters, or other custom/proprietary commands. Presently, | |
99 | * the driver supports the "get statistics", "set multicast list", and | |
100 | * "set mac address" functions defined by Linux. A list of possible | |
101 | * enhancements include: | |
102 | * | |
103 | * - Custom ioctl interface for executing port interface commands | |
104 | * - Custom ioctl interface for adding unicast addresses to | |
105 | * adapter CAM (to support bridge functions). | |
106 | * - Custom ioctl interface for supporting firmware upgrades. | |
107 | * | |
108 | * Hardware (port interface) Support Routines - | |
109 | * The driver function names that start with "dfx_hw_" represent | |
110 | * low-level port interface routines that are called frequently. They | |
111 | * include issuing a DMA or port control command to the adapter, | |
112 | * resetting the adapter, or reading the adapter state. Since the | |
113 | * driver initialization and run-time code must make calls into the | |
114 | * port interface, these routines were written to be as generic and | |
115 | * usable as possible. | |
116 | * | |
117 | * Receive Path - | |
118 | * The adapter DMA engine supports a 256 entry receive descriptor block | |
119 | * of which up to 255 entries can be used at any given time. The | |
120 | * architecture is a standard producer, consumer, completion model in | |
121 | * which the driver "produces" receive buffers to the adapter, the | |
122 | * adapter "consumes" the receive buffers by DMAing incoming packet data, | |
123 | * and the driver "completes" the receive buffers by servicing the | |
124 | * incoming packet, then "produces" a new buffer and starts the cycle | |
125 | * again. Receive buffers can be fragmented in up to 16 fragments | |
126 | * (descriptor entries). For simplicity, this driver posts | |
127 | * single-fragment receive buffers of 4608 bytes, then allocates a | |
128 | * sk_buff, copies the data, then reposts the buffer. To reduce CPU | |
129 | * utilization, a better approach would be to pass up the receive | |
130 | * buffer (no extra copy) then allocate and post a replacement buffer. | |
131 | * This is a performance enhancement that should be looked into at | |
132 | * some point. | |
133 | * | |
134 | * Transmit Path - | |
135 | * Like the receive path, the adapter DMA engine supports a 256 entry | |
136 | * transmit descriptor block of which up to 255 entries can be used at | |
137 | * any given time. Transmit buffers can be fragmented in up to 255 | |
138 | * fragments (descriptor entries). This driver always posts one | |
139 | * fragment per transmit packet request. | |
140 | * | |
141 | * The fragment contains the entire packet from FC to end of data. | |
142 | * Before posting the buffer to the adapter, the driver sets a three-byte | |
143 | * packet request header (PRH) which is required by the Motorola MAC chip | |
144 | * used on the adapters. The PRH tells the MAC the type of token to | |
145 | * receive/send, whether or not to generate and append the CRC, whether | |
146 | * synchronous or asynchronous framing is used, etc. Since the PRH | |
147 | * definition is not necessarily consistent across all FDDI chipsets, | |
148 | * the driver, rather than the common FDDI packet handler routines, | |
149 | * sets these bytes. | |
150 | * | |
151 | * To reduce the amount of descriptor fetches needed per transmit request, | |
152 | * the driver takes advantage of the fact that there are at least three | |
153 | * bytes available before the skb->data field on the outgoing transmit | |
154 | * request. This is guaranteed by having fddi_setup() in net_init.c set | |
155 | * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest | |
156 | * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" | |
157 | * bytes which we'll use to store the PRH. | |
158 | * | |
159 | * There's a subtle advantage to adding these pad bytes to the | |
160 | * hard_header_len, it ensures that the data portion of the packet for | |
161 | * an 802.2 SNAP frame is longword aligned. Other FDDI driver | |
162 | * implementations may not need the extra padding and can start copying | |
163 | * or DMAing directly from the FC byte which starts at skb->data. Should | |
164 | * another driver implementation need ADDITIONAL padding, the net_init.c | |
165 | * module should be updated and dev->hard_header_len should be increased. | |
166 | * NOTE: To maintain the alignment on the data portion of the packet, | |
167 | * dev->hard_header_len should always be evenly divisible by 4 and at | |
168 | * least 24 bytes in size. | |
169 | * | |
170 | * Modification History: | |
171 | * Date Name Description | |
172 | * 16-Aug-96 LVS Created. | |
173 | * 20-Aug-96 LVS Updated dfx_probe so that version information | |
174 | * string is only displayed if 1 or more cards are | |
175 | * found. Changed dfx_rcv_queue_process to copy | |
176 | * 3 NULL bytes before FC to ensure that data is | |
177 | * longword aligned in receive buffer. | |
178 | * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable | |
179 | * LLC group promiscuous mode if multicast list | |
180 | * is too large. LLC individual/group promiscuous | |
181 | * mode is now disabled if IFF_PROMISC flag not set. | |
182 | * dfx_xmt_queue_pkt no longer checks for NULL skb | |
183 | * on Alan Cox recommendation. Added node address | |
184 | * override support. | |
185 | * 12-Sep-96 LVS Reset current address to factory address during | |
186 | * device open. Updated transmit path to post a | |
187 | * single fragment which includes PRH->end of data. | |
188 | * Mar 2000 AC Did various cleanups for 2.3.x | |
189 | * Jun 2000 jgarzik PCI and resource alloc cleanups | |
190 | * Jul 2000 tjeerd Much cleanup and some bug fixes | |
191 | * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup | |
192 | * Feb 2001 Skb allocation fixes | |
193 | * Feb 2001 davej PCI enable cleanups. | |
194 | * 04 Aug 2003 macro Converted to the DMA API. | |
195 | * 14 Aug 2004 macro Fix device names reported. | |
feea1db2 | 196 | * 14 Jun 2005 macro Use irqreturn_t. |
b2e68aa3 | 197 | * 23 Oct 2006 macro Big-endian host support. |
e89a2cfb | 198 | * 14 Dec 2006 macro TURBOchannel support. |
8848761f | 199 | * 01 Jul 2014 macro Fixes for DMA on 64-bit hosts. |
1da177e4 LT |
200 | */ |
201 | ||
202 | /* Include files */ | |
e89a2cfb | 203 | #include <linux/bitops.h> |
fcdff139 | 204 | #include <linux/compiler.h> |
1da177e4 | 205 | #include <linux/delay.h> |
e89a2cfb MR |
206 | #include <linux/dma-mapping.h> |
207 | #include <linux/eisa.h> | |
208 | #include <linux/errno.h> | |
209 | #include <linux/fddidevice.h> | |
e89a2cfb MR |
210 | #include <linux/interrupt.h> |
211 | #include <linux/ioport.h> | |
212 | #include <linux/kernel.h> | |
213 | #include <linux/module.h> | |
1da177e4 | 214 | #include <linux/netdevice.h> |
e89a2cfb | 215 | #include <linux/pci.h> |
1da177e4 | 216 | #include <linux/skbuff.h> |
e89a2cfb MR |
217 | #include <linux/slab.h> |
218 | #include <linux/string.h> | |
219 | #include <linux/tc.h> | |
1da177e4 LT |
220 | |
221 | #include <asm/byteorder.h> | |
222 | #include <asm/io.h> | |
223 | ||
224 | #include "defxx.h" | |
225 | ||
226 | /* Version information string should be updated prior to each new release! */ | |
227 | #define DRV_NAME "defxx" | |
8848761f MR |
228 | #define DRV_VERSION "v1.11" |
229 | #define DRV_RELDATE "2014/07/01" | |
1da177e4 | 230 | |
c354dfc3 | 231 | static char version[] = |
1da177e4 LT |
232 | DRV_NAME ": " DRV_VERSION " " DRV_RELDATE |
233 | " Lawrence V. Stefani and others\n"; | |
234 | ||
235 | #define DYNAMIC_BUFFERS 1 | |
236 | ||
237 | #define SKBUFF_RX_COPYBREAK 200 | |
238 | /* | |
239 | * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte | |
240 | * alignment for compatibility with old EISA boards. | |
241 | */ | |
242 | #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) | |
243 | ||
e89a2cfb MR |
244 | #ifdef CONFIG_EISA |
245 | #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type) | |
246 | #else | |
247 | #define DFX_BUS_EISA(dev) 0 | |
248 | #endif | |
249 | ||
250 | #ifdef CONFIG_TC | |
251 | #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type) | |
252 | #else | |
253 | #define DFX_BUS_TC(dev) 0 | |
254 | #endif | |
255 | ||
256 | #ifdef CONFIG_DEFXX_MMIO | |
257 | #define DFX_MMIO 1 | |
258 | #else | |
259 | #define DFX_MMIO 0 | |
260 | #endif | |
261 | ||
1da177e4 LT |
262 | /* Define module-wide (static) routines */ |
263 | ||
264 | static void dfx_bus_init(struct net_device *dev); | |
e89a2cfb | 265 | static void dfx_bus_uninit(struct net_device *dev); |
1da177e4 LT |
266 | static void dfx_bus_config_check(DFX_board_t *bp); |
267 | ||
e89a2cfb MR |
268 | static int dfx_driver_init(struct net_device *dev, |
269 | const char *print_name, | |
270 | resource_size_t bar_start); | |
1da177e4 LT |
271 | static int dfx_adap_init(DFX_board_t *bp, int get_buffers); |
272 | ||
273 | static int dfx_open(struct net_device *dev); | |
274 | static int dfx_close(struct net_device *dev); | |
275 | ||
276 | static void dfx_int_pr_halt_id(DFX_board_t *bp); | |
277 | static void dfx_int_type_0_process(DFX_board_t *bp); | |
278 | static void dfx_int_common(struct net_device *dev); | |
7d12e780 | 279 | static irqreturn_t dfx_interrupt(int irq, void *dev_id); |
1da177e4 LT |
280 | |
281 | static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); | |
282 | static void dfx_ctl_set_multicast_list(struct net_device *dev); | |
283 | static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); | |
284 | static int dfx_ctl_update_cam(DFX_board_t *bp); | |
285 | static int dfx_ctl_update_filters(DFX_board_t *bp); | |
286 | ||
287 | static int dfx_hw_dma_cmd_req(DFX_board_t *bp); | |
288 | static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); | |
289 | static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); | |
290 | static int dfx_hw_adap_state_rd(DFX_board_t *bp); | |
291 | static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); | |
292 | ||
293 | static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); | |
294 | static void dfx_rcv_queue_process(DFX_board_t *bp); | |
1b037474 | 295 | #ifdef DYNAMIC_BUFFERS |
1da177e4 | 296 | static void dfx_rcv_flush(DFX_board_t *bp); |
1b037474 MR |
297 | #else |
298 | static inline void dfx_rcv_flush(DFX_board_t *bp) {} | |
299 | #endif | |
1da177e4 | 300 | |
61357325 SH |
301 | static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, |
302 | struct net_device *dev); | |
1da177e4 LT |
303 | static int dfx_xmt_done(DFX_board_t *bp); |
304 | static void dfx_xmt_flush(DFX_board_t *bp); | |
305 | ||
306 | /* Define module-wide (static) variables */ | |
307 | ||
e89a2cfb MR |
308 | static struct pci_driver dfx_pci_driver; |
309 | static struct eisa_driver dfx_eisa_driver; | |
310 | static struct tc_driver dfx_tc_driver; | |
1da177e4 | 311 | |
6aa20a22 | 312 | |
1da177e4 LT |
313 | /* |
314 | * ======================= | |
1da177e4 LT |
315 | * = dfx_port_write_long = |
316 | * = dfx_port_read_long = | |
317 | * ======================= | |
6aa20a22 | 318 | * |
1da177e4 LT |
319 | * Overview: |
320 | * Routines for reading and writing values from/to adapter | |
6aa20a22 | 321 | * |
1da177e4 LT |
322 | * Returns: |
323 | * None | |
6aa20a22 | 324 | * |
1da177e4 | 325 | * Arguments: |
e89a2cfb MR |
326 | * bp - pointer to board information |
327 | * offset - register offset from base I/O address | |
328 | * data - for dfx_port_write_long, this is a value to write; | |
329 | * for dfx_port_read_long, this is a pointer to store | |
330 | * the read value | |
1da177e4 LT |
331 | * |
332 | * Functional Description: | |
333 | * These routines perform the correct operation to read or write | |
334 | * the adapter register. | |
6aa20a22 | 335 | * |
1da177e4 LT |
336 | * EISA port block base addresses are based on the slot number in which the |
337 | * controller is installed. For example, if the EISA controller is installed | |
338 | * in slot 4, the port block base address is 0x4000. If the controller is | |
339 | * installed in slot 2, the port block base address is 0x2000, and so on. | |
340 | * This port block can be used to access PDQ, ESIC, and DEFEA on-board | |
341 | * registers using the register offsets defined in DEFXX.H. | |
342 | * | |
343 | * PCI port block base addresses are assigned by the PCI BIOS or system | |
e89a2cfb | 344 | * firmware. There is one 128 byte port block which can be accessed. It |
1da177e4 LT |
345 | * allows for I/O mapping of both PDQ and PFI registers using the register |
346 | * offsets defined in DEFXX.H. | |
347 | * | |
348 | * Return Codes: | |
349 | * None | |
350 | * | |
351 | * Assumptions: | |
e89a2cfb | 352 | * bp->base is a valid base I/O address for this adapter. |
1da177e4 LT |
353 | * offset is a valid register offset for this adapter. |
354 | * | |
355 | * Side Effects: | |
356 | * Rather than produce macros for these functions, these routines | |
357 | * are defined using "inline" to ensure that the compiler will | |
358 | * generate inline code and not waste a procedure call and return. | |
359 | * This provides all the benefits of macros, but with the | |
360 | * advantage of strict data type checking. | |
361 | */ | |
362 | ||
e89a2cfb MR |
363 | static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data) |
364 | { | |
365 | writel(data, bp->base.mem + offset); | |
366 | mb(); | |
367 | } | |
1da177e4 | 368 | |
e89a2cfb MR |
369 | static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data) |
370 | { | |
371 | outl(data, bp->base.port + offset); | |
372 | } | |
1da177e4 | 373 | |
e89a2cfb MR |
374 | static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data) |
375 | { | |
fcdff139 | 376 | struct device __maybe_unused *bdev = bp->bus_dev; |
e89a2cfb MR |
377 | int dfx_bus_tc = DFX_BUS_TC(bdev); |
378 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
1da177e4 | 379 | |
e89a2cfb MR |
380 | if (dfx_use_mmio) |
381 | dfx_writel(bp, offset, data); | |
382 | else | |
383 | dfx_outl(bp, offset, data); | |
384 | } | |
1da177e4 | 385 | |
1da177e4 | 386 | |
e89a2cfb MR |
387 | static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data) |
388 | { | |
389 | mb(); | |
390 | *data = readl(bp->base.mem + offset); | |
391 | } | |
1da177e4 | 392 | |
e89a2cfb MR |
393 | static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data) |
394 | { | |
395 | *data = inl(bp->base.port + offset); | |
396 | } | |
1da177e4 | 397 | |
e89a2cfb MR |
398 | static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data) |
399 | { | |
fcdff139 | 400 | struct device __maybe_unused *bdev = bp->bus_dev; |
e89a2cfb MR |
401 | int dfx_bus_tc = DFX_BUS_TC(bdev); |
402 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
1da177e4 | 403 | |
e89a2cfb MR |
404 | if (dfx_use_mmio) |
405 | dfx_readl(bp, offset, data); | |
406 | else | |
407 | dfx_inl(bp, offset, data); | |
408 | } | |
1da177e4 | 409 | |
1da177e4 | 410 | |
e89a2cfb MR |
411 | /* |
412 | * ================ | |
413 | * = dfx_get_bars = | |
414 | * ================ | |
415 | * | |
416 | * Overview: | |
417 | * Retrieves the address range used to access control and status | |
418 | * registers. | |
419 | * | |
420 | * Returns: | |
421 | * None | |
422 | * | |
423 | * Arguments: | |
424 | * bdev - pointer to device information | |
425 | * bar_start - pointer to store the start address | |
426 | * bar_len - pointer to store the length of the area | |
427 | * | |
428 | * Assumptions: | |
429 | * I am sure there are some. | |
430 | * | |
431 | * Side Effects: | |
432 | * None | |
433 | */ | |
434 | static void dfx_get_bars(struct device *bdev, | |
435 | resource_size_t *bar_start, resource_size_t *bar_len) | |
436 | { | |
5349d937 | 437 | int dfx_bus_pci = dev_is_pci(bdev); |
e89a2cfb MR |
438 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
439 | int dfx_bus_tc = DFX_BUS_TC(bdev); | |
440 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
1da177e4 | 441 | |
e89a2cfb MR |
442 | if (dfx_bus_pci) { |
443 | int num = dfx_use_mmio ? 0 : 1; | |
1da177e4 | 444 | |
e89a2cfb MR |
445 | *bar_start = pci_resource_start(to_pci_dev(bdev), num); |
446 | *bar_len = pci_resource_len(to_pci_dev(bdev), num); | |
447 | } | |
448 | if (dfx_bus_eisa) { | |
449 | unsigned long base_addr = to_eisa_device(bdev)->base_addr; | |
fef85fc4 MR |
450 | resource_size_t bar_lo; |
451 | resource_size_t bar_hi; | |
e89a2cfb MR |
452 | |
453 | if (dfx_use_mmio) { | |
fef85fc4 MR |
454 | bar_lo = inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_2); |
455 | bar_lo <<= 8; | |
456 | bar_lo |= inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_1); | |
457 | bar_lo <<= 8; | |
458 | bar_lo |= inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_0); | |
459 | bar_lo <<= 8; | |
460 | *bar_start = bar_lo; | |
461 | bar_hi = inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_2); | |
462 | bar_hi <<= 8; | |
463 | bar_hi |= inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_1); | |
464 | bar_hi <<= 8; | |
465 | bar_hi |= inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_0); | |
466 | bar_hi <<= 8; | |
467 | *bar_len = ((bar_hi - bar_lo) | PI_MEM_ADD_MASK_M) + 1; | |
e89a2cfb MR |
468 | } else { |
469 | *bar_start = base_addr; | |
b98dfaf2 MR |
470 | *bar_len = PI_ESIC_K_CSR_IO_LEN + |
471 | PI_ESIC_K_BURST_HOLDOFF_LEN; | |
e89a2cfb MR |
472 | } |
473 | } | |
474 | if (dfx_bus_tc) { | |
475 | *bar_start = to_tc_dev(bdev)->resource.start + | |
476 | PI_TC_K_CSR_OFFSET; | |
477 | *bar_len = PI_TC_K_CSR_LEN; | |
478 | } | |
479 | } | |
6aa20a22 | 480 | |
fd8f4997 SH |
481 | static const struct net_device_ops dfx_netdev_ops = { |
482 | .ndo_open = dfx_open, | |
483 | .ndo_stop = dfx_close, | |
484 | .ndo_start_xmit = dfx_xmt_queue_pkt, | |
485 | .ndo_get_stats = dfx_ctl_get_stats, | |
afc4b13d | 486 | .ndo_set_rx_mode = dfx_ctl_set_multicast_list, |
fd8f4997 SH |
487 | .ndo_set_mac_address = dfx_ctl_set_mac_address, |
488 | }; | |
489 | ||
1da177e4 | 490 | /* |
e89a2cfb MR |
491 | * ================ |
492 | * = dfx_register = | |
493 | * ================ | |
6aa20a22 | 494 | * |
1da177e4 | 495 | * Overview: |
e89a2cfb | 496 | * Initializes a supported FDDI controller |
6aa20a22 | 497 | * |
1da177e4 LT |
498 | * Returns: |
499 | * Condition code | |
6aa20a22 | 500 | * |
1da177e4 | 501 | * Arguments: |
e89a2cfb | 502 | * bdev - pointer to device information |
1da177e4 LT |
503 | * |
504 | * Functional Description: | |
505 | * | |
506 | * Return Codes: | |
507 | * 0 - This device (fddi0, fddi1, etc) configured successfully | |
508 | * -EBUSY - Failed to get resources, or dfx_driver_init failed. | |
509 | * | |
510 | * Assumptions: | |
511 | * It compiles so it should work :-( (PCI cards do :-) | |
512 | * | |
513 | * Side Effects: | |
514 | * Device structures for FDDI adapters (fddi0, fddi1, etc) are | |
515 | * initialized and the board resources are read and stored in | |
516 | * the device structure. | |
517 | */ | |
c354dfc3 | 518 | static int dfx_register(struct device *bdev) |
1da177e4 LT |
519 | { |
520 | static int version_disp; | |
5349d937 | 521 | int dfx_bus_pci = dev_is_pci(bdev); |
fef85fc4 | 522 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
e89a2cfb MR |
523 | int dfx_bus_tc = DFX_BUS_TC(bdev); |
524 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
fb28ad35 | 525 | const char *print_name = dev_name(bdev); |
1da177e4 LT |
526 | struct net_device *dev; |
527 | DFX_board_t *bp; /* board pointer */ | |
e89a2cfb MR |
528 | resource_size_t bar_start = 0; /* pointer to port */ |
529 | resource_size_t bar_len = 0; /* resource length */ | |
1da177e4 | 530 | int alloc_size; /* total buffer size used */ |
e89a2cfb MR |
531 | struct resource *region; |
532 | int err = 0; | |
1da177e4 LT |
533 | |
534 | if (!version_disp) { /* display version info if adapter is found */ | |
535 | version_disp = 1; /* set display flag to TRUE so that */ | |
536 | printk(version); /* we only display this string ONCE */ | |
537 | } | |
538 | ||
1da177e4 LT |
539 | dev = alloc_fddidev(sizeof(*bp)); |
540 | if (!dev) { | |
e89a2cfb | 541 | printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n", |
1da177e4 LT |
542 | print_name); |
543 | return -ENOMEM; | |
544 | } | |
545 | ||
546 | /* Enable PCI device. */ | |
a65da0c3 MR |
547 | if (dfx_bus_pci) { |
548 | err = pci_enable_device(to_pci_dev(bdev)); | |
549 | if (err) { | |
550 | pr_err("%s: Cannot enable PCI device, aborting\n", | |
551 | print_name); | |
552 | goto err_out; | |
553 | } | |
1da177e4 LT |
554 | } |
555 | ||
e89a2cfb MR |
556 | SET_NETDEV_DEV(dev, bdev); |
557 | ||
558 | bp = netdev_priv(dev); | |
559 | bp->bus_dev = bdev; | |
560 | dev_set_drvdata(bdev, dev); | |
1da177e4 | 561 | |
e89a2cfb | 562 | dfx_get_bars(bdev, &bar_start, &bar_len); |
fef85fc4 MR |
563 | if (dfx_bus_eisa && dfx_use_mmio && bar_start == 0) { |
564 | pr_err("%s: Cannot use MMIO, no address set, aborting\n", | |
565 | print_name); | |
566 | pr_err("%s: Run ECU and set adapter's MMIO location\n", | |
567 | print_name); | |
568 | pr_err("%s: Or recompile driver with \"CONFIG_DEFXX_MMIO=n\"" | |
569 | "\n", print_name); | |
570 | err = -ENXIO; | |
571 | goto err_out; | |
572 | } | |
1da177e4 | 573 | |
e89a2cfb MR |
574 | if (dfx_use_mmio) |
575 | region = request_mem_region(bar_start, bar_len, print_name); | |
576 | else | |
577 | region = request_region(bar_start, bar_len, print_name); | |
578 | if (!region) { | |
1da177e4 | 579 | printk(KERN_ERR "%s: Cannot reserve I/O resource " |
e89a2cfb MR |
580 | "0x%lx @ 0x%lx, aborting\n", |
581 | print_name, (long)bar_len, (long)bar_start); | |
1da177e4 | 582 | err = -EBUSY; |
e89a2cfb | 583 | goto err_out_disable; |
1da177e4 LT |
584 | } |
585 | ||
e89a2cfb MR |
586 | /* Set up I/O base address. */ |
587 | if (dfx_use_mmio) { | |
588 | bp->base.mem = ioremap_nocache(bar_start, bar_len); | |
589 | if (!bp->base.mem) { | |
590 | printk(KERN_ERR "%s: Cannot map MMIO\n", print_name); | |
8a323526 | 591 | err = -ENOMEM; |
e89a2cfb MR |
592 | goto err_out_region; |
593 | } | |
594 | } else { | |
595 | bp->base.port = bar_start; | |
596 | dev->base_addr = bar_start; | |
597 | } | |
1da177e4 | 598 | |
e89a2cfb | 599 | /* Initialize new device structure */ |
fd8f4997 | 600 | dev->netdev_ops = &dfx_netdev_ops; |
1da177e4 | 601 | |
e89a2cfb MR |
602 | if (dfx_bus_pci) |
603 | pci_set_master(to_pci_dev(bdev)); | |
1da177e4 | 604 | |
e89a2cfb | 605 | if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) { |
1da177e4 | 606 | err = -ENODEV; |
e89a2cfb | 607 | goto err_out_unmap; |
1da177e4 LT |
608 | } |
609 | ||
610 | err = register_netdev(dev); | |
611 | if (err) | |
612 | goto err_out_kfree; | |
613 | ||
614 | printk("%s: registered as %s\n", print_name, dev->name); | |
615 | return 0; | |
616 | ||
617 | err_out_kfree: | |
618 | alloc_size = sizeof(PI_DESCR_BLOCK) + | |
619 | PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + | |
620 | #ifndef DYNAMIC_BUFFERS | |
621 | (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + | |
622 | #endif | |
623 | sizeof(PI_CONSUMER_BLOCK) + | |
624 | (PI_ALIGN_K_DESC_BLK - 1); | |
625 | if (bp->kmalloced) | |
e89a2cfb MR |
626 | dma_free_coherent(bdev, alloc_size, |
627 | bp->kmalloced, bp->kmalloced_dma); | |
628 | ||
629 | err_out_unmap: | |
630 | if (dfx_use_mmio) | |
631 | iounmap(bp->base.mem); | |
632 | ||
1da177e4 | 633 | err_out_region: |
e89a2cfb MR |
634 | if (dfx_use_mmio) |
635 | release_mem_region(bar_start, bar_len); | |
636 | else | |
637 | release_region(bar_start, bar_len); | |
638 | ||
639 | err_out_disable: | |
640 | if (dfx_bus_pci) | |
641 | pci_disable_device(to_pci_dev(bdev)); | |
642 | ||
1da177e4 LT |
643 | err_out: |
644 | free_netdev(dev); | |
645 | return err; | |
646 | } | |
647 | ||
6aa20a22 | 648 | |
1da177e4 LT |
649 | /* |
650 | * ================ | |
651 | * = dfx_bus_init = | |
652 | * ================ | |
6aa20a22 | 653 | * |
1da177e4 | 654 | * Overview: |
e89a2cfb | 655 | * Initializes the bus-specific controller logic. |
6aa20a22 | 656 | * |
1da177e4 LT |
657 | * Returns: |
658 | * None | |
6aa20a22 | 659 | * |
1da177e4 LT |
660 | * Arguments: |
661 | * dev - pointer to device information | |
662 | * | |
663 | * Functional Description: | |
664 | * Determine and save adapter IRQ in device table, | |
665 | * then perform bus-specific logic initialization. | |
666 | * | |
667 | * Return Codes: | |
668 | * None | |
669 | * | |
670 | * Assumptions: | |
e89a2cfb | 671 | * bp->base has already been set with the proper |
1da177e4 LT |
672 | * base I/O address for this device. |
673 | * | |
674 | * Side Effects: | |
675 | * Interrupts are enabled at the adapter bus-specific logic. | |
676 | * Note: Interrupts at the DMA engine (PDQ chip) are not | |
677 | * enabled yet. | |
678 | */ | |
679 | ||
c354dfc3 | 680 | static void dfx_bus_init(struct net_device *dev) |
1da177e4 | 681 | { |
e89a2cfb MR |
682 | DFX_board_t *bp = netdev_priv(dev); |
683 | struct device *bdev = bp->bus_dev; | |
5349d937 | 684 | int dfx_bus_pci = dev_is_pci(bdev); |
e89a2cfb MR |
685 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
686 | int dfx_bus_tc = DFX_BUS_TC(bdev); | |
687 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
688 | u8 val; | |
1da177e4 LT |
689 | |
690 | DBG_printk("In dfx_bus_init...\n"); | |
691 | ||
e89a2cfb | 692 | /* Initialize a pointer back to the net_device struct */ |
1da177e4 LT |
693 | bp->dev = dev; |
694 | ||
695 | /* Initialize adapter based on bus type */ | |
696 | ||
e89a2cfb MR |
697 | if (dfx_bus_tc) |
698 | dev->irq = to_tc_dev(bdev)->interrupt; | |
699 | if (dfx_bus_eisa) { | |
700 | unsigned long base_addr = to_eisa_device(bdev)->base_addr; | |
1da177e4 | 701 | |
b98dfaf2 MR |
702 | /* Disable the board before fiddling with the decoders. */ |
703 | outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL); | |
704 | ||
e89a2cfb MR |
705 | /* Get the interrupt level from the ESIC chip. */ |
706 | val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); | |
707 | val &= PI_CONFIG_STAT_0_M_IRQ; | |
708 | val >>= PI_CONFIG_STAT_0_V_IRQ; | |
1da177e4 | 709 | |
e89a2cfb MR |
710 | switch (val) { |
711 | case PI_CONFIG_STAT_0_IRQ_K_9: | |
712 | dev->irq = 9; | |
713 | break; | |
1da177e4 | 714 | |
e89a2cfb MR |
715 | case PI_CONFIG_STAT_0_IRQ_K_10: |
716 | dev->irq = 10; | |
717 | break; | |
1da177e4 | 718 | |
e89a2cfb MR |
719 | case PI_CONFIG_STAT_0_IRQ_K_11: |
720 | dev->irq = 11; | |
721 | break; | |
1da177e4 | 722 | |
e89a2cfb MR |
723 | case PI_CONFIG_STAT_0_IRQ_K_15: |
724 | dev->irq = 15; | |
725 | break; | |
726 | } | |
1da177e4 | 727 | |
e89a2cfb | 728 | /* |
fef85fc4 | 729 | * Enable memory decoding (MEMCS1) and/or port decoding |
e89a2cfb | 730 | * (IOCS1/IOCS0) as appropriate in Function Control |
fef85fc4 MR |
731 | * Register. MEMCS1 or IOCS0 is used for PDQ registers, |
732 | * taking 16 32-bit words, while IOCS1 is used for the | |
733 | * Burst Holdoff register, taking a single 32-bit word | |
734 | * only. We use the slot-specific I/O range as per the | |
735 | * ESIC spec, that is set bits 15:12 in the mask registers | |
736 | * to mask them out. | |
e89a2cfb | 737 | */ |
1da177e4 | 738 | |
e89a2cfb | 739 | /* Set the decode range of the board. */ |
b98dfaf2 | 740 | val = 0; |
8a189f12 | 741 | outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_1); |
b98dfaf2 MR |
742 | val = PI_DEFEA_K_CSR_IO; |
743 | outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0); | |
744 | ||
745 | val = PI_IO_CMP_M_SLOT; | |
8a189f12 | 746 | outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_1); |
b98dfaf2 MR |
747 | val = (PI_ESIC_K_CSR_IO_LEN - 1) & ~3; |
748 | outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0); | |
749 | ||
750 | val = 0; | |
751 | outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1); | |
752 | val = PI_DEFEA_K_BURST_HOLDOFF; | |
753 | outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0); | |
754 | ||
755 | val = PI_IO_CMP_M_SLOT; | |
8a189f12 | 756 | outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_1); |
b98dfaf2 MR |
757 | val = (PI_ESIC_K_BURST_HOLDOFF_LEN - 1) & ~3; |
758 | outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0); | |
e89a2cfb MR |
759 | |
760 | /* Enable the decoders. */ | |
fef85fc4 | 761 | val = PI_FUNCTION_CNTRL_M_IOCS1; |
e89a2cfb | 762 | if (dfx_use_mmio) |
fef85fc4 MR |
763 | val |= PI_FUNCTION_CNTRL_M_MEMCS1; |
764 | else | |
765 | val |= PI_FUNCTION_CNTRL_M_IOCS0; | |
8a189f12 | 766 | outb(val, base_addr + PI_ESIC_K_FUNCTION_CNTRL); |
1da177e4 LT |
767 | |
768 | /* | |
e89a2cfb MR |
769 | * Enable access to the rest of the module |
770 | * (including PDQ and packet memory). | |
1da177e4 | 771 | */ |
e89a2cfb | 772 | val = PI_SLOT_CNTRL_M_ENB; |
8a189f12 | 773 | outb(val, base_addr + PI_ESIC_K_SLOT_CNTRL); |
1da177e4 | 774 | |
e89a2cfb MR |
775 | /* |
776 | * Map PDQ registers into memory or port space. This is | |
777 | * done with a bit in the Burst Holdoff register. | |
778 | */ | |
779 | val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); | |
780 | if (dfx_use_mmio) | |
b1a6d3ec | 781 | val |= PI_BURST_HOLDOFF_M_MEM_MAP; |
e89a2cfb | 782 | else |
b1a6d3ec | 783 | val &= ~PI_BURST_HOLDOFF_M_MEM_MAP; |
8a189f12 | 784 | outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF); |
1da177e4 LT |
785 | |
786 | /* Enable interrupts at EISA bus interface chip (ESIC) */ | |
e89a2cfb MR |
787 | val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
788 | val |= PI_CONFIG_STAT_0_M_INT_ENB; | |
8a189f12 | 789 | outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
e89a2cfb MR |
790 | } |
791 | if (dfx_bus_pci) { | |
792 | struct pci_dev *pdev = to_pci_dev(bdev); | |
1da177e4 LT |
793 | |
794 | /* Get the interrupt level from the PCI Configuration Table */ | |
795 | ||
796 | dev->irq = pdev->irq; | |
797 | ||
798 | /* Check Latency Timer and set if less than minimal */ | |
799 | ||
800 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); | |
e89a2cfb | 801 | if (val < PFI_K_LAT_TIMER_MIN) { |
1da177e4 LT |
802 | val = PFI_K_LAT_TIMER_DEF; |
803 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); | |
e89a2cfb | 804 | } |
1da177e4 LT |
805 | |
806 | /* Enable interrupts at PCI bus interface chip (PFI) */ | |
e89a2cfb MR |
807 | val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; |
808 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); | |
809 | } | |
810 | } | |
1da177e4 | 811 | |
e89a2cfb MR |
812 | /* |
813 | * ================== | |
814 | * = dfx_bus_uninit = | |
815 | * ================== | |
816 | * | |
817 | * Overview: | |
818 | * Uninitializes the bus-specific controller logic. | |
819 | * | |
820 | * Returns: | |
821 | * None | |
822 | * | |
823 | * Arguments: | |
824 | * dev - pointer to device information | |
825 | * | |
826 | * Functional Description: | |
827 | * Perform bus-specific logic uninitialization. | |
828 | * | |
829 | * Return Codes: | |
830 | * None | |
831 | * | |
832 | * Assumptions: | |
833 | * bp->base has already been set with the proper | |
834 | * base I/O address for this device. | |
835 | * | |
836 | * Side Effects: | |
837 | * Interrupts are disabled at the adapter bus-specific logic. | |
838 | */ | |
839 | ||
c354dfc3 | 840 | static void dfx_bus_uninit(struct net_device *dev) |
e89a2cfb MR |
841 | { |
842 | DFX_board_t *bp = netdev_priv(dev); | |
843 | struct device *bdev = bp->bus_dev; | |
5349d937 | 844 | int dfx_bus_pci = dev_is_pci(bdev); |
e89a2cfb MR |
845 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
846 | u8 val; | |
847 | ||
848 | DBG_printk("In dfx_bus_uninit...\n"); | |
849 | ||
850 | /* Uninitialize adapter based on bus type */ | |
851 | ||
852 | if (dfx_bus_eisa) { | |
853 | unsigned long base_addr = to_eisa_device(bdev)->base_addr; | |
854 | ||
855 | /* Disable interrupts at EISA bus interface chip (ESIC) */ | |
856 | val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); | |
857 | val &= ~PI_CONFIG_STAT_0_M_INT_ENB; | |
8a189f12 | 858 | outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
6a931423 MR |
859 | |
860 | /* Disable the board. */ | |
861 | outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL); | |
862 | ||
863 | /* Disable memory and port decoders. */ | |
864 | outb(0, base_addr + PI_ESIC_K_FUNCTION_CNTRL); | |
e89a2cfb MR |
865 | } |
866 | if (dfx_bus_pci) { | |
867 | /* Disable interrupts at PCI bus interface chip (PFI) */ | |
868 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0); | |
1da177e4 | 869 | } |
e89a2cfb | 870 | } |
1da177e4 | 871 | |
6aa20a22 | 872 | |
1da177e4 LT |
873 | /* |
874 | * ======================== | |
875 | * = dfx_bus_config_check = | |
876 | * ======================== | |
6aa20a22 | 877 | * |
1da177e4 LT |
878 | * Overview: |
879 | * Checks the configuration (burst size, full-duplex, etc.) If any parameters | |
880 | * are illegal, then this routine will set new defaults. | |
6aa20a22 | 881 | * |
1da177e4 LT |
882 | * Returns: |
883 | * None | |
6aa20a22 | 884 | * |
1da177e4 LT |
885 | * Arguments: |
886 | * bp - pointer to board information | |
887 | * | |
888 | * Functional Description: | |
889 | * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later | |
890 | * PDQ, and all FDDI PCI controllers, all values are legal. | |
891 | * | |
892 | * Return Codes: | |
893 | * None | |
894 | * | |
895 | * Assumptions: | |
896 | * dfx_adap_init has NOT been called yet so burst size and other items have | |
897 | * not been set. | |
898 | * | |
899 | * Side Effects: | |
900 | * None | |
901 | */ | |
902 | ||
c354dfc3 | 903 | static void dfx_bus_config_check(DFX_board_t *bp) |
1da177e4 | 904 | { |
fcdff139 | 905 | struct device __maybe_unused *bdev = bp->bus_dev; |
e89a2cfb | 906 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
1da177e4 | 907 | int status; /* return code from adapter port control call */ |
1da177e4 LT |
908 | u32 host_data; /* LW data returned from port control call */ |
909 | ||
910 | DBG_printk("In dfx_bus_config_check...\n"); | |
911 | ||
912 | /* Configuration check only valid for EISA adapter */ | |
913 | ||
e89a2cfb | 914 | if (dfx_bus_eisa) { |
1da177e4 LT |
915 | /* |
916 | * First check if revision 2 EISA controller. Rev. 1 cards used | |
917 | * PDQ revision B, so no workaround needed in this case. Rev. 3 | |
918 | * cards used PDQ revision E, so no workaround needed in this | |
919 | * case, either. Only Rev. 2 cards used either Rev. D or E | |
920 | * chips, so we must verify the chip revision on Rev. 2 cards. | |
921 | */ | |
e89a2cfb | 922 | if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) { |
1da177e4 | 923 | /* |
e89a2cfb MR |
924 | * Revision 2 FDDI EISA controller found, |
925 | * so let's check PDQ revision of adapter. | |
1da177e4 | 926 | */ |
1da177e4 LT |
927 | status = dfx_hw_port_ctrl_req(bp, |
928 | PI_PCTRL_M_SUB_CMD, | |
929 | PI_SUB_CMD_K_PDQ_REV_GET, | |
930 | 0, | |
931 | &host_data); | |
932 | if ((status != DFX_K_SUCCESS) || (host_data == 2)) | |
933 | { | |
934 | /* | |
935 | * Either we couldn't determine the PDQ revision, or | |
936 | * we determined that it is at revision D. In either case, | |
937 | * we need to implement the workaround. | |
938 | */ | |
939 | ||
940 | /* Ensure that the burst size is set to 8 longwords or less */ | |
941 | ||
942 | switch (bp->burst_size) | |
943 | { | |
944 | case PI_PDATA_B_DMA_BURST_SIZE_32: | |
945 | case PI_PDATA_B_DMA_BURST_SIZE_16: | |
946 | bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; | |
947 | break; | |
948 | ||
949 | default: | |
950 | break; | |
951 | } | |
952 | ||
953 | /* Ensure that full-duplex mode is not enabled */ | |
954 | ||
955 | bp->full_duplex_enb = PI_SNMP_K_FALSE; | |
956 | } | |
957 | } | |
958 | } | |
959 | } | |
960 | ||
6aa20a22 | 961 | |
1da177e4 LT |
962 | /* |
963 | * =================== | |
964 | * = dfx_driver_init = | |
965 | * =================== | |
6aa20a22 | 966 | * |
1da177e4 LT |
967 | * Overview: |
968 | * Initializes remaining adapter board structure information | |
969 | * and makes sure adapter is in a safe state prior to dfx_open(). | |
6aa20a22 | 970 | * |
1da177e4 LT |
971 | * Returns: |
972 | * Condition code | |
6aa20a22 | 973 | * |
1da177e4 LT |
974 | * Arguments: |
975 | * dev - pointer to device information | |
976 | * print_name - printable device name | |
977 | * | |
978 | * Functional Description: | |
979 | * This function allocates additional resources such as the host memory | |
980 | * blocks needed by the adapter (eg. descriptor and consumer blocks). | |
981 | * Remaining bus initialization steps are also completed. The adapter | |
982 | * is also reset so that it is in the DMA_UNAVAILABLE state. The OS | |
983 | * must call dfx_open() to open the adapter and bring it on-line. | |
984 | * | |
985 | * Return Codes: | |
986 | * DFX_K_SUCCESS - initialization succeeded | |
987 | * DFX_K_FAILURE - initialization failed - could not allocate memory | |
988 | * or read adapter MAC address | |
989 | * | |
990 | * Assumptions: | |
991 | * Memory allocated from pci_alloc_consistent() call is physically | |
992 | * contiguous, locked memory. | |
993 | * | |
994 | * Side Effects: | |
995 | * Adapter is reset and should be in DMA_UNAVAILABLE state before | |
996 | * returning from this routine. | |
997 | */ | |
998 | ||
1dd06ae8 GKH |
999 | static int dfx_driver_init(struct net_device *dev, const char *print_name, |
1000 | resource_size_t bar_start) | |
1da177e4 | 1001 | { |
e89a2cfb MR |
1002 | DFX_board_t *bp = netdev_priv(dev); |
1003 | struct device *bdev = bp->bus_dev; | |
5349d937 | 1004 | int dfx_bus_pci = dev_is_pci(bdev); |
e89a2cfb MR |
1005 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
1006 | int dfx_bus_tc = DFX_BUS_TC(bdev); | |
1007 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
1008 | int alloc_size; /* total buffer size needed */ | |
1009 | char *top_v, *curr_v; /* virtual addrs into memory block */ | |
1010 | dma_addr_t top_p, curr_p; /* physical addrs into memory block */ | |
eca1ad82 AV |
1011 | u32 data; /* host data register value */ |
1012 | __le32 le32; | |
e89a2cfb | 1013 | char *board_name = NULL; |
1da177e4 LT |
1014 | |
1015 | DBG_printk("In dfx_driver_init...\n"); | |
1016 | ||
1017 | /* Initialize bus-specific hardware registers */ | |
1018 | ||
1019 | dfx_bus_init(dev); | |
1020 | ||
1021 | /* | |
1022 | * Initialize default values for configurable parameters | |
1023 | * | |
1024 | * Note: All of these parameters are ones that a user may | |
1025 | * want to customize. It'd be nice to break these | |
1026 | * out into Space.c or someplace else that's more | |
1027 | * accessible/understandable than this file. | |
1028 | */ | |
1029 | ||
1030 | bp->full_duplex_enb = PI_SNMP_K_FALSE; | |
1031 | bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ | |
1032 | bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; | |
1033 | bp->rcv_bufs_to_post = RCV_BUFS_DEF; | |
1034 | ||
1035 | /* | |
1036 | * Ensure that HW configuration is OK | |
1037 | * | |
1038 | * Note: Depending on the hardware revision, we may need to modify | |
1039 | * some of the configurable parameters to workaround hardware | |
1040 | * limitations. We'll perform this configuration check AFTER | |
1041 | * setting the parameters to their default values. | |
1042 | */ | |
1043 | ||
1044 | dfx_bus_config_check(bp); | |
1045 | ||
1046 | /* Disable PDQ interrupts first */ | |
1047 | ||
1048 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1049 | ||
1050 | /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ | |
1051 | ||
1052 | (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); | |
1053 | ||
1054 | /* Read the factory MAC address from the adapter then save it */ | |
1055 | ||
1056 | if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, | |
1057 | &data) != DFX_K_SUCCESS) { | |
1058 | printk("%s: Could not read adapter factory MAC address!\n", | |
1059 | print_name); | |
807540ba | 1060 | return DFX_K_FAILURE; |
1da177e4 | 1061 | } |
e89a2cfb MR |
1062 | le32 = cpu_to_le32(data); |
1063 | memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32)); | |
1da177e4 LT |
1064 | |
1065 | if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, | |
1066 | &data) != DFX_K_SUCCESS) { | |
1067 | printk("%s: Could not read adapter factory MAC address!\n", | |
1068 | print_name); | |
807540ba | 1069 | return DFX_K_FAILURE; |
1da177e4 | 1070 | } |
e89a2cfb MR |
1071 | le32 = cpu_to_le32(data); |
1072 | memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16)); | |
1da177e4 LT |
1073 | |
1074 | /* | |
1075 | * Set current address to factory address | |
1076 | * | |
1077 | * Note: Node address override support is handled through | |
1078 | * dfx_ctl_set_mac_address. | |
1079 | */ | |
1080 | ||
1081 | memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); | |
e89a2cfb MR |
1082 | if (dfx_bus_tc) |
1083 | board_name = "DEFTA"; | |
1084 | if (dfx_bus_eisa) | |
1085 | board_name = "DEFEA"; | |
1086 | if (dfx_bus_pci) | |
1087 | board_name = "DEFPA"; | |
69d279ea | 1088 | pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n", |
e89a2cfb | 1089 | print_name, board_name, dfx_use_mmio ? "" : "I/O ", |
69d279ea | 1090 | (long long)bar_start, dev->irq, dev->dev_addr); |
1da177e4 LT |
1091 | |
1092 | /* | |
1093 | * Get memory for descriptor block, consumer block, and other buffers | |
1094 | * that need to be DMA read or written to by the adapter. | |
1095 | */ | |
1096 | ||
1097 | alloc_size = sizeof(PI_DESCR_BLOCK) + | |
1098 | PI_CMD_REQ_K_SIZE_MAX + | |
1099 | PI_CMD_RSP_K_SIZE_MAX + | |
1100 | #ifndef DYNAMIC_BUFFERS | |
1101 | (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + | |
1102 | #endif | |
1103 | sizeof(PI_CONSUMER_BLOCK) + | |
1104 | (PI_ALIGN_K_DESC_BLK - 1); | |
ede23fa8 JP |
1105 | bp->kmalloced = top_v = dma_zalloc_coherent(bp->bus_dev, alloc_size, |
1106 | &bp->kmalloced_dma, | |
1107 | GFP_ATOMIC); | |
d0320f75 | 1108 | if (top_v == NULL) |
807540ba | 1109 | return DFX_K_FAILURE; |
d0320f75 | 1110 | |
1da177e4 LT |
1111 | top_p = bp->kmalloced_dma; /* get physical address of buffer */ |
1112 | ||
1113 | /* | |
1114 | * To guarantee the 8K alignment required for the descriptor block, 8K - 1 | |
1115 | * plus the amount of memory needed was allocated. The physical address | |
1116 | * is now 8K aligned. By carving up the memory in a specific order, | |
1117 | * we'll guarantee the alignment requirements for all other structures. | |
1118 | * | |
1119 | * Note: If the assumptions change regarding the non-paged, non-cached, | |
1120 | * physically contiguous nature of the memory block or the address | |
1121 | * alignments, then we'll need to implement a different algorithm | |
1122 | * for allocating the needed memory. | |
1123 | */ | |
1124 | ||
1125 | curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); | |
1126 | curr_v = top_v + (curr_p - top_p); | |
1127 | ||
1128 | /* Reserve space for descriptor block */ | |
1129 | ||
1130 | bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; | |
1131 | bp->descr_block_phys = curr_p; | |
1132 | curr_v += sizeof(PI_DESCR_BLOCK); | |
1133 | curr_p += sizeof(PI_DESCR_BLOCK); | |
1134 | ||
1135 | /* Reserve space for command request buffer */ | |
1136 | ||
1137 | bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; | |
1138 | bp->cmd_req_phys = curr_p; | |
1139 | curr_v += PI_CMD_REQ_K_SIZE_MAX; | |
1140 | curr_p += PI_CMD_REQ_K_SIZE_MAX; | |
1141 | ||
1142 | /* Reserve space for command response buffer */ | |
1143 | ||
1144 | bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; | |
1145 | bp->cmd_rsp_phys = curr_p; | |
1146 | curr_v += PI_CMD_RSP_K_SIZE_MAX; | |
1147 | curr_p += PI_CMD_RSP_K_SIZE_MAX; | |
1148 | ||
1149 | /* Reserve space for the LLC host receive queue buffers */ | |
1150 | ||
1151 | bp->rcv_block_virt = curr_v; | |
1152 | bp->rcv_block_phys = curr_p; | |
1153 | ||
1154 | #ifndef DYNAMIC_BUFFERS | |
1155 | curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); | |
1156 | curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); | |
1157 | #endif | |
1158 | ||
1159 | /* Reserve space for the consumer block */ | |
1160 | ||
1161 | bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; | |
1162 | bp->cons_block_phys = curr_p; | |
1163 | ||
1164 | /* Display virtual and physical addresses if debug driver */ | |
1165 | ||
51ba0ed1 MR |
1166 | DBG_printk("%s: Descriptor block virt = %p, phys = %pad\n", |
1167 | print_name, bp->descr_block_virt, &bp->descr_block_phys); | |
1168 | DBG_printk("%s: Command Request buffer virt = %p, phys = %pad\n", | |
1169 | print_name, bp->cmd_req_virt, &bp->cmd_req_phys); | |
1170 | DBG_printk("%s: Command Response buffer virt = %p, phys = %pad\n", | |
1171 | print_name, bp->cmd_rsp_virt, &bp->cmd_rsp_phys); | |
1172 | DBG_printk("%s: Receive buffer block virt = %p, phys = %pad\n", | |
1173 | print_name, bp->rcv_block_virt, &bp->rcv_block_phys); | |
1174 | DBG_printk("%s: Consumer block virt = %p, phys = %pad\n", | |
1175 | print_name, bp->cons_block_virt, &bp->cons_block_phys); | |
1da177e4 | 1176 | |
807540ba | 1177 | return DFX_K_SUCCESS; |
1da177e4 LT |
1178 | } |
1179 | ||
6aa20a22 | 1180 | |
1da177e4 LT |
1181 | /* |
1182 | * ================= | |
1183 | * = dfx_adap_init = | |
1184 | * ================= | |
6aa20a22 | 1185 | * |
1da177e4 LT |
1186 | * Overview: |
1187 | * Brings the adapter to the link avail/link unavailable state. | |
6aa20a22 | 1188 | * |
1da177e4 LT |
1189 | * Returns: |
1190 | * Condition code | |
6aa20a22 | 1191 | * |
1da177e4 LT |
1192 | * Arguments: |
1193 | * bp - pointer to board information | |
1194 | * get_buffers - non-zero if buffers to be allocated | |
1195 | * | |
1196 | * Functional Description: | |
1197 | * Issues the low-level firmware/hardware calls necessary to bring | |
1198 | * the adapter up, or to properly reset and restore adapter during | |
1199 | * run-time. | |
1200 | * | |
1201 | * Return Codes: | |
1202 | * DFX_K_SUCCESS - Adapter brought up successfully | |
1203 | * DFX_K_FAILURE - Adapter initialization failed | |
1204 | * | |
1205 | * Assumptions: | |
1206 | * bp->reset_type should be set to a valid reset type value before | |
1207 | * calling this routine. | |
1208 | * | |
1209 | * Side Effects: | |
1210 | * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state | |
1211 | * upon a successful return of this routine. | |
1212 | */ | |
1213 | ||
1214 | static int dfx_adap_init(DFX_board_t *bp, int get_buffers) | |
1215 | { | |
1216 | DBG_printk("In dfx_adap_init...\n"); | |
1217 | ||
1218 | /* Disable PDQ interrupts first */ | |
1219 | ||
1220 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1221 | ||
1222 | /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ | |
1223 | ||
1224 | if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) | |
1225 | { | |
1226 | printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); | |
807540ba | 1227 | return DFX_K_FAILURE; |
1da177e4 LT |
1228 | } |
1229 | ||
1230 | /* | |
1231 | * When the PDQ is reset, some false Type 0 interrupts may be pending, | |
1232 | * so we'll acknowledge all Type 0 interrupts now before continuing. | |
1233 | */ | |
1234 | ||
1235 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); | |
1236 | ||
1237 | /* | |
1238 | * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state | |
1239 | * | |
1240 | * Note: We only need to clear host copies of these registers. The PDQ reset | |
1241 | * takes care of the on-board register values. | |
1242 | */ | |
1243 | ||
1244 | bp->cmd_req_reg.lword = 0; | |
1245 | bp->cmd_rsp_reg.lword = 0; | |
1246 | bp->rcv_xmt_reg.lword = 0; | |
1247 | ||
1248 | /* Clear consumer block before going to DMA_AVAILABLE state */ | |
1249 | ||
1250 | memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); | |
1251 | ||
1252 | /* Initialize the DMA Burst Size */ | |
1253 | ||
1254 | if (dfx_hw_port_ctrl_req(bp, | |
1255 | PI_PCTRL_M_SUB_CMD, | |
1256 | PI_SUB_CMD_K_BURST_SIZE_SET, | |
1257 | bp->burst_size, | |
1258 | NULL) != DFX_K_SUCCESS) | |
1259 | { | |
1260 | printk("%s: Could not set adapter burst size!\n", bp->dev->name); | |
807540ba | 1261 | return DFX_K_FAILURE; |
1da177e4 LT |
1262 | } |
1263 | ||
1264 | /* | |
1265 | * Set base address of Consumer Block | |
1266 | * | |
1267 | * Assumption: 32-bit physical address of consumer block is 64 byte | |
1268 | * aligned. That is, bits 0-5 of the address must be zero. | |
1269 | */ | |
1270 | ||
1271 | if (dfx_hw_port_ctrl_req(bp, | |
1272 | PI_PCTRL_M_CONS_BLOCK, | |
1273 | bp->cons_block_phys, | |
1274 | 0, | |
1275 | NULL) != DFX_K_SUCCESS) | |
1276 | { | |
1277 | printk("%s: Could not set consumer block address!\n", bp->dev->name); | |
807540ba | 1278 | return DFX_K_FAILURE; |
1da177e4 LT |
1279 | } |
1280 | ||
1281 | /* | |
b2e68aa3 MR |
1282 | * Set the base address of Descriptor Block and bring adapter |
1283 | * to DMA_AVAILABLE state. | |
1da177e4 | 1284 | * |
b2e68aa3 MR |
1285 | * Note: We also set the literal and data swapping requirements |
1286 | * in this command. | |
1da177e4 | 1287 | * |
b2e68aa3 MR |
1288 | * Assumption: 32-bit physical address of descriptor block |
1289 | * is 8Kbyte aligned. | |
1da177e4 | 1290 | */ |
b2e68aa3 MR |
1291 | if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, |
1292 | (u32)(bp->descr_block_phys | | |
1293 | PI_PDATA_A_INIT_M_BSWAP_INIT), | |
1294 | 0, NULL) != DFX_K_SUCCESS) { | |
1295 | printk("%s: Could not set descriptor block address!\n", | |
1296 | bp->dev->name); | |
1297 | return DFX_K_FAILURE; | |
1298 | } | |
1da177e4 LT |
1299 | |
1300 | /* Set transmit flush timeout value */ | |
1301 | ||
1302 | bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; | |
1303 | bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; | |
1304 | bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ | |
1305 | bp->cmd_req_virt->char_set.item[0].item_index = 0; | |
1306 | bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; | |
1307 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1308 | { | |
1309 | printk("%s: DMA command request failed!\n", bp->dev->name); | |
807540ba | 1310 | return DFX_K_FAILURE; |
1da177e4 LT |
1311 | } |
1312 | ||
1313 | /* Set the initial values for eFDXEnable and MACTReq MIB objects */ | |
1314 | ||
1315 | bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; | |
1316 | bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; | |
1317 | bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; | |
1318 | bp->cmd_req_virt->snmp_set.item[0].item_index = 0; | |
1319 | bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; | |
1320 | bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; | |
1321 | bp->cmd_req_virt->snmp_set.item[1].item_index = 0; | |
1322 | bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; | |
1323 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1324 | { | |
1325 | printk("%s: DMA command request failed!\n", bp->dev->name); | |
807540ba | 1326 | return DFX_K_FAILURE; |
1da177e4 LT |
1327 | } |
1328 | ||
1329 | /* Initialize adapter CAM */ | |
1330 | ||
1331 | if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) | |
1332 | { | |
1333 | printk("%s: Adapter CAM update failed!\n", bp->dev->name); | |
807540ba | 1334 | return DFX_K_FAILURE; |
1da177e4 LT |
1335 | } |
1336 | ||
1337 | /* Initialize adapter filters */ | |
1338 | ||
1339 | if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) | |
1340 | { | |
1341 | printk("%s: Adapter filters update failed!\n", bp->dev->name); | |
807540ba | 1342 | return DFX_K_FAILURE; |
1da177e4 LT |
1343 | } |
1344 | ||
1345 | /* | |
1346 | * Remove any existing dynamic buffers (i.e. if the adapter is being | |
1347 | * reinitialized) | |
1348 | */ | |
1349 | ||
1350 | if (get_buffers) | |
1351 | dfx_rcv_flush(bp); | |
1352 | ||
1353 | /* Initialize receive descriptor block and produce buffers */ | |
1354 | ||
1355 | if (dfx_rcv_init(bp, get_buffers)) | |
1356 | { | |
1357 | printk("%s: Receive buffer allocation failed\n", bp->dev->name); | |
1358 | if (get_buffers) | |
1359 | dfx_rcv_flush(bp); | |
807540ba | 1360 | return DFX_K_FAILURE; |
1da177e4 LT |
1361 | } |
1362 | ||
1363 | /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ | |
1364 | ||
1365 | bp->cmd_req_virt->cmd_type = PI_CMD_K_START; | |
1366 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1367 | { | |
1368 | printk("%s: Start command failed\n", bp->dev->name); | |
1369 | if (get_buffers) | |
1370 | dfx_rcv_flush(bp); | |
807540ba | 1371 | return DFX_K_FAILURE; |
1da177e4 LT |
1372 | } |
1373 | ||
1374 | /* Initialization succeeded, reenable PDQ interrupts */ | |
1375 | ||
1376 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); | |
807540ba | 1377 | return DFX_K_SUCCESS; |
1da177e4 LT |
1378 | } |
1379 | ||
6aa20a22 | 1380 | |
1da177e4 LT |
1381 | /* |
1382 | * ============ | |
1383 | * = dfx_open = | |
1384 | * ============ | |
6aa20a22 | 1385 | * |
1da177e4 LT |
1386 | * Overview: |
1387 | * Opens the adapter | |
6aa20a22 | 1388 | * |
1da177e4 LT |
1389 | * Returns: |
1390 | * Condition code | |
6aa20a22 | 1391 | * |
1da177e4 LT |
1392 | * Arguments: |
1393 | * dev - pointer to device information | |
1394 | * | |
1395 | * Functional Description: | |
1396 | * This function brings the adapter to an operational state. | |
1397 | * | |
1398 | * Return Codes: | |
1399 | * 0 - Adapter was successfully opened | |
1400 | * -EAGAIN - Could not register IRQ or adapter initialization failed | |
1401 | * | |
1402 | * Assumptions: | |
1403 | * This routine should only be called for a device that was | |
1404 | * initialized successfully. | |
1405 | * | |
1406 | * Side Effects: | |
1407 | * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state | |
1408 | * if the open is successful. | |
1409 | */ | |
1410 | ||
1411 | static int dfx_open(struct net_device *dev) | |
1412 | { | |
e89a2cfb | 1413 | DFX_board_t *bp = netdev_priv(dev); |
1da177e4 | 1414 | int ret; |
1da177e4 LT |
1415 | |
1416 | DBG_printk("In dfx_open...\n"); | |
6aa20a22 | 1417 | |
1da177e4 LT |
1418 | /* Register IRQ - support shared interrupts by passing device ptr */ |
1419 | ||
e89a2cfb MR |
1420 | ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, |
1421 | dev); | |
1da177e4 LT |
1422 | if (ret) { |
1423 | printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); | |
1424 | return ret; | |
1425 | } | |
1426 | ||
1427 | /* | |
1428 | * Set current address to factory MAC address | |
1429 | * | |
1430 | * Note: We've already done this step in dfx_driver_init. | |
1431 | * However, it's possible that a user has set a node | |
1432 | * address override, then closed and reopened the | |
1433 | * adapter. Unless we reset the device address field | |
1434 | * now, we'll continue to use the existing modified | |
1435 | * address. | |
1436 | */ | |
1437 | ||
1438 | memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); | |
1439 | ||
1440 | /* Clear local unicast/multicast address tables and counts */ | |
1441 | ||
1442 | memset(bp->uc_table, 0, sizeof(bp->uc_table)); | |
1443 | memset(bp->mc_table, 0, sizeof(bp->mc_table)); | |
1444 | bp->uc_count = 0; | |
1445 | bp->mc_count = 0; | |
1446 | ||
1447 | /* Disable promiscuous filter settings */ | |
1448 | ||
1449 | bp->ind_group_prom = PI_FSTATE_K_BLOCK; | |
1450 | bp->group_prom = PI_FSTATE_K_BLOCK; | |
1451 | ||
1452 | spin_lock_init(&bp->lock); | |
1453 | ||
1454 | /* Reset and initialize adapter */ | |
1455 | ||
1456 | bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ | |
1457 | if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) | |
1458 | { | |
1459 | printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); | |
1460 | free_irq(dev->irq, dev); | |
1461 | return -EAGAIN; | |
1462 | } | |
1463 | ||
1464 | /* Set device structure info */ | |
1465 | netif_start_queue(dev); | |
807540ba | 1466 | return 0; |
1da177e4 LT |
1467 | } |
1468 | ||
6aa20a22 | 1469 | |
1da177e4 LT |
1470 | /* |
1471 | * ============= | |
1472 | * = dfx_close = | |
1473 | * ============= | |
6aa20a22 | 1474 | * |
1da177e4 LT |
1475 | * Overview: |
1476 | * Closes the device/module. | |
6aa20a22 | 1477 | * |
1da177e4 LT |
1478 | * Returns: |
1479 | * Condition code | |
6aa20a22 | 1480 | * |
1da177e4 LT |
1481 | * Arguments: |
1482 | * dev - pointer to device information | |
1483 | * | |
1484 | * Functional Description: | |
1485 | * This routine closes the adapter and brings it to a safe state. | |
1486 | * The interrupt service routine is deregistered with the OS. | |
1487 | * The adapter can be opened again with another call to dfx_open(). | |
1488 | * | |
1489 | * Return Codes: | |
1490 | * Always return 0. | |
1491 | * | |
1492 | * Assumptions: | |
1493 | * No further requests for this adapter are made after this routine is | |
1494 | * called. dfx_open() can be called to reset and reinitialize the | |
1495 | * adapter. | |
1496 | * | |
1497 | * Side Effects: | |
1498 | * Adapter should be in DMA_UNAVAILABLE state upon completion of this | |
1499 | * routine. | |
1500 | */ | |
1501 | ||
1502 | static int dfx_close(struct net_device *dev) | |
1503 | { | |
e89a2cfb | 1504 | DFX_board_t *bp = netdev_priv(dev); |
1da177e4 LT |
1505 | |
1506 | DBG_printk("In dfx_close...\n"); | |
1507 | ||
1508 | /* Disable PDQ interrupts first */ | |
1509 | ||
1510 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1511 | ||
1512 | /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ | |
1513 | ||
1514 | (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); | |
1515 | ||
1516 | /* | |
1517 | * Flush any pending transmit buffers | |
1518 | * | |
1519 | * Note: It's important that we flush the transmit buffers | |
1520 | * BEFORE we clear our copy of the Type 2 register. | |
1521 | * Otherwise, we'll have no idea how many buffers | |
1522 | * we need to free. | |
1523 | */ | |
1524 | ||
1525 | dfx_xmt_flush(bp); | |
1526 | ||
1527 | /* | |
1528 | * Clear Type 1 and Type 2 registers after adapter reset | |
1529 | * | |
1530 | * Note: Even though we're closing the adapter, it's | |
1531 | * possible that an interrupt will occur after | |
1532 | * dfx_close is called. Without some assurance to | |
1533 | * the contrary we want to make sure that we don't | |
1534 | * process receive and transmit LLC frames and update | |
1535 | * the Type 2 register with bad information. | |
1536 | */ | |
1537 | ||
1538 | bp->cmd_req_reg.lword = 0; | |
1539 | bp->cmd_rsp_reg.lword = 0; | |
1540 | bp->rcv_xmt_reg.lword = 0; | |
1541 | ||
1542 | /* Clear consumer block for the same reason given above */ | |
1543 | ||
1544 | memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); | |
1545 | ||
1546 | /* Release all dynamically allocate skb in the receive ring. */ | |
1547 | ||
1548 | dfx_rcv_flush(bp); | |
1549 | ||
1550 | /* Clear device structure flags */ | |
1551 | ||
1552 | netif_stop_queue(dev); | |
6aa20a22 | 1553 | |
1da177e4 LT |
1554 | /* Deregister (free) IRQ */ |
1555 | ||
1556 | free_irq(dev->irq, dev); | |
6aa20a22 | 1557 | |
807540ba | 1558 | return 0; |
1da177e4 LT |
1559 | } |
1560 | ||
6aa20a22 | 1561 | |
1da177e4 LT |
1562 | /* |
1563 | * ====================== | |
1564 | * = dfx_int_pr_halt_id = | |
1565 | * ====================== | |
6aa20a22 | 1566 | * |
1da177e4 LT |
1567 | * Overview: |
1568 | * Displays halt id's in string form. | |
6aa20a22 | 1569 | * |
1da177e4 LT |
1570 | * Returns: |
1571 | * None | |
6aa20a22 | 1572 | * |
1da177e4 LT |
1573 | * Arguments: |
1574 | * bp - pointer to board information | |
1575 | * | |
1576 | * Functional Description: | |
1577 | * Determine current halt id and display appropriate string. | |
1578 | * | |
1579 | * Return Codes: | |
1580 | * None | |
1581 | * | |
1582 | * Assumptions: | |
1583 | * None | |
1584 | * | |
1585 | * Side Effects: | |
1586 | * None | |
1587 | */ | |
1588 | ||
1589 | static void dfx_int_pr_halt_id(DFX_board_t *bp) | |
1590 | { | |
1591 | PI_UINT32 port_status; /* PDQ port status register value */ | |
1592 | PI_UINT32 halt_id; /* PDQ port status halt ID */ | |
1593 | ||
1594 | /* Read the latest port status */ | |
1595 | ||
1596 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); | |
1597 | ||
1598 | /* Display halt state transition information */ | |
1599 | ||
1600 | halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; | |
1601 | switch (halt_id) | |
1602 | { | |
1603 | case PI_HALT_ID_K_SELFTEST_TIMEOUT: | |
1604 | printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); | |
1605 | break; | |
1606 | ||
1607 | case PI_HALT_ID_K_PARITY_ERROR: | |
1608 | printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); | |
1609 | break; | |
1610 | ||
1611 | case PI_HALT_ID_K_HOST_DIR_HALT: | |
1612 | printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); | |
1613 | break; | |
1614 | ||
1615 | case PI_HALT_ID_K_SW_FAULT: | |
1616 | printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); | |
1617 | break; | |
1618 | ||
1619 | case PI_HALT_ID_K_HW_FAULT: | |
1620 | printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); | |
1621 | break; | |
1622 | ||
1623 | case PI_HALT_ID_K_PC_TRACE: | |
1624 | printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); | |
1625 | break; | |
1626 | ||
1627 | case PI_HALT_ID_K_DMA_ERROR: | |
1628 | printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); | |
1629 | break; | |
1630 | ||
1631 | case PI_HALT_ID_K_IMAGE_CRC_ERROR: | |
1632 | printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); | |
1633 | break; | |
1634 | ||
1635 | case PI_HALT_ID_K_BUS_EXCEPTION: | |
1636 | printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); | |
1637 | break; | |
1638 | ||
1639 | default: | |
1640 | printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); | |
1641 | break; | |
1642 | } | |
1643 | } | |
1644 | ||
6aa20a22 | 1645 | |
1da177e4 LT |
1646 | /* |
1647 | * ========================== | |
1648 | * = dfx_int_type_0_process = | |
1649 | * ========================== | |
6aa20a22 | 1650 | * |
1da177e4 LT |
1651 | * Overview: |
1652 | * Processes Type 0 interrupts. | |
6aa20a22 | 1653 | * |
1da177e4 LT |
1654 | * Returns: |
1655 | * None | |
6aa20a22 | 1656 | * |
1da177e4 LT |
1657 | * Arguments: |
1658 | * bp - pointer to board information | |
1659 | * | |
1660 | * Functional Description: | |
1661 | * Processes all enabled Type 0 interrupts. If the reason for the interrupt | |
1662 | * is a serious fault on the adapter, then an error message is displayed | |
1663 | * and the adapter is reset. | |
1664 | * | |
1665 | * One tricky potential timing window is the rapid succession of "link avail" | |
1666 | * "link unavail" state change interrupts. The acknowledgement of the Type 0 | |
1667 | * interrupt must be done before reading the state from the Port Status | |
1668 | * register. This is true because a state change could occur after reading | |
1669 | * the data, but before acknowledging the interrupt. If this state change | |
1670 | * does happen, it would be lost because the driver is using the old state, | |
1671 | * and it will never know about the new state because it subsequently | |
1672 | * acknowledges the state change interrupt. | |
1673 | * | |
1674 | * INCORRECT CORRECT | |
1675 | * read type 0 int reasons read type 0 int reasons | |
1676 | * read adapter state ack type 0 interrupts | |
1677 | * ack type 0 interrupts read adapter state | |
1678 | * ... process interrupt ... ... process interrupt ... | |
1679 | * | |
1680 | * Return Codes: | |
1681 | * None | |
1682 | * | |
1683 | * Assumptions: | |
1684 | * None | |
1685 | * | |
1686 | * Side Effects: | |
1687 | * An adapter reset may occur if the adapter has any Type 0 error interrupts | |
1688 | * or if the port status indicates that the adapter is halted. The driver | |
1689 | * is responsible for reinitializing the adapter with the current CAM | |
1690 | * contents and adapter filter settings. | |
1691 | */ | |
1692 | ||
1693 | static void dfx_int_type_0_process(DFX_board_t *bp) | |
1694 | ||
1695 | { | |
1696 | PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ | |
1697 | PI_UINT32 state; /* current adap state (from port status) */ | |
1698 | ||
1699 | /* | |
1700 | * Read host interrupt Type 0 register to determine which Type 0 | |
1701 | * interrupts are pending. Immediately write it back out to clear | |
1702 | * those interrupts. | |
1703 | */ | |
1704 | ||
1705 | dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); | |
1706 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); | |
1707 | ||
1708 | /* Check for Type 0 error interrupts */ | |
1709 | ||
1710 | if (type_0_status & (PI_TYPE_0_STAT_M_NXM | | |
1711 | PI_TYPE_0_STAT_M_PM_PAR_ERR | | |
1712 | PI_TYPE_0_STAT_M_BUS_PAR_ERR)) | |
1713 | { | |
1714 | /* Check for Non-Existent Memory error */ | |
1715 | ||
1716 | if (type_0_status & PI_TYPE_0_STAT_M_NXM) | |
1717 | printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); | |
1718 | ||
1719 | /* Check for Packet Memory Parity error */ | |
1720 | ||
1721 | if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) | |
1722 | printk("%s: Packet Memory Parity Error\n", bp->dev->name); | |
1723 | ||
1724 | /* Check for Host Bus Parity error */ | |
1725 | ||
1726 | if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) | |
1727 | printk("%s: Host Bus Parity Error\n", bp->dev->name); | |
1728 | ||
1729 | /* Reset adapter and bring it back on-line */ | |
1730 | ||
1731 | bp->link_available = PI_K_FALSE; /* link is no longer available */ | |
1732 | bp->reset_type = 0; /* rerun on-board diagnostics */ | |
1733 | printk("%s: Resetting adapter...\n", bp->dev->name); | |
1734 | if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) | |
1735 | { | |
1736 | printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); | |
1737 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1738 | return; | |
1739 | } | |
1740 | printk("%s: Adapter reset successful!\n", bp->dev->name); | |
1741 | return; | |
1742 | } | |
1743 | ||
1744 | /* Check for transmit flush interrupt */ | |
1745 | ||
1746 | if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) | |
1747 | { | |
1748 | /* Flush any pending xmt's and acknowledge the flush interrupt */ | |
1749 | ||
1750 | bp->link_available = PI_K_FALSE; /* link is no longer available */ | |
1751 | dfx_xmt_flush(bp); /* flush any outstanding packets */ | |
1752 | (void) dfx_hw_port_ctrl_req(bp, | |
1753 | PI_PCTRL_M_XMT_DATA_FLUSH_DONE, | |
1754 | 0, | |
1755 | 0, | |
1756 | NULL); | |
1757 | } | |
1758 | ||
1759 | /* Check for adapter state change */ | |
1760 | ||
1761 | if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) | |
6aa20a22 | 1762 | { |
1da177e4 LT |
1763 | /* Get latest adapter state */ |
1764 | ||
1765 | state = dfx_hw_adap_state_rd(bp); /* get adapter state */ | |
1766 | if (state == PI_STATE_K_HALTED) | |
1767 | { | |
1768 | /* | |
1769 | * Adapter has transitioned to HALTED state, try to reset | |
1770 | * adapter to bring it back on-line. If reset fails, | |
1771 | * leave the adapter in the broken state. | |
1772 | */ | |
1773 | ||
1774 | printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); | |
1775 | dfx_int_pr_halt_id(bp); /* display halt id as string */ | |
1776 | ||
1777 | /* Reset adapter and bring it back on-line */ | |
1778 | ||
1779 | bp->link_available = PI_K_FALSE; /* link is no longer available */ | |
1780 | bp->reset_type = 0; /* rerun on-board diagnostics */ | |
1781 | printk("%s: Resetting adapter...\n", bp->dev->name); | |
1782 | if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) | |
1783 | { | |
1784 | printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); | |
1785 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1786 | return; | |
1787 | } | |
1788 | printk("%s: Adapter reset successful!\n", bp->dev->name); | |
1789 | } | |
1790 | else if (state == PI_STATE_K_LINK_AVAIL) | |
1791 | { | |
1792 | bp->link_available = PI_K_TRUE; /* set link available flag */ | |
1793 | } | |
1794 | } | |
1795 | } | |
1796 | ||
6aa20a22 | 1797 | |
1da177e4 LT |
1798 | /* |
1799 | * ================== | |
1800 | * = dfx_int_common = | |
1801 | * ================== | |
6aa20a22 | 1802 | * |
1da177e4 LT |
1803 | * Overview: |
1804 | * Interrupt service routine (ISR) | |
6aa20a22 | 1805 | * |
1da177e4 LT |
1806 | * Returns: |
1807 | * None | |
6aa20a22 | 1808 | * |
1da177e4 LT |
1809 | * Arguments: |
1810 | * bp - pointer to board information | |
1811 | * | |
1812 | * Functional Description: | |
1813 | * This is the ISR which processes incoming adapter interrupts. | |
1814 | * | |
1815 | * Return Codes: | |
1816 | * None | |
1817 | * | |
1818 | * Assumptions: | |
1819 | * This routine assumes PDQ interrupts have not been disabled. | |
1820 | * When interrupts are disabled at the PDQ, the Port Status register | |
1821 | * is automatically cleared. This routine uses the Port Status | |
1822 | * register value to determine whether a Type 0 interrupt occurred, | |
1823 | * so it's important that adapter interrupts are not normally | |
1824 | * enabled/disabled at the PDQ. | |
1825 | * | |
1826 | * It's vital that this routine is NOT reentered for the | |
1827 | * same board and that the OS is not in another section of | |
1828 | * code (eg. dfx_xmt_queue_pkt) for the same board on a | |
1829 | * different thread. | |
1830 | * | |
1831 | * Side Effects: | |
1832 | * Pending interrupts are serviced. Depending on the type of | |
1833 | * interrupt, acknowledging and clearing the interrupt at the | |
1834 | * PDQ involves writing a register to clear the interrupt bit | |
1835 | * or updating completion indices. | |
1836 | */ | |
1837 | ||
1838 | static void dfx_int_common(struct net_device *dev) | |
1839 | { | |
e89a2cfb | 1840 | DFX_board_t *bp = netdev_priv(dev); |
1da177e4 LT |
1841 | PI_UINT32 port_status; /* Port Status register */ |
1842 | ||
1843 | /* Process xmt interrupts - frequent case, so always call this routine */ | |
1844 | ||
1845 | if(dfx_xmt_done(bp)) /* free consumed xmt packets */ | |
1846 | netif_wake_queue(dev); | |
1847 | ||
1848 | /* Process rcv interrupts - frequent case, so always call this routine */ | |
1849 | ||
1850 | dfx_rcv_queue_process(bp); /* service received LLC frames */ | |
1851 | ||
1852 | /* | |
1853 | * Transmit and receive producer and completion indices are updated on the | |
1854 | * adapter by writing to the Type 2 Producer register. Since the frequent | |
1855 | * case is that we'll be processing either LLC transmit or receive buffers, | |
1856 | * we'll optimize I/O writes by doing a single register write here. | |
1857 | */ | |
1858 | ||
1859 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); | |
1860 | ||
1861 | /* Read PDQ Port Status register to find out which interrupts need processing */ | |
1862 | ||
1863 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); | |
1864 | ||
1865 | /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ | |
1866 | ||
1867 | if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) | |
1868 | dfx_int_type_0_process(bp); /* process Type 0 interrupts */ | |
1869 | } | |
1870 | ||
6aa20a22 | 1871 | |
1da177e4 LT |
1872 | /* |
1873 | * ================= | |
1874 | * = dfx_interrupt = | |
1875 | * ================= | |
feea1db2 | 1876 | * |
1da177e4 LT |
1877 | * Overview: |
1878 | * Interrupt processing routine | |
feea1db2 | 1879 | * |
1da177e4 | 1880 | * Returns: |
feea1db2 MR |
1881 | * Whether a valid interrupt was seen. |
1882 | * | |
1da177e4 LT |
1883 | * Arguments: |
1884 | * irq - interrupt vector | |
1885 | * dev_id - pointer to device information | |
1da177e4 LT |
1886 | * |
1887 | * Functional Description: | |
1888 | * This routine calls the interrupt processing routine for this adapter. It | |
1889 | * disables and reenables adapter interrupts, as appropriate. We can support | |
1890 | * shared interrupts since the incoming dev_id pointer provides our device | |
1891 | * structure context. | |
1892 | * | |
1893 | * Return Codes: | |
feea1db2 MR |
1894 | * IRQ_HANDLED - an IRQ was handled. |
1895 | * IRQ_NONE - no IRQ was handled. | |
1da177e4 LT |
1896 | * |
1897 | * Assumptions: | |
1898 | * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC | |
1899 | * on Intel-based systems) is done by the operating system outside this | |
1900 | * routine. | |
1901 | * | |
1902 | * System interrupts are enabled through this call. | |
1903 | * | |
1904 | * Side Effects: | |
1905 | * Interrupts are disabled, then reenabled at the adapter. | |
1906 | */ | |
1907 | ||
7d12e780 | 1908 | static irqreturn_t dfx_interrupt(int irq, void *dev_id) |
feea1db2 | 1909 | { |
e89a2cfb MR |
1910 | struct net_device *dev = dev_id; |
1911 | DFX_board_t *bp = netdev_priv(dev); | |
1912 | struct device *bdev = bp->bus_dev; | |
5349d937 | 1913 | int dfx_bus_pci = dev_is_pci(bdev); |
e89a2cfb MR |
1914 | int dfx_bus_eisa = DFX_BUS_EISA(bdev); |
1915 | int dfx_bus_tc = DFX_BUS_TC(bdev); | |
1da177e4 LT |
1916 | |
1917 | /* Service adapter interrupts */ | |
1918 | ||
e89a2cfb | 1919 | if (dfx_bus_pci) { |
feea1db2 | 1920 | u32 status; |
1da177e4 | 1921 | |
feea1db2 MR |
1922 | dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); |
1923 | if (!(status & PFI_STATUS_M_PDQ_INT)) | |
1924 | return IRQ_NONE; | |
1da177e4 | 1925 | |
feea1db2 MR |
1926 | spin_lock(&bp->lock); |
1927 | ||
1928 | /* Disable PDQ-PFI interrupts at PFI */ | |
1929 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, | |
1930 | PFI_MODE_M_DMA_ENB); | |
1da177e4 | 1931 | |
feea1db2 | 1932 | /* Call interrupt service routine for this adapter */ |
1da177e4 LT |
1933 | dfx_int_common(dev); |
1934 | ||
1935 | /* Clear PDQ interrupt status bit and reenable interrupts */ | |
feea1db2 MR |
1936 | dfx_port_write_long(bp, PFI_K_REG_STATUS, |
1937 | PFI_STATUS_M_PDQ_INT); | |
1da177e4 | 1938 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, |
feea1db2 MR |
1939 | (PFI_MODE_M_PDQ_INT_ENB | |
1940 | PFI_MODE_M_DMA_ENB)); | |
1da177e4 | 1941 | |
feea1db2 | 1942 | spin_unlock(&bp->lock); |
e89a2cfb MR |
1943 | } |
1944 | if (dfx_bus_eisa) { | |
1945 | unsigned long base_addr = to_eisa_device(bdev)->base_addr; | |
feea1db2 | 1946 | u8 status; |
1da177e4 | 1947 | |
e89a2cfb | 1948 | status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
feea1db2 MR |
1949 | if (!(status & PI_CONFIG_STAT_0_M_PEND)) |
1950 | return IRQ_NONE; | |
1da177e4 | 1951 | |
feea1db2 MR |
1952 | spin_lock(&bp->lock); |
1953 | ||
1954 | /* Disable interrupts at the ESIC */ | |
1955 | status &= ~PI_CONFIG_STAT_0_M_INT_ENB; | |
8a189f12 | 1956 | outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
feea1db2 MR |
1957 | |
1958 | /* Call interrupt service routine for this adapter */ | |
1da177e4 LT |
1959 | dfx_int_common(dev); |
1960 | ||
1961 | /* Reenable interrupts at the ESIC */ | |
e89a2cfb | 1962 | status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
feea1db2 | 1963 | status |= PI_CONFIG_STAT_0_M_INT_ENB; |
8a189f12 | 1964 | outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); |
e89a2cfb MR |
1965 | |
1966 | spin_unlock(&bp->lock); | |
1967 | } | |
1968 | if (dfx_bus_tc) { | |
1969 | u32 status; | |
1970 | ||
1971 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status); | |
1972 | if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING | | |
1973 | PI_PSTATUS_M_XMT_DATA_PENDING | | |
1974 | PI_PSTATUS_M_SMT_HOST_PENDING | | |
1975 | PI_PSTATUS_M_UNSOL_PENDING | | |
1976 | PI_PSTATUS_M_CMD_RSP_PENDING | | |
1977 | PI_PSTATUS_M_CMD_REQ_PENDING | | |
1978 | PI_PSTATUS_M_TYPE_0_PENDING))) | |
1979 | return IRQ_NONE; | |
1980 | ||
1981 | spin_lock(&bp->lock); | |
1982 | ||
1983 | /* Call interrupt service routine for this adapter */ | |
1984 | dfx_int_common(dev); | |
1da177e4 | 1985 | |
feea1db2 | 1986 | spin_unlock(&bp->lock); |
1da177e4 LT |
1987 | } |
1988 | ||
feea1db2 MR |
1989 | return IRQ_HANDLED; |
1990 | } | |
1991 | ||
6aa20a22 | 1992 | |
1da177e4 LT |
1993 | /* |
1994 | * ===================== | |
1995 | * = dfx_ctl_get_stats = | |
1996 | * ===================== | |
6aa20a22 | 1997 | * |
1da177e4 LT |
1998 | * Overview: |
1999 | * Get statistics for FDDI adapter | |
6aa20a22 | 2000 | * |
1da177e4 LT |
2001 | * Returns: |
2002 | * Pointer to FDDI statistics structure | |
6aa20a22 | 2003 | * |
1da177e4 LT |
2004 | * Arguments: |
2005 | * dev - pointer to device information | |
2006 | * | |
2007 | * Functional Description: | |
2008 | * Gets current MIB objects from adapter, then | |
2009 | * returns FDDI statistics structure as defined | |
2010 | * in if_fddi.h. | |
2011 | * | |
2012 | * Note: Since the FDDI statistics structure is | |
2013 | * still new and the device structure doesn't | |
2014 | * have an FDDI-specific get statistics handler, | |
2015 | * we'll return the FDDI statistics structure as | |
2016 | * a pointer to an Ethernet statistics structure. | |
2017 | * That way, at least the first part of the statistics | |
2018 | * structure can be decoded properly, and it allows | |
2019 | * "smart" applications to perform a second cast to | |
2020 | * decode the FDDI-specific statistics. | |
2021 | * | |
2022 | * We'll have to pay attention to this routine as the | |
2023 | * device structure becomes more mature and LAN media | |
2024 | * independent. | |
2025 | * | |
2026 | * Return Codes: | |
2027 | * None | |
2028 | * | |
2029 | * Assumptions: | |
2030 | * None | |
2031 | * | |
2032 | * Side Effects: | |
2033 | * None | |
2034 | */ | |
2035 | ||
2036 | static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) | |
2037 | { | |
e89a2cfb | 2038 | DFX_board_t *bp = netdev_priv(dev); |
1da177e4 LT |
2039 | |
2040 | /* Fill the bp->stats structure with driver-maintained counters */ | |
2041 | ||
2042 | bp->stats.gen.rx_packets = bp->rcv_total_frames; | |
2043 | bp->stats.gen.tx_packets = bp->xmt_total_frames; | |
2044 | bp->stats.gen.rx_bytes = bp->rcv_total_bytes; | |
2045 | bp->stats.gen.tx_bytes = bp->xmt_total_bytes; | |
2046 | bp->stats.gen.rx_errors = bp->rcv_crc_errors + | |
2047 | bp->rcv_frame_status_errors + | |
2048 | bp->rcv_length_errors; | |
2049 | bp->stats.gen.tx_errors = bp->xmt_length_errors; | |
2050 | bp->stats.gen.rx_dropped = bp->rcv_discards; | |
2051 | bp->stats.gen.tx_dropped = bp->xmt_discards; | |
2052 | bp->stats.gen.multicast = bp->rcv_multicast_frames; | |
2053 | bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ | |
2054 | ||
2055 | /* Get FDDI SMT MIB objects */ | |
2056 | ||
2057 | bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; | |
2058 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
807540ba | 2059 | return (struct net_device_stats *)&bp->stats; |
1da177e4 LT |
2060 | |
2061 | /* Fill the bp->stats structure with the SMT MIB object values */ | |
2062 | ||
2063 | memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); | |
2064 | bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; | |
2065 | bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; | |
2066 | bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; | |
2067 | memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); | |
2068 | bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; | |
2069 | bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; | |
2070 | bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; | |
2071 | bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; | |
2072 | bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; | |
2073 | bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; | |
2074 | bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; | |
2075 | bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; | |
2076 | bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; | |
2077 | bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; | |
2078 | bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; | |
2079 | bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; | |
2080 | bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; | |
2081 | bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; | |
2082 | bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; | |
2083 | bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; | |
2084 | bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; | |
2085 | bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; | |
2086 | bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; | |
2087 | bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; | |
2088 | bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; | |
2089 | bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; | |
2090 | bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; | |
2091 | bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; | |
2092 | memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); | |
2093 | memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); | |
2094 | memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); | |
2095 | memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); | |
2096 | bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; | |
2097 | bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; | |
2098 | bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; | |
2099 | memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); | |
2100 | bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; | |
2101 | bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; | |
2102 | bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; | |
2103 | bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; | |
2104 | bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; | |
2105 | bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; | |
2106 | bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; | |
2107 | bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; | |
2108 | bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; | |
2109 | bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; | |
2110 | bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; | |
2111 | bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; | |
2112 | bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; | |
2113 | bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; | |
2114 | bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; | |
2115 | bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; | |
2116 | memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); | |
2117 | bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; | |
2118 | bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; | |
2119 | bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; | |
2120 | bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; | |
2121 | bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; | |
2122 | bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; | |
2123 | bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; | |
2124 | bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; | |
2125 | bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; | |
2126 | bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; | |
2127 | memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); | |
2128 | memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); | |
2129 | bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; | |
2130 | bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; | |
2131 | bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; | |
2132 | bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; | |
2133 | bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; | |
2134 | bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; | |
2135 | bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; | |
2136 | bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; | |
2137 | bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; | |
2138 | bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; | |
2139 | bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; | |
2140 | bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; | |
2141 | bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; | |
2142 | bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; | |
2143 | bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; | |
2144 | bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; | |
2145 | bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; | |
2146 | bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; | |
2147 | bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; | |
2148 | bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; | |
2149 | bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; | |
2150 | bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; | |
2151 | bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; | |
2152 | bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; | |
2153 | bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; | |
2154 | bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; | |
2155 | ||
2156 | /* Get FDDI counters */ | |
2157 | ||
2158 | bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; | |
2159 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
807540ba | 2160 | return (struct net_device_stats *)&bp->stats; |
1da177e4 LT |
2161 | |
2162 | /* Fill the bp->stats structure with the FDDI counter values */ | |
2163 | ||
2164 | bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; | |
2165 | bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; | |
2166 | bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; | |
2167 | bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; | |
2168 | bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; | |
2169 | bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; | |
2170 | bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; | |
2171 | bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; | |
2172 | bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; | |
2173 | bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; | |
2174 | bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; | |
2175 | ||
807540ba | 2176 | return (struct net_device_stats *)&bp->stats; |
1da177e4 LT |
2177 | } |
2178 | ||
6aa20a22 | 2179 | |
1da177e4 LT |
2180 | /* |
2181 | * ============================== | |
2182 | * = dfx_ctl_set_multicast_list = | |
2183 | * ============================== | |
6aa20a22 | 2184 | * |
1da177e4 LT |
2185 | * Overview: |
2186 | * Enable/Disable LLC frame promiscuous mode reception | |
2187 | * on the adapter and/or update multicast address table. | |
6aa20a22 | 2188 | * |
1da177e4 LT |
2189 | * Returns: |
2190 | * None | |
6aa20a22 | 2191 | * |
1da177e4 LT |
2192 | * Arguments: |
2193 | * dev - pointer to device information | |
2194 | * | |
2195 | * Functional Description: | |
2196 | * This routine follows a fairly simple algorithm for setting the | |
2197 | * adapter filters and CAM: | |
2198 | * | |
2199 | * if IFF_PROMISC flag is set | |
2200 | * enable LLC individual/group promiscuous mode | |
2201 | * else | |
2202 | * disable LLC individual/group promiscuous mode | |
2203 | * if number of incoming multicast addresses > | |
2204 | * (CAM max size - number of unicast addresses in CAM) | |
2205 | * enable LLC group promiscuous mode | |
2206 | * set driver-maintained multicast address count to zero | |
2207 | * else | |
2208 | * disable LLC group promiscuous mode | |
2209 | * set driver-maintained multicast address count to incoming count | |
2210 | * update adapter CAM | |
2211 | * update adapter filters | |
2212 | * | |
2213 | * Return Codes: | |
2214 | * None | |
2215 | * | |
2216 | * Assumptions: | |
2217 | * Multicast addresses are presented in canonical (LSB) format. | |
2218 | * | |
2219 | * Side Effects: | |
2220 | * On-board adapter CAM and filters are updated. | |
2221 | */ | |
2222 | ||
2223 | static void dfx_ctl_set_multicast_list(struct net_device *dev) | |
e89a2cfb MR |
2224 | { |
2225 | DFX_board_t *bp = netdev_priv(dev); | |
1da177e4 | 2226 | int i; /* used as index in for loop */ |
22bedad3 | 2227 | struct netdev_hw_addr *ha; |
1da177e4 LT |
2228 | |
2229 | /* Enable LLC frame promiscuous mode, if necessary */ | |
2230 | ||
2231 | if (dev->flags & IFF_PROMISC) | |
2232 | bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ | |
2233 | ||
2234 | /* Else, update multicast address table */ | |
2235 | ||
2236 | else | |
2237 | { | |
2238 | bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ | |
2239 | /* | |
2240 | * Check whether incoming multicast address count exceeds table size | |
2241 | * | |
2242 | * Note: The adapters utilize an on-board 64 entry CAM for | |
2243 | * supporting perfect filtering of multicast packets | |
2244 | * and bridge functions when adding unicast addresses. | |
2245 | * There is no hash function available. To support | |
2246 | * additional multicast addresses, the all multicast | |
2247 | * filter (LLC group promiscuous mode) must be enabled. | |
2248 | * | |
2249 | * The firmware reserves two CAM entries for SMT-related | |
2250 | * multicast addresses, which leaves 62 entries available. | |
2251 | * The following code ensures that we're not being asked | |
2252 | * to add more than 62 addresses to the CAM. If we are, | |
2253 | * the driver will enable the all multicast filter. | |
2254 | * Should the number of multicast addresses drop below | |
2255 | * the high water mark, the filter will be disabled and | |
2256 | * perfect filtering will be used. | |
2257 | */ | |
2258 | ||
4cd24eaf | 2259 | if (netdev_mc_count(dev) > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) |
1da177e4 LT |
2260 | { |
2261 | bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ | |
2262 | bp->mc_count = 0; /* Don't add mc addrs to CAM */ | |
2263 | } | |
2264 | else | |
2265 | { | |
2266 | bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ | |
4cd24eaf | 2267 | bp->mc_count = netdev_mc_count(dev); /* Add mc addrs to CAM */ |
1da177e4 LT |
2268 | } |
2269 | ||
2270 | /* Copy addresses to multicast address table, then update adapter CAM */ | |
2271 | ||
e1d44477 | 2272 | i = 0; |
22bedad3 | 2273 | netdev_for_each_mc_addr(ha, dev) |
e1d44477 | 2274 | memcpy(&bp->mc_table[i++ * FDDI_K_ALEN], |
22bedad3 | 2275 | ha->addr, FDDI_K_ALEN); |
e1d44477 | 2276 | |
1da177e4 LT |
2277 | if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) |
2278 | { | |
2279 | DBG_printk("%s: Could not update multicast address table!\n", dev->name); | |
2280 | } | |
2281 | else | |
2282 | { | |
2283 | DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | /* Update adapter filters */ | |
2288 | ||
2289 | if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) | |
2290 | { | |
2291 | DBG_printk("%s: Could not update adapter filters!\n", dev->name); | |
2292 | } | |
2293 | else | |
2294 | { | |
2295 | DBG_printk("%s: Adapter filters updated!\n", dev->name); | |
2296 | } | |
2297 | } | |
2298 | ||
6aa20a22 | 2299 | |
1da177e4 LT |
2300 | /* |
2301 | * =========================== | |
2302 | * = dfx_ctl_set_mac_address = | |
2303 | * =========================== | |
6aa20a22 | 2304 | * |
1da177e4 LT |
2305 | * Overview: |
2306 | * Add node address override (unicast address) to adapter | |
2307 | * CAM and update dev_addr field in device table. | |
6aa20a22 | 2308 | * |
1da177e4 LT |
2309 | * Returns: |
2310 | * None | |
6aa20a22 | 2311 | * |
1da177e4 LT |
2312 | * Arguments: |
2313 | * dev - pointer to device information | |
2314 | * addr - pointer to sockaddr structure containing unicast address to add | |
2315 | * | |
2316 | * Functional Description: | |
2317 | * The adapter supports node address overrides by adding one or more | |
2318 | * unicast addresses to the adapter CAM. This is similar to adding | |
2319 | * multicast addresses. In this routine we'll update the driver and | |
2320 | * device structures with the new address, then update the adapter CAM | |
2321 | * to ensure that the adapter will copy and strip frames destined and | |
2322 | * sourced by that address. | |
2323 | * | |
2324 | * Return Codes: | |
2325 | * Always returns zero. | |
2326 | * | |
2327 | * Assumptions: | |
2328 | * The address pointed to by addr->sa_data is a valid unicast | |
2329 | * address and is presented in canonical (LSB) format. | |
2330 | * | |
2331 | * Side Effects: | |
2332 | * On-board adapter CAM is updated. On-board adapter filters | |
2333 | * may be updated. | |
2334 | */ | |
2335 | ||
2336 | static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) | |
2337 | { | |
1da177e4 | 2338 | struct sockaddr *p_sockaddr = (struct sockaddr *)addr; |
e89a2cfb | 2339 | DFX_board_t *bp = netdev_priv(dev); |
1da177e4 LT |
2340 | |
2341 | /* Copy unicast address to driver-maintained structs and update count */ | |
2342 | ||
2343 | memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ | |
2344 | memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ | |
2345 | bp->uc_count = 1; | |
2346 | ||
2347 | /* | |
2348 | * Verify we're not exceeding the CAM size by adding unicast address | |
2349 | * | |
2350 | * Note: It's possible that before entering this routine we've | |
2351 | * already filled the CAM with 62 multicast addresses. | |
2352 | * Since we need to place the node address override into | |
2353 | * the CAM, we have to check to see that we're not | |
2354 | * exceeding the CAM size. If we are, we have to enable | |
2355 | * the LLC group (multicast) promiscuous mode filter as | |
2356 | * in dfx_ctl_set_multicast_list. | |
2357 | */ | |
2358 | ||
2359 | if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) | |
2360 | { | |
2361 | bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ | |
2362 | bp->mc_count = 0; /* Don't add mc addrs to CAM */ | |
2363 | ||
2364 | /* Update adapter filters */ | |
2365 | ||
2366 | if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) | |
2367 | { | |
2368 | DBG_printk("%s: Could not update adapter filters!\n", dev->name); | |
2369 | } | |
2370 | else | |
2371 | { | |
2372 | DBG_printk("%s: Adapter filters updated!\n", dev->name); | |
2373 | } | |
2374 | } | |
2375 | ||
2376 | /* Update adapter CAM with new unicast address */ | |
2377 | ||
2378 | if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) | |
2379 | { | |
2380 | DBG_printk("%s: Could not set new MAC address!\n", dev->name); | |
2381 | } | |
2382 | else | |
2383 | { | |
2384 | DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); | |
2385 | } | |
807540ba | 2386 | return 0; /* always return zero */ |
1da177e4 LT |
2387 | } |
2388 | ||
6aa20a22 | 2389 | |
1da177e4 LT |
2390 | /* |
2391 | * ====================== | |
2392 | * = dfx_ctl_update_cam = | |
2393 | * ====================== | |
2394 | * | |
2395 | * Overview: | |
2396 | * Procedure to update adapter CAM (Content Addressable Memory) | |
2397 | * with desired unicast and multicast address entries. | |
2398 | * | |
2399 | * Returns: | |
2400 | * Condition code | |
2401 | * | |
2402 | * Arguments: | |
2403 | * bp - pointer to board information | |
2404 | * | |
2405 | * Functional Description: | |
2406 | * Updates adapter CAM with current contents of board structure | |
2407 | * unicast and multicast address tables. Since there are only 62 | |
2408 | * free entries in CAM, this routine ensures that the command | |
2409 | * request buffer is not overrun. | |
2410 | * | |
2411 | * Return Codes: | |
2412 | * DFX_K_SUCCESS - Request succeeded | |
2413 | * DFX_K_FAILURE - Request failed | |
2414 | * | |
2415 | * Assumptions: | |
2416 | * All addresses being added (unicast and multicast) are in canonical | |
2417 | * order. | |
2418 | * | |
2419 | * Side Effects: | |
2420 | * On-board adapter CAM is updated. | |
2421 | */ | |
2422 | ||
2423 | static int dfx_ctl_update_cam(DFX_board_t *bp) | |
2424 | { | |
2425 | int i; /* used as index */ | |
2426 | PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ | |
2427 | ||
2428 | /* | |
2429 | * Fill in command request information | |
2430 | * | |
2431 | * Note: Even though both the unicast and multicast address | |
2432 | * table entries are stored as contiguous 6 byte entries, | |
2433 | * the firmware address filter set command expects each | |
2434 | * entry to be two longwords (8 bytes total). We must be | |
2435 | * careful to only copy the six bytes of each unicast and | |
2436 | * multicast table entry into each command entry. This | |
2437 | * is also why we must first clear the entire command | |
2438 | * request buffer. | |
2439 | */ | |
2440 | ||
2441 | memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ | |
2442 | bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; | |
2443 | p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; | |
2444 | ||
2445 | /* Now add unicast addresses to command request buffer, if any */ | |
2446 | ||
2447 | for (i=0; i < (int)bp->uc_count; i++) | |
2448 | { | |
2449 | if (i < PI_CMD_ADDR_FILTER_K_SIZE) | |
2450 | { | |
2451 | memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); | |
2452 | p_addr++; /* point to next command entry */ | |
2453 | } | |
2454 | } | |
2455 | ||
2456 | /* Now add multicast addresses to command request buffer, if any */ | |
2457 | ||
2458 | for (i=0; i < (int)bp->mc_count; i++) | |
2459 | { | |
2460 | if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) | |
2461 | { | |
2462 | memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); | |
2463 | p_addr++; /* point to next command entry */ | |
2464 | } | |
2465 | } | |
2466 | ||
2467 | /* Issue command to update adapter CAM, then return */ | |
2468 | ||
2469 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
807540ba ED |
2470 | return DFX_K_FAILURE; |
2471 | return DFX_K_SUCCESS; | |
1da177e4 LT |
2472 | } |
2473 | ||
6aa20a22 | 2474 | |
1da177e4 LT |
2475 | /* |
2476 | * ========================== | |
2477 | * = dfx_ctl_update_filters = | |
2478 | * ========================== | |
2479 | * | |
2480 | * Overview: | |
2481 | * Procedure to update adapter filters with desired | |
2482 | * filter settings. | |
6aa20a22 | 2483 | * |
1da177e4 LT |
2484 | * Returns: |
2485 | * Condition code | |
6aa20a22 | 2486 | * |
1da177e4 LT |
2487 | * Arguments: |
2488 | * bp - pointer to board information | |
2489 | * | |
2490 | * Functional Description: | |
2491 | * Enables or disables filter using current filter settings. | |
2492 | * | |
2493 | * Return Codes: | |
2494 | * DFX_K_SUCCESS - Request succeeded. | |
2495 | * DFX_K_FAILURE - Request failed. | |
2496 | * | |
2497 | * Assumptions: | |
2498 | * We must always pass up packets destined to the broadcast | |
2499 | * address (FF-FF-FF-FF-FF-FF), so we'll always keep the | |
2500 | * broadcast filter enabled. | |
2501 | * | |
2502 | * Side Effects: | |
2503 | * On-board adapter filters are updated. | |
2504 | */ | |
2505 | ||
2506 | static int dfx_ctl_update_filters(DFX_board_t *bp) | |
2507 | { | |
2508 | int i = 0; /* used as index */ | |
2509 | ||
2510 | /* Fill in command request information */ | |
2511 | ||
2512 | bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; | |
2513 | ||
2514 | /* Initialize Broadcast filter - * ALWAYS ENABLED * */ | |
2515 | ||
2516 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; | |
2517 | bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; | |
2518 | ||
2519 | /* Initialize LLC Individual/Group Promiscuous filter */ | |
2520 | ||
2521 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; | |
2522 | bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; | |
2523 | ||
2524 | /* Initialize LLC Group Promiscuous filter */ | |
2525 | ||
2526 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; | |
2527 | bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; | |
2528 | ||
2529 | /* Terminate the item code list */ | |
2530 | ||
2531 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; | |
2532 | ||
2533 | /* Issue command to update adapter filters, then return */ | |
2534 | ||
2535 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
807540ba ED |
2536 | return DFX_K_FAILURE; |
2537 | return DFX_K_SUCCESS; | |
1da177e4 LT |
2538 | } |
2539 | ||
6aa20a22 | 2540 | |
1da177e4 LT |
2541 | /* |
2542 | * ====================== | |
2543 | * = dfx_hw_dma_cmd_req = | |
2544 | * ====================== | |
6aa20a22 | 2545 | * |
1da177e4 LT |
2546 | * Overview: |
2547 | * Sends PDQ DMA command to adapter firmware | |
6aa20a22 | 2548 | * |
1da177e4 LT |
2549 | * Returns: |
2550 | * Condition code | |
6aa20a22 | 2551 | * |
1da177e4 LT |
2552 | * Arguments: |
2553 | * bp - pointer to board information | |
2554 | * | |
2555 | * Functional Description: | |
2556 | * The command request and response buffers are posted to the adapter in the manner | |
2557 | * described in the PDQ Port Specification: | |
2558 | * | |
2559 | * 1. Command Response Buffer is posted to adapter. | |
2560 | * 2. Command Request Buffer is posted to adapter. | |
2561 | * 3. Command Request consumer index is polled until it indicates that request | |
2562 | * buffer has been DMA'd to adapter. | |
2563 | * 4. Command Response consumer index is polled until it indicates that response | |
2564 | * buffer has been DMA'd from adapter. | |
2565 | * | |
2566 | * This ordering ensures that a response buffer is already available for the firmware | |
2567 | * to use once it's done processing the request buffer. | |
2568 | * | |
2569 | * Return Codes: | |
2570 | * DFX_K_SUCCESS - DMA command succeeded | |
2571 | * DFX_K_OUTSTATE - Adapter is NOT in proper state | |
2572 | * DFX_K_HW_TIMEOUT - DMA command timed out | |
2573 | * | |
2574 | * Assumptions: | |
2575 | * Command request buffer has already been filled with desired DMA command. | |
2576 | * | |
2577 | * Side Effects: | |
2578 | * None | |
2579 | */ | |
2580 | ||
2581 | static int dfx_hw_dma_cmd_req(DFX_board_t *bp) | |
2582 | { | |
2583 | int status; /* adapter status */ | |
2584 | int timeout_cnt; /* used in for loops */ | |
6aa20a22 | 2585 | |
1da177e4 | 2586 | /* Make sure the adapter is in a state that we can issue the DMA command in */ |
6aa20a22 | 2587 | |
1da177e4 LT |
2588 | status = dfx_hw_adap_state_rd(bp); |
2589 | if ((status == PI_STATE_K_RESET) || | |
2590 | (status == PI_STATE_K_HALTED) || | |
2591 | (status == PI_STATE_K_DMA_UNAVAIL) || | |
2592 | (status == PI_STATE_K_UPGRADE)) | |
807540ba | 2593 | return DFX_K_OUTSTATE; |
1da177e4 LT |
2594 | |
2595 | /* Put response buffer on the command response queue */ | |
2596 | ||
2597 | bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | | |
2598 | ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); | |
2599 | bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; | |
2600 | ||
2601 | /* Bump (and wrap) the producer index and write out to register */ | |
2602 | ||
2603 | bp->cmd_rsp_reg.index.prod += 1; | |
2604 | bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; | |
2605 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); | |
2606 | ||
2607 | /* Put request buffer on the command request queue */ | |
6aa20a22 | 2608 | |
1da177e4 LT |
2609 | bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | |
2610 | PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); | |
2611 | bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; | |
2612 | ||
2613 | /* Bump (and wrap) the producer index and write out to register */ | |
2614 | ||
2615 | bp->cmd_req_reg.index.prod += 1; | |
2616 | bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; | |
2617 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); | |
2618 | ||
2619 | /* | |
2620 | * Here we wait for the command request consumer index to be equal | |
2621 | * to the producer, indicating that the adapter has DMAed the request. | |
2622 | */ | |
2623 | ||
2624 | for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) | |
2625 | { | |
2626 | if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) | |
2627 | break; | |
2628 | udelay(100); /* wait for 100 microseconds */ | |
2629 | } | |
6aa20a22 | 2630 | if (timeout_cnt == 0) |
807540ba | 2631 | return DFX_K_HW_TIMEOUT; |
1da177e4 LT |
2632 | |
2633 | /* Bump (and wrap) the completion index and write out to register */ | |
2634 | ||
2635 | bp->cmd_req_reg.index.comp += 1; | |
2636 | bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; | |
2637 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); | |
2638 | ||
2639 | /* | |
2640 | * Here we wait for the command response consumer index to be equal | |
2641 | * to the producer, indicating that the adapter has DMAed the response. | |
2642 | */ | |
2643 | ||
2644 | for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) | |
2645 | { | |
2646 | if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) | |
2647 | break; | |
2648 | udelay(100); /* wait for 100 microseconds */ | |
2649 | } | |
6aa20a22 | 2650 | if (timeout_cnt == 0) |
807540ba | 2651 | return DFX_K_HW_TIMEOUT; |
1da177e4 LT |
2652 | |
2653 | /* Bump (and wrap) the completion index and write out to register */ | |
2654 | ||
2655 | bp->cmd_rsp_reg.index.comp += 1; | |
2656 | bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; | |
2657 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); | |
807540ba | 2658 | return DFX_K_SUCCESS; |
1da177e4 LT |
2659 | } |
2660 | ||
6aa20a22 | 2661 | |
1da177e4 LT |
2662 | /* |
2663 | * ======================== | |
2664 | * = dfx_hw_port_ctrl_req = | |
2665 | * ======================== | |
6aa20a22 | 2666 | * |
1da177e4 LT |
2667 | * Overview: |
2668 | * Sends PDQ port control command to adapter firmware | |
6aa20a22 | 2669 | * |
1da177e4 LT |
2670 | * Returns: |
2671 | * Host data register value in host_data if ptr is not NULL | |
6aa20a22 | 2672 | * |
1da177e4 LT |
2673 | * Arguments: |
2674 | * bp - pointer to board information | |
2675 | * command - port control command | |
2676 | * data_a - port data A register value | |
2677 | * data_b - port data B register value | |
2678 | * host_data - ptr to host data register value | |
2679 | * | |
2680 | * Functional Description: | |
2681 | * Send generic port control command to adapter by writing | |
2682 | * to various PDQ port registers, then polling for completion. | |
2683 | * | |
2684 | * Return Codes: | |
2685 | * DFX_K_SUCCESS - port control command succeeded | |
2686 | * DFX_K_HW_TIMEOUT - port control command timed out | |
2687 | * | |
2688 | * Assumptions: | |
2689 | * None | |
2690 | * | |
2691 | * Side Effects: | |
2692 | * None | |
2693 | */ | |
2694 | ||
2695 | static int dfx_hw_port_ctrl_req( | |
2696 | DFX_board_t *bp, | |
2697 | PI_UINT32 command, | |
2698 | PI_UINT32 data_a, | |
2699 | PI_UINT32 data_b, | |
2700 | PI_UINT32 *host_data | |
2701 | ) | |
2702 | ||
2703 | { | |
2704 | PI_UINT32 port_cmd; /* Port Control command register value */ | |
2705 | int timeout_cnt; /* used in for loops */ | |
2706 | ||
2707 | /* Set Command Error bit in command longword */ | |
6aa20a22 | 2708 | |
1da177e4 LT |
2709 | port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); |
2710 | ||
2711 | /* Issue port command to the adapter */ | |
2712 | ||
2713 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); | |
2714 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); | |
2715 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); | |
2716 | ||
2717 | /* Now wait for command to complete */ | |
2718 | ||
2719 | if (command == PI_PCTRL_M_BLAST_FLASH) | |
2720 | timeout_cnt = 600000; /* set command timeout count to 60 seconds */ | |
2721 | else | |
2722 | timeout_cnt = 20000; /* set command timeout count to 2 seconds */ | |
2723 | ||
2724 | for (; timeout_cnt > 0; timeout_cnt--) | |
2725 | { | |
2726 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); | |
2727 | if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) | |
2728 | break; | |
2729 | udelay(100); /* wait for 100 microseconds */ | |
2730 | } | |
6aa20a22 | 2731 | if (timeout_cnt == 0) |
807540ba | 2732 | return DFX_K_HW_TIMEOUT; |
1da177e4 LT |
2733 | |
2734 | /* | |
6aa20a22 JG |
2735 | * If the address of host_data is non-zero, assume caller has supplied a |
2736 | * non NULL pointer, and return the contents of the HOST_DATA register in | |
1da177e4 LT |
2737 | * it. |
2738 | */ | |
2739 | ||
2740 | if (host_data != NULL) | |
2741 | dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); | |
807540ba | 2742 | return DFX_K_SUCCESS; |
1da177e4 LT |
2743 | } |
2744 | ||
6aa20a22 | 2745 | |
1da177e4 LT |
2746 | /* |
2747 | * ===================== | |
2748 | * = dfx_hw_adap_reset = | |
2749 | * ===================== | |
6aa20a22 | 2750 | * |
1da177e4 LT |
2751 | * Overview: |
2752 | * Resets adapter | |
6aa20a22 | 2753 | * |
1da177e4 LT |
2754 | * Returns: |
2755 | * None | |
6aa20a22 | 2756 | * |
1da177e4 LT |
2757 | * Arguments: |
2758 | * bp - pointer to board information | |
2759 | * type - type of reset to perform | |
2760 | * | |
2761 | * Functional Description: | |
2762 | * Issue soft reset to adapter by writing to PDQ Port Reset | |
2763 | * register. Use incoming reset type to tell adapter what | |
2764 | * kind of reset operation to perform. | |
2765 | * | |
2766 | * Return Codes: | |
2767 | * None | |
2768 | * | |
2769 | * Assumptions: | |
2770 | * This routine merely issues a soft reset to the adapter. | |
2771 | * It is expected that after this routine returns, the caller | |
2772 | * will appropriately poll the Port Status register for the | |
2773 | * adapter to enter the proper state. | |
2774 | * | |
2775 | * Side Effects: | |
2776 | * Internal adapter registers are cleared. | |
2777 | */ | |
2778 | ||
2779 | static void dfx_hw_adap_reset( | |
2780 | DFX_board_t *bp, | |
2781 | PI_UINT32 type | |
2782 | ) | |
2783 | ||
2784 | { | |
2785 | /* Set Reset type and assert reset */ | |
2786 | ||
2787 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ | |
2788 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); | |
2789 | ||
2790 | /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ | |
2791 | ||
2792 | udelay(20); | |
2793 | ||
2794 | /* Deassert reset */ | |
2795 | ||
2796 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); | |
2797 | } | |
2798 | ||
6aa20a22 | 2799 | |
1da177e4 LT |
2800 | /* |
2801 | * ======================== | |
2802 | * = dfx_hw_adap_state_rd = | |
2803 | * ======================== | |
6aa20a22 | 2804 | * |
1da177e4 LT |
2805 | * Overview: |
2806 | * Returns current adapter state | |
6aa20a22 | 2807 | * |
1da177e4 LT |
2808 | * Returns: |
2809 | * Adapter state per PDQ Port Specification | |
6aa20a22 | 2810 | * |
1da177e4 LT |
2811 | * Arguments: |
2812 | * bp - pointer to board information | |
2813 | * | |
2814 | * Functional Description: | |
2815 | * Reads PDQ Port Status register and returns adapter state. | |
2816 | * | |
2817 | * Return Codes: | |
2818 | * None | |
2819 | * | |
2820 | * Assumptions: | |
2821 | * None | |
2822 | * | |
2823 | * Side Effects: | |
2824 | * None | |
2825 | */ | |
2826 | ||
2827 | static int dfx_hw_adap_state_rd(DFX_board_t *bp) | |
2828 | { | |
2829 | PI_UINT32 port_status; /* Port Status register value */ | |
2830 | ||
2831 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); | |
807540ba | 2832 | return (port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE; |
1da177e4 LT |
2833 | } |
2834 | ||
6aa20a22 | 2835 | |
1da177e4 LT |
2836 | /* |
2837 | * ===================== | |
2838 | * = dfx_hw_dma_uninit = | |
2839 | * ===================== | |
6aa20a22 | 2840 | * |
1da177e4 LT |
2841 | * Overview: |
2842 | * Brings adapter to DMA_UNAVAILABLE state | |
6aa20a22 | 2843 | * |
1da177e4 LT |
2844 | * Returns: |
2845 | * Condition code | |
6aa20a22 | 2846 | * |
1da177e4 LT |
2847 | * Arguments: |
2848 | * bp - pointer to board information | |
2849 | * type - type of reset to perform | |
2850 | * | |
2851 | * Functional Description: | |
2852 | * Bring adapter to DMA_UNAVAILABLE state by performing the following: | |
2853 | * 1. Set reset type bit in Port Data A Register then reset adapter. | |
2854 | * 2. Check that adapter is in DMA_UNAVAILABLE state. | |
2855 | * | |
2856 | * Return Codes: | |
2857 | * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state | |
2858 | * DFX_K_HW_TIMEOUT - adapter did not reset properly | |
2859 | * | |
2860 | * Assumptions: | |
2861 | * None | |
2862 | * | |
2863 | * Side Effects: | |
2864 | * Internal adapter registers are cleared. | |
2865 | */ | |
2866 | ||
2867 | static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) | |
2868 | { | |
2869 | int timeout_cnt; /* used in for loops */ | |
2870 | ||
2871 | /* Set reset type bit and reset adapter */ | |
2872 | ||
2873 | dfx_hw_adap_reset(bp, type); | |
2874 | ||
2875 | /* Now wait for adapter to enter DMA_UNAVAILABLE state */ | |
2876 | ||
2877 | for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) | |
2878 | { | |
2879 | if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) | |
2880 | break; | |
2881 | udelay(100); /* wait for 100 microseconds */ | |
2882 | } | |
6aa20a22 | 2883 | if (timeout_cnt == 0) |
807540ba ED |
2884 | return DFX_K_HW_TIMEOUT; |
2885 | return DFX_K_SUCCESS; | |
1da177e4 | 2886 | } |
6aa20a22 | 2887 | |
1da177e4 LT |
2888 | /* |
2889 | * Align an sk_buff to a boundary power of 2 | |
2890 | * | |
2891 | */ | |
1b037474 | 2892 | #ifdef DYNAMIC_BUFFERS |
1da177e4 LT |
2893 | static void my_skb_align(struct sk_buff *skb, int n) |
2894 | { | |
2895 | unsigned long x = (unsigned long)skb->data; | |
2896 | unsigned long v; | |
6aa20a22 | 2897 | |
1da177e4 | 2898 | v = ALIGN(x, n); /* Where we want to be */ |
6aa20a22 | 2899 | |
1da177e4 LT |
2900 | skb_reserve(skb, v - x); |
2901 | } | |
1b037474 | 2902 | #endif |
6aa20a22 | 2903 | |
1da177e4 LT |
2904 | /* |
2905 | * ================ | |
2906 | * = dfx_rcv_init = | |
2907 | * ================ | |
6aa20a22 | 2908 | * |
1da177e4 LT |
2909 | * Overview: |
2910 | * Produces buffers to adapter LLC Host receive descriptor block | |
6aa20a22 | 2911 | * |
1da177e4 LT |
2912 | * Returns: |
2913 | * None | |
6aa20a22 | 2914 | * |
1da177e4 LT |
2915 | * Arguments: |
2916 | * bp - pointer to board information | |
2917 | * get_buffers - non-zero if buffers to be allocated | |
2918 | * | |
2919 | * Functional Description: | |
2920 | * This routine can be called during dfx_adap_init() or during an adapter | |
2921 | * reset. It initializes the descriptor block and produces all allocated | |
2922 | * LLC Host queue receive buffers. | |
2923 | * | |
2924 | * Return Codes: | |
2925 | * Return 0 on success or -ENOMEM if buffer allocation failed (when using | |
2926 | * dynamic buffer allocation). If the buffer allocation failed, the | |
2927 | * already allocated buffers will not be released and the caller should do | |
2928 | * this. | |
2929 | * | |
2930 | * Assumptions: | |
2931 | * The PDQ has been reset and the adapter and driver maintained Type 2 | |
2932 | * register indices are cleared. | |
2933 | * | |
2934 | * Side Effects: | |
2935 | * Receive buffers are posted to the adapter LLC queue and the adapter | |
2936 | * is notified. | |
2937 | */ | |
2938 | ||
2939 | static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) | |
2940 | { | |
2941 | int i, j; /* used in for loop */ | |
2942 | ||
2943 | /* | |
2944 | * Since each receive buffer is a single fragment of same length, initialize | |
2945 | * first longword in each receive descriptor for entire LLC Host descriptor | |
2946 | * block. Also initialize second longword in each receive descriptor with | |
2947 | * physical address of receive buffer. We'll always allocate receive | |
2948 | * buffers in powers of 2 so that we can easily fill the 256 entry descriptor | |
2949 | * block and produce new receive buffers by simply updating the receive | |
2950 | * producer index. | |
2951 | * | |
2952 | * Assumptions: | |
2953 | * To support all shipping versions of PDQ, the receive buffer size | |
2954 | * must be mod 128 in length and the physical address must be 128 byte | |
2955 | * aligned. In other words, bits 0-6 of the length and address must | |
2956 | * be zero for the following descriptor field entries to be correct on | |
2957 | * all PDQ-based boards. We guaranteed both requirements during | |
2958 | * driver initialization when we allocated memory for the receive buffers. | |
2959 | */ | |
2960 | ||
2961 | if (get_buffers) { | |
2962 | #ifdef DYNAMIC_BUFFERS | |
2963 | for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) | |
2964 | for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) | |
2965 | { | |
b37cccf0 MR |
2966 | struct sk_buff *newskb; |
2967 | dma_addr_t dma_addr; | |
2968 | ||
2969 | newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, | |
2970 | GFP_NOIO); | |
1da177e4 LT |
2971 | if (!newskb) |
2972 | return -ENOMEM; | |
1da177e4 LT |
2973 | /* |
2974 | * align to 128 bytes for compatibility with | |
2975 | * the old EISA boards. | |
2976 | */ | |
6aa20a22 | 2977 | |
1da177e4 | 2978 | my_skb_align(newskb, 128); |
b37cccf0 MR |
2979 | dma_addr = dma_map_single(bp->bus_dev, |
2980 | newskb->data, | |
2981 | PI_RCV_DATA_K_SIZE_MAX, | |
2982 | DMA_FROM_DEVICE); | |
2983 | if (dma_mapping_error(bp->bus_dev, dma_addr)) { | |
2984 | dev_kfree_skb(newskb); | |
2985 | return -ENOMEM; | |
2986 | } | |
2987 | bp->descr_block_virt->rcv_data[i + j].long_0 = | |
2988 | (u32)(PI_RCV_DESCR_M_SOP | | |
2989 | ((PI_RCV_DATA_K_SIZE_MAX / | |
2990 | PI_ALIGN_K_RCV_DATA_BUFF) << | |
2991 | PI_RCV_DESCR_V_SEG_LEN)); | |
1da177e4 | 2992 | bp->descr_block_virt->rcv_data[i + j].long_1 = |
b37cccf0 MR |
2993 | (u32)dma_addr; |
2994 | ||
1da177e4 LT |
2995 | /* |
2996 | * p_rcv_buff_va is only used inside the | |
2997 | * kernel so we put the skb pointer here. | |
2998 | */ | |
2999 | bp->p_rcv_buff_va[i+j] = (char *) newskb; | |
3000 | } | |
3001 | #else | |
3002 | for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) | |
3003 | for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) | |
3004 | { | |
3005 | bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | | |
3006 | ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); | |
3007 | bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); | |
c2fd03a0 | 3008 | bp->p_rcv_buff_va[i+j] = (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); |
1da177e4 LT |
3009 | } |
3010 | #endif | |
3011 | } | |
3012 | ||
3013 | /* Update receive producer and Type 2 register */ | |
3014 | ||
3015 | bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; | |
3016 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); | |
3017 | return 0; | |
3018 | } | |
3019 | ||
6aa20a22 | 3020 | |
1da177e4 LT |
3021 | /* |
3022 | * ========================= | |
3023 | * = dfx_rcv_queue_process = | |
3024 | * ========================= | |
6aa20a22 | 3025 | * |
1da177e4 LT |
3026 | * Overview: |
3027 | * Process received LLC frames. | |
6aa20a22 | 3028 | * |
1da177e4 LT |
3029 | * Returns: |
3030 | * None | |
6aa20a22 | 3031 | * |
1da177e4 LT |
3032 | * Arguments: |
3033 | * bp - pointer to board information | |
3034 | * | |
3035 | * Functional Description: | |
3036 | * Received LLC frames are processed until there are no more consumed frames. | |
3037 | * Once all frames are processed, the receive buffers are returned to the | |
3038 | * adapter. Note that this algorithm fixes the length of time that can be spent | |
3039 | * in this routine, because there are a fixed number of receive buffers to | |
3040 | * process and buffers are not produced until this routine exits and returns | |
3041 | * to the ISR. | |
3042 | * | |
3043 | * Return Codes: | |
3044 | * None | |
3045 | * | |
3046 | * Assumptions: | |
3047 | * None | |
3048 | * | |
3049 | * Side Effects: | |
3050 | * None | |
3051 | */ | |
3052 | ||
3053 | static void dfx_rcv_queue_process( | |
3054 | DFX_board_t *bp | |
3055 | ) | |
3056 | ||
3057 | { | |
3058 | PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ | |
3059 | char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ | |
3060 | u32 descr, pkt_len; /* FMC descriptor field and packet length */ | |
b37cccf0 | 3061 | struct sk_buff *skb = NULL; /* pointer to a sk_buff to hold incoming packet data */ |
1da177e4 LT |
3062 | |
3063 | /* Service all consumed LLC receive frames */ | |
3064 | ||
3065 | p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); | |
3066 | while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) | |
3067 | { | |
3068 | /* Process any errors */ | |
8848761f | 3069 | dma_addr_t dma_addr; |
1da177e4 LT |
3070 | int entry; |
3071 | ||
3072 | entry = bp->rcv_xmt_reg.index.rcv_comp; | |
3073 | #ifdef DYNAMIC_BUFFERS | |
3074 | p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); | |
3075 | #else | |
c2fd03a0 | 3076 | p_buff = bp->p_rcv_buff_va[entry]; |
1da177e4 | 3077 | #endif |
8848761f MR |
3078 | dma_addr = bp->descr_block_virt->rcv_data[entry].long_1; |
3079 | dma_sync_single_for_cpu(bp->bus_dev, | |
3080 | dma_addr + RCV_BUFF_K_DESCR, | |
3081 | sizeof(u32), | |
3082 | DMA_FROM_DEVICE); | |
1da177e4 LT |
3083 | memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); |
3084 | ||
3085 | if (descr & PI_FMC_DESCR_M_RCC_FLUSH) | |
3086 | { | |
3087 | if (descr & PI_FMC_DESCR_M_RCC_CRC) | |
3088 | bp->rcv_crc_errors++; | |
3089 | else | |
3090 | bp->rcv_frame_status_errors++; | |
3091 | } | |
3092 | else | |
3093 | { | |
3094 | int rx_in_place = 0; | |
3095 | ||
3096 | /* The frame was received without errors - verify packet length */ | |
3097 | ||
3098 | pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); | |
3099 | pkt_len -= 4; /* subtract 4 byte CRC */ | |
3100 | if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) | |
3101 | bp->rcv_length_errors++; | |
3102 | else{ | |
3103 | #ifdef DYNAMIC_BUFFERS | |
b37cccf0 MR |
3104 | struct sk_buff *newskb = NULL; |
3105 | ||
1da177e4 | 3106 | if (pkt_len > SKBUFF_RX_COPYBREAK) { |
b37cccf0 | 3107 | dma_addr_t new_dma_addr; |
1da177e4 | 3108 | |
a630be70 MR |
3109 | newskb = netdev_alloc_skb(bp->dev, |
3110 | NEW_SKB_SIZE); | |
1da177e4 | 3111 | if (newskb){ |
b37cccf0 MR |
3112 | my_skb_align(newskb, 128); |
3113 | new_dma_addr = dma_map_single( | |
3114 | bp->bus_dev, | |
3115 | newskb->data, | |
3116 | PI_RCV_DATA_K_SIZE_MAX, | |
3117 | DMA_FROM_DEVICE); | |
3118 | if (dma_mapping_error( | |
3119 | bp->bus_dev, | |
3120 | new_dma_addr)) { | |
3121 | dev_kfree_skb(newskb); | |
3122 | newskb = NULL; | |
3123 | } | |
3124 | } | |
3125 | if (newskb) { | |
1da177e4 | 3126 | rx_in_place = 1; |
6aa20a22 | 3127 | |
1da177e4 | 3128 | skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; |
e89a2cfb | 3129 | dma_unmap_single(bp->bus_dev, |
8848761f | 3130 | dma_addr, |
d68ab591 | 3131 | PI_RCV_DATA_K_SIZE_MAX, |
e89a2cfb | 3132 | DMA_FROM_DEVICE); |
1da177e4 LT |
3133 | skb_reserve(skb, RCV_BUFF_K_PADDING); |
3134 | bp->p_rcv_buff_va[entry] = (char *)newskb; | |
b37cccf0 MR |
3135 | bp->descr_block_virt->rcv_data[entry].long_1 = (u32)new_dma_addr; |
3136 | } | |
3137 | } | |
3138 | if (!newskb) | |
1da177e4 | 3139 | #endif |
a630be70 MR |
3140 | /* Alloc new buffer to pass up, |
3141 | * add room for PRH. */ | |
3142 | skb = netdev_alloc_skb(bp->dev, | |
3143 | pkt_len + 3); | |
1da177e4 LT |
3144 | if (skb == NULL) |
3145 | { | |
3146 | printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); | |
3147 | bp->rcv_discards++; | |
3148 | break; | |
3149 | } | |
3150 | else { | |
f46d53d0 | 3151 | if (!rx_in_place) { |
1da177e4 | 3152 | /* Receive buffer allocated, pass receive packet up */ |
8848761f MR |
3153 | dma_sync_single_for_cpu( |
3154 | bp->bus_dev, | |
3155 | dma_addr + | |
3156 | RCV_BUFF_K_PADDING, | |
3157 | pkt_len + 3, | |
3158 | DMA_FROM_DEVICE); | |
1da177e4 | 3159 | |
27d7ff46 ACM |
3160 | skb_copy_to_linear_data(skb, |
3161 | p_buff + RCV_BUFF_K_PADDING, | |
3162 | pkt_len + 3); | |
1da177e4 | 3163 | } |
6aa20a22 | 3164 | |
1da177e4 LT |
3165 | skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ |
3166 | skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ | |
1da177e4 LT |
3167 | skb->protocol = fddi_type_trans(skb, bp->dev); |
3168 | bp->rcv_total_bytes += skb->len; | |
3169 | netif_rx(skb); | |
3170 | ||
3171 | /* Update the rcv counters */ | |
1da177e4 LT |
3172 | bp->rcv_total_frames++; |
3173 | if (*(p_buff + RCV_BUFF_K_DA) & 0x01) | |
3174 | bp->rcv_multicast_frames++; | |
3175 | } | |
3176 | } | |
3177 | } | |
3178 | ||
3179 | /* | |
3180 | * Advance the producer (for recycling) and advance the completion | |
3181 | * (for servicing received frames). Note that it is okay to | |
3182 | * advance the producer without checking that it passes the | |
3183 | * completion index because they are both advanced at the same | |
3184 | * rate. | |
3185 | */ | |
3186 | ||
3187 | bp->rcv_xmt_reg.index.rcv_prod += 1; | |
3188 | bp->rcv_xmt_reg.index.rcv_comp += 1; | |
3189 | } | |
3190 | } | |
3191 | ||
6aa20a22 | 3192 | |
1da177e4 LT |
3193 | /* |
3194 | * ===================== | |
3195 | * = dfx_xmt_queue_pkt = | |
3196 | * ===================== | |
6aa20a22 | 3197 | * |
1da177e4 LT |
3198 | * Overview: |
3199 | * Queues packets for transmission | |
6aa20a22 | 3200 | * |
1da177e4 LT |
3201 | * Returns: |
3202 | * Condition code | |
6aa20a22 | 3203 | * |
1da177e4 LT |
3204 | * Arguments: |
3205 | * skb - pointer to sk_buff to queue for transmission | |
3206 | * dev - pointer to device information | |
3207 | * | |
3208 | * Functional Description: | |
3209 | * Here we assume that an incoming skb transmit request | |
3210 | * is contained in a single physically contiguous buffer | |
3211 | * in which the virtual address of the start of packet | |
3212 | * (skb->data) can be converted to a physical address | |
3213 | * by using pci_map_single(). | |
3214 | * | |
3215 | * Since the adapter architecture requires a three byte | |
3216 | * packet request header to prepend the start of packet, | |
3217 | * we'll write the three byte field immediately prior to | |
3218 | * the FC byte. This assumption is valid because we've | |
3219 | * ensured that dev->hard_header_len includes three pad | |
3220 | * bytes. By posting a single fragment to the adapter, | |
3221 | * we'll reduce the number of descriptor fetches and | |
3222 | * bus traffic needed to send the request. | |
3223 | * | |
3224 | * Also, we can't free the skb until after it's been DMA'd | |
3225 | * out by the adapter, so we'll queue it in the driver and | |
3226 | * return it in dfx_xmt_done. | |
3227 | * | |
3228 | * Return Codes: | |
3229 | * 0 - driver queued packet, link is unavailable, or skbuff was bad | |
3230 | * 1 - caller should requeue the sk_buff for later transmission | |
3231 | * | |
3232 | * Assumptions: | |
3233 | * First and foremost, we assume the incoming skb pointer | |
3234 | * is NOT NULL and is pointing to a valid sk_buff structure. | |
3235 | * | |
3236 | * The outgoing packet is complete, starting with the | |
3237 | * frame control byte including the last byte of data, | |
3238 | * but NOT including the 4 byte CRC. We'll let the | |
3239 | * adapter hardware generate and append the CRC. | |
3240 | * | |
3241 | * The entire packet is stored in one physically | |
3242 | * contiguous buffer which is not cached and whose | |
3243 | * 32-bit physical address can be determined. | |
3244 | * | |
3245 | * It's vital that this routine is NOT reentered for the | |
3246 | * same board and that the OS is not in another section of | |
3247 | * code (eg. dfx_int_common) for the same board on a | |
3248 | * different thread. | |
3249 | * | |
3250 | * Side Effects: | |
3251 | * None | |
3252 | */ | |
3253 | ||
61357325 SH |
3254 | static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, |
3255 | struct net_device *dev) | |
1da177e4 | 3256 | { |
e89a2cfb | 3257 | DFX_board_t *bp = netdev_priv(dev); |
1da177e4 LT |
3258 | u8 prod; /* local transmit producer index */ |
3259 | PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ | |
3260 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ | |
b37cccf0 | 3261 | dma_addr_t dma_addr; |
1da177e4 LT |
3262 | unsigned long flags; |
3263 | ||
3264 | netif_stop_queue(dev); | |
6aa20a22 | 3265 | |
1da177e4 LT |
3266 | /* |
3267 | * Verify that incoming transmit request is OK | |
3268 | * | |
3269 | * Note: The packet size check is consistent with other | |
3270 | * Linux device drivers, although the correct packet | |
3271 | * size should be verified before calling the | |
3272 | * transmit routine. | |
3273 | */ | |
3274 | ||
3275 | if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) | |
3276 | { | |
6aa20a22 | 3277 | printk("%s: Invalid packet length - %u bytes\n", |
1da177e4 LT |
3278 | dev->name, skb->len); |
3279 | bp->xmt_length_errors++; /* bump error counter */ | |
3280 | netif_wake_queue(dev); | |
3281 | dev_kfree_skb(skb); | |
ec634fe3 | 3282 | return NETDEV_TX_OK; /* return "success" */ |
1da177e4 LT |
3283 | } |
3284 | /* | |
3285 | * See if adapter link is available, if not, free buffer | |
3286 | * | |
3287 | * Note: If the link isn't available, free buffer and return 0 | |
3288 | * rather than tell the upper layer to requeue the packet. | |
3289 | * The methodology here is that by the time the link | |
3290 | * becomes available, the packet to be sent will be | |
3291 | * fairly stale. By simply dropping the packet, the | |
3292 | * higher layer protocols will eventually time out | |
3293 | * waiting for response packets which it won't receive. | |
3294 | */ | |
3295 | ||
3296 | if (bp->link_available == PI_K_FALSE) | |
3297 | { | |
3298 | if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ | |
3299 | bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ | |
3300 | else | |
3301 | { | |
3302 | bp->xmt_discards++; /* bump error counter */ | |
3303 | dev_kfree_skb(skb); /* free sk_buff now */ | |
3304 | netif_wake_queue(dev); | |
ec634fe3 | 3305 | return NETDEV_TX_OK; /* return "success" */ |
1da177e4 LT |
3306 | } |
3307 | } | |
3308 | ||
b37cccf0 MR |
3309 | /* Write the three PRH bytes immediately before the FC byte */ |
3310 | ||
3311 | skb_push(skb, 3); | |
3312 | skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ | |
3313 | skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ | |
3314 | skb->data[2] = DFX_PRH2_BYTE; /* specification */ | |
3315 | ||
3316 | dma_addr = dma_map_single(bp->bus_dev, skb->data, skb->len, | |
3317 | DMA_TO_DEVICE); | |
3318 | if (dma_mapping_error(bp->bus_dev, dma_addr)) { | |
3319 | skb_pull(skb, 3); | |
3320 | return NETDEV_TX_BUSY; | |
3321 | } | |
3322 | ||
1da177e4 | 3323 | spin_lock_irqsave(&bp->lock, flags); |
6aa20a22 | 3324 | |
1da177e4 LT |
3325 | /* Get the current producer and the next free xmt data descriptor */ |
3326 | ||
3327 | prod = bp->rcv_xmt_reg.index.xmt_prod; | |
3328 | p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); | |
3329 | ||
3330 | /* | |
3331 | * Get pointer to auxiliary queue entry to contain information | |
3332 | * for this packet. | |
3333 | * | |
3334 | * Note: The current xmt producer index will become the | |
3335 | * current xmt completion index when we complete this | |
3336 | * packet later on. So, we'll get the pointer to the | |
3337 | * next auxiliary queue entry now before we bump the | |
3338 | * producer index. | |
3339 | */ | |
3340 | ||
3341 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ | |
3342 | ||
1da177e4 LT |
3343 | /* |
3344 | * Write the descriptor with buffer info and bump producer | |
3345 | * | |
3346 | * Note: Since we need to start DMA from the packet request | |
3347 | * header, we'll add 3 bytes to the DMA buffer length, | |
3348 | * and we'll determine the physical address of the | |
3349 | * buffer from the PRH, not skb->data. | |
3350 | * | |
3351 | * Assumptions: | |
3352 | * 1. Packet starts with the frame control (FC) byte | |
3353 | * at skb->data. | |
3354 | * 2. The 4-byte CRC is not appended to the buffer or | |
3355 | * included in the length. | |
3356 | * 3. Packet length (skb->len) is from FC to end of | |
3357 | * data, inclusive. | |
3358 | * 4. The packet length does not exceed the maximum | |
3359 | * FDDI LLC frame length of 4491 bytes. | |
3360 | * 5. The entire packet is contained in a physically | |
3361 | * contiguous, non-cached, locked memory space | |
3362 | * comprised of a single buffer pointed to by | |
3363 | * skb->data. | |
3364 | * 6. The physical address of the start of packet | |
3365 | * can be determined from the virtual address | |
3366 | * by using pci_map_single() and is only 32-bits | |
3367 | * wide. | |
3368 | */ | |
3369 | ||
3370 | p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); | |
b37cccf0 | 3371 | p_xmt_descr->long_1 = (u32)dma_addr; |
1da177e4 LT |
3372 | |
3373 | /* | |
3374 | * Verify that descriptor is actually available | |
3375 | * | |
3376 | * Note: If descriptor isn't available, return 1 which tells | |
3377 | * the upper layer to requeue the packet for later | |
3378 | * transmission. | |
3379 | * | |
3380 | * We need to ensure that the producer never reaches the | |
3381 | * completion, except to indicate that the queue is empty. | |
3382 | */ | |
3383 | ||
3384 | if (prod == bp->rcv_xmt_reg.index.xmt_comp) | |
3385 | { | |
3386 | skb_pull(skb,3); | |
3387 | spin_unlock_irqrestore(&bp->lock, flags); | |
5b548140 | 3388 | return NETDEV_TX_BUSY; /* requeue packet for later */ |
1da177e4 LT |
3389 | } |
3390 | ||
3391 | /* | |
3392 | * Save info for this packet for xmt done indication routine | |
3393 | * | |
3394 | * Normally, we'd save the producer index in the p_xmt_drv_descr | |
3395 | * structure so that we'd have it handy when we complete this | |
3396 | * packet later (in dfx_xmt_done). However, since the current | |
3397 | * transmit architecture guarantees a single fragment for the | |
3398 | * entire packet, we can simply bump the completion index by | |
3399 | * one (1) for each completed packet. | |
3400 | * | |
3401 | * Note: If this assumption changes and we're presented with | |
3402 | * an inconsistent number of transmit fragments for packet | |
3403 | * data, we'll need to modify this code to save the current | |
3404 | * transmit producer index. | |
3405 | */ | |
3406 | ||
3407 | p_xmt_drv_descr->p_skb = skb; | |
3408 | ||
3409 | /* Update Type 2 register */ | |
3410 | ||
3411 | bp->rcv_xmt_reg.index.xmt_prod = prod; | |
3412 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); | |
3413 | spin_unlock_irqrestore(&bp->lock, flags); | |
3414 | netif_wake_queue(dev); | |
ec634fe3 | 3415 | return NETDEV_TX_OK; /* packet queued to adapter */ |
1da177e4 LT |
3416 | } |
3417 | ||
6aa20a22 | 3418 | |
1da177e4 LT |
3419 | /* |
3420 | * ================ | |
3421 | * = dfx_xmt_done = | |
3422 | * ================ | |
6aa20a22 | 3423 | * |
1da177e4 LT |
3424 | * Overview: |
3425 | * Processes all frames that have been transmitted. | |
6aa20a22 | 3426 | * |
1da177e4 LT |
3427 | * Returns: |
3428 | * None | |
6aa20a22 | 3429 | * |
1da177e4 LT |
3430 | * Arguments: |
3431 | * bp - pointer to board information | |
3432 | * | |
3433 | * Functional Description: | |
3434 | * For all consumed transmit descriptors that have not | |
3435 | * yet been completed, we'll free the skb we were holding | |
3436 | * onto using dev_kfree_skb and bump the appropriate | |
3437 | * counters. | |
3438 | * | |
3439 | * Return Codes: | |
3440 | * None | |
3441 | * | |
3442 | * Assumptions: | |
3443 | * The Type 2 register is not updated in this routine. It is | |
3444 | * assumed that it will be updated in the ISR when dfx_xmt_done | |
3445 | * returns. | |
3446 | * | |
3447 | * Side Effects: | |
3448 | * None | |
3449 | */ | |
3450 | ||
3451 | static int dfx_xmt_done(DFX_board_t *bp) | |
3452 | { | |
3453 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ | |
3454 | PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ | |
3455 | u8 comp; /* local transmit completion index */ | |
3456 | int freed = 0; /* buffers freed */ | |
3457 | ||
3458 | /* Service all consumed transmit frames */ | |
3459 | ||
3460 | p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); | |
3461 | while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) | |
3462 | { | |
3463 | /* Get pointer to the transmit driver descriptor block information */ | |
3464 | ||
3465 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); | |
3466 | ||
3467 | /* Increment transmit counters */ | |
3468 | ||
3469 | bp->xmt_total_frames++; | |
3470 | bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; | |
3471 | ||
3472 | /* Return skb to operating system */ | |
3473 | comp = bp->rcv_xmt_reg.index.xmt_comp; | |
e89a2cfb | 3474 | dma_unmap_single(bp->bus_dev, |
1da177e4 LT |
3475 | bp->descr_block_virt->xmt_data[comp].long_1, |
3476 | p_xmt_drv_descr->p_skb->len, | |
e89a2cfb | 3477 | DMA_TO_DEVICE); |
1da177e4 LT |
3478 | dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); |
3479 | ||
3480 | /* | |
3481 | * Move to start of next packet by updating completion index | |
3482 | * | |
3483 | * Here we assume that a transmit packet request is always | |
3484 | * serviced by posting one fragment. We can therefore | |
3485 | * simplify the completion code by incrementing the | |
3486 | * completion index by one. This code will need to be | |
3487 | * modified if this assumption changes. See comments | |
3488 | * in dfx_xmt_queue_pkt for more details. | |
3489 | */ | |
3490 | ||
3491 | bp->rcv_xmt_reg.index.xmt_comp += 1; | |
3492 | freed++; | |
3493 | } | |
3494 | return freed; | |
3495 | } | |
3496 | ||
6aa20a22 | 3497 | |
1da177e4 LT |
3498 | /* |
3499 | * ================= | |
3500 | * = dfx_rcv_flush = | |
3501 | * ================= | |
6aa20a22 | 3502 | * |
1da177e4 LT |
3503 | * Overview: |
3504 | * Remove all skb's in the receive ring. | |
6aa20a22 | 3505 | * |
1da177e4 LT |
3506 | * Returns: |
3507 | * None | |
6aa20a22 | 3508 | * |
1da177e4 LT |
3509 | * Arguments: |
3510 | * bp - pointer to board information | |
3511 | * | |
3512 | * Functional Description: | |
3513 | * Free's all the dynamically allocated skb's that are | |
3514 | * currently attached to the device receive ring. This | |
3515 | * function is typically only used when the device is | |
3516 | * initialized or reinitialized. | |
3517 | * | |
3518 | * Return Codes: | |
3519 | * None | |
3520 | * | |
3521 | * Side Effects: | |
3522 | * None | |
3523 | */ | |
3524 | #ifdef DYNAMIC_BUFFERS | |
3525 | static void dfx_rcv_flush( DFX_board_t *bp ) | |
3526 | { | |
3527 | int i, j; | |
3528 | ||
3529 | for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) | |
3530 | for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) | |
3531 | { | |
3532 | struct sk_buff *skb; | |
3533 | skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; | |
6329fe5c MR |
3534 | if (skb) { |
3535 | dma_unmap_single(bp->bus_dev, | |
3536 | bp->descr_block_virt->rcv_data[i+j].long_1, | |
3537 | PI_RCV_DATA_K_SIZE_MAX, | |
3538 | DMA_FROM_DEVICE); | |
1da177e4 | 3539 | dev_kfree_skb(skb); |
6329fe5c | 3540 | } |
1da177e4 LT |
3541 | bp->p_rcv_buff_va[i+j] = NULL; |
3542 | } | |
3543 | ||
3544 | } | |
1da177e4 LT |
3545 | #endif /* DYNAMIC_BUFFERS */ |
3546 | ||
3547 | /* | |
3548 | * ================= | |
3549 | * = dfx_xmt_flush = | |
3550 | * ================= | |
6aa20a22 | 3551 | * |
1da177e4 LT |
3552 | * Overview: |
3553 | * Processes all frames whether they've been transmitted | |
3554 | * or not. | |
6aa20a22 | 3555 | * |
1da177e4 LT |
3556 | * Returns: |
3557 | * None | |
6aa20a22 | 3558 | * |
1da177e4 LT |
3559 | * Arguments: |
3560 | * bp - pointer to board information | |
3561 | * | |
3562 | * Functional Description: | |
3563 | * For all produced transmit descriptors that have not | |
3564 | * yet been completed, we'll free the skb we were holding | |
3565 | * onto using dev_kfree_skb and bump the appropriate | |
3566 | * counters. Of course, it's possible that some of | |
3567 | * these transmit requests actually did go out, but we | |
3568 | * won't make that distinction here. Finally, we'll | |
3569 | * update the consumer index to match the producer. | |
3570 | * | |
3571 | * Return Codes: | |
3572 | * None | |
3573 | * | |
3574 | * Assumptions: | |
3575 | * This routine does NOT update the Type 2 register. It | |
3576 | * is assumed that this routine is being called during a | |
3577 | * transmit flush interrupt, or a shutdown or close routine. | |
3578 | * | |
3579 | * Side Effects: | |
3580 | * None | |
3581 | */ | |
3582 | ||
3583 | static void dfx_xmt_flush( DFX_board_t *bp ) | |
3584 | { | |
3585 | u32 prod_cons; /* rcv/xmt consumer block longword */ | |
3586 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ | |
3587 | u8 comp; /* local transmit completion index */ | |
3588 | ||
3589 | /* Flush all outstanding transmit frames */ | |
3590 | ||
3591 | while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) | |
3592 | { | |
3593 | /* Get pointer to the transmit driver descriptor block information */ | |
3594 | ||
3595 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); | |
3596 | ||
3597 | /* Return skb to operating system */ | |
3598 | comp = bp->rcv_xmt_reg.index.xmt_comp; | |
e89a2cfb | 3599 | dma_unmap_single(bp->bus_dev, |
1da177e4 LT |
3600 | bp->descr_block_virt->xmt_data[comp].long_1, |
3601 | p_xmt_drv_descr->p_skb->len, | |
e89a2cfb | 3602 | DMA_TO_DEVICE); |
1da177e4 LT |
3603 | dev_kfree_skb(p_xmt_drv_descr->p_skb); |
3604 | ||
3605 | /* Increment transmit error counter */ | |
3606 | ||
3607 | bp->xmt_discards++; | |
3608 | ||
3609 | /* | |
3610 | * Move to start of next packet by updating completion index | |
3611 | * | |
3612 | * Here we assume that a transmit packet request is always | |
3613 | * serviced by posting one fragment. We can therefore | |
3614 | * simplify the completion code by incrementing the | |
3615 | * completion index by one. This code will need to be | |
3616 | * modified if this assumption changes. See comments | |
3617 | * in dfx_xmt_queue_pkt for more details. | |
3618 | */ | |
3619 | ||
3620 | bp->rcv_xmt_reg.index.xmt_comp += 1; | |
3621 | } | |
3622 | ||
3623 | /* Update the transmit consumer index in the consumer block */ | |
3624 | ||
3625 | prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); | |
3626 | prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); | |
3627 | bp->cons_block_virt->xmt_rcv_data = prod_cons; | |
3628 | } | |
3629 | ||
e89a2cfb MR |
3630 | /* |
3631 | * ================== | |
3632 | * = dfx_unregister = | |
3633 | * ================== | |
3634 | * | |
3635 | * Overview: | |
3636 | * Shuts down an FDDI controller | |
3637 | * | |
3638 | * Returns: | |
3639 | * Condition code | |
3640 | * | |
3641 | * Arguments: | |
3642 | * bdev - pointer to device information | |
3643 | * | |
3644 | * Functional Description: | |
3645 | * | |
3646 | * Return Codes: | |
3647 | * None | |
3648 | * | |
3649 | * Assumptions: | |
3650 | * It compiles so it should work :-( (PCI cards do :-) | |
3651 | * | |
3652 | * Side Effects: | |
3653 | * Device structures for FDDI adapters (fddi0, fddi1, etc) are | |
3654 | * freed. | |
3655 | */ | |
c354dfc3 | 3656 | static void dfx_unregister(struct device *bdev) |
1da177e4 | 3657 | { |
e89a2cfb MR |
3658 | struct net_device *dev = dev_get_drvdata(bdev); |
3659 | DFX_board_t *bp = netdev_priv(dev); | |
5349d937 | 3660 | int dfx_bus_pci = dev_is_pci(bdev); |
e89a2cfb MR |
3661 | int dfx_bus_tc = DFX_BUS_TC(bdev); |
3662 | int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; | |
3663 | resource_size_t bar_start = 0; /* pointer to port */ | |
3664 | resource_size_t bar_len = 0; /* resource length */ | |
1da177e4 LT |
3665 | int alloc_size; /* total buffer size used */ |
3666 | ||
3667 | unregister_netdev(dev); | |
1da177e4 LT |
3668 | |
3669 | alloc_size = sizeof(PI_DESCR_BLOCK) + | |
3670 | PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + | |
3671 | #ifndef DYNAMIC_BUFFERS | |
3672 | (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + | |
3673 | #endif | |
3674 | sizeof(PI_CONSUMER_BLOCK) + | |
3675 | (PI_ALIGN_K_DESC_BLK - 1); | |
3676 | if (bp->kmalloced) | |
e89a2cfb MR |
3677 | dma_free_coherent(bdev, alloc_size, |
3678 | bp->kmalloced, bp->kmalloced_dma); | |
3679 | ||
3680 | dfx_bus_uninit(dev); | |
3681 | ||
3682 | dfx_get_bars(bdev, &bar_start, &bar_len); | |
3683 | if (dfx_use_mmio) { | |
3684 | iounmap(bp->base.mem); | |
3685 | release_mem_region(bar_start, bar_len); | |
3686 | } else | |
3687 | release_region(bar_start, bar_len); | |
3688 | ||
3689 | if (dfx_bus_pci) | |
3690 | pci_disable_device(to_pci_dev(bdev)); | |
3691 | ||
1da177e4 LT |
3692 | free_netdev(dev); |
3693 | } | |
3694 | ||
1da177e4 | 3695 | |
c354dfc3 BP |
3696 | static int __maybe_unused dfx_dev_register(struct device *); |
3697 | static int __maybe_unused dfx_dev_unregister(struct device *); | |
1da177e4 | 3698 | |
e89a2cfb | 3699 | #ifdef CONFIG_PCI |
1dd06ae8 | 3700 | static int dfx_pci_register(struct pci_dev *, const struct pci_device_id *); |
c354dfc3 | 3701 | static void dfx_pci_unregister(struct pci_dev *); |
e89a2cfb | 3702 | |
9baa3c34 | 3703 | static const struct pci_device_id dfx_pci_table[] = { |
e89a2cfb MR |
3704 | { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) }, |
3705 | { } | |
1da177e4 | 3706 | }; |
e89a2cfb | 3707 | MODULE_DEVICE_TABLE(pci, dfx_pci_table); |
1da177e4 | 3708 | |
e89a2cfb | 3709 | static struct pci_driver dfx_pci_driver = { |
1da177e4 | 3710 | .name = "defxx", |
e89a2cfb MR |
3711 | .id_table = dfx_pci_table, |
3712 | .probe = dfx_pci_register, | |
c354dfc3 | 3713 | .remove = dfx_pci_unregister, |
1da177e4 LT |
3714 | }; |
3715 | ||
c354dfc3 | 3716 | static int dfx_pci_register(struct pci_dev *pdev, |
1dd06ae8 | 3717 | const struct pci_device_id *ent) |
e89a2cfb MR |
3718 | { |
3719 | return dfx_register(&pdev->dev); | |
3720 | } | |
1da177e4 | 3721 | |
c354dfc3 | 3722 | static void dfx_pci_unregister(struct pci_dev *pdev) |
1da177e4 | 3723 | { |
e89a2cfb MR |
3724 | dfx_unregister(&pdev->dev); |
3725 | } | |
3726 | #endif /* CONFIG_PCI */ | |
3727 | ||
3728 | #ifdef CONFIG_EISA | |
3729 | static struct eisa_device_id dfx_eisa_table[] = { | |
3730 | { "DEC3001", DEFEA_PROD_ID_1 }, | |
3731 | { "DEC3002", DEFEA_PROD_ID_2 }, | |
3732 | { "DEC3003", DEFEA_PROD_ID_3 }, | |
3733 | { "DEC3004", DEFEA_PROD_ID_4 }, | |
3734 | { } | |
3735 | }; | |
3736 | MODULE_DEVICE_TABLE(eisa, dfx_eisa_table); | |
3737 | ||
3738 | static struct eisa_driver dfx_eisa_driver = { | |
3739 | .id_table = dfx_eisa_table, | |
3740 | .driver = { | |
3741 | .name = "defxx", | |
3742 | .bus = &eisa_bus_type, | |
3743 | .probe = dfx_dev_register, | |
c354dfc3 | 3744 | .remove = dfx_dev_unregister, |
e89a2cfb MR |
3745 | }, |
3746 | }; | |
3747 | #endif /* CONFIG_EISA */ | |
3748 | ||
3749 | #ifdef CONFIG_TC | |
3750 | static struct tc_device_id const dfx_tc_table[] = { | |
3751 | { "DEC ", "PMAF-FA " }, | |
3752 | { "DEC ", "PMAF-FD " }, | |
3753 | { "DEC ", "PMAF-FS " }, | |
3754 | { "DEC ", "PMAF-FU " }, | |
3755 | { } | |
3756 | }; | |
3757 | MODULE_DEVICE_TABLE(tc, dfx_tc_table); | |
3758 | ||
3759 | static struct tc_driver dfx_tc_driver = { | |
3760 | .id_table = dfx_tc_table, | |
3761 | .driver = { | |
3762 | .name = "defxx", | |
3763 | .bus = &tc_bus_type, | |
3764 | .probe = dfx_dev_register, | |
c354dfc3 | 3765 | .remove = dfx_dev_unregister, |
e89a2cfb MR |
3766 | }, |
3767 | }; | |
3768 | #endif /* CONFIG_TC */ | |
1da177e4 | 3769 | |
c354dfc3 | 3770 | static int __maybe_unused dfx_dev_register(struct device *dev) |
e89a2cfb MR |
3771 | { |
3772 | int status; | |
1da177e4 | 3773 | |
e89a2cfb MR |
3774 | status = dfx_register(dev); |
3775 | if (!status) | |
3776 | get_device(dev); | |
3777 | return status; | |
1da177e4 LT |
3778 | } |
3779 | ||
c354dfc3 | 3780 | static int __maybe_unused dfx_dev_unregister(struct device *dev) |
1da177e4 | 3781 | { |
e89a2cfb MR |
3782 | put_device(dev); |
3783 | dfx_unregister(dev); | |
3784 | return 0; | |
3785 | } | |
6aa20a22 | 3786 | |
1da177e4 | 3787 | |
c354dfc3 | 3788 | static int dfx_init(void) |
e89a2cfb MR |
3789 | { |
3790 | int status; | |
3791 | ||
3792 | status = pci_register_driver(&dfx_pci_driver); | |
3793 | if (!status) | |
3794 | status = eisa_driver_register(&dfx_eisa_driver); | |
3795 | if (!status) | |
3796 | status = tc_register_driver(&dfx_tc_driver); | |
3797 | return status; | |
1da177e4 LT |
3798 | } |
3799 | ||
c354dfc3 | 3800 | static void dfx_cleanup(void) |
1da177e4 | 3801 | { |
e89a2cfb MR |
3802 | tc_unregister_driver(&dfx_tc_driver); |
3803 | eisa_driver_unregister(&dfx_eisa_driver); | |
3804 | pci_unregister_driver(&dfx_pci_driver); | |
6aa20a22 | 3805 | } |
1da177e4 LT |
3806 | |
3807 | module_init(dfx_init); | |
3808 | module_exit(dfx_cleanup); | |
3809 | MODULE_AUTHOR("Lawrence V. Stefani"); | |
e89a2cfb | 3810 | MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver " |
1da177e4 LT |
3811 | DRV_VERSION " " DRV_RELDATE); |
3812 | MODULE_LICENSE("GPL"); |