Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b SG |
20 | * |
21 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
1da177e4 | 47 | |
080853af | 48 | #include <asm/cacheflush.h> |
196719ec | 49 | |
b5680e0b | 50 | #ifndef CONFIG_ARM |
1da177e4 LT |
51 | #include <asm/coldfire.h> |
52 | #include <asm/mcfsim.h> | |
196719ec | 53 | #endif |
6f501b17 | 54 | |
1da177e4 | 55 | #include "fec.h" |
1da177e4 | 56 | |
085e79ed | 57 | #if defined(CONFIG_ARM) |
196719ec SH |
58 | #define FEC_ALIGNMENT 0xf |
59 | #else | |
60 | #define FEC_ALIGNMENT 0x3 | |
61 | #endif | |
62 | ||
b5680e0b SG |
63 | #define DRIVER_NAME "fec" |
64 | ||
65 | /* Controller is ENET-MAC */ | |
66 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
67 | /* Controller needs driver to swap frame */ | |
68 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
69 | ||
70 | static struct platform_device_id fec_devtype[] = { | |
71 | { | |
72 | .name = DRIVER_NAME, | |
73 | .driver_data = 0, | |
74 | }, { | |
75 | .name = "imx28-fec", | |
76 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
9eb0e6f2 AL |
77 | }, |
78 | { } | |
b5680e0b SG |
79 | }; |
80 | ||
49da97dc SG |
81 | static unsigned char macaddr[ETH_ALEN]; |
82 | module_param_array(macaddr, byte, NULL, 0); | |
83 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 84 | |
49da97dc | 85 | #if defined(CONFIG_M5272) |
1da177e4 LT |
86 | /* |
87 | * Some hardware gets it MAC address out of local flash memory. | |
88 | * if this is non-zero then assume it is the address to get MAC from. | |
89 | */ | |
90 | #if defined(CONFIG_NETtel) | |
91 | #define FEC_FLASHMAC 0xf0006006 | |
92 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
93 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
94 | #elif defined(CONFIG_CANCam) |
95 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
96 | #elif defined (CONFIG_M5272C3) |
97 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
98 | #elif defined(CONFIG_MOD5272) | |
99 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
100 | #else |
101 | #define FEC_FLASHMAC 0 | |
102 | #endif | |
43be6366 | 103 | #endif /* CONFIG_M5272 */ |
ead73183 | 104 | |
1da177e4 LT |
105 | /* The number of Tx and Rx buffers. These are allocated from the page |
106 | * pool. The code may assume these are power of two, so it it best | |
107 | * to keep them that size. | |
108 | * We don't need to allocate pages for the transmitter. We just use | |
109 | * the skbuffer directly. | |
110 | */ | |
111 | #define FEC_ENET_RX_PAGES 8 | |
112 | #define FEC_ENET_RX_FRSIZE 2048 | |
113 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
114 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
115 | #define FEC_ENET_TX_FRSIZE 2048 | |
116 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
117 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
118 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
119 | ||
562d2f8c | 120 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 121 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
122 | #endif |
123 | ||
22f6b860 | 124 | /* Interrupt events/masks. */ |
1da177e4 LT |
125 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
126 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
127 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
128 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
129 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
130 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
131 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
132 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
133 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
134 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
135 | ||
4bee1f9a WS |
136 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
137 | ||
1da177e4 LT |
138 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
139 | */ | |
140 | #define PKT_MAXBUF_SIZE 1518 | |
141 | #define PKT_MINBUF_SIZE 64 | |
142 | #define PKT_MAXBLR_SIZE 1520 | |
143 | ||
144 | ||
145 | /* | |
6b265293 | 146 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
147 | * size bits. Other FEC hardware does not, so we need to take that into |
148 | * account when setting it. | |
149 | */ | |
562d2f8c | 150 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 151 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
152 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
153 | #else | |
154 | #define OPT_FRAME_SIZE 0 | |
155 | #endif | |
156 | ||
157 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
158 | * tx_bd_base always point to the base of the buffer descriptors. The | |
159 | * cur_rx and cur_tx point to the currently available buffer. | |
160 | * The dirty_tx tracks the current buffer that is being sent by the | |
161 | * controller. The cur_tx and dirty_tx are equal under both completely | |
162 | * empty and completely full conditions. The empty/ready indicator in | |
163 | * the buffer descriptor determines the actual condition. | |
164 | */ | |
165 | struct fec_enet_private { | |
166 | /* Hardware registers of the FEC device */ | |
f44d6305 | 167 | void __iomem *hwp; |
1da177e4 | 168 | |
cb84d6e7 GU |
169 | struct net_device *netdev; |
170 | ||
ead73183 SH |
171 | struct clk *clk; |
172 | ||
1da177e4 LT |
173 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
174 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
175 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 176 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
177 | ushort skb_cur; |
178 | ushort skb_dirty; | |
179 | ||
22f6b860 | 180 | /* CPM dual port RAM relative addresses */ |
4661e75b | 181 | dma_addr_t bd_dma; |
22f6b860 | 182 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
183 | struct bufdesc *rx_bd_base; |
184 | struct bufdesc *tx_bd_base; | |
185 | /* The next free ring entry */ | |
db8880bc | 186 | struct bufdesc *cur_rx, *cur_tx; |
22f6b860 | 187 | /* The ring entries to be free()ed */ |
2e28532f SH |
188 | struct bufdesc *dirty_tx; |
189 | ||
1da177e4 | 190 | uint tx_full; |
3b2b74ca SS |
191 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
192 | spinlock_t hw_lock; | |
1da177e4 | 193 | |
db8880bc | 194 | struct platform_device *pdev; |
1da177e4 | 195 | |
e6b043d5 | 196 | int opened; |
1da177e4 | 197 | |
e6b043d5 | 198 | /* Phylib and MDIO interface */ |
db8880bc UKK |
199 | struct mii_bus *mii_bus; |
200 | struct phy_device *phy_dev; | |
201 | int mii_timeout; | |
202 | uint phy_speed; | |
5eb32bd0 | 203 | phy_interface_t phy_interface; |
1da177e4 | 204 | int link; |
1da177e4 | 205 | int full_duplex; |
97b72e43 | 206 | struct completion mdio_done; |
1da177e4 LT |
207 | }; |
208 | ||
e6b043d5 BW |
209 | /* FEC MII MMFR bits definition */ |
210 | #define FEC_MMFR_ST (1 << 30) | |
211 | #define FEC_MMFR_OP_READ (2 << 28) | |
212 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
213 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
214 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
215 | #define FEC_MMFR_TA (2 << 16) | |
216 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 217 | |
97b72e43 | 218 | #define FEC_MII_TIMEOUT 1000 /* us */ |
1da177e4 | 219 | |
22f6b860 SH |
220 | /* Transmitter timeout */ |
221 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 222 | |
b5680e0b SG |
223 | static void *swap_buffer(void *bufaddr, int len) |
224 | { | |
225 | int i; | |
226 | unsigned int *buf = bufaddr; | |
227 | ||
228 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
229 | *buf = cpu_to_be32(*buf); | |
230 | ||
231 | return bufaddr; | |
232 | } | |
233 | ||
c7621cb3 | 234 | static netdev_tx_t |
c556167f | 235 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 236 | { |
c556167f | 237 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
238 | const struct platform_device_id *id_entry = |
239 | platform_get_device_id(fep->pdev); | |
2e28532f | 240 | struct bufdesc *bdp; |
9555b31e | 241 | void *bufaddr; |
0e702ab3 | 242 | unsigned short status; |
3b2b74ca | 243 | unsigned long flags; |
1da177e4 | 244 | |
1da177e4 LT |
245 | if (!fep->link) { |
246 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 247 | return NETDEV_TX_BUSY; |
1da177e4 LT |
248 | } |
249 | ||
3b2b74ca | 250 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
251 | /* Fill in a Tx ring entry */ |
252 | bdp = fep->cur_tx; | |
253 | ||
0e702ab3 | 254 | status = bdp->cbd_sc; |
22f6b860 | 255 | |
0e702ab3 | 256 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 257 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 258 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 259 | */ |
c556167f | 260 | printk("%s: tx queue full!.\n", ndev->name); |
3b2b74ca | 261 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 262 | return NETDEV_TX_BUSY; |
1da177e4 | 263 | } |
1da177e4 | 264 | |
22f6b860 | 265 | /* Clear all of the status flags */ |
0e702ab3 | 266 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 267 | |
22f6b860 | 268 | /* Set buffer length and buffer pointer */ |
9555b31e | 269 | bufaddr = skb->data; |
1da177e4 LT |
270 | bdp->cbd_datlen = skb->len; |
271 | ||
272 | /* | |
22f6b860 SH |
273 | * On some FEC implementations data must be aligned on |
274 | * 4-byte boundaries. Use bounce buffers to copy data | |
275 | * and get it aligned. Ugh. | |
1da177e4 | 276 | */ |
9555b31e | 277 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
278 | unsigned int index; |
279 | index = bdp - fep->tx_bd_base; | |
8a73b0bc | 280 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 281 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
282 | } |
283 | ||
b5680e0b SG |
284 | /* |
285 | * Some design made an incorrect assumption on endian mode of | |
286 | * the system that it's running on. As the result, driver has to | |
287 | * swap every frame going to and coming from the controller. | |
288 | */ | |
289 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
290 | swap_buffer(bufaddr, skb->len); | |
291 | ||
22f6b860 | 292 | /* Save skb pointer */ |
1da177e4 LT |
293 | fep->tx_skbuff[fep->skb_cur] = skb; |
294 | ||
c556167f | 295 | ndev->stats.tx_bytes += skb->len; |
1da177e4 | 296 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 297 | |
1da177e4 LT |
298 | /* Push the data cache so the CPM does not get stale memory |
299 | * data. | |
300 | */ | |
d1ab1f54 | 301 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 302 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 303 | |
0e702ab3 GU |
304 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
305 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 306 | */ |
0e702ab3 | 307 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 308 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 309 | bdp->cbd_sc = status; |
1da177e4 | 310 | |
1da177e4 | 311 | /* Trigger transmission start */ |
f44d6305 | 312 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 313 | |
22f6b860 SH |
314 | /* If this was the last BD in the ring, start at the beginning again. */ |
315 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 316 | bdp = fep->tx_bd_base; |
22f6b860 | 317 | else |
1da177e4 | 318 | bdp++; |
1da177e4 LT |
319 | |
320 | if (bdp == fep->dirty_tx) { | |
321 | fep->tx_full = 1; | |
c556167f | 322 | netif_stop_queue(ndev); |
1da177e4 LT |
323 | } |
324 | ||
2e28532f | 325 | fep->cur_tx = bdp; |
1da177e4 | 326 | |
18a03b97 RC |
327 | skb_tx_timestamp(skb); |
328 | ||
a0087a36 RC |
329 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
330 | ||
6ed10654 | 331 | return NETDEV_TX_OK; |
1da177e4 LT |
332 | } |
333 | ||
45993653 UKK |
334 | /* This function is called to start or restart the FEC during a link |
335 | * change. This only happens when switching between half and full | |
336 | * duplex. | |
337 | */ | |
1da177e4 | 338 | static void |
45993653 | 339 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 340 | { |
c556167f | 341 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
342 | const struct platform_device_id *id_entry = |
343 | platform_get_device_id(fep->pdev); | |
344 | int i; | |
cd1f402c UKK |
345 | u32 temp_mac[2]; |
346 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
1da177e4 | 347 | |
45993653 UKK |
348 | /* Whack a reset. We should wait for this. */ |
349 | writel(1, fep->hwp + FEC_ECNTRL); | |
350 | udelay(10); | |
1da177e4 | 351 | |
45993653 UKK |
352 | /* |
353 | * enet-mac reset will reset mac address registers too, | |
354 | * so need to reconfigure it. | |
355 | */ | |
356 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
357 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
358 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
359 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
360 | } | |
1da177e4 | 361 | |
45993653 UKK |
362 | /* Clear any outstanding interrupt. */ |
363 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 364 | |
45993653 UKK |
365 | /* Reset all multicast. */ |
366 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
367 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
368 | #ifndef CONFIG_M5272 | |
369 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
370 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
371 | #endif | |
1da177e4 | 372 | |
45993653 UKK |
373 | /* Set maximum receive buffer size. */ |
374 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 375 | |
45993653 UKK |
376 | /* Set receive and transmit descriptor base. */ |
377 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
378 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, | |
379 | fep->hwp + FEC_X_DES_START); | |
380 | ||
381 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
382 | fep->cur_rx = fep->rx_bd_base; | |
383 | ||
384 | /* Reset SKB transmit buffers. */ | |
385 | fep->skb_cur = fep->skb_dirty = 0; | |
386 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { | |
387 | if (fep->tx_skbuff[i]) { | |
388 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
389 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 390 | } |
45993653 | 391 | } |
97b72e43 | 392 | |
45993653 UKK |
393 | /* Enable MII mode */ |
394 | if (duplex) { | |
cd1f402c | 395 | /* FD enable */ |
45993653 UKK |
396 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
397 | } else { | |
cd1f402c UKK |
398 | /* No Rcv on Xmit */ |
399 | rcntl |= 0x02; | |
45993653 UKK |
400 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
401 | } | |
cd1f402c | 402 | |
45993653 UKK |
403 | fep->full_duplex = duplex; |
404 | ||
405 | /* Set MII speed */ | |
406 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
407 | ||
408 | /* | |
409 | * The phy interface and speed need to get configured | |
410 | * differently on enet-mac. | |
411 | */ | |
412 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
413 | /* Enable flow control and length check */ |
414 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 UKK |
415 | |
416 | /* MII or RMII */ | |
417 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 418 | rcntl |= (1 << 8); |
45993653 | 419 | else |
cd1f402c | 420 | rcntl &= ~(1 << 8); |
45993653 UKK |
421 | |
422 | /* 10M or 100M */ | |
423 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_100) | |
cd1f402c | 424 | rcntl &= ~(1 << 9); |
45993653 | 425 | else |
cd1f402c | 426 | rcntl |= (1 << 9); |
45993653 | 427 | |
45993653 UKK |
428 | } else { |
429 | #ifdef FEC_MIIGSK_ENR | |
430 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { | |
431 | /* disable the gasket and wait */ | |
432 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
433 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
434 | udelay(1); | |
435 | ||
436 | /* | |
437 | * configure the gasket: | |
438 | * RMII, 50 MHz, no loopback, no echo | |
439 | */ | |
440 | writel(1, fep->hwp + FEC_MIIGSK_CFGR); | |
441 | ||
442 | /* re-enable the gasket */ | |
443 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 444 | } |
45993653 UKK |
445 | #endif |
446 | } | |
cd1f402c | 447 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 448 | |
45993653 UKK |
449 | /* And last, enable the transmit and receive processing */ |
450 | writel(2, fep->hwp + FEC_ECNTRL); | |
451 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
452 | ||
453 | /* Enable interrupts we wish to service */ | |
454 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
455 | } | |
456 | ||
457 | static void | |
458 | fec_stop(struct net_device *ndev) | |
459 | { | |
460 | struct fec_enet_private *fep = netdev_priv(ndev); | |
461 | ||
462 | /* We cannot expect a graceful transmit stop without link !!! */ | |
463 | if (fep->link) { | |
464 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
465 | udelay(10); | |
466 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
467 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
468 | } | |
469 | ||
470 | /* Whack a reset. We should wait for this. */ | |
471 | writel(1, fep->hwp + FEC_ECNTRL); | |
472 | udelay(10); | |
473 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
474 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1da177e4 LT |
475 | } |
476 | ||
477 | ||
45993653 UKK |
478 | static void |
479 | fec_timeout(struct net_device *ndev) | |
480 | { | |
481 | struct fec_enet_private *fep = netdev_priv(ndev); | |
482 | ||
483 | ndev->stats.tx_errors++; | |
484 | ||
485 | fec_restart(ndev, fep->full_duplex); | |
486 | netif_wake_queue(ndev); | |
487 | } | |
488 | ||
1da177e4 | 489 | static void |
c556167f | 490 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
491 | { |
492 | struct fec_enet_private *fep; | |
2e28532f | 493 | struct bufdesc *bdp; |
0e702ab3 | 494 | unsigned short status; |
1da177e4 LT |
495 | struct sk_buff *skb; |
496 | ||
c556167f | 497 | fep = netdev_priv(ndev); |
81538e74 | 498 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
499 | bdp = fep->dirty_tx; |
500 | ||
0e702ab3 | 501 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
502 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
503 | break; | |
504 | ||
d1ab1f54 UKK |
505 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
506 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 507 | bdp->cbd_bufaddr = 0; |
1da177e4 LT |
508 | |
509 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
510 | /* Check for errors. */ | |
0e702ab3 | 511 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
512 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
513 | BD_ENET_TX_CSL)) { | |
c556167f | 514 | ndev->stats.tx_errors++; |
0e702ab3 | 515 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 516 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 517 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 518 | ndev->stats.tx_window_errors++; |
0e702ab3 | 519 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 520 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 521 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 522 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 523 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 524 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 525 | } else { |
c556167f | 526 | ndev->stats.tx_packets++; |
1da177e4 LT |
527 | } |
528 | ||
0e702ab3 | 529 | if (status & BD_ENET_TX_READY) |
1da177e4 | 530 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 531 | |
1da177e4 LT |
532 | /* Deferred means some collisions occurred during transmit, |
533 | * but we eventually sent the packet OK. | |
534 | */ | |
0e702ab3 | 535 | if (status & BD_ENET_TX_DEF) |
c556167f | 536 | ndev->stats.collisions++; |
6aa20a22 | 537 | |
22f6b860 | 538 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
539 | dev_kfree_skb_any(skb); |
540 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
541 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 542 | |
22f6b860 | 543 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 544 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
545 | bdp = fep->tx_bd_base; |
546 | else | |
547 | bdp++; | |
6aa20a22 | 548 | |
22f6b860 | 549 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
550 | */ |
551 | if (fep->tx_full) { | |
552 | fep->tx_full = 0; | |
c556167f UKK |
553 | if (netif_queue_stopped(ndev)) |
554 | netif_wake_queue(ndev); | |
1da177e4 LT |
555 | } |
556 | } | |
2e28532f | 557 | fep->dirty_tx = bdp; |
81538e74 | 558 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
559 | } |
560 | ||
561 | ||
562 | /* During a receive, the cur_rx points to the current incoming buffer. | |
563 | * When we update through the ring, if the next incoming buffer has | |
564 | * not been given to the system, we just set the empty indicator, | |
565 | * effectively tossing the packet. | |
566 | */ | |
567 | static void | |
c556167f | 568 | fec_enet_rx(struct net_device *ndev) |
1da177e4 | 569 | { |
c556167f | 570 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
571 | const struct platform_device_id *id_entry = |
572 | platform_get_device_id(fep->pdev); | |
2e28532f | 573 | struct bufdesc *bdp; |
0e702ab3 | 574 | unsigned short status; |
1da177e4 LT |
575 | struct sk_buff *skb; |
576 | ushort pkt_len; | |
577 | __u8 *data; | |
6aa20a22 | 578 | |
0e702ab3 GU |
579 | #ifdef CONFIG_M532x |
580 | flush_cache_all(); | |
6aa20a22 | 581 | #endif |
1da177e4 | 582 | |
81538e74 | 583 | spin_lock(&fep->hw_lock); |
3b2b74ca | 584 | |
1da177e4 LT |
585 | /* First, grab all of the stats for the incoming packet. |
586 | * These get messed up if we get called due to a busy condition. | |
587 | */ | |
588 | bdp = fep->cur_rx; | |
589 | ||
22f6b860 | 590 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 591 | |
22f6b860 SH |
592 | /* Since we have allocated space to hold a complete frame, |
593 | * the last indicator should be set. | |
594 | */ | |
595 | if ((status & BD_ENET_RX_LAST) == 0) | |
596 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 597 | |
22f6b860 SH |
598 | if (!fep->opened) |
599 | goto rx_processing_done; | |
1da177e4 | 600 | |
22f6b860 SH |
601 | /* Check for errors. */ |
602 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 603 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 604 | ndev->stats.rx_errors++; |
22f6b860 SH |
605 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
606 | /* Frame too long or too short. */ | |
c556167f | 607 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
608 | } |
609 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 610 | ndev->stats.rx_frame_errors++; |
22f6b860 | 611 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 612 | ndev->stats.rx_crc_errors++; |
22f6b860 | 613 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 614 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 615 | } |
1da177e4 | 616 | |
22f6b860 SH |
617 | /* Report late collisions as a frame error. |
618 | * On this error, the BD is closed, but we don't know what we | |
619 | * have in the buffer. So, just drop this frame on the floor. | |
620 | */ | |
621 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
622 | ndev->stats.rx_errors++; |
623 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
624 | goto rx_processing_done; |
625 | } | |
1da177e4 | 626 | |
22f6b860 | 627 | /* Process the incoming frame. */ |
c556167f | 628 | ndev->stats.rx_packets++; |
22f6b860 | 629 | pkt_len = bdp->cbd_datlen; |
c556167f | 630 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 631 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 632 | |
d1ab1f54 UKK |
633 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
634 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 635 | |
b5680e0b SG |
636 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
637 | swap_buffer(data, pkt_len); | |
638 | ||
22f6b860 SH |
639 | /* This does 16 byte alignment, exactly what we need. |
640 | * The packet length includes FCS, but we don't want to | |
641 | * include that when passing upstream as it messes up | |
642 | * bridging applications. | |
643 | */ | |
8549889c | 644 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 645 | |
8549889c | 646 | if (unlikely(!skb)) { |
22f6b860 | 647 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
648 | ndev->name); |
649 | ndev->stats.rx_dropped++; | |
22f6b860 | 650 | } else { |
8549889c | 651 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
652 | skb_put(skb, pkt_len - 4); /* Make room */ |
653 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 654 | skb->protocol = eth_type_trans(skb, ndev); |
18a03b97 RC |
655 | if (!skb_defer_rx_timestamp(skb)) |
656 | netif_rx(skb); | |
22f6b860 | 657 | } |
f0b3fbea | 658 | |
d1ab1f54 UKK |
659 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
660 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
661 | rx_processing_done: |
662 | /* Clear the status flags for this buffer */ | |
663 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 664 | |
22f6b860 SH |
665 | /* Mark the buffer empty */ |
666 | status |= BD_ENET_RX_EMPTY; | |
667 | bdp->cbd_sc = status; | |
6aa20a22 | 668 | |
22f6b860 SH |
669 | /* Update BD pointer to next entry */ |
670 | if (status & BD_ENET_RX_WRAP) | |
671 | bdp = fep->rx_bd_base; | |
672 | else | |
673 | bdp++; | |
674 | /* Doing this here will keep the FEC running while we process | |
675 | * incoming frames. On a heavily loaded network, we should be | |
676 | * able to keep up at the expense of system resources. | |
677 | */ | |
678 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
679 | } | |
2e28532f | 680 | fep->cur_rx = bdp; |
1da177e4 | 681 | |
81538e74 | 682 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
683 | } |
684 | ||
45993653 UKK |
685 | static irqreturn_t |
686 | fec_enet_interrupt(int irq, void *dev_id) | |
687 | { | |
688 | struct net_device *ndev = dev_id; | |
689 | struct fec_enet_private *fep = netdev_priv(ndev); | |
690 | uint int_events; | |
691 | irqreturn_t ret = IRQ_NONE; | |
692 | ||
693 | do { | |
694 | int_events = readl(fep->hwp + FEC_IEVENT); | |
695 | writel(int_events, fep->hwp + FEC_IEVENT); | |
696 | ||
697 | if (int_events & FEC_ENET_RXF) { | |
698 | ret = IRQ_HANDLED; | |
699 | fec_enet_rx(ndev); | |
700 | } | |
701 | ||
702 | /* Transmit OK, or non-fatal error. Update the buffer | |
703 | * descriptors. FEC handles all errors, we just discover | |
704 | * them as part of the transmit process. | |
705 | */ | |
706 | if (int_events & FEC_ENET_TXF) { | |
707 | ret = IRQ_HANDLED; | |
708 | fec_enet_tx(ndev); | |
709 | } | |
710 | ||
711 | if (int_events & FEC_ENET_MII) { | |
712 | ret = IRQ_HANDLED; | |
713 | complete(&fep->mdio_done); | |
714 | } | |
715 | } while (int_events); | |
716 | ||
717 | return ret; | |
718 | } | |
719 | ||
720 | ||
721 | ||
e6b043d5 | 722 | /* ------------------------------------------------------------------------- */ |
c556167f | 723 | static void __inline__ fec_get_mac(struct net_device *ndev) |
1da177e4 | 724 | { |
c556167f | 725 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 726 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 727 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 728 | |
49da97dc SG |
729 | /* |
730 | * try to get mac address in following order: | |
731 | * | |
732 | * 1) module parameter via kernel command line in form | |
733 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
734 | */ | |
735 | iap = macaddr; | |
736 | ||
737 | /* | |
738 | * 2) from flash or fuse (via platform data) | |
739 | */ | |
740 | if (!is_valid_ether_addr(iap)) { | |
741 | #ifdef CONFIG_M5272 | |
742 | if (FEC_FLASHMAC) | |
743 | iap = (unsigned char *)FEC_FLASHMAC; | |
744 | #else | |
745 | if (pdata) | |
746 | memcpy(iap, pdata->mac, ETH_ALEN); | |
747 | #endif | |
748 | } | |
749 | ||
750 | /* | |
751 | * 3) FEC mac registers set by bootloader | |
752 | */ | |
753 | if (!is_valid_ether_addr(iap)) { | |
754 | *((unsigned long *) &tmpaddr[0]) = | |
755 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
756 | *((unsigned short *) &tmpaddr[4]) = | |
757 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 758 | iap = &tmpaddr[0]; |
1da177e4 LT |
759 | } |
760 | ||
c556167f | 761 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 762 | |
49da97dc SG |
763 | /* Adjust MAC if using macaddr */ |
764 | if (iap == macaddr) | |
c556167f | 765 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id; |
1da177e4 LT |
766 | } |
767 | ||
e6b043d5 | 768 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 769 | |
e6b043d5 BW |
770 | /* |
771 | * Phy section | |
772 | */ | |
c556167f | 773 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 774 | { |
c556167f | 775 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
776 | struct phy_device *phy_dev = fep->phy_dev; |
777 | unsigned long flags; | |
1da177e4 | 778 | |
e6b043d5 | 779 | int status_change = 0; |
1da177e4 | 780 | |
e6b043d5 | 781 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 782 | |
e6b043d5 BW |
783 | /* Prevent a state halted on mii error */ |
784 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
785 | phy_dev->state = PHY_RESUMING; | |
786 | goto spin_unlock; | |
787 | } | |
1da177e4 | 788 | |
e6b043d5 BW |
789 | /* Duplex link change */ |
790 | if (phy_dev->link) { | |
791 | if (fep->full_duplex != phy_dev->duplex) { | |
c556167f | 792 | fec_restart(ndev, phy_dev->duplex); |
e6b043d5 BW |
793 | status_change = 1; |
794 | } | |
795 | } | |
1da177e4 | 796 | |
e6b043d5 BW |
797 | /* Link on or off change */ |
798 | if (phy_dev->link != fep->link) { | |
799 | fep->link = phy_dev->link; | |
800 | if (phy_dev->link) | |
c556167f | 801 | fec_restart(ndev, phy_dev->duplex); |
1da177e4 | 802 | else |
c556167f | 803 | fec_stop(ndev); |
e6b043d5 | 804 | status_change = 1; |
1da177e4 | 805 | } |
6aa20a22 | 806 | |
e6b043d5 BW |
807 | spin_unlock: |
808 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 809 | |
e6b043d5 BW |
810 | if (status_change) |
811 | phy_print_status(phy_dev); | |
812 | } | |
1da177e4 | 813 | |
e6b043d5 | 814 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 815 | { |
e6b043d5 | 816 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 817 | unsigned long time_left; |
1da177e4 | 818 | |
e6b043d5 | 819 | fep->mii_timeout = 0; |
97b72e43 | 820 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
821 | |
822 | /* start a read op */ | |
823 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
824 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
825 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
826 | ||
827 | /* wait for end of transfer */ | |
97b72e43 BS |
828 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
829 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
830 | if (time_left == 0) { | |
831 | fep->mii_timeout = 1; | |
832 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
833 | return -ETIMEDOUT; | |
1da177e4 | 834 | } |
1da177e4 | 835 | |
e6b043d5 BW |
836 | /* return value */ |
837 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 838 | } |
6aa20a22 | 839 | |
e6b043d5 BW |
840 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
841 | u16 value) | |
1da177e4 | 842 | { |
e6b043d5 | 843 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 844 | unsigned long time_left; |
1da177e4 | 845 | |
e6b043d5 | 846 | fep->mii_timeout = 0; |
97b72e43 | 847 | init_completion(&fep->mdio_done); |
1da177e4 | 848 | |
862f0982 SG |
849 | /* start a write op */ |
850 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
851 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
852 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
853 | fep->hwp + FEC_MII_DATA); | |
854 | ||
855 | /* wait for end of transfer */ | |
97b72e43 BS |
856 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
857 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
858 | if (time_left == 0) { | |
859 | fep->mii_timeout = 1; | |
860 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
861 | return -ETIMEDOUT; | |
e6b043d5 | 862 | } |
1da177e4 | 863 | |
e6b043d5 BW |
864 | return 0; |
865 | } | |
1da177e4 | 866 | |
e6b043d5 | 867 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 868 | { |
e6b043d5 | 869 | return 0; |
1da177e4 LT |
870 | } |
871 | ||
c556167f | 872 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 873 | { |
c556167f | 874 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 875 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
876 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
877 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
878 | int phy_id; | |
b5680e0b | 879 | int dev_id = fep->pdev->id; |
562d2f8c | 880 | |
418bd0d4 BW |
881 | fep->phy_dev = NULL; |
882 | ||
6fcc040f GU |
883 | /* check for attached phy */ |
884 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
885 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
886 | continue; | |
887 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
888 | continue; | |
889 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
890 | continue; | |
b5680e0b SG |
891 | if (dev_id--) |
892 | continue; | |
6fcc040f GU |
893 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
894 | break; | |
e6b043d5 | 895 | } |
1da177e4 | 896 | |
6fcc040f GU |
897 | if (phy_id >= PHY_MAX_ADDR) { |
898 | printk(KERN_INFO "%s: no PHY, assuming direct connection " | |
c556167f | 899 | "to switch\n", ndev->name); |
6fcc040f GU |
900 | strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); |
901 | phy_id = 0; | |
902 | } | |
903 | ||
904 | snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); | |
c556167f | 905 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0, |
6fcc040f GU |
906 | PHY_INTERFACE_MODE_MII); |
907 | if (IS_ERR(phy_dev)) { | |
c556167f | 908 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 909 | return PTR_ERR(phy_dev); |
e6b043d5 | 910 | } |
1da177e4 | 911 | |
e6b043d5 BW |
912 | /* mask with MAC supported features */ |
913 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
914 | phy_dev->advertising = phy_dev->supported; | |
1da177e4 | 915 | |
e6b043d5 BW |
916 | fep->phy_dev = phy_dev; |
917 | fep->link = 0; | |
918 | fep->full_duplex = 0; | |
1da177e4 | 919 | |
418bd0d4 | 920 | printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " |
c556167f | 921 | "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name, |
418bd0d4 BW |
922 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
923 | fep->phy_dev->irq); | |
924 | ||
e6b043d5 | 925 | return 0; |
1da177e4 LT |
926 | } |
927 | ||
e6b043d5 | 928 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 929 | { |
b5680e0b | 930 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
931 | struct net_device *ndev = platform_get_drvdata(pdev); |
932 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
933 | const struct platform_device_id *id_entry = |
934 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 935 | int err = -ENXIO, i; |
6b265293 | 936 | |
b5680e0b SG |
937 | /* |
938 | * The dual fec interfaces are not equivalent with enet-mac. | |
939 | * Here are the differences: | |
940 | * | |
941 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
942 | * - fec0 acts as the 1588 time master while fec1 is slave | |
943 | * - external phys can only be configured by fec0 | |
944 | * | |
945 | * That is to say fec1 can not work independently. It only works | |
946 | * when fec0 is working. The reason behind this design is that the | |
947 | * second interface is added primarily for Switch mode. | |
948 | * | |
949 | * Because of the last point above, both phys are attached on fec0 | |
950 | * mdio interface in board design, and need to be configured by | |
951 | * fec0 mii_bus. | |
952 | */ | |
953 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) { | |
954 | /* fec1 uses fec0 mii_bus */ | |
955 | fep->mii_bus = fec0_mii_bus; | |
956 | return 0; | |
957 | } | |
958 | ||
e6b043d5 | 959 | fep->mii_timeout = 0; |
1da177e4 | 960 | |
e6b043d5 BW |
961 | /* |
962 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
963 | */ | |
964 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; | |
965 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 | 966 | |
e6b043d5 BW |
967 | fep->mii_bus = mdiobus_alloc(); |
968 | if (fep->mii_bus == NULL) { | |
969 | err = -ENOMEM; | |
970 | goto err_out; | |
1da177e4 LT |
971 | } |
972 | ||
e6b043d5 BW |
973 | fep->mii_bus->name = "fec_enet_mii_bus"; |
974 | fep->mii_bus->read = fec_enet_mdio_read; | |
975 | fep->mii_bus->write = fec_enet_mdio_write; | |
976 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
6fcc040f | 977 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1); |
e6b043d5 BW |
978 | fep->mii_bus->priv = fep; |
979 | fep->mii_bus->parent = &pdev->dev; | |
980 | ||
981 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
982 | if (!fep->mii_bus->irq) { | |
983 | err = -ENOMEM; | |
984 | goto err_out_free_mdiobus; | |
1da177e4 LT |
985 | } |
986 | ||
e6b043d5 BW |
987 | for (i = 0; i < PHY_MAX_ADDR; i++) |
988 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 989 | |
e6b043d5 BW |
990 | if (mdiobus_register(fep->mii_bus)) |
991 | goto err_out_free_mdio_irq; | |
1da177e4 | 992 | |
b5680e0b SG |
993 | /* save fec0 mii_bus */ |
994 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
995 | fec0_mii_bus = fep->mii_bus; | |
996 | ||
e6b043d5 | 997 | return 0; |
1da177e4 | 998 | |
e6b043d5 BW |
999 | err_out_free_mdio_irq: |
1000 | kfree(fep->mii_bus->irq); | |
1001 | err_out_free_mdiobus: | |
1002 | mdiobus_free(fep->mii_bus); | |
1003 | err_out: | |
1004 | return err; | |
1da177e4 LT |
1005 | } |
1006 | ||
e6b043d5 | 1007 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1008 | { |
e6b043d5 BW |
1009 | if (fep->phy_dev) |
1010 | phy_disconnect(fep->phy_dev); | |
1011 | mdiobus_unregister(fep->mii_bus); | |
1012 | kfree(fep->mii_bus->irq); | |
1013 | mdiobus_free(fep->mii_bus); | |
1da177e4 LT |
1014 | } |
1015 | ||
c556167f | 1016 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1017 | struct ethtool_cmd *cmd) |
1da177e4 | 1018 | { |
c556167f | 1019 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1020 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1021 | |
e6b043d5 BW |
1022 | if (!phydev) |
1023 | return -ENODEV; | |
1da177e4 | 1024 | |
e6b043d5 | 1025 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1026 | } |
1027 | ||
c556167f | 1028 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1029 | struct ethtool_cmd *cmd) |
1da177e4 | 1030 | { |
c556167f | 1031 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1032 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1033 | |
e6b043d5 BW |
1034 | if (!phydev) |
1035 | return -ENODEV; | |
1da177e4 | 1036 | |
e6b043d5 | 1037 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1038 | } |
1039 | ||
c556167f | 1040 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1041 | struct ethtool_drvinfo *info) |
1da177e4 | 1042 | { |
c556167f | 1043 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1044 | |
e6b043d5 BW |
1045 | strcpy(info->driver, fep->pdev->dev.driver->name); |
1046 | strcpy(info->version, "Revision: 1.0"); | |
c556167f | 1047 | strcpy(info->bus_info, dev_name(&ndev->dev)); |
1da177e4 LT |
1048 | } |
1049 | ||
e6b043d5 BW |
1050 | static struct ethtool_ops fec_enet_ethtool_ops = { |
1051 | .get_settings = fec_enet_get_settings, | |
1052 | .set_settings = fec_enet_set_settings, | |
1053 | .get_drvinfo = fec_enet_get_drvinfo, | |
1054 | .get_link = ethtool_op_get_link, | |
1055 | }; | |
1da177e4 | 1056 | |
c556167f | 1057 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1058 | { |
c556167f | 1059 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1060 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1061 | |
c556167f | 1062 | if (!netif_running(ndev)) |
e6b043d5 | 1063 | return -EINVAL; |
1da177e4 | 1064 | |
e6b043d5 BW |
1065 | if (!phydev) |
1066 | return -ENODEV; | |
1067 | ||
28b04113 | 1068 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1069 | } |
1070 | ||
c556167f | 1071 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1072 | { |
c556167f | 1073 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1074 | int i; |
1075 | struct sk_buff *skb; | |
1076 | struct bufdesc *bdp; | |
1077 | ||
1078 | bdp = fep->rx_bd_base; | |
1079 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1080 | skb = fep->rx_skbuff[i]; | |
1081 | ||
1082 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1083 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1084 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1085 | if (skb) | |
1086 | dev_kfree_skb(skb); | |
1087 | bdp++; | |
1088 | } | |
1089 | ||
1090 | bdp = fep->tx_bd_base; | |
1091 | for (i = 0; i < TX_RING_SIZE; i++) | |
1092 | kfree(fep->tx_bounce[i]); | |
1093 | } | |
1094 | ||
c556167f | 1095 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1096 | { |
c556167f | 1097 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1098 | int i; |
1099 | struct sk_buff *skb; | |
1100 | struct bufdesc *bdp; | |
1101 | ||
1102 | bdp = fep->rx_bd_base; | |
1103 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1104 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); | |
1105 | if (!skb) { | |
c556167f | 1106 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1107 | return -ENOMEM; |
1108 | } | |
1109 | fep->rx_skbuff[i] = skb; | |
1110 | ||
d1ab1f54 | 1111 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1112 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1113 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
1114 | bdp++; | |
1115 | } | |
1116 | ||
1117 | /* Set the last buffer to wrap. */ | |
1118 | bdp--; | |
1119 | bdp->cbd_sc |= BD_SC_WRAP; | |
1120 | ||
1121 | bdp = fep->tx_bd_base; | |
1122 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1123 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1124 | ||
1125 | bdp->cbd_sc = 0; | |
1126 | bdp->cbd_bufaddr = 0; | |
1127 | bdp++; | |
1128 | } | |
1129 | ||
1130 | /* Set the last buffer to wrap. */ | |
1131 | bdp--; | |
1132 | bdp->cbd_sc |= BD_SC_WRAP; | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1da177e4 | 1137 | static int |
c556167f | 1138 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1139 | { |
c556167f | 1140 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1141 | int ret; |
1da177e4 LT |
1142 | |
1143 | /* I should reset the ring buffers here, but I don't yet know | |
1144 | * a simple way to do that. | |
1145 | */ | |
1da177e4 | 1146 | |
c556167f | 1147 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1148 | if (ret) |
1149 | return ret; | |
1150 | ||
418bd0d4 | 1151 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1152 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1153 | if (ret) { |
c556167f | 1154 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1155 | return ret; |
1156 | } | |
e6b043d5 | 1157 | phy_start(fep->phy_dev); |
c556167f | 1158 | netif_start_queue(ndev); |
1da177e4 | 1159 | fep->opened = 1; |
22f6b860 | 1160 | return 0; |
1da177e4 LT |
1161 | } |
1162 | ||
1163 | static int | |
c556167f | 1164 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1165 | { |
c556167f | 1166 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1167 | |
22f6b860 | 1168 | /* Don't know what to do yet. */ |
1da177e4 | 1169 | fep->opened = 0; |
c556167f UKK |
1170 | netif_stop_queue(ndev); |
1171 | fec_stop(ndev); | |
1da177e4 | 1172 | |
e497ba82 UKK |
1173 | if (fep->phy_dev) { |
1174 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1175 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1176 | } |
418bd0d4 | 1177 | |
db8880bc | 1178 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1179 | |
1da177e4 LT |
1180 | return 0; |
1181 | } | |
1182 | ||
1da177e4 LT |
1183 | /* Set or clear the multicast filter for this adaptor. |
1184 | * Skeleton taken from sunlance driver. | |
1185 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1186 | * MAC address filtering. Some of the drivers check to make sure it is | |
1187 | * a group multicast address, and discard those that are not. I guess I | |
1188 | * will do the same for now, but just remove the test if you want | |
1189 | * individual filtering as well (do the upper net layers want or support | |
1190 | * this kind of feature?). | |
1191 | */ | |
1192 | ||
1193 | #define HASH_BITS 6 /* #bits in hash */ | |
1194 | #define CRC32_POLY 0xEDB88320 | |
1195 | ||
c556167f | 1196 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1197 | { |
c556167f | 1198 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1199 | struct netdev_hw_addr *ha; |
48e2f183 | 1200 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1201 | unsigned char hash; |
1202 | ||
c556167f | 1203 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1204 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1205 | tmp |= 0x8; | |
1206 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1207 | return; |
1208 | } | |
1da177e4 | 1209 | |
4e831836 SH |
1210 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1211 | tmp &= ~0x8; | |
1212 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1213 | ||
c556167f | 1214 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1215 | /* Catch all multicast addresses, so set the |
1216 | * filter to all 1's | |
1217 | */ | |
1218 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1219 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1220 | ||
1221 | return; | |
1222 | } | |
1223 | ||
1224 | /* Clear filter and add the addresses in hash register | |
1225 | */ | |
1226 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1227 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1228 | ||
c556167f | 1229 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1230 | /* calculate crc32 value of mac address */ |
1231 | crc = 0xffffffff; | |
1232 | ||
c556167f | 1233 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1234 | data = ha->addr[i]; |
4e831836 SH |
1235 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1236 | crc = (crc >> 1) ^ | |
1237 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1238 | } |
1239 | } | |
4e831836 SH |
1240 | |
1241 | /* only upper 6 bits (HASH_BITS) are used | |
1242 | * which point to specific bit in he hash registers | |
1243 | */ | |
1244 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1245 | ||
1246 | if (hash > 31) { | |
1247 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1248 | tmp |= 1 << (hash - 32); | |
1249 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1250 | } else { | |
1251 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1252 | tmp |= 1 << hash; | |
1253 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1254 | } | |
1da177e4 LT |
1255 | } |
1256 | } | |
1257 | ||
22f6b860 | 1258 | /* Set a MAC change in hardware. */ |
009fda83 | 1259 | static int |
c556167f | 1260 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1261 | { |
c556167f | 1262 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1263 | struct sockaddr *addr = p; |
1264 | ||
1265 | if (!is_valid_ether_addr(addr->sa_data)) | |
1266 | return -EADDRNOTAVAIL; | |
1267 | ||
c556167f | 1268 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1269 | |
c556167f UKK |
1270 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1271 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1272 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1273 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1274 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1275 | return 0; |
1da177e4 LT |
1276 | } |
1277 | ||
009fda83 SH |
1278 | static const struct net_device_ops fec_netdev_ops = { |
1279 | .ndo_open = fec_enet_open, | |
1280 | .ndo_stop = fec_enet_close, | |
1281 | .ndo_start_xmit = fec_enet_start_xmit, | |
1282 | .ndo_set_multicast_list = set_multicast_list, | |
635ecaa7 | 1283 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1284 | .ndo_validate_addr = eth_validate_addr, |
1285 | .ndo_tx_timeout = fec_timeout, | |
1286 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1287 | .ndo_do_ioctl = fec_enet_ioctl, |
009fda83 SH |
1288 | }; |
1289 | ||
1da177e4 LT |
1290 | /* |
1291 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1292 | * |
1da177e4 | 1293 | */ |
c556167f | 1294 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1295 | { |
c556167f | 1296 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1297 | struct bufdesc *cbd_base; |
633e7533 | 1298 | struct bufdesc *bdp; |
f0b3fbea | 1299 | int i; |
1da177e4 | 1300 | |
8d4dd5cf SH |
1301 | /* Allocate memory for buffer descriptors. */ |
1302 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1303 | GFP_KERNEL); | |
1304 | if (!cbd_base) { | |
562d2f8c GU |
1305 | printk("FEC: allocate descriptor memory failed?\n"); |
1306 | return -ENOMEM; | |
1307 | } | |
1308 | ||
3b2b74ca | 1309 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1310 | |
c556167f | 1311 | fep->netdev = ndev; |
1da177e4 | 1312 | |
49da97dc | 1313 | /* Get the Ethernet address */ |
c556167f | 1314 | fec_get_mac(ndev); |
1da177e4 | 1315 | |
8d4dd5cf | 1316 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1317 | fep->rx_bd_base = cbd_base; |
1318 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1319 | ||
22f6b860 | 1320 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1321 | ndev->watchdog_timeo = TX_TIMEOUT; |
1322 | ndev->netdev_ops = &fec_netdev_ops; | |
1323 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 RH |
1324 | |
1325 | /* Initialize the receive buffer descriptors. */ | |
1326 | bdp = fep->rx_bd_base; | |
1327 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1328 | ||
1329 | /* Initialize the BD for every fragment in the page. */ | |
1330 | bdp->cbd_sc = 0; | |
1331 | bdp++; | |
1332 | } | |
1333 | ||
1334 | /* Set the last buffer to wrap */ | |
1335 | bdp--; | |
1336 | bdp->cbd_sc |= BD_SC_WRAP; | |
1337 | ||
1338 | /* ...and the same for transmit */ | |
1339 | bdp = fep->tx_bd_base; | |
1340 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1341 | ||
1342 | /* Initialize the BD for every fragment in the page. */ | |
1343 | bdp->cbd_sc = 0; | |
1344 | bdp->cbd_bufaddr = 0; | |
1345 | bdp++; | |
1346 | } | |
1347 | ||
1348 | /* Set the last buffer to wrap */ | |
1349 | bdp--; | |
1350 | bdp->cbd_sc |= BD_SC_WRAP; | |
1351 | ||
c556167f | 1352 | fec_restart(ndev, 0); |
1da177e4 | 1353 | |
1da177e4 LT |
1354 | return 0; |
1355 | } | |
1356 | ||
ead73183 SH |
1357 | static int __devinit |
1358 | fec_probe(struct platform_device *pdev) | |
1359 | { | |
1360 | struct fec_enet_private *fep; | |
5eb32bd0 | 1361 | struct fec_platform_data *pdata; |
ead73183 SH |
1362 | struct net_device *ndev; |
1363 | int i, irq, ret = 0; | |
1364 | struct resource *r; | |
1365 | ||
1366 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1367 | if (!r) | |
1368 | return -ENXIO; | |
1369 | ||
1370 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1371 | if (!r) | |
1372 | return -EBUSY; | |
1373 | ||
1374 | /* Init network device */ | |
1375 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1376 | if (!ndev) { |
1377 | ret = -ENOMEM; | |
1378 | goto failed_alloc_etherdev; | |
1379 | } | |
ead73183 SH |
1380 | |
1381 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1382 | ||
1383 | /* setup board info structure */ | |
1384 | fep = netdev_priv(ndev); | |
ead73183 | 1385 | |
24e531b4 | 1386 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1387 | fep->pdev = pdev; |
ead73183 | 1388 | |
24e531b4 | 1389 | if (!fep->hwp) { |
ead73183 SH |
1390 | ret = -ENOMEM; |
1391 | goto failed_ioremap; | |
1392 | } | |
1393 | ||
1394 | platform_set_drvdata(pdev, ndev); | |
1395 | ||
5eb32bd0 BS |
1396 | pdata = pdev->dev.platform_data; |
1397 | if (pdata) | |
1398 | fep->phy_interface = pdata->phy; | |
1399 | ||
ead73183 SH |
1400 | /* This device has up to three irqs on some platforms */ |
1401 | for (i = 0; i < 3; i++) { | |
1402 | irq = platform_get_irq(pdev, i); | |
1403 | if (i && irq < 0) | |
1404 | break; | |
1405 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1406 | if (ret) { | |
b2b09ad6 | 1407 | while (--i >= 0) { |
ead73183 SH |
1408 | irq = platform_get_irq(pdev, i); |
1409 | free_irq(irq, ndev); | |
ead73183 SH |
1410 | } |
1411 | goto failed_irq; | |
1412 | } | |
1413 | } | |
1414 | ||
1415 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1416 | if (IS_ERR(fep->clk)) { | |
1417 | ret = PTR_ERR(fep->clk); | |
1418 | goto failed_clk; | |
1419 | } | |
1420 | clk_enable(fep->clk); | |
1421 | ||
8649a230 | 1422 | ret = fec_enet_init(ndev); |
ead73183 SH |
1423 | if (ret) |
1424 | goto failed_init; | |
1425 | ||
e6b043d5 BW |
1426 | ret = fec_enet_mii_init(pdev); |
1427 | if (ret) | |
1428 | goto failed_mii_init; | |
1429 | ||
03c698c9 OS |
1430 | /* Carrier starts down, phylib will bring it up */ |
1431 | netif_carrier_off(ndev); | |
1432 | ||
ead73183 SH |
1433 | ret = register_netdev(ndev); |
1434 | if (ret) | |
1435 | goto failed_register; | |
1436 | ||
1437 | return 0; | |
1438 | ||
1439 | failed_register: | |
e6b043d5 BW |
1440 | fec_enet_mii_remove(fep); |
1441 | failed_mii_init: | |
ead73183 SH |
1442 | failed_init: |
1443 | clk_disable(fep->clk); | |
1444 | clk_put(fep->clk); | |
1445 | failed_clk: | |
1446 | for (i = 0; i < 3; i++) { | |
1447 | irq = platform_get_irq(pdev, i); | |
1448 | if (irq > 0) | |
1449 | free_irq(irq, ndev); | |
1450 | } | |
1451 | failed_irq: | |
24e531b4 | 1452 | iounmap(fep->hwp); |
ead73183 SH |
1453 | failed_ioremap: |
1454 | free_netdev(ndev); | |
28e2188e UKK |
1455 | failed_alloc_etherdev: |
1456 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1457 | |
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | static int __devexit | |
1462 | fec_drv_remove(struct platform_device *pdev) | |
1463 | { | |
1464 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1465 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1466 | struct resource *r; |
ead73183 | 1467 | |
ead73183 | 1468 | fec_stop(ndev); |
e6b043d5 | 1469 | fec_enet_mii_remove(fep); |
ead73183 SH |
1470 | clk_disable(fep->clk); |
1471 | clk_put(fep->clk); | |
24e531b4 | 1472 | iounmap(fep->hwp); |
ead73183 SH |
1473 | unregister_netdev(ndev); |
1474 | free_netdev(ndev); | |
28e2188e UKK |
1475 | |
1476 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1477 | BUG_ON(!r); | |
1478 | release_mem_region(r->start, resource_size(r)); | |
1479 | ||
b3cde36c UKK |
1480 | platform_set_drvdata(pdev, NULL); |
1481 | ||
ead73183 SH |
1482 | return 0; |
1483 | } | |
1484 | ||
59d4289b | 1485 | #ifdef CONFIG_PM |
ead73183 | 1486 | static int |
87cad5c3 | 1487 | fec_suspend(struct device *dev) |
ead73183 | 1488 | { |
87cad5c3 | 1489 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1490 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1491 | |
04e5216d UKK |
1492 | if (netif_running(ndev)) { |
1493 | fec_stop(ndev); | |
1494 | netif_device_detach(ndev); | |
ead73183 | 1495 | } |
04e5216d UKK |
1496 | clk_disable(fep->clk); |
1497 | ||
ead73183 SH |
1498 | return 0; |
1499 | } | |
1500 | ||
1501 | static int | |
87cad5c3 | 1502 | fec_resume(struct device *dev) |
ead73183 | 1503 | { |
87cad5c3 | 1504 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1505 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1506 | |
04e5216d UKK |
1507 | clk_enable(fep->clk); |
1508 | if (netif_running(ndev)) { | |
1509 | fec_restart(ndev, fep->full_duplex); | |
1510 | netif_device_attach(ndev); | |
ead73183 | 1511 | } |
04e5216d | 1512 | |
ead73183 SH |
1513 | return 0; |
1514 | } | |
1515 | ||
59d4289b DK |
1516 | static const struct dev_pm_ops fec_pm_ops = { |
1517 | .suspend = fec_suspend, | |
1518 | .resume = fec_resume, | |
1519 | .freeze = fec_suspend, | |
1520 | .thaw = fec_resume, | |
1521 | .poweroff = fec_suspend, | |
1522 | .restore = fec_resume, | |
1523 | }; | |
87cad5c3 | 1524 | #endif |
59d4289b | 1525 | |
ead73183 SH |
1526 | static struct platform_driver fec_driver = { |
1527 | .driver = { | |
b5680e0b | 1528 | .name = DRIVER_NAME, |
87cad5c3 EB |
1529 | .owner = THIS_MODULE, |
1530 | #ifdef CONFIG_PM | |
1531 | .pm = &fec_pm_ops, | |
1532 | #endif | |
ead73183 | 1533 | }, |
b5680e0b | 1534 | .id_table = fec_devtype, |
87cad5c3 EB |
1535 | .probe = fec_probe, |
1536 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1537 | }; |
1538 | ||
1539 | static int __init | |
1540 | fec_enet_module_init(void) | |
1541 | { | |
1542 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1543 | ||
1544 | return platform_driver_register(&fec_driver); | |
1545 | } | |
1546 | ||
1547 | static void __exit | |
1548 | fec_enet_cleanup(void) | |
1549 | { | |
1550 | platform_driver_unregister(&fec_driver); | |
1551 | } | |
1552 | ||
1553 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1554 | module_init(fec_enet_module_init); |
1555 | ||
1556 | MODULE_LICENSE("GPL"); |