Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
5 | * This version of the driver is specific to the FADS implementation, | |
6 | * since the board contains control registers external to the processor | |
7 | * for the control of the LevelOne LXT970 transceiver. The MPC860T manual | |
8 | * describes connections using the internal parallel port I/O, which | |
9 | * is basically all of Port D. | |
10 | * | |
7dd6a2aa | 11 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
12 | * pages and then divide them into 2K frame buffers. This way I know I |
13 | * have buffers large enough to hold one frame within one buffer descriptor. | |
14 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
15 | * will be much more memory efficient and will easily handle lots of | |
16 | * small packets. | |
17 | * | |
18 | * Much better multiple PHY support by Magnus Damm. | |
19 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
20 | * | |
562d2f8c GU |
21 | * Support for FEC controller of ColdFire processors. |
22 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
23 | * |
24 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 25 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
26 | */ |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/kernel.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/ptrace.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/workqueue.h> | |
44 | #include <linux/bitops.h> | |
45 | ||
46 | #include <asm/irq.h> | |
47 | #include <asm/uaccess.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/pgtable.h> | |
080853af | 50 | #include <asm/cacheflush.h> |
1da177e4 | 51 | |
7dd6a2aa | 52 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ |
562d2f8c | 53 | defined(CONFIG_M5272) || defined(CONFIG_M528x) || \ |
6b265293 | 54 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
1da177e4 LT |
55 | #include <asm/coldfire.h> |
56 | #include <asm/mcfsim.h> | |
57 | #include "fec.h" | |
58 | #else | |
59 | #include <asm/8xx_immap.h> | |
60 | #include <asm/mpc8xx.h> | |
61 | #include "commproc.h" | |
62 | #endif | |
63 | ||
64 | #if defined(CONFIG_FEC2) | |
65 | #define FEC_MAX_PORTS 2 | |
66 | #else | |
67 | #define FEC_MAX_PORTS 1 | |
68 | #endif | |
69 | ||
c1d96156 SS |
70 | #if defined(CONFIG_FADS) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_M5272) |
71 | #define HAVE_mii_link_interrupt | |
72 | #endif | |
73 | ||
1da177e4 LT |
74 | /* |
75 | * Define the fixed address of the FEC hardware. | |
76 | */ | |
77 | static unsigned int fec_hw[] = { | |
78 | #if defined(CONFIG_M5272) | |
79 | (MCF_MBAR + 0x840), | |
80 | #elif defined(CONFIG_M527x) | |
81 | (MCF_MBAR + 0x1000), | |
82 | (MCF_MBAR + 0x1800), | |
7dd6a2aa | 83 | #elif defined(CONFIG_M523x) || defined(CONFIG_M528x) |
1da177e4 | 84 | (MCF_MBAR + 0x1000), |
562d2f8c GU |
85 | #elif defined(CONFIG_M520x) |
86 | (MCF_MBAR+0x30000), | |
6b265293 MW |
87 | #elif defined(CONFIG_M532x) |
88 | (MCF_MBAR+0xfc030000), | |
1da177e4 LT |
89 | #else |
90 | &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec), | |
91 | #endif | |
92 | }; | |
93 | ||
94 | static unsigned char fec_mac_default[] = { | |
95 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
96 | }; | |
97 | ||
98 | /* | |
99 | * Some hardware gets it MAC address out of local flash memory. | |
100 | * if this is non-zero then assume it is the address to get MAC from. | |
101 | */ | |
102 | #if defined(CONFIG_NETtel) | |
103 | #define FEC_FLASHMAC 0xf0006006 | |
104 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
105 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
106 | #elif defined(CONFIG_CANCam) |
107 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
108 | #elif defined (CONFIG_M5272C3) |
109 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
110 | #elif defined(CONFIG_MOD5272) | |
111 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
112 | #else |
113 | #define FEC_FLASHMAC 0 | |
114 | #endif | |
115 | ||
1da177e4 LT |
116 | /* Forward declarations of some structures to support different PHYs |
117 | */ | |
118 | ||
119 | typedef struct { | |
120 | uint mii_data; | |
121 | void (*funct)(uint mii_reg, struct net_device *dev); | |
122 | } phy_cmd_t; | |
123 | ||
124 | typedef struct { | |
125 | uint id; | |
126 | char *name; | |
127 | ||
128 | const phy_cmd_t *config; | |
129 | const phy_cmd_t *startup; | |
130 | const phy_cmd_t *ack_int; | |
131 | const phy_cmd_t *shutdown; | |
132 | } phy_info_t; | |
133 | ||
134 | /* The number of Tx and Rx buffers. These are allocated from the page | |
135 | * pool. The code may assume these are power of two, so it it best | |
136 | * to keep them that size. | |
137 | * We don't need to allocate pages for the transmitter. We just use | |
138 | * the skbuffer directly. | |
139 | */ | |
140 | #define FEC_ENET_RX_PAGES 8 | |
141 | #define FEC_ENET_RX_FRSIZE 2048 | |
142 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
143 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
144 | #define FEC_ENET_TX_FRSIZE 2048 | |
145 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
146 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
147 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
148 | ||
562d2f8c | 149 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 150 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
151 | #endif |
152 | ||
1da177e4 LT |
153 | /* Interrupt events/masks. |
154 | */ | |
155 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ | |
156 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
157 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
158 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
159 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
160 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
161 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
162 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
163 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
164 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
165 | ||
166 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
167 | */ | |
168 | #define PKT_MAXBUF_SIZE 1518 | |
169 | #define PKT_MINBUF_SIZE 64 | |
170 | #define PKT_MAXBLR_SIZE 1520 | |
171 | ||
172 | ||
173 | /* | |
6b265293 | 174 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
175 | * size bits. Other FEC hardware does not, so we need to take that into |
176 | * account when setting it. | |
177 | */ | |
562d2f8c | 178 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
6b265293 | 179 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
1da177e4 LT |
180 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
181 | #else | |
182 | #define OPT_FRAME_SIZE 0 | |
183 | #endif | |
184 | ||
185 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
186 | * tx_bd_base always point to the base of the buffer descriptors. The | |
187 | * cur_rx and cur_tx point to the currently available buffer. | |
188 | * The dirty_tx tracks the current buffer that is being sent by the | |
189 | * controller. The cur_tx and dirty_tx are equal under both completely | |
190 | * empty and completely full conditions. The empty/ready indicator in | |
191 | * the buffer descriptor determines the actual condition. | |
192 | */ | |
193 | struct fec_enet_private { | |
194 | /* Hardware registers of the FEC device */ | |
195 | volatile fec_t *hwp; | |
196 | ||
cb84d6e7 GU |
197 | struct net_device *netdev; |
198 | ||
1da177e4 LT |
199 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
200 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
201 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
202 | ushort skb_cur; | |
203 | ushort skb_dirty; | |
204 | ||
205 | /* CPM dual port RAM relative addresses. | |
206 | */ | |
207 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ | |
208 | cbd_t *tx_bd_base; | |
209 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ | |
210 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ | |
1da177e4 LT |
211 | uint tx_full; |
212 | spinlock_t lock; | |
213 | ||
214 | uint phy_id; | |
215 | uint phy_id_done; | |
216 | uint phy_status; | |
217 | uint phy_speed; | |
7dd6a2aa | 218 | phy_info_t const *phy; |
1da177e4 LT |
219 | struct work_struct phy_task; |
220 | ||
221 | uint sequence_done; | |
222 | uint mii_phy_task_queued; | |
223 | ||
224 | uint phy_addr; | |
225 | ||
226 | int index; | |
227 | int opened; | |
228 | int link; | |
229 | int old_link; | |
230 | int full_duplex; | |
1da177e4 LT |
231 | }; |
232 | ||
233 | static int fec_enet_open(struct net_device *dev); | |
234 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
235 | static void fec_enet_mii(struct net_device *dev); | |
7d12e780 | 236 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
237 | static void fec_enet_tx(struct net_device *dev); |
238 | static void fec_enet_rx(struct net_device *dev); | |
239 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
240 | static void set_multicast_list(struct net_device *dev); |
241 | static void fec_restart(struct net_device *dev, int duplex); | |
242 | static void fec_stop(struct net_device *dev); | |
243 | static void fec_set_mac_address(struct net_device *dev); | |
244 | ||
245 | ||
246 | /* MII processing. We keep this as simple as possible. Requests are | |
247 | * placed on the list (if there is room). When the request is finished | |
248 | * by the MII, an optional function may be called. | |
249 | */ | |
250 | typedef struct mii_list { | |
251 | uint mii_regval; | |
252 | void (*mii_func)(uint val, struct net_device *dev); | |
253 | struct mii_list *mii_next; | |
254 | } mii_list_t; | |
255 | ||
256 | #define NMII 20 | |
7dd6a2aa GU |
257 | static mii_list_t mii_cmds[NMII]; |
258 | static mii_list_t *mii_free; | |
259 | static mii_list_t *mii_head; | |
260 | static mii_list_t *mii_tail; | |
1da177e4 | 261 | |
6aa20a22 | 262 | static int mii_queue(struct net_device *dev, int request, |
1da177e4 LT |
263 | void (*func)(uint, struct net_device *)); |
264 | ||
265 | /* Make MII read/write commands for the FEC. | |
266 | */ | |
267 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
268 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | |
269 | (VAL & 0xffff)) | |
270 | #define mk_mii_end 0 | |
271 | ||
272 | /* Transmitter timeout. | |
273 | */ | |
274 | #define TX_TIMEOUT (2*HZ) | |
275 | ||
276 | /* Register definitions for the PHY. | |
277 | */ | |
278 | ||
279 | #define MII_REG_CR 0 /* Control Register */ | |
280 | #define MII_REG_SR 1 /* Status Register */ | |
281 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | |
282 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | |
6aa20a22 | 283 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
1da177e4 LT |
284 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
285 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | |
286 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | |
287 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | |
288 | ||
289 | /* values for phy_status */ | |
290 | ||
291 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | |
292 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | |
293 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | |
294 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | |
6aa20a22 | 295 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
1da177e4 | 296 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
6aa20a22 | 297 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
1da177e4 LT |
298 | |
299 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | |
300 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | |
301 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | |
302 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | |
303 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | |
6aa20a22 | 304 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
1da177e4 | 305 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
6aa20a22 | 306 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
1da177e4 LT |
307 | |
308 | ||
309 | static int | |
310 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
311 | { | |
312 | struct fec_enet_private *fep; | |
313 | volatile fec_t *fecp; | |
314 | volatile cbd_t *bdp; | |
0e702ab3 | 315 | unsigned short status; |
1da177e4 LT |
316 | |
317 | fep = netdev_priv(dev); | |
318 | fecp = (volatile fec_t*)dev->base_addr; | |
319 | ||
320 | if (!fep->link) { | |
321 | /* Link is down or autonegotiation is in progress. */ | |
322 | return 1; | |
323 | } | |
324 | ||
325 | /* Fill in a Tx ring entry */ | |
326 | bdp = fep->cur_tx; | |
327 | ||
0e702ab3 | 328 | status = bdp->cbd_sc; |
1da177e4 | 329 | #ifndef final_version |
0e702ab3 | 330 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
331 | /* Ooops. All transmit buffers are full. Bail out. |
332 | * This should not happen, since dev->tbusy should be set. | |
333 | */ | |
334 | printk("%s: tx queue full!.\n", dev->name); | |
335 | return 1; | |
336 | } | |
337 | #endif | |
338 | ||
339 | /* Clear all of the status flags. | |
340 | */ | |
0e702ab3 | 341 | status &= ~BD_ENET_TX_STATS; |
1da177e4 LT |
342 | |
343 | /* Set buffer length and buffer pointer. | |
344 | */ | |
345 | bdp->cbd_bufaddr = __pa(skb->data); | |
346 | bdp->cbd_datlen = skb->len; | |
347 | ||
348 | /* | |
349 | * On some FEC implementations data must be aligned on | |
350 | * 4-byte boundaries. Use bounce buffers to copy data | |
351 | * and get it aligned. Ugh. | |
352 | */ | |
353 | if (bdp->cbd_bufaddr & 0x3) { | |
354 | unsigned int index; | |
355 | index = bdp - fep->tx_bd_base; | |
356 | memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen); | |
357 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); | |
358 | } | |
359 | ||
360 | /* Save skb pointer. | |
361 | */ | |
362 | fep->tx_skbuff[fep->skb_cur] = skb; | |
363 | ||
09f75cd7 | 364 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 365 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 366 | |
1da177e4 LT |
367 | /* Push the data cache so the CPM does not get stale memory |
368 | * data. | |
369 | */ | |
370 | flush_dcache_range((unsigned long)skb->data, | |
371 | (unsigned long)skb->data + skb->len); | |
372 | ||
373 | spin_lock_irq(&fep->lock); | |
374 | ||
0e702ab3 GU |
375 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
376 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 LT |
377 | */ |
378 | ||
0e702ab3 | 379 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 380 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 381 | bdp->cbd_sc = status; |
1da177e4 LT |
382 | |
383 | dev->trans_start = jiffies; | |
384 | ||
385 | /* Trigger transmission start */ | |
0e702ab3 | 386 | fecp->fec_x_des_active = 0; |
1da177e4 LT |
387 | |
388 | /* If this was the last BD in the ring, start at the beginning again. | |
389 | */ | |
0e702ab3 | 390 | if (status & BD_ENET_TX_WRAP) { |
1da177e4 LT |
391 | bdp = fep->tx_bd_base; |
392 | } else { | |
393 | bdp++; | |
394 | } | |
395 | ||
396 | if (bdp == fep->dirty_tx) { | |
397 | fep->tx_full = 1; | |
398 | netif_stop_queue(dev); | |
399 | } | |
400 | ||
401 | fep->cur_tx = (cbd_t *)bdp; | |
402 | ||
403 | spin_unlock_irq(&fep->lock); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static void | |
409 | fec_timeout(struct net_device *dev) | |
410 | { | |
411 | struct fec_enet_private *fep = netdev_priv(dev); | |
412 | ||
413 | printk("%s: transmit timed out.\n", dev->name); | |
09f75cd7 | 414 | dev->stats.tx_errors++; |
1da177e4 LT |
415 | #ifndef final_version |
416 | { | |
417 | int i; | |
418 | cbd_t *bdp; | |
419 | ||
420 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | |
421 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | |
422 | (unsigned long)fep->dirty_tx, | |
423 | (unsigned long)fep->cur_rx); | |
424 | ||
425 | bdp = fep->tx_bd_base; | |
426 | printk(" tx: %u buffers\n", TX_RING_SIZE); | |
427 | for (i = 0 ; i < TX_RING_SIZE; i++) { | |
6aa20a22 | 428 | printk(" %08x: %04x %04x %08x\n", |
1da177e4 LT |
429 | (uint) bdp, |
430 | bdp->cbd_sc, | |
431 | bdp->cbd_datlen, | |
432 | (int) bdp->cbd_bufaddr); | |
433 | bdp++; | |
434 | } | |
435 | ||
436 | bdp = fep->rx_bd_base; | |
437 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); | |
438 | for (i = 0 ; i < RX_RING_SIZE; i++) { | |
439 | printk(" %08x: %04x %04x %08x\n", | |
440 | (uint) bdp, | |
441 | bdp->cbd_sc, | |
442 | bdp->cbd_datlen, | |
443 | (int) bdp->cbd_bufaddr); | |
444 | bdp++; | |
445 | } | |
446 | } | |
447 | #endif | |
7dd6a2aa | 448 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
449 | netif_wake_queue(dev); |
450 | } | |
451 | ||
452 | /* The interrupt handler. | |
453 | * This is called from the MPC core interrupt. | |
454 | */ | |
455 | static irqreturn_t | |
7d12e780 | 456 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
457 | { |
458 | struct net_device *dev = dev_id; | |
459 | volatile fec_t *fecp; | |
460 | uint int_events; | |
461 | int handled = 0; | |
462 | ||
463 | fecp = (volatile fec_t*)dev->base_addr; | |
464 | ||
465 | /* Get the interrupt events that caused us to be here. | |
466 | */ | |
467 | while ((int_events = fecp->fec_ievent) != 0) { | |
468 | fecp->fec_ievent = int_events; | |
469 | ||
470 | /* Handle receive event in its own function. | |
471 | */ | |
472 | if (int_events & FEC_ENET_RXF) { | |
473 | handled = 1; | |
474 | fec_enet_rx(dev); | |
475 | } | |
476 | ||
477 | /* Transmit OK, or non-fatal error. Update the buffer | |
478 | descriptors. FEC handles all errors, we just discover | |
479 | them as part of the transmit process. | |
480 | */ | |
481 | if (int_events & FEC_ENET_TXF) { | |
482 | handled = 1; | |
483 | fec_enet_tx(dev); | |
484 | } | |
485 | ||
486 | if (int_events & FEC_ENET_MII) { | |
487 | handled = 1; | |
488 | fec_enet_mii(dev); | |
489 | } | |
6aa20a22 | 490 | |
1da177e4 LT |
491 | } |
492 | return IRQ_RETVAL(handled); | |
493 | } | |
494 | ||
495 | ||
496 | static void | |
497 | fec_enet_tx(struct net_device *dev) | |
498 | { | |
499 | struct fec_enet_private *fep; | |
500 | volatile cbd_t *bdp; | |
0e702ab3 | 501 | unsigned short status; |
1da177e4 LT |
502 | struct sk_buff *skb; |
503 | ||
504 | fep = netdev_priv(dev); | |
505 | spin_lock(&fep->lock); | |
506 | bdp = fep->dirty_tx; | |
507 | ||
0e702ab3 | 508 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
1da177e4 LT |
509 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
510 | ||
511 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
512 | /* Check for errors. */ | |
0e702ab3 | 513 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
514 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
515 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 516 | dev->stats.tx_errors++; |
0e702ab3 | 517 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 518 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 519 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 520 | dev->stats.tx_window_errors++; |
0e702ab3 | 521 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 522 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 523 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 524 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 525 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 526 | dev->stats.tx_carrier_errors++; |
1da177e4 | 527 | } else { |
09f75cd7 | 528 | dev->stats.tx_packets++; |
1da177e4 LT |
529 | } |
530 | ||
531 | #ifndef final_version | |
0e702ab3 | 532 | if (status & BD_ENET_TX_READY) |
1da177e4 LT |
533 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
534 | #endif | |
535 | /* Deferred means some collisions occurred during transmit, | |
536 | * but we eventually sent the packet OK. | |
537 | */ | |
0e702ab3 | 538 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 539 | dev->stats.collisions++; |
6aa20a22 | 540 | |
1da177e4 LT |
541 | /* Free the sk buffer associated with this last transmit. |
542 | */ | |
543 | dev_kfree_skb_any(skb); | |
544 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
545 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 546 | |
1da177e4 LT |
547 | /* Update pointer to next buffer descriptor to be transmitted. |
548 | */ | |
0e702ab3 | 549 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
550 | bdp = fep->tx_bd_base; |
551 | else | |
552 | bdp++; | |
6aa20a22 | 553 | |
1da177e4 LT |
554 | /* Since we have freed up a buffer, the ring is no longer |
555 | * full. | |
556 | */ | |
557 | if (fep->tx_full) { | |
558 | fep->tx_full = 0; | |
559 | if (netif_queue_stopped(dev)) | |
560 | netif_wake_queue(dev); | |
561 | } | |
562 | } | |
563 | fep->dirty_tx = (cbd_t *)bdp; | |
564 | spin_unlock(&fep->lock); | |
565 | } | |
566 | ||
567 | ||
568 | /* During a receive, the cur_rx points to the current incoming buffer. | |
569 | * When we update through the ring, if the next incoming buffer has | |
570 | * not been given to the system, we just set the empty indicator, | |
571 | * effectively tossing the packet. | |
572 | */ | |
573 | static void | |
574 | fec_enet_rx(struct net_device *dev) | |
575 | { | |
576 | struct fec_enet_private *fep; | |
577 | volatile fec_t *fecp; | |
578 | volatile cbd_t *bdp; | |
0e702ab3 | 579 | unsigned short status; |
1da177e4 LT |
580 | struct sk_buff *skb; |
581 | ushort pkt_len; | |
582 | __u8 *data; | |
6aa20a22 | 583 | |
0e702ab3 GU |
584 | #ifdef CONFIG_M532x |
585 | flush_cache_all(); | |
6aa20a22 | 586 | #endif |
1da177e4 LT |
587 | |
588 | fep = netdev_priv(dev); | |
589 | fecp = (volatile fec_t*)dev->base_addr; | |
590 | ||
591 | /* First, grab all of the stats for the incoming packet. | |
592 | * These get messed up if we get called due to a busy condition. | |
593 | */ | |
594 | bdp = fep->cur_rx; | |
595 | ||
0e702ab3 | 596 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 LT |
597 | |
598 | #ifndef final_version | |
599 | /* Since we have allocated space to hold a complete frame, | |
600 | * the last indicator should be set. | |
601 | */ | |
0e702ab3 | 602 | if ((status & BD_ENET_RX_LAST) == 0) |
1da177e4 LT |
603 | printk("FEC ENET: rcv is not +last\n"); |
604 | #endif | |
605 | ||
606 | if (!fep->opened) | |
607 | goto rx_processing_done; | |
608 | ||
609 | /* Check for errors. */ | |
0e702ab3 | 610 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
1da177e4 | 611 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
09f75cd7 | 612 | dev->stats.rx_errors++; |
0e702ab3 | 613 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
1da177e4 | 614 | /* Frame too long or too short. */ |
09f75cd7 | 615 | dev->stats.rx_length_errors++; |
1da177e4 | 616 | } |
0e702ab3 | 617 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
09f75cd7 | 618 | dev->stats.rx_frame_errors++; |
0e702ab3 | 619 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
09f75cd7 | 620 | dev->stats.rx_crc_errors++; |
0e702ab3 | 621 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
09f75cd7 | 622 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
623 | } |
624 | ||
625 | /* Report late collisions as a frame error. | |
626 | * On this error, the BD is closed, but we don't know what we | |
627 | * have in the buffer. So, just drop this frame on the floor. | |
628 | */ | |
0e702ab3 | 629 | if (status & BD_ENET_RX_CL) { |
09f75cd7 JG |
630 | dev->stats.rx_errors++; |
631 | dev->stats.rx_frame_errors++; | |
1da177e4 LT |
632 | goto rx_processing_done; |
633 | } | |
634 | ||
635 | /* Process the incoming frame. | |
636 | */ | |
09f75cd7 | 637 | dev->stats.rx_packets++; |
1da177e4 | 638 | pkt_len = bdp->cbd_datlen; |
09f75cd7 | 639 | dev->stats.rx_bytes += pkt_len; |
1da177e4 LT |
640 | data = (__u8*)__va(bdp->cbd_bufaddr); |
641 | ||
642 | /* This does 16 byte alignment, exactly what we need. | |
643 | * The packet length includes FCS, but we don't want to | |
644 | * include that when passing upstream as it messes up | |
645 | * bridging applications. | |
646 | */ | |
647 | skb = dev_alloc_skb(pkt_len-4); | |
648 | ||
649 | if (skb == NULL) { | |
650 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | |
09f75cd7 | 651 | dev->stats.rx_dropped++; |
1da177e4 | 652 | } else { |
1da177e4 | 653 | skb_put(skb,pkt_len-4); /* Make room */ |
8c7b7faa | 654 | skb_copy_to_linear_data(skb, data, pkt_len-4); |
1da177e4 LT |
655 | skb->protocol=eth_type_trans(skb,dev); |
656 | netif_rx(skb); | |
657 | } | |
658 | rx_processing_done: | |
659 | ||
660 | /* Clear the status flags for this buffer. | |
661 | */ | |
0e702ab3 | 662 | status &= ~BD_ENET_RX_STATS; |
1da177e4 LT |
663 | |
664 | /* Mark the buffer empty. | |
665 | */ | |
0e702ab3 GU |
666 | status |= BD_ENET_RX_EMPTY; |
667 | bdp->cbd_sc = status; | |
1da177e4 LT |
668 | |
669 | /* Update BD pointer to next entry. | |
670 | */ | |
0e702ab3 | 671 | if (status & BD_ENET_RX_WRAP) |
1da177e4 LT |
672 | bdp = fep->rx_bd_base; |
673 | else | |
674 | bdp++; | |
6aa20a22 | 675 | |
1da177e4 LT |
676 | #if 1 |
677 | /* Doing this here will keep the FEC running while we process | |
678 | * incoming frames. On a heavily loaded network, we should be | |
679 | * able to keep up at the expense of system resources. | |
680 | */ | |
0e702ab3 | 681 | fecp->fec_r_des_active = 0; |
1da177e4 | 682 | #endif |
0e702ab3 | 683 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
1da177e4 LT |
684 | fep->cur_rx = (cbd_t *)bdp; |
685 | ||
686 | #if 0 | |
687 | /* Doing this here will allow us to process all frames in the | |
688 | * ring before the FEC is allowed to put more there. On a heavily | |
689 | * loaded network, some frames may be lost. Unfortunately, this | |
690 | * increases the interrupt overhead since we can potentially work | |
691 | * our way back to the interrupt return only to come right back | |
692 | * here. | |
693 | */ | |
0e702ab3 | 694 | fecp->fec_r_des_active = 0; |
1da177e4 LT |
695 | #endif |
696 | } | |
697 | ||
698 | ||
0e702ab3 | 699 | /* called from interrupt context */ |
1da177e4 LT |
700 | static void |
701 | fec_enet_mii(struct net_device *dev) | |
702 | { | |
703 | struct fec_enet_private *fep; | |
704 | volatile fec_t *ep; | |
705 | mii_list_t *mip; | |
706 | uint mii_reg; | |
707 | ||
708 | fep = netdev_priv(dev); | |
709 | ep = fep->hwp; | |
710 | mii_reg = ep->fec_mii_data; | |
0e702ab3 GU |
711 | |
712 | spin_lock(&fep->lock); | |
6aa20a22 | 713 | |
1da177e4 LT |
714 | if ((mip = mii_head) == NULL) { |
715 | printk("MII and no head!\n"); | |
0e702ab3 | 716 | goto unlock; |
1da177e4 LT |
717 | } |
718 | ||
719 | if (mip->mii_func != NULL) | |
720 | (*(mip->mii_func))(mii_reg, dev); | |
721 | ||
722 | mii_head = mip->mii_next; | |
723 | mip->mii_next = mii_free; | |
724 | mii_free = mip; | |
725 | ||
726 | if ((mip = mii_head) != NULL) | |
727 | ep->fec_mii_data = mip->mii_regval; | |
0e702ab3 GU |
728 | |
729 | unlock: | |
730 | spin_unlock(&fep->lock); | |
1da177e4 LT |
731 | } |
732 | ||
733 | static int | |
734 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | |
735 | { | |
736 | struct fec_enet_private *fep; | |
737 | unsigned long flags; | |
738 | mii_list_t *mip; | |
739 | int retval; | |
740 | ||
741 | /* Add PHY address to register command. | |
742 | */ | |
743 | fep = netdev_priv(dev); | |
744 | regval |= fep->phy_addr << 23; | |
745 | ||
746 | retval = 0; | |
747 | ||
0e702ab3 | 748 | spin_lock_irqsave(&fep->lock,flags); |
1da177e4 LT |
749 | |
750 | if ((mip = mii_free) != NULL) { | |
751 | mii_free = mip->mii_next; | |
752 | mip->mii_regval = regval; | |
753 | mip->mii_func = func; | |
754 | mip->mii_next = NULL; | |
755 | if (mii_head) { | |
756 | mii_tail->mii_next = mip; | |
757 | mii_tail = mip; | |
f909b1ef | 758 | } else { |
1da177e4 LT |
759 | mii_head = mii_tail = mip; |
760 | fep->hwp->fec_mii_data = regval; | |
761 | } | |
f909b1ef | 762 | } else { |
1da177e4 LT |
763 | retval = 1; |
764 | } | |
765 | ||
0e702ab3 | 766 | spin_unlock_irqrestore(&fep->lock,flags); |
1da177e4 LT |
767 | |
768 | return(retval); | |
769 | } | |
770 | ||
771 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | |
772 | { | |
1da177e4 LT |
773 | if(!c) |
774 | return; | |
775 | ||
be6cb66d PDM |
776 | for (; c->mii_data != mk_mii_end; c++) |
777 | mii_queue(dev, c->mii_data, c->funct); | |
1da177e4 LT |
778 | } |
779 | ||
780 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | |
781 | { | |
782 | struct fec_enet_private *fep = netdev_priv(dev); | |
783 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 784 | uint status; |
1da177e4 | 785 | |
7dd6a2aa | 786 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
1da177e4 LT |
787 | |
788 | if (mii_reg & 0x0004) | |
7dd6a2aa | 789 | status |= PHY_STAT_LINK; |
1da177e4 | 790 | if (mii_reg & 0x0010) |
7dd6a2aa | 791 | status |= PHY_STAT_FAULT; |
1da177e4 | 792 | if (mii_reg & 0x0020) |
7dd6a2aa | 793 | status |= PHY_STAT_ANC; |
7dd6a2aa | 794 | *s = status; |
1da177e4 LT |
795 | } |
796 | ||
797 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | |
798 | { | |
799 | struct fec_enet_private *fep = netdev_priv(dev); | |
800 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 801 | uint status; |
1da177e4 | 802 | |
7dd6a2aa | 803 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
1da177e4 LT |
804 | |
805 | if (mii_reg & 0x1000) | |
7dd6a2aa | 806 | status |= PHY_CONF_ANE; |
1da177e4 | 807 | if (mii_reg & 0x4000) |
7dd6a2aa GU |
808 | status |= PHY_CONF_LOOP; |
809 | *s = status; | |
1da177e4 LT |
810 | } |
811 | ||
812 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | |
813 | { | |
814 | struct fec_enet_private *fep = netdev_priv(dev); | |
815 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 816 | uint status; |
1da177e4 | 817 | |
7dd6a2aa | 818 | status = *s & ~(PHY_CONF_SPMASK); |
1da177e4 LT |
819 | |
820 | if (mii_reg & 0x0020) | |
7dd6a2aa | 821 | status |= PHY_CONF_10HDX; |
1da177e4 | 822 | if (mii_reg & 0x0040) |
7dd6a2aa | 823 | status |= PHY_CONF_10FDX; |
1da177e4 | 824 | if (mii_reg & 0x0080) |
7dd6a2aa | 825 | status |= PHY_CONF_100HDX; |
1da177e4 | 826 | if (mii_reg & 0x00100) |
7dd6a2aa GU |
827 | status |= PHY_CONF_100FDX; |
828 | *s = status; | |
1da177e4 LT |
829 | } |
830 | ||
831 | /* ------------------------------------------------------------------------- */ | |
832 | /* The Level one LXT970 is used by many boards */ | |
833 | ||
834 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | |
835 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
836 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
837 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
838 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | |
839 | ||
840 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | |
841 | { | |
842 | struct fec_enet_private *fep = netdev_priv(dev); | |
843 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 844 | uint status; |
1da177e4 | 845 | |
7dd6a2aa | 846 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
847 | if (mii_reg & 0x0800) { |
848 | if (mii_reg & 0x1000) | |
7dd6a2aa | 849 | status |= PHY_STAT_100FDX; |
1da177e4 | 850 | else |
7dd6a2aa | 851 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
852 | } else { |
853 | if (mii_reg & 0x1000) | |
7dd6a2aa | 854 | status |= PHY_STAT_10FDX; |
1da177e4 | 855 | else |
7dd6a2aa | 856 | status |= PHY_STAT_10HDX; |
1da177e4 | 857 | } |
7dd6a2aa | 858 | *s = status; |
1da177e4 LT |
859 | } |
860 | ||
7dd6a2aa | 861 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
1da177e4 LT |
862 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
863 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
864 | { mk_mii_end, } | |
7dd6a2aa GU |
865 | }; |
866 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
867 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
868 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
869 | { mk_mii_end, } | |
7dd6a2aa GU |
870 | }; |
871 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { | |
1da177e4 LT |
872 | /* read SR and ISR to acknowledge */ |
873 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
874 | { mk_mii_read(MII_LXT970_ISR), NULL }, | |
875 | ||
876 | /* find out the current status */ | |
877 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | |
878 | { mk_mii_end, } | |
7dd6a2aa GU |
879 | }; |
880 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
881 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
882 | { mk_mii_end, } | |
7dd6a2aa GU |
883 | }; |
884 | static phy_info_t const phy_info_lxt970 = { | |
6aa20a22 | 885 | .id = 0x07810000, |
7dd6a2aa GU |
886 | .name = "LXT970", |
887 | .config = phy_cmd_lxt970_config, | |
888 | .startup = phy_cmd_lxt970_startup, | |
889 | .ack_int = phy_cmd_lxt970_ack_int, | |
890 | .shutdown = phy_cmd_lxt970_shutdown | |
1da177e4 | 891 | }; |
6aa20a22 | 892 | |
1da177e4 LT |
893 | /* ------------------------------------------------------------------------- */ |
894 | /* The Level one LXT971 is used on some of my custom boards */ | |
895 | ||
896 | /* register definitions for the 971 */ | |
897 | ||
898 | #define MII_LXT971_PCR 16 /* Port Control Register */ | |
899 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | |
900 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
901 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
902 | #define MII_LXT971_LCR 20 /* LED Control Register */ | |
903 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | |
904 | ||
6aa20a22 | 905 | /* |
1da177e4 LT |
906 | * I had some nice ideas of running the MDIO faster... |
907 | * The 971 should support 8MHz and I tried it, but things acted really | |
908 | * weird, so 2.5 MHz ought to be enough for anyone... | |
909 | */ | |
910 | ||
911 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | |
912 | { | |
913 | struct fec_enet_private *fep = netdev_priv(dev); | |
914 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 915 | uint status; |
1da177e4 | 916 | |
7dd6a2aa | 917 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
1da177e4 LT |
918 | |
919 | if (mii_reg & 0x0400) { | |
920 | fep->link = 1; | |
7dd6a2aa | 921 | status |= PHY_STAT_LINK; |
1da177e4 LT |
922 | } else { |
923 | fep->link = 0; | |
924 | } | |
925 | if (mii_reg & 0x0080) | |
7dd6a2aa | 926 | status |= PHY_STAT_ANC; |
1da177e4 LT |
927 | if (mii_reg & 0x4000) { |
928 | if (mii_reg & 0x0200) | |
7dd6a2aa | 929 | status |= PHY_STAT_100FDX; |
1da177e4 | 930 | else |
7dd6a2aa | 931 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
932 | } else { |
933 | if (mii_reg & 0x0200) | |
7dd6a2aa | 934 | status |= PHY_STAT_10FDX; |
1da177e4 | 935 | else |
7dd6a2aa | 936 | status |= PHY_STAT_10HDX; |
1da177e4 LT |
937 | } |
938 | if (mii_reg & 0x0008) | |
7dd6a2aa | 939 | status |= PHY_STAT_FAULT; |
1da177e4 | 940 | |
7dd6a2aa GU |
941 | *s = status; |
942 | } | |
6aa20a22 | 943 | |
7dd6a2aa | 944 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
6aa20a22 | 945 | /* limit to 10MBit because my prototype board |
1da177e4 LT |
946 | * doesn't work with 100. */ |
947 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
948 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
949 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
950 | { mk_mii_end, } | |
7dd6a2aa GU |
951 | }; |
952 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
953 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
954 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
955 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ | |
956 | /* Somehow does the 971 tell me that the link is down | |
957 | * the first read after power-up. | |
958 | * read here to get a valid value in ack_int */ | |
6aa20a22 | 959 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 960 | { mk_mii_end, } |
7dd6a2aa GU |
961 | }; |
962 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { | |
963 | /* acknowledge the int before reading status ! */ | |
964 | { mk_mii_read(MII_LXT971_ISR), NULL }, | |
1da177e4 LT |
965 | /* find out the current status */ |
966 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
967 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
1da177e4 | 968 | { mk_mii_end, } |
7dd6a2aa GU |
969 | }; |
970 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
971 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
972 | { mk_mii_end, } | |
7dd6a2aa GU |
973 | }; |
974 | static phy_info_t const phy_info_lxt971 = { | |
6aa20a22 | 975 | .id = 0x0001378e, |
7dd6a2aa GU |
976 | .name = "LXT971", |
977 | .config = phy_cmd_lxt971_config, | |
978 | .startup = phy_cmd_lxt971_startup, | |
979 | .ack_int = phy_cmd_lxt971_ack_int, | |
980 | .shutdown = phy_cmd_lxt971_shutdown | |
1da177e4 LT |
981 | }; |
982 | ||
983 | /* ------------------------------------------------------------------------- */ | |
984 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | |
985 | ||
986 | /* register definitions */ | |
987 | ||
988 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | |
989 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | |
990 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | |
991 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | |
992 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | |
993 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | |
994 | ||
995 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | |
996 | { | |
997 | struct fec_enet_private *fep = netdev_priv(dev); | |
998 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 999 | uint status; |
1da177e4 | 1000 | |
7dd6a2aa | 1001 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
1002 | |
1003 | switch((mii_reg >> 2) & 7) { | |
7dd6a2aa GU |
1004 | case 1: status |= PHY_STAT_10HDX; break; |
1005 | case 2: status |= PHY_STAT_100HDX; break; | |
1006 | case 5: status |= PHY_STAT_10FDX; break; | |
1007 | case 6: status |= PHY_STAT_100FDX; break; | |
1da177e4 LT |
1008 | } |
1009 | ||
7dd6a2aa GU |
1010 | *s = status; |
1011 | } | |
1012 | ||
1013 | static phy_cmd_t const phy_cmd_qs6612_config[] = { | |
6aa20a22 | 1014 | /* The PHY powers up isolated on the RPX, |
1da177e4 LT |
1015 | * so send a command to allow operation. |
1016 | */ | |
1017 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | |
1018 | ||
1019 | /* parse cr and anar to get some info */ | |
1020 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1021 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1022 | { mk_mii_end, } | |
7dd6a2aa GU |
1023 | }; |
1024 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1025 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
1026 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1027 | { mk_mii_end, } | |
7dd6a2aa GU |
1028 | }; |
1029 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { | |
1da177e4 LT |
1030 | /* we need to read ISR, SR and ANER to acknowledge */ |
1031 | { mk_mii_read(MII_QS6612_ISR), NULL }, | |
1032 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1033 | { mk_mii_read(MII_REG_ANER), NULL }, | |
1034 | ||
1035 | /* read pcr to get info */ | |
1036 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | |
1037 | { mk_mii_end, } | |
7dd6a2aa GU |
1038 | }; |
1039 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1040 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
1041 | { mk_mii_end, } | |
7dd6a2aa GU |
1042 | }; |
1043 | static phy_info_t const phy_info_qs6612 = { | |
6aa20a22 | 1044 | .id = 0x00181440, |
7dd6a2aa GU |
1045 | .name = "QS6612", |
1046 | .config = phy_cmd_qs6612_config, | |
1047 | .startup = phy_cmd_qs6612_startup, | |
1048 | .ack_int = phy_cmd_qs6612_ack_int, | |
1049 | .shutdown = phy_cmd_qs6612_shutdown | |
1da177e4 LT |
1050 | }; |
1051 | ||
1052 | /* ------------------------------------------------------------------------- */ | |
1053 | /* AMD AM79C874 phy */ | |
1054 | ||
1055 | /* register definitions for the 874 */ | |
1056 | ||
1057 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ | |
1058 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ | |
1059 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | |
1060 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ | |
1061 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ | |
1062 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | |
1063 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ | |
1064 | ||
1065 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) | |
1066 | { | |
1067 | struct fec_enet_private *fep = netdev_priv(dev); | |
1068 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1069 | uint status; |
1da177e4 | 1070 | |
7dd6a2aa | 1071 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
1da177e4 LT |
1072 | |
1073 | if (mii_reg & 0x0080) | |
7dd6a2aa | 1074 | status |= PHY_STAT_ANC; |
1da177e4 | 1075 | if (mii_reg & 0x0400) |
7dd6a2aa | 1076 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
1da177e4 | 1077 | else |
7dd6a2aa GU |
1078 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
1079 | ||
1080 | *s = status; | |
1da177e4 LT |
1081 | } |
1082 | ||
7dd6a2aa | 1083 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
1da177e4 LT |
1084 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1085 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1086 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1087 | { mk_mii_end, } | |
7dd6a2aa GU |
1088 | }; |
1089 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1090 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
1091 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1092 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1093 | { mk_mii_end, } |
7dd6a2aa GU |
1094 | }; |
1095 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { | |
1da177e4 LT |
1096 | /* find out the current status */ |
1097 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1098 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1099 | /* we only need to read ISR to acknowledge */ | |
1100 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | |
1101 | { mk_mii_end, } | |
7dd6a2aa GU |
1102 | }; |
1103 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1104 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
1105 | { mk_mii_end, } | |
7dd6a2aa GU |
1106 | }; |
1107 | static phy_info_t const phy_info_am79c874 = { | |
1108 | .id = 0x00022561, | |
1109 | .name = "AM79C874", | |
1110 | .config = phy_cmd_am79c874_config, | |
1111 | .startup = phy_cmd_am79c874_startup, | |
1112 | .ack_int = phy_cmd_am79c874_ack_int, | |
1113 | .shutdown = phy_cmd_am79c874_shutdown | |
1da177e4 LT |
1114 | }; |
1115 | ||
7dd6a2aa | 1116 | |
1da177e4 LT |
1117 | /* ------------------------------------------------------------------------- */ |
1118 | /* Kendin KS8721BL phy */ | |
1119 | ||
1120 | /* register definitions for the 8721 */ | |
1121 | ||
1122 | #define MII_KS8721BL_RXERCR 21 | |
1123 | #define MII_KS8721BL_ICSR 22 | |
1124 | #define MII_KS8721BL_PHYCR 31 | |
1125 | ||
7dd6a2aa | 1126 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
1da177e4 LT |
1127 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1128 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1129 | { mk_mii_end, } | |
7dd6a2aa GU |
1130 | }; |
1131 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1132 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
1133 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1134 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1135 | { mk_mii_end, } |
7dd6a2aa GU |
1136 | }; |
1137 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { | |
1da177e4 LT |
1138 | /* find out the current status */ |
1139 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1140 | /* we only need to read ISR to acknowledge */ | |
1141 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, | |
1142 | { mk_mii_end, } | |
7dd6a2aa GU |
1143 | }; |
1144 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1145 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
1146 | { mk_mii_end, } | |
7dd6a2aa GU |
1147 | }; |
1148 | static phy_info_t const phy_info_ks8721bl = { | |
6aa20a22 | 1149 | .id = 0x00022161, |
7dd6a2aa GU |
1150 | .name = "KS8721BL", |
1151 | .config = phy_cmd_ks8721bl_config, | |
1152 | .startup = phy_cmd_ks8721bl_startup, | |
1153 | .ack_int = phy_cmd_ks8721bl_ack_int, | |
1154 | .shutdown = phy_cmd_ks8721bl_shutdown | |
1da177e4 LT |
1155 | }; |
1156 | ||
562d2f8c GU |
1157 | /* ------------------------------------------------------------------------- */ |
1158 | /* register definitions for the DP83848 */ | |
1159 | ||
1160 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ | |
1161 | ||
1162 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) | |
1163 | { | |
1164 | struct fec_enet_private *fep = dev->priv; | |
1165 | volatile uint *s = &(fep->phy_status); | |
1166 | ||
1167 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); | |
1168 | ||
1169 | /* Link up */ | |
1170 | if (mii_reg & 0x0001) { | |
1171 | fep->link = 1; | |
1172 | *s |= PHY_STAT_LINK; | |
1173 | } else | |
1174 | fep->link = 0; | |
1175 | /* Status of link */ | |
1176 | if (mii_reg & 0x0010) /* Autonegotioation complete */ | |
1177 | *s |= PHY_STAT_ANC; | |
1178 | if (mii_reg & 0x0002) { /* 10MBps? */ | |
1179 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1180 | *s |= PHY_STAT_10FDX; | |
1181 | else | |
1182 | *s |= PHY_STAT_10HDX; | |
1183 | } else { /* 100 Mbps? */ | |
1184 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1185 | *s |= PHY_STAT_100FDX; | |
1186 | else | |
1187 | *s |= PHY_STAT_100HDX; | |
1188 | } | |
1189 | if (mii_reg & 0x0008) | |
1190 | *s |= PHY_STAT_FAULT; | |
1191 | } | |
1192 | ||
1193 | static phy_info_t phy_info_dp83848= { | |
1194 | 0x020005c9, | |
1195 | "DP83848", | |
1196 | ||
1197 | (const phy_cmd_t []) { /* config */ | |
1198 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1199 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1200 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, | |
1201 | { mk_mii_end, } | |
1202 | }, | |
1203 | (const phy_cmd_t []) { /* startup - enable interrupts */ | |
1204 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1205 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1206 | { mk_mii_end, } | |
1207 | }, | |
1208 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ | |
1209 | { mk_mii_end, } | |
1210 | }, | |
1211 | (const phy_cmd_t []) { /* shutdown */ | |
1212 | { mk_mii_end, } | |
1213 | }, | |
1214 | }; | |
1215 | ||
1da177e4 LT |
1216 | /* ------------------------------------------------------------------------- */ |
1217 | ||
7dd6a2aa | 1218 | static phy_info_t const * const phy_info[] = { |
1da177e4 LT |
1219 | &phy_info_lxt970, |
1220 | &phy_info_lxt971, | |
1221 | &phy_info_qs6612, | |
1222 | &phy_info_am79c874, | |
1223 | &phy_info_ks8721bl, | |
562d2f8c | 1224 | &phy_info_dp83848, |
1da177e4 LT |
1225 | NULL |
1226 | }; | |
1227 | ||
1228 | /* ------------------------------------------------------------------------- */ | |
c1d96156 | 1229 | #ifdef HAVE_mii_link_interrupt |
1da177e4 LT |
1230 | #ifdef CONFIG_RPXCLASSIC |
1231 | static void | |
1232 | mii_link_interrupt(void *dev_id); | |
1233 | #else | |
1234 | static irqreturn_t | |
7d12e780 | 1235 | mii_link_interrupt(int irq, void * dev_id); |
1da177e4 | 1236 | #endif |
6b265293 | 1237 | #endif |
1da177e4 LT |
1238 | |
1239 | #if defined(CONFIG_M5272) | |
1da177e4 LT |
1240 | /* |
1241 | * Code specific to Coldfire 5272 setup. | |
1242 | */ | |
1243 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1244 | { | |
1245 | volatile unsigned long *icrp; | |
7dd6a2aa GU |
1246 | static const struct idesc { |
1247 | char *name; | |
1248 | unsigned short irq; | |
7d12e780 | 1249 | irq_handler_t handler; |
7dd6a2aa GU |
1250 | } *idp, id[] = { |
1251 | { "fec(RX)", 86, fec_enet_interrupt }, | |
1252 | { "fec(TX)", 87, fec_enet_interrupt }, | |
1253 | { "fec(OTHER)", 88, fec_enet_interrupt }, | |
1254 | { "fec(MII)", 66, mii_link_interrupt }, | |
1255 | { NULL }, | |
1256 | }; | |
1da177e4 LT |
1257 | |
1258 | /* Setup interrupt handlers. */ | |
7dd6a2aa | 1259 | for (idp = id; idp->name; idp++) { |
0a504779 | 1260 | if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0) |
7dd6a2aa GU |
1261 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); |
1262 | } | |
1da177e4 LT |
1263 | |
1264 | /* Unmask interrupt at ColdFire 5272 SIM */ | |
1265 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3); | |
1266 | *icrp = 0x00000ddd; | |
1267 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1268 | *icrp = 0x0d000000; |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1272 | { | |
1273 | volatile fec_t *fecp; | |
1274 | ||
1275 | fecp = fep->hwp; | |
1276 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1277 | fecp->fec_x_cntrl = 0x00; | |
1278 | ||
1279 | /* | |
1280 | * Set MII speed to 2.5 MHz | |
1281 | * See 5272 manual section 11.5.8: MSCR | |
1282 | */ | |
1283 | fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2; | |
1284 | fecp->fec_mii_speed = fep->phy_speed; | |
1285 | ||
1286 | fec_restart(dev, 0); | |
1287 | } | |
1288 | ||
1289 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1290 | { | |
1291 | struct fec_enet_private *fep = netdev_priv(dev); | |
1292 | volatile fec_t *fecp; | |
7dd6a2aa | 1293 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1294 | |
1295 | fecp = fep->hwp; | |
1296 | ||
7dd6a2aa | 1297 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1298 | /* |
1299 | * Get MAC address from FLASH. | |
1300 | * If it is all 1's or 0's, use the default. | |
1301 | */ | |
7dd6a2aa | 1302 | iap = (unsigned char *)FEC_FLASHMAC; |
1da177e4 LT |
1303 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1304 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1305 | iap = fec_mac_default; | |
1306 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1307 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1308 | iap = fec_mac_default; | |
1309 | } else { | |
1310 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1311 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1312 | iap = &tmpaddr[0]; | |
1313 | } | |
1314 | ||
7dd6a2aa | 1315 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1316 | |
1317 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1318 | if (iap == fec_mac_default) |
1319 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1320 | } |
1321 | ||
1322 | static void __inline__ fec_enable_phy_intr(void) | |
1323 | { | |
1324 | } | |
1325 | ||
1326 | static void __inline__ fec_disable_phy_intr(void) | |
1327 | { | |
1328 | volatile unsigned long *icrp; | |
1329 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1330 | *icrp = 0x08000000; |
1da177e4 LT |
1331 | } |
1332 | ||
1333 | static void __inline__ fec_phy_ack_intr(void) | |
1334 | { | |
1335 | volatile unsigned long *icrp; | |
1336 | /* Acknowledge the interrupt */ | |
1337 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1338 | *icrp = 0x0d000000; |
1da177e4 LT |
1339 | } |
1340 | ||
1341 | static void __inline__ fec_localhw_setup(void) | |
1342 | { | |
1343 | } | |
1344 | ||
1345 | /* | |
1346 | * Do not need to make region uncached on 5272. | |
1347 | */ | |
1348 | static void __inline__ fec_uncache(unsigned long addr) | |
1349 | { | |
1350 | } | |
1351 | ||
1352 | /* ------------------------------------------------------------------------- */ | |
1353 | ||
7dd6a2aa | 1354 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) |
1da177e4 LT |
1355 | |
1356 | /* | |
7dd6a2aa GU |
1357 | * Code specific to Coldfire 5230/5231/5232/5234/5235, |
1358 | * the 5270/5271/5274/5275 and 5280/5282 setups. | |
1da177e4 LT |
1359 | */ |
1360 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1361 | { | |
1362 | struct fec_enet_private *fep; | |
1363 | int b; | |
7dd6a2aa GU |
1364 | static const struct idesc { |
1365 | char *name; | |
1366 | unsigned short irq; | |
1367 | } *idp, id[] = { | |
1368 | { "fec(TXF)", 23 }, | |
7dd6a2aa | 1369 | { "fec(RXF)", 27 }, |
7dd6a2aa | 1370 | { "fec(MII)", 29 }, |
7dd6a2aa GU |
1371 | { NULL }, |
1372 | }; | |
1da177e4 LT |
1373 | |
1374 | fep = netdev_priv(dev); | |
1375 | b = (fep->index) ? 128 : 64; | |
1376 | ||
1377 | /* Setup interrupt handlers. */ | |
7dd6a2aa | 1378 | for (idp = id; idp->name; idp++) { |
0a504779 | 1379 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0) |
7dd6a2aa GU |
1380 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1381 | } | |
1da177e4 LT |
1382 | |
1383 | /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */ | |
1384 | { | |
1385 | volatile unsigned char *icrp; | |
1386 | volatile unsigned long *imrp; | |
83901fc1 | 1387 | int i, ilip; |
1da177e4 LT |
1388 | |
1389 | b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0; | |
1390 | icrp = (volatile unsigned char *) (MCF_IPSBAR + b + | |
1391 | MCFINTC_ICR0); | |
83901fc1 WC |
1392 | for (i = 23, ilip = 0x28; (i < 36); i++) |
1393 | icrp[i] = ilip--; | |
1da177e4 LT |
1394 | |
1395 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1396 | MCFINTC_IMRH); | |
1397 | *imrp &= ~0x0000000f; | |
1398 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1399 | MCFINTC_IMRL); | |
1400 | *imrp &= ~0xff800001; | |
1401 | } | |
1402 | ||
1403 | #if defined(CONFIG_M528x) | |
1404 | /* Set up gpio outputs for MII lines */ | |
1405 | { | |
7dd6a2aa GU |
1406 | volatile u16 *gpio_paspar; |
1407 | volatile u8 *gpio_pehlpar; | |
6aa20a22 | 1408 | |
7dd6a2aa GU |
1409 | gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056); |
1410 | gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058); | |
1411 | *gpio_paspar |= 0x0f00; | |
1412 | *gpio_pehlpar = 0xc0; | |
1da177e4 LT |
1413 | } |
1414 | #endif | |
b8a94b3d MC |
1415 | |
1416 | #if defined(CONFIG_M527x) | |
1417 | /* Set up gpio outputs for MII lines */ | |
1418 | { | |
1419 | volatile u8 *gpio_par_fec; | |
1420 | volatile u16 *gpio_par_feci2c; | |
1421 | ||
1422 | gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082); | |
1423 | /* Set up gpio outputs for FEC0 MII lines */ | |
1424 | gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078); | |
1425 | ||
1426 | *gpio_par_feci2c |= 0x0f00; | |
1427 | *gpio_par_fec |= 0xc0; | |
1428 | ||
1429 | #if defined(CONFIG_FEC2) | |
1430 | /* Set up gpio outputs for FEC1 MII lines */ | |
1431 | gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079); | |
1432 | ||
1433 | *gpio_par_feci2c |= 0x00a0; | |
1434 | *gpio_par_fec |= 0xc0; | |
1435 | #endif /* CONFIG_FEC2 */ | |
1436 | } | |
1437 | #endif /* CONFIG_M527x */ | |
1da177e4 LT |
1438 | } |
1439 | ||
1440 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1441 | { | |
1442 | volatile fec_t *fecp; | |
1443 | ||
1444 | fecp = fep->hwp; | |
1445 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1446 | fecp->fec_x_cntrl = 0x00; | |
1447 | ||
1448 | /* | |
1449 | * Set MII speed to 2.5 MHz | |
1450 | * See 5282 manual section 17.5.4.7: MSCR | |
1451 | */ | |
1452 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1453 | fecp->fec_mii_speed = fep->phy_speed; | |
1454 | ||
1455 | fec_restart(dev, 0); | |
1456 | } | |
1457 | ||
1458 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1459 | { | |
1460 | struct fec_enet_private *fep = netdev_priv(dev); | |
1461 | volatile fec_t *fecp; | |
7dd6a2aa | 1462 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1463 | |
1464 | fecp = fep->hwp; | |
1465 | ||
7dd6a2aa | 1466 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1467 | /* |
1468 | * Get MAC address from FLASH. | |
1469 | * If it is all 1's or 0's, use the default. | |
1470 | */ | |
7dd6a2aa | 1471 | iap = FEC_FLASHMAC; |
1da177e4 LT |
1472 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1473 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1474 | iap = fec_mac_default; | |
1475 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1476 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1477 | iap = fec_mac_default; | |
1478 | } else { | |
1479 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1480 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1481 | iap = &tmpaddr[0]; | |
1482 | } | |
1483 | ||
7dd6a2aa | 1484 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1485 | |
1486 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1487 | if (iap == fec_mac_default) |
1488 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1489 | } |
1490 | ||
1491 | static void __inline__ fec_enable_phy_intr(void) | |
1492 | { | |
1493 | } | |
1494 | ||
1495 | static void __inline__ fec_disable_phy_intr(void) | |
1496 | { | |
1497 | } | |
1498 | ||
1499 | static void __inline__ fec_phy_ack_intr(void) | |
1500 | { | |
1501 | } | |
1502 | ||
1503 | static void __inline__ fec_localhw_setup(void) | |
1504 | { | |
1505 | } | |
1506 | ||
1507 | /* | |
1508 | * Do not need to make region uncached on 5272. | |
1509 | */ | |
1510 | static void __inline__ fec_uncache(unsigned long addr) | |
1511 | { | |
1512 | } | |
1513 | ||
1514 | /* ------------------------------------------------------------------------- */ | |
1515 | ||
562d2f8c GU |
1516 | #elif defined(CONFIG_M520x) |
1517 | ||
1518 | /* | |
1519 | * Code specific to Coldfire 520x | |
1520 | */ | |
1521 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1522 | { | |
1523 | struct fec_enet_private *fep; | |
1524 | int b; | |
1525 | static const struct idesc { | |
1526 | char *name; | |
1527 | unsigned short irq; | |
1528 | } *idp, id[] = { | |
1529 | { "fec(TXF)", 23 }, | |
562d2f8c | 1530 | { "fec(RXF)", 27 }, |
562d2f8c | 1531 | { "fec(MII)", 29 }, |
562d2f8c GU |
1532 | { NULL }, |
1533 | }; | |
1534 | ||
1535 | fep = netdev_priv(dev); | |
1536 | b = 64 + 13; | |
1537 | ||
1538 | /* Setup interrupt handlers. */ | |
1539 | for (idp = id; idp->name; idp++) { | |
0a504779 | 1540 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
562d2f8c GU |
1541 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1542 | } | |
1543 | ||
1544 | /* Unmask interrupts at ColdFire interrupt controller */ | |
1545 | { | |
1546 | volatile unsigned char *icrp; | |
1547 | volatile unsigned long *imrp; | |
1548 | ||
1549 | icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1550 | MCFINTC_ICR0); | |
1551 | for (b = 36; (b < 49); b++) | |
1552 | icrp[b] = 0x04; | |
1553 | imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1554 | MCFINTC_IMRH); | |
1555 | *imrp &= ~0x0001FFF0; | |
1556 | } | |
1557 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0; | |
1558 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f; | |
1559 | } | |
1560 | ||
1561 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1562 | { | |
1563 | volatile fec_t *fecp; | |
1564 | ||
1565 | fecp = fep->hwp; | |
1566 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1567 | fecp->fec_x_cntrl = 0x00; | |
1568 | ||
1569 | /* | |
1570 | * Set MII speed to 2.5 MHz | |
1571 | * See 5282 manual section 17.5.4.7: MSCR | |
1572 | */ | |
1573 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1574 | fecp->fec_mii_speed = fep->phy_speed; | |
1575 | ||
1576 | fec_restart(dev, 0); | |
1577 | } | |
1578 | ||
1579 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1580 | { | |
1581 | struct fec_enet_private *fep = netdev_priv(dev); | |
1582 | volatile fec_t *fecp; | |
1583 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1584 | ||
1585 | fecp = fep->hwp; | |
1586 | ||
1587 | if (FEC_FLASHMAC) { | |
1588 | /* | |
1589 | * Get MAC address from FLASH. | |
1590 | * If it is all 1's or 0's, use the default. | |
1591 | */ | |
1592 | iap = FEC_FLASHMAC; | |
1593 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1594 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1595 | iap = fec_mac_default; | |
1596 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1597 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1598 | iap = fec_mac_default; | |
1599 | } else { | |
1600 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1601 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1602 | iap = &tmpaddr[0]; | |
1603 | } | |
1604 | ||
1605 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1606 | ||
1607 | /* Adjust MAC if using default MAC address */ | |
1608 | if (iap == fec_mac_default) | |
1609 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1610 | } | |
1611 | ||
1612 | static void __inline__ fec_enable_phy_intr(void) | |
1613 | { | |
1614 | } | |
1615 | ||
1616 | static void __inline__ fec_disable_phy_intr(void) | |
1617 | { | |
1618 | } | |
1619 | ||
1620 | static void __inline__ fec_phy_ack_intr(void) | |
1621 | { | |
1622 | } | |
1623 | ||
1624 | static void __inline__ fec_localhw_setup(void) | |
1625 | { | |
1626 | } | |
1627 | ||
1628 | static void __inline__ fec_uncache(unsigned long addr) | |
1629 | { | |
1630 | } | |
1631 | ||
1632 | /* ------------------------------------------------------------------------- */ | |
1633 | ||
6b265293 MW |
1634 | #elif defined(CONFIG_M532x) |
1635 | /* | |
1636 | * Code specific for M532x | |
1637 | */ | |
1638 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1639 | { | |
1640 | struct fec_enet_private *fep; | |
1641 | int b; | |
1642 | static const struct idesc { | |
1643 | char *name; | |
1644 | unsigned short irq; | |
1645 | } *idp, id[] = { | |
1646 | { "fec(TXF)", 36 }, | |
6b265293 | 1647 | { "fec(RXF)", 40 }, |
6b265293 | 1648 | { "fec(MII)", 42 }, |
6b265293 MW |
1649 | { NULL }, |
1650 | }; | |
1651 | ||
1652 | fep = netdev_priv(dev); | |
1653 | b = (fep->index) ? 128 : 64; | |
1654 | ||
1655 | /* Setup interrupt handlers. */ | |
1656 | for (idp = id; idp->name; idp++) { | |
0a504779 | 1657 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
6aa20a22 | 1658 | printk("FEC: Could not allocate %s IRQ(%d)!\n", |
6b265293 MW |
1659 | idp->name, b+idp->irq); |
1660 | } | |
1661 | ||
1662 | /* Unmask interrupts */ | |
1663 | MCF_INTC0_ICR36 = 0x2; | |
1664 | MCF_INTC0_ICR37 = 0x2; | |
1665 | MCF_INTC0_ICR38 = 0x2; | |
1666 | MCF_INTC0_ICR39 = 0x2; | |
1667 | MCF_INTC0_ICR40 = 0x2; | |
1668 | MCF_INTC0_ICR41 = 0x2; | |
1669 | MCF_INTC0_ICR42 = 0x2; | |
1670 | MCF_INTC0_ICR43 = 0x2; | |
1671 | MCF_INTC0_ICR44 = 0x2; | |
1672 | MCF_INTC0_ICR45 = 0x2; | |
1673 | MCF_INTC0_ICR46 = 0x2; | |
1674 | MCF_INTC0_ICR47 = 0x2; | |
1675 | MCF_INTC0_ICR48 = 0x2; | |
1676 | ||
1677 | MCF_INTC0_IMRH &= ~( | |
1678 | MCF_INTC_IMRH_INT_MASK36 | | |
1679 | MCF_INTC_IMRH_INT_MASK37 | | |
1680 | MCF_INTC_IMRH_INT_MASK38 | | |
1681 | MCF_INTC_IMRH_INT_MASK39 | | |
1682 | MCF_INTC_IMRH_INT_MASK40 | | |
1683 | MCF_INTC_IMRH_INT_MASK41 | | |
1684 | MCF_INTC_IMRH_INT_MASK42 | | |
1685 | MCF_INTC_IMRH_INT_MASK43 | | |
1686 | MCF_INTC_IMRH_INT_MASK44 | | |
1687 | MCF_INTC_IMRH_INT_MASK45 | | |
1688 | MCF_INTC_IMRH_INT_MASK46 | | |
1689 | MCF_INTC_IMRH_INT_MASK47 | | |
1690 | MCF_INTC_IMRH_INT_MASK48 ); | |
1691 | ||
1692 | /* Set up gpio outputs for MII lines */ | |
1693 | MCF_GPIO_PAR_FECI2C |= (0 | | |
1694 | MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | | |
1695 | MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); | |
1696 | MCF_GPIO_PAR_FEC = (0 | | |
1697 | MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | | |
1698 | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); | |
1699 | } | |
1700 | ||
1701 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1702 | { | |
1703 | volatile fec_t *fecp; | |
1704 | ||
1705 | fecp = fep->hwp; | |
1706 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1707 | fecp->fec_x_cntrl = 0x00; | |
1708 | ||
1709 | /* | |
1710 | * Set MII speed to 2.5 MHz | |
1711 | */ | |
1712 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1713 | fecp->fec_mii_speed = fep->phy_speed; | |
1714 | ||
1715 | fec_restart(dev, 0); | |
1716 | } | |
1717 | ||
1718 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1719 | { | |
1720 | struct fec_enet_private *fep = netdev_priv(dev); | |
1721 | volatile fec_t *fecp; | |
1722 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1723 | ||
1724 | fecp = fep->hwp; | |
1725 | ||
1726 | if (FEC_FLASHMAC) { | |
1727 | /* | |
1728 | * Get MAC address from FLASH. | |
1729 | * If it is all 1's or 0's, use the default. | |
1730 | */ | |
1731 | iap = FEC_FLASHMAC; | |
1732 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1733 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1734 | iap = fec_mac_default; | |
1735 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1736 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1737 | iap = fec_mac_default; | |
1738 | } else { | |
1739 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1740 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1741 | iap = &tmpaddr[0]; | |
1742 | } | |
1743 | ||
1744 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1745 | ||
1746 | /* Adjust MAC if using default MAC address */ | |
1747 | if (iap == fec_mac_default) | |
1748 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1749 | } | |
1750 | ||
1751 | static void __inline__ fec_enable_phy_intr(void) | |
1752 | { | |
1753 | } | |
1754 | ||
1755 | static void __inline__ fec_disable_phy_intr(void) | |
1756 | { | |
1757 | } | |
1758 | ||
1759 | static void __inline__ fec_phy_ack_intr(void) | |
1760 | { | |
1761 | } | |
1762 | ||
1763 | static void __inline__ fec_localhw_setup(void) | |
1764 | { | |
1765 | } | |
1766 | ||
1767 | /* | |
1768 | * Do not need to make region uncached on 532x. | |
1769 | */ | |
1770 | static void __inline__ fec_uncache(unsigned long addr) | |
1771 | { | |
1772 | } | |
1773 | ||
1774 | /* ------------------------------------------------------------------------- */ | |
1775 | ||
1776 | ||
1da177e4 LT |
1777 | #else |
1778 | ||
1779 | /* | |
7dd6a2aa | 1780 | * Code specific to the MPC860T setup. |
1da177e4 LT |
1781 | */ |
1782 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1783 | { | |
1784 | volatile immap_t *immap; | |
1785 | ||
1786 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | |
1787 | ||
1788 | if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) | |
1789 | panic("Could not allocate FEC IRQ!"); | |
1790 | ||
1791 | #ifdef CONFIG_RPXCLASSIC | |
1792 | /* Make Port C, bit 15 an input that causes interrupts. | |
1793 | */ | |
1794 | immap->im_ioport.iop_pcpar &= ~0x0001; | |
1795 | immap->im_ioport.iop_pcdir &= ~0x0001; | |
1796 | immap->im_ioport.iop_pcso &= ~0x0001; | |
1797 | immap->im_ioport.iop_pcint |= 0x0001; | |
1798 | cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); | |
1799 | ||
1800 | /* Make LEDS reflect Link status. | |
1801 | */ | |
1802 | *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; | |
1803 | #endif | |
1804 | #ifdef CONFIG_FADS | |
1805 | if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0) | |
1806 | panic("Could not allocate MII IRQ!"); | |
1807 | #endif | |
1808 | } | |
1809 | ||
1810 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1811 | { | |
1da177e4 | 1812 | bd_t *bd; |
1da177e4 | 1813 | |
1da177e4 | 1814 | bd = (bd_t *)__res; |
7dd6a2aa | 1815 | memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN); |
1da177e4 LT |
1816 | |
1817 | #ifdef CONFIG_RPXCLASSIC | |
1818 | /* The Embedded Planet boards have only one MAC address in | |
1819 | * the EEPROM, but can have two Ethernet ports. For the | |
1820 | * FEC port, we create another address by setting one of | |
1821 | * the address bits above something that would have (up to | |
1822 | * now) been allocated. | |
1823 | */ | |
7dd6a2aa | 1824 | dev->dev_adrd[3] |= 0x80; |
1da177e4 | 1825 | #endif |
1da177e4 LT |
1826 | } |
1827 | ||
1828 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1829 | { | |
1830 | extern uint _get_IMMR(void); | |
1831 | volatile immap_t *immap; | |
1832 | volatile fec_t *fecp; | |
1833 | ||
1834 | fecp = fep->hwp; | |
1835 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | |
1836 | ||
1837 | /* Configure all of port D for MII. | |
1838 | */ | |
1839 | immap->im_ioport.iop_pdpar = 0x1fff; | |
1840 | ||
1841 | /* Bits moved from Rev. D onward. | |
1842 | */ | |
1843 | if ((_get_IMMR() & 0xffff) < 0x0501) | |
1844 | immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ | |
1845 | else | |
1846 | immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ | |
6aa20a22 | 1847 | |
1da177e4 LT |
1848 | /* Set MII speed to 2.5 MHz |
1849 | */ | |
6aa20a22 | 1850 | fecp->fec_mii_speed = fep->phy_speed = |
1da177e4 LT |
1851 | ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e; |
1852 | } | |
1853 | ||
1854 | static void __inline__ fec_enable_phy_intr(void) | |
1855 | { | |
1856 | volatile fec_t *fecp; | |
1857 | ||
1858 | fecp = fep->hwp; | |
1859 | ||
6aa20a22 | 1860 | /* Enable MII command finished interrupt |
1da177e4 LT |
1861 | */ |
1862 | fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; | |
1863 | } | |
1864 | ||
1865 | static void __inline__ fec_disable_phy_intr(void) | |
1866 | { | |
1867 | } | |
1868 | ||
1869 | static void __inline__ fec_phy_ack_intr(void) | |
1870 | { | |
1871 | } | |
1872 | ||
1873 | static void __inline__ fec_localhw_setup(void) | |
1874 | { | |
1875 | volatile fec_t *fecp; | |
1876 | ||
1877 | fecp = fep->hwp; | |
1878 | fecp->fec_r_hash = PKT_MAXBUF_SIZE; | |
1879 | /* Enable big endian and don't care about SDMA FC. | |
1880 | */ | |
1881 | fecp->fec_fun_code = 0x78000000; | |
1882 | } | |
1883 | ||
1884 | static void __inline__ fec_uncache(unsigned long addr) | |
1885 | { | |
1886 | pte_t *pte; | |
1887 | pte = va_to_pte(mem_addr); | |
1888 | pte_val(*pte) |= _PAGE_NO_CACHE; | |
1889 | flush_tlb_page(init_mm.mmap, mem_addr); | |
1890 | } | |
1891 | ||
1892 | #endif | |
1893 | ||
1894 | /* ------------------------------------------------------------------------- */ | |
1895 | ||
1896 | static void mii_display_status(struct net_device *dev) | |
1897 | { | |
1898 | struct fec_enet_private *fep = netdev_priv(dev); | |
1899 | volatile uint *s = &(fep->phy_status); | |
1900 | ||
1901 | if (!fep->link && !fep->old_link) { | |
1902 | /* Link is still down - don't print anything */ | |
1903 | return; | |
1904 | } | |
1905 | ||
1906 | printk("%s: status: ", dev->name); | |
1907 | ||
1908 | if (!fep->link) { | |
1909 | printk("link down"); | |
1910 | } else { | |
1911 | printk("link up"); | |
1912 | ||
1913 | switch(*s & PHY_STAT_SPMASK) { | |
1914 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; | |
1915 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; | |
1916 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; | |
1917 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; | |
1918 | default: | |
1919 | printk(", Unknown speed/duplex"); | |
1920 | } | |
1921 | ||
1922 | if (*s & PHY_STAT_ANC) | |
1923 | printk(", auto-negotiation complete"); | |
1924 | } | |
1925 | ||
1926 | if (*s & PHY_STAT_FAULT) | |
1927 | printk(", remote fault"); | |
1928 | ||
1929 | printk(".\n"); | |
1930 | } | |
1931 | ||
cb84d6e7 | 1932 | static void mii_display_config(struct work_struct *work) |
1da177e4 | 1933 | { |
cb84d6e7 GU |
1934 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1935 | struct net_device *dev = fep->netdev; | |
7dd6a2aa | 1936 | uint status = fep->phy_status; |
1da177e4 LT |
1937 | |
1938 | /* | |
1939 | ** When we get here, phy_task is already removed from | |
1940 | ** the workqueue. It is thus safe to allow to reuse it. | |
1941 | */ | |
1942 | fep->mii_phy_task_queued = 0; | |
1943 | printk("%s: config: auto-negotiation ", dev->name); | |
1944 | ||
7dd6a2aa | 1945 | if (status & PHY_CONF_ANE) |
1da177e4 LT |
1946 | printk("on"); |
1947 | else | |
1948 | printk("off"); | |
1949 | ||
7dd6a2aa | 1950 | if (status & PHY_CONF_100FDX) |
1da177e4 | 1951 | printk(", 100FDX"); |
7dd6a2aa | 1952 | if (status & PHY_CONF_100HDX) |
1da177e4 | 1953 | printk(", 100HDX"); |
7dd6a2aa | 1954 | if (status & PHY_CONF_10FDX) |
1da177e4 | 1955 | printk(", 10FDX"); |
7dd6a2aa | 1956 | if (status & PHY_CONF_10HDX) |
1da177e4 | 1957 | printk(", 10HDX"); |
7dd6a2aa | 1958 | if (!(status & PHY_CONF_SPMASK)) |
1da177e4 LT |
1959 | printk(", No speed/duplex selected?"); |
1960 | ||
7dd6a2aa | 1961 | if (status & PHY_CONF_LOOP) |
1da177e4 | 1962 | printk(", loopback enabled"); |
6aa20a22 | 1963 | |
1da177e4 LT |
1964 | printk(".\n"); |
1965 | ||
1966 | fep->sequence_done = 1; | |
1967 | } | |
1968 | ||
cb84d6e7 | 1969 | static void mii_relink(struct work_struct *work) |
1da177e4 | 1970 | { |
cb84d6e7 GU |
1971 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1972 | struct net_device *dev = fep->netdev; | |
1da177e4 LT |
1973 | int duplex; |
1974 | ||
1975 | /* | |
1976 | ** When we get here, phy_task is already removed from | |
1977 | ** the workqueue. It is thus safe to allow to reuse it. | |
1978 | */ | |
1979 | fep->mii_phy_task_queued = 0; | |
1980 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | |
1981 | mii_display_status(dev); | |
1982 | fep->old_link = fep->link; | |
1983 | ||
1984 | if (fep->link) { | |
1985 | duplex = 0; | |
6aa20a22 | 1986 | if (fep->phy_status |
1da177e4 LT |
1987 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
1988 | duplex = 1; | |
1989 | fec_restart(dev, duplex); | |
f909b1ef | 1990 | } else |
1da177e4 LT |
1991 | fec_stop(dev); |
1992 | ||
1993 | #if 0 | |
1994 | enable_irq(fep->mii_irq); | |
1995 | #endif | |
1996 | ||
1997 | } | |
1998 | ||
1999 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ | |
2000 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | |
2001 | { | |
2002 | struct fec_enet_private *fep = netdev_priv(dev); | |
2003 | ||
2004 | /* | |
2005 | ** We cannot queue phy_task twice in the workqueue. It | |
2006 | ** would cause an endless loop in the workqueue. | |
2007 | ** Fortunately, if the last mii_relink entry has not yet been | |
2008 | ** executed now, it will do the job for the current interrupt, | |
2009 | ** which is just what we want. | |
2010 | */ | |
2011 | if (fep->mii_phy_task_queued) | |
2012 | return; | |
2013 | ||
2014 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 2015 | INIT_WORK(&fep->phy_task, mii_relink); |
1da177e4 LT |
2016 | schedule_work(&fep->phy_task); |
2017 | } | |
2018 | ||
7dd6a2aa | 2019 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
1da177e4 LT |
2020 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
2021 | { | |
2022 | struct fec_enet_private *fep = netdev_priv(dev); | |
2023 | ||
2024 | if (fep->mii_phy_task_queued) | |
2025 | return; | |
2026 | ||
2027 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 2028 | INIT_WORK(&fep->phy_task, mii_display_config); |
1da177e4 LT |
2029 | schedule_work(&fep->phy_task); |
2030 | } | |
2031 | ||
7dd6a2aa GU |
2032 | phy_cmd_t const phy_cmd_relink[] = { |
2033 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, | |
2034 | { mk_mii_end, } | |
2035 | }; | |
2036 | phy_cmd_t const phy_cmd_config[] = { | |
2037 | { mk_mii_read(MII_REG_CR), mii_queue_config }, | |
2038 | { mk_mii_end, } | |
2039 | }; | |
1da177e4 LT |
2040 | |
2041 | /* Read remainder of PHY ID. | |
2042 | */ | |
2043 | static void | |
2044 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | |
2045 | { | |
2046 | struct fec_enet_private *fep; | |
2047 | int i; | |
2048 | ||
2049 | fep = netdev_priv(dev); | |
2050 | fep->phy_id |= (mii_reg & 0xffff); | |
2051 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); | |
2052 | ||
2053 | for(i = 0; phy_info[i]; i++) { | |
2054 | if(phy_info[i]->id == (fep->phy_id >> 4)) | |
2055 | break; | |
2056 | } | |
2057 | ||
2058 | if (phy_info[i]) | |
2059 | printk(" -- %s\n", phy_info[i]->name); | |
2060 | else | |
2061 | printk(" -- unknown PHY!\n"); | |
6aa20a22 | 2062 | |
1da177e4 LT |
2063 | fep->phy = phy_info[i]; |
2064 | fep->phy_id_done = 1; | |
2065 | } | |
2066 | ||
2067 | /* Scan all of the MII PHY addresses looking for someone to respond | |
2068 | * with a valid ID. This usually happens quickly. | |
2069 | */ | |
2070 | static void | |
2071 | mii_discover_phy(uint mii_reg, struct net_device *dev) | |
2072 | { | |
2073 | struct fec_enet_private *fep; | |
2074 | volatile fec_t *fecp; | |
2075 | uint phytype; | |
2076 | ||
2077 | fep = netdev_priv(dev); | |
2078 | fecp = fep->hwp; | |
2079 | ||
2080 | if (fep->phy_addr < 32) { | |
2081 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | |
6aa20a22 | 2082 | |
1da177e4 LT |
2083 | /* Got first part of ID, now get remainder. |
2084 | */ | |
2085 | fep->phy_id = phytype << 16; | |
2086 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), | |
2087 | mii_discover_phy3); | |
f909b1ef | 2088 | } else { |
1da177e4 LT |
2089 | fep->phy_addr++; |
2090 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | |
2091 | mii_discover_phy); | |
2092 | } | |
2093 | } else { | |
2094 | printk("FEC: No PHY device found.\n"); | |
2095 | /* Disable external MII interface */ | |
2096 | fecp->fec_mii_speed = fep->phy_speed = 0; | |
2097 | fec_disable_phy_intr(); | |
2098 | } | |
2099 | } | |
2100 | ||
2101 | /* This interrupt occurs when the PHY detects a link change. | |
2102 | */ | |
c1d96156 | 2103 | #ifdef HAVE_mii_link_interrupt |
1da177e4 LT |
2104 | #ifdef CONFIG_RPXCLASSIC |
2105 | static void | |
2106 | mii_link_interrupt(void *dev_id) | |
2107 | #else | |
2108 | static irqreturn_t | |
7d12e780 | 2109 | mii_link_interrupt(int irq, void * dev_id) |
1da177e4 LT |
2110 | #endif |
2111 | { | |
2112 | struct net_device *dev = dev_id; | |
2113 | struct fec_enet_private *fep = netdev_priv(dev); | |
2114 | ||
2115 | fec_phy_ack_intr(); | |
2116 | ||
2117 | #if 0 | |
2118 | disable_irq(fep->mii_irq); /* disable now, enable later */ | |
2119 | #endif | |
2120 | ||
2121 | mii_do_cmd(dev, fep->phy->ack_int); | |
2122 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | |
2123 | ||
2124 | return IRQ_HANDLED; | |
2125 | } | |
c1d96156 | 2126 | #endif |
1da177e4 LT |
2127 | |
2128 | static int | |
2129 | fec_enet_open(struct net_device *dev) | |
2130 | { | |
2131 | struct fec_enet_private *fep = netdev_priv(dev); | |
2132 | ||
2133 | /* I should reset the ring buffers here, but I don't yet know | |
2134 | * a simple way to do that. | |
2135 | */ | |
2136 | fec_set_mac_address(dev); | |
2137 | ||
2138 | fep->sequence_done = 0; | |
2139 | fep->link = 0; | |
2140 | ||
2141 | if (fep->phy) { | |
2142 | mii_do_cmd(dev, fep->phy->ack_int); | |
2143 | mii_do_cmd(dev, fep->phy->config); | |
2144 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | |
2145 | ||
6b265293 MW |
2146 | /* Poll until the PHY tells us its configuration |
2147 | * (not link state). | |
2148 | * Request is initiated by mii_do_cmd above, but answer | |
2149 | * comes by interrupt. | |
2150 | * This should take about 25 usec per register at 2.5 MHz, | |
2151 | * and we read approximately 5 registers. | |
1da177e4 LT |
2152 | */ |
2153 | while(!fep->sequence_done) | |
2154 | schedule(); | |
2155 | ||
2156 | mii_do_cmd(dev, fep->phy->startup); | |
2157 | ||
2158 | /* Set the initial link state to true. A lot of hardware | |
2159 | * based on this device does not implement a PHY interrupt, | |
2160 | * so we are never notified of link change. | |
2161 | */ | |
2162 | fep->link = 1; | |
2163 | } else { | |
2164 | fep->link = 1; /* lets just try it and see */ | |
2165 | /* no phy, go full duplex, it's most likely a hub chip */ | |
2166 | fec_restart(dev, 1); | |
2167 | } | |
2168 | ||
2169 | netif_start_queue(dev); | |
2170 | fep->opened = 1; | |
2171 | return 0; /* Success */ | |
2172 | } | |
2173 | ||
2174 | static int | |
2175 | fec_enet_close(struct net_device *dev) | |
2176 | { | |
2177 | struct fec_enet_private *fep = netdev_priv(dev); | |
2178 | ||
2179 | /* Don't know what to do yet. | |
2180 | */ | |
2181 | fep->opened = 0; | |
2182 | netif_stop_queue(dev); | |
2183 | fec_stop(dev); | |
2184 | ||
2185 | return 0; | |
2186 | } | |
2187 | ||
1da177e4 LT |
2188 | /* Set or clear the multicast filter for this adaptor. |
2189 | * Skeleton taken from sunlance driver. | |
2190 | * The CPM Ethernet implementation allows Multicast as well as individual | |
2191 | * MAC address filtering. Some of the drivers check to make sure it is | |
2192 | * a group multicast address, and discard those that are not. I guess I | |
2193 | * will do the same for now, but just remove the test if you want | |
2194 | * individual filtering as well (do the upper net layers want or support | |
2195 | * this kind of feature?). | |
2196 | */ | |
2197 | ||
2198 | #define HASH_BITS 6 /* #bits in hash */ | |
2199 | #define CRC32_POLY 0xEDB88320 | |
2200 | ||
2201 | static void set_multicast_list(struct net_device *dev) | |
2202 | { | |
2203 | struct fec_enet_private *fep; | |
2204 | volatile fec_t *ep; | |
2205 | struct dev_mc_list *dmi; | |
2206 | unsigned int i, j, bit, data, crc; | |
2207 | unsigned char hash; | |
2208 | ||
2209 | fep = netdev_priv(dev); | |
2210 | ep = fep->hwp; | |
2211 | ||
2212 | if (dev->flags&IFF_PROMISC) { | |
1da177e4 LT |
2213 | ep->fec_r_cntrl |= 0x0008; |
2214 | } else { | |
2215 | ||
2216 | ep->fec_r_cntrl &= ~0x0008; | |
2217 | ||
2218 | if (dev->flags & IFF_ALLMULTI) { | |
2219 | /* Catch all multicast addresses, so set the | |
2220 | * filter to all 1's. | |
2221 | */ | |
cc462f7d GU |
2222 | ep->fec_grp_hash_table_high = 0xffffffff; |
2223 | ep->fec_grp_hash_table_low = 0xffffffff; | |
1da177e4 LT |
2224 | } else { |
2225 | /* Clear filter and add the addresses in hash register. | |
2226 | */ | |
cc462f7d GU |
2227 | ep->fec_grp_hash_table_high = 0; |
2228 | ep->fec_grp_hash_table_low = 0; | |
6aa20a22 | 2229 | |
1da177e4 LT |
2230 | dmi = dev->mc_list; |
2231 | ||
2232 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) | |
2233 | { | |
2234 | /* Only support group multicast for now. | |
2235 | */ | |
2236 | if (!(dmi->dmi_addr[0] & 1)) | |
2237 | continue; | |
6aa20a22 | 2238 | |
1da177e4 LT |
2239 | /* calculate crc32 value of mac address |
2240 | */ | |
2241 | crc = 0xffffffff; | |
2242 | ||
2243 | for (i = 0; i < dmi->dmi_addrlen; i++) | |
2244 | { | |
2245 | data = dmi->dmi_addr[i]; | |
2246 | for (bit = 0; bit < 8; bit++, data >>= 1) | |
2247 | { | |
2248 | crc = (crc >> 1) ^ | |
2249 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
2250 | } | |
2251 | } | |
2252 | ||
2253 | /* only upper 6 bits (HASH_BITS) are used | |
2254 | which point to specific bit in he hash registers | |
2255 | */ | |
2256 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
6aa20a22 | 2257 | |
1da177e4 | 2258 | if (hash > 31) |
cc462f7d | 2259 | ep->fec_grp_hash_table_high |= 1 << (hash - 32); |
1da177e4 | 2260 | else |
cc462f7d | 2261 | ep->fec_grp_hash_table_low |= 1 << hash; |
1da177e4 LT |
2262 | } |
2263 | } | |
2264 | } | |
2265 | } | |
2266 | ||
2267 | /* Set a MAC change in hardware. | |
2268 | */ | |
2269 | static void | |
2270 | fec_set_mac_address(struct net_device *dev) | |
2271 | { | |
1da177e4 LT |
2272 | volatile fec_t *fecp; |
2273 | ||
7dd6a2aa | 2274 | fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp; |
1da177e4 LT |
2275 | |
2276 | /* Set station address. */ | |
7dd6a2aa GU |
2277 | fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
2278 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24); | |
2279 | fecp->fec_addr_high = (dev->dev_addr[5] << 16) | | |
2280 | (dev->dev_addr[4] << 24); | |
1da177e4 LT |
2281 | |
2282 | } | |
2283 | ||
2284 | /* Initialize the FEC Ethernet on 860T (or ColdFire 5272). | |
2285 | */ | |
2286 | /* | |
2287 | * XXX: We need to clean up on failure exits here. | |
2288 | */ | |
2289 | int __init fec_enet_init(struct net_device *dev) | |
2290 | { | |
2291 | struct fec_enet_private *fep = netdev_priv(dev); | |
2292 | unsigned long mem_addr; | |
2293 | volatile cbd_t *bdp; | |
2294 | cbd_t *cbd_base; | |
2295 | volatile fec_t *fecp; | |
2296 | int i, j; | |
2297 | static int index = 0; | |
2298 | ||
2299 | /* Only allow us to be probed once. */ | |
2300 | if (index >= FEC_MAX_PORTS) | |
2301 | return -ENXIO; | |
2302 | ||
562d2f8c GU |
2303 | /* Allocate memory for buffer descriptors. |
2304 | */ | |
2305 | mem_addr = __get_free_page(GFP_KERNEL); | |
2306 | if (mem_addr == 0) { | |
2307 | printk("FEC: allocate descriptor memory failed?\n"); | |
2308 | return -ENOMEM; | |
2309 | } | |
2310 | ||
1da177e4 LT |
2311 | /* Create an Ethernet device instance. |
2312 | */ | |
2313 | fecp = (volatile fec_t *) fec_hw[index]; | |
2314 | ||
2315 | fep->index = index; | |
2316 | fep->hwp = fecp; | |
cb84d6e7 | 2317 | fep->netdev = dev; |
1da177e4 LT |
2318 | |
2319 | /* Whack a reset. We should wait for this. | |
2320 | */ | |
2321 | fecp->fec_ecntrl = 1; | |
2322 | udelay(10); | |
2323 | ||
1da177e4 LT |
2324 | /* Set the Ethernet address. If using multiple Enets on the 8xx, |
2325 | * this needs some work to get unique addresses. | |
2326 | * | |
2327 | * This is our default MAC address unless the user changes | |
2328 | * it via eth_mac_addr (our dev->set_mac_addr handler). | |
2329 | */ | |
2330 | fec_get_mac(dev); | |
2331 | ||
1da177e4 LT |
2332 | cbd_base = (cbd_t *)mem_addr; |
2333 | /* XXX: missing check for allocation failure */ | |
2334 | ||
2335 | fec_uncache(mem_addr); | |
2336 | ||
2337 | /* Set receive and transmit descriptor base. | |
2338 | */ | |
2339 | fep->rx_bd_base = cbd_base; | |
2340 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
2341 | ||
2342 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2343 | fep->cur_rx = fep->rx_bd_base; | |
2344 | ||
2345 | fep->skb_cur = fep->skb_dirty = 0; | |
2346 | ||
2347 | /* Initialize the receive buffer descriptors. | |
2348 | */ | |
2349 | bdp = fep->rx_bd_base; | |
2350 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | |
2351 | ||
2352 | /* Allocate a page. | |
2353 | */ | |
2354 | mem_addr = __get_free_page(GFP_KERNEL); | |
2355 | /* XXX: missing check for allocation failure */ | |
2356 | ||
2357 | fec_uncache(mem_addr); | |
2358 | ||
2359 | /* Initialize the BD for every fragment in the page. | |
2360 | */ | |
2361 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { | |
2362 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2363 | bdp->cbd_bufaddr = __pa(mem_addr); | |
2364 | mem_addr += FEC_ENET_RX_FRSIZE; | |
2365 | bdp++; | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | /* Set the last buffer to wrap. | |
2370 | */ | |
2371 | bdp--; | |
2372 | bdp->cbd_sc |= BD_SC_WRAP; | |
2373 | ||
2374 | /* ...and the same for transmmit. | |
2375 | */ | |
2376 | bdp = fep->tx_bd_base; | |
2377 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { | |
2378 | if (j >= FEC_ENET_TX_FRPPG) { | |
2379 | mem_addr = __get_free_page(GFP_KERNEL); | |
2380 | j = 1; | |
2381 | } else { | |
2382 | mem_addr += FEC_ENET_TX_FRSIZE; | |
2383 | j++; | |
2384 | } | |
2385 | fep->tx_bounce[i] = (unsigned char *) mem_addr; | |
2386 | ||
2387 | /* Initialize the BD for every fragment in the page. | |
2388 | */ | |
2389 | bdp->cbd_sc = 0; | |
2390 | bdp->cbd_bufaddr = 0; | |
2391 | bdp++; | |
2392 | } | |
2393 | ||
2394 | /* Set the last buffer to wrap. | |
2395 | */ | |
2396 | bdp--; | |
2397 | bdp->cbd_sc |= BD_SC_WRAP; | |
2398 | ||
2399 | /* Set receive and transmit descriptor base. | |
2400 | */ | |
2401 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); | |
2402 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); | |
2403 | ||
2404 | /* Install our interrupt handlers. This varies depending on | |
2405 | * the architecture. | |
2406 | */ | |
2407 | fec_request_intrs(dev); | |
2408 | ||
cc462f7d GU |
2409 | fecp->fec_grp_hash_table_high = 0; |
2410 | fecp->fec_grp_hash_table_low = 0; | |
562d2f8c GU |
2411 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; |
2412 | fecp->fec_ecntrl = 2; | |
6b265293 | 2413 | fecp->fec_r_des_active = 0; |
cc462f7d GU |
2414 | #ifndef CONFIG_M5272 |
2415 | fecp->fec_hash_table_high = 0; | |
2416 | fecp->fec_hash_table_low = 0; | |
2417 | #endif | |
562d2f8c | 2418 | |
1da177e4 LT |
2419 | dev->base_addr = (unsigned long)fecp; |
2420 | ||
2421 | /* The FEC Ethernet specific entries in the device structure. */ | |
2422 | dev->open = fec_enet_open; | |
2423 | dev->hard_start_xmit = fec_enet_start_xmit; | |
2424 | dev->tx_timeout = fec_timeout; | |
2425 | dev->watchdog_timeo = TX_TIMEOUT; | |
2426 | dev->stop = fec_enet_close; | |
1da177e4 LT |
2427 | dev->set_multicast_list = set_multicast_list; |
2428 | ||
2429 | for (i=0; i<NMII-1; i++) | |
2430 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | |
2431 | mii_free = mii_cmds; | |
2432 | ||
2433 | /* setup MII interface */ | |
2434 | fec_set_mii(dev, fep); | |
2435 | ||
6b265293 MW |
2436 | /* Clear and enable interrupts */ |
2437 | fecp->fec_ievent = 0xffc00000; | |
398ec922 | 2438 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); |
6b265293 | 2439 | |
1da177e4 LT |
2440 | /* Queue up command to detect the PHY and initialize the |
2441 | * remainder of the interface. | |
2442 | */ | |
2443 | fep->phy_id_done = 0; | |
2444 | fep->phy_addr = 0; | |
2445 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | |
2446 | ||
2447 | index++; | |
2448 | return 0; | |
2449 | } | |
2450 | ||
2451 | /* This function is called to start or restart the FEC during a link | |
2452 | * change. This only happens when switching between half and full | |
2453 | * duplex. | |
2454 | */ | |
2455 | static void | |
2456 | fec_restart(struct net_device *dev, int duplex) | |
2457 | { | |
2458 | struct fec_enet_private *fep; | |
2459 | volatile cbd_t *bdp; | |
2460 | volatile fec_t *fecp; | |
2461 | int i; | |
2462 | ||
2463 | fep = netdev_priv(dev); | |
2464 | fecp = fep->hwp; | |
2465 | ||
2466 | /* Whack a reset. We should wait for this. | |
2467 | */ | |
2468 | fecp->fec_ecntrl = 1; | |
2469 | udelay(10); | |
2470 | ||
1da177e4 LT |
2471 | /* Clear any outstanding interrupt. |
2472 | */ | |
7dd6a2aa | 2473 | fecp->fec_ievent = 0xffc00000; |
1da177e4 LT |
2474 | fec_enable_phy_intr(); |
2475 | ||
2476 | /* Set station address. | |
2477 | */ | |
7dd6a2aa | 2478 | fec_set_mac_address(dev); |
1da177e4 LT |
2479 | |
2480 | /* Reset all multicast. | |
2481 | */ | |
cc462f7d GU |
2482 | fecp->fec_grp_hash_table_high = 0; |
2483 | fecp->fec_grp_hash_table_low = 0; | |
1da177e4 LT |
2484 | |
2485 | /* Set maximum receive buffer size. | |
2486 | */ | |
2487 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | |
2488 | ||
2489 | fec_localhw_setup(); | |
2490 | ||
2491 | /* Set receive and transmit descriptor base. | |
2492 | */ | |
2493 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); | |
2494 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); | |
2495 | ||
2496 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2497 | fep->cur_rx = fep->rx_bd_base; | |
2498 | ||
2499 | /* Reset SKB transmit buffers. | |
2500 | */ | |
2501 | fep->skb_cur = fep->skb_dirty = 0; | |
2502 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | |
2503 | if (fep->tx_skbuff[i] != NULL) { | |
2504 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
2505 | fep->tx_skbuff[i] = NULL; | |
2506 | } | |
2507 | } | |
2508 | ||
2509 | /* Initialize the receive buffer descriptors. | |
2510 | */ | |
2511 | bdp = fep->rx_bd_base; | |
2512 | for (i=0; i<RX_RING_SIZE; i++) { | |
2513 | ||
2514 | /* Initialize the BD for every fragment in the page. | |
2515 | */ | |
2516 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2517 | bdp++; | |
2518 | } | |
2519 | ||
2520 | /* Set the last buffer to wrap. | |
2521 | */ | |
2522 | bdp--; | |
2523 | bdp->cbd_sc |= BD_SC_WRAP; | |
2524 | ||
2525 | /* ...and the same for transmmit. | |
2526 | */ | |
2527 | bdp = fep->tx_bd_base; | |
2528 | for (i=0; i<TX_RING_SIZE; i++) { | |
2529 | ||
2530 | /* Initialize the BD for every fragment in the page. | |
2531 | */ | |
2532 | bdp->cbd_sc = 0; | |
2533 | bdp->cbd_bufaddr = 0; | |
2534 | bdp++; | |
2535 | } | |
2536 | ||
2537 | /* Set the last buffer to wrap. | |
2538 | */ | |
2539 | bdp--; | |
2540 | bdp->cbd_sc |= BD_SC_WRAP; | |
2541 | ||
2542 | /* Enable MII mode. | |
2543 | */ | |
2544 | if (duplex) { | |
2545 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */ | |
2546 | fecp->fec_x_cntrl = 0x04; /* FD enable */ | |
f909b1ef | 2547 | } else { |
1da177e4 LT |
2548 | /* MII enable|No Rcv on Xmit */ |
2549 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06; | |
2550 | fecp->fec_x_cntrl = 0x00; | |
2551 | } | |
2552 | fep->full_duplex = duplex; | |
2553 | ||
2554 | /* Set MII speed. | |
2555 | */ | |
2556 | fecp->fec_mii_speed = fep->phy_speed; | |
2557 | ||
2558 | /* And last, enable the transmit and receive processing. | |
2559 | */ | |
2560 | fecp->fec_ecntrl = 2; | |
6b265293 MW |
2561 | fecp->fec_r_des_active = 0; |
2562 | ||
2563 | /* Enable interrupts we wish to service. | |
2564 | */ | |
398ec922 | 2565 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); |
1da177e4 LT |
2566 | } |
2567 | ||
2568 | static void | |
2569 | fec_stop(struct net_device *dev) | |
2570 | { | |
2571 | volatile fec_t *fecp; | |
2572 | struct fec_enet_private *fep; | |
2573 | ||
2574 | fep = netdev_priv(dev); | |
2575 | fecp = fep->hwp; | |
2576 | ||
677177c5 PDM |
2577 | /* |
2578 | ** We cannot expect a graceful transmit stop without link !!! | |
2579 | */ | |
2580 | if (fep->link) | |
2581 | { | |
2582 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ | |
2583 | udelay(10); | |
2584 | if (!(fecp->fec_ievent & FEC_ENET_GRA)) | |
2585 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
2586 | } | |
1da177e4 LT |
2587 | |
2588 | /* Whack a reset. We should wait for this. | |
2589 | */ | |
2590 | fecp->fec_ecntrl = 1; | |
2591 | udelay(10); | |
2592 | ||
2593 | /* Clear outstanding MII command interrupts. | |
2594 | */ | |
2595 | fecp->fec_ievent = FEC_ENET_MII; | |
2596 | fec_enable_phy_intr(); | |
2597 | ||
2598 | fecp->fec_imask = FEC_ENET_MII; | |
2599 | fecp->fec_mii_speed = fep->phy_speed; | |
2600 | } | |
2601 | ||
2602 | static int __init fec_enet_module_init(void) | |
2603 | { | |
2604 | struct net_device *dev; | |
c1d96156 | 2605 | int i, err; |
0795af57 | 2606 | DECLARE_MAC_BUF(mac); |
7dd6a2aa GU |
2607 | |
2608 | printk("FEC ENET Version 0.2\n"); | |
1da177e4 LT |
2609 | |
2610 | for (i = 0; (i < FEC_MAX_PORTS); i++) { | |
2611 | dev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
2612 | if (!dev) | |
2613 | return -ENOMEM; | |
2614 | err = fec_enet_init(dev); | |
2615 | if (err) { | |
2616 | free_netdev(dev); | |
2617 | continue; | |
2618 | } | |
2619 | if (register_netdev(dev) != 0) { | |
2620 | /* XXX: missing cleanup here */ | |
2621 | free_netdev(dev); | |
2622 | return -EIO; | |
2623 | } | |
7dd6a2aa | 2624 | |
0795af57 JP |
2625 | printk("%s: ethernet %s\n", |
2626 | dev->name, print_mac(mac, dev->dev_addr)); | |
1da177e4 LT |
2627 | } |
2628 | return 0; | |
2629 | } | |
2630 | ||
2631 | module_init(fec_enet_module_init); | |
2632 | ||
2633 | MODULE_LICENSE("GPL"); |