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5d031e9e DP |
1 | /* |
2 | * drivers/drivers/net/fec_mpc52xx/fec.h | |
3 | * | |
4 | * Driver for the MPC5200 Fast Ethernet Controller | |
5 | * | |
6 | * Author: Dale Farnsworth <dfarnsworth@mvista.com> | |
7 | * | |
8 | * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under | |
9 | * the terms of the GNU General Public License version 2. This program | |
10 | * is licensed "as is" without any warranty of any kind, whether express | |
11 | * or implied. | |
12 | */ | |
13 | ||
14 | #ifndef __DRIVERS_NET_MPC52XX_FEC_H__ | |
15 | #define __DRIVERS_NET_MPC52XX_FEC_H__ | |
16 | ||
17 | #include <linux/phy.h> | |
18 | ||
19 | /* Tunable constant */ | |
20 | /* FEC_RX_BUFFER_SIZE includes 4 bytes for CRC32 */ | |
21 | #define FEC_RX_BUFFER_SIZE 1522 /* max receive packet size */ | |
22 | #define FEC_RX_NUM_BD 256 | |
23 | #define FEC_TX_NUM_BD 64 | |
24 | ||
25 | #define FEC_RESET_DELAY 50 /* uS */ | |
26 | ||
27 | #define FEC_WATCHDOG_TIMEOUT ((400*HZ)/1000) | |
28 | ||
5d031e9e DP |
29 | /* ======================================================================== */ |
30 | /* Hardware register sets & bits */ | |
31 | /* ======================================================================== */ | |
32 | ||
33 | struct mpc52xx_fec { | |
34 | u32 fec_id; /* FEC + 0x000 */ | |
35 | u32 ievent; /* FEC + 0x004 */ | |
36 | u32 imask; /* FEC + 0x008 */ | |
37 | ||
38 | u32 reserved0[1]; /* FEC + 0x00C */ | |
39 | u32 r_des_active; /* FEC + 0x010 */ | |
40 | u32 x_des_active; /* FEC + 0x014 */ | |
41 | u32 r_des_active_cl; /* FEC + 0x018 */ | |
42 | u32 x_des_active_cl; /* FEC + 0x01C */ | |
43 | u32 ivent_set; /* FEC + 0x020 */ | |
44 | u32 ecntrl; /* FEC + 0x024 */ | |
45 | ||
46 | u32 reserved1[6]; /* FEC + 0x028-03C */ | |
47 | u32 mii_data; /* FEC + 0x040 */ | |
48 | u32 mii_speed; /* FEC + 0x044 */ | |
49 | u32 mii_status; /* FEC + 0x048 */ | |
50 | ||
51 | u32 reserved2[5]; /* FEC + 0x04C-05C */ | |
52 | u32 mib_data; /* FEC + 0x060 */ | |
53 | u32 mib_control; /* FEC + 0x064 */ | |
54 | ||
55 | u32 reserved3[6]; /* FEC + 0x068-7C */ | |
56 | u32 r_activate; /* FEC + 0x080 */ | |
57 | u32 r_cntrl; /* FEC + 0x084 */ | |
58 | u32 r_hash; /* FEC + 0x088 */ | |
59 | u32 r_data; /* FEC + 0x08C */ | |
60 | u32 ar_done; /* FEC + 0x090 */ | |
61 | u32 r_test; /* FEC + 0x094 */ | |
62 | u32 r_mib; /* FEC + 0x098 */ | |
63 | u32 r_da_low; /* FEC + 0x09C */ | |
64 | u32 r_da_high; /* FEC + 0x0A0 */ | |
65 | ||
66 | u32 reserved4[7]; /* FEC + 0x0A4-0BC */ | |
67 | u32 x_activate; /* FEC + 0x0C0 */ | |
68 | u32 x_cntrl; /* FEC + 0x0C4 */ | |
69 | u32 backoff; /* FEC + 0x0C8 */ | |
70 | u32 x_data; /* FEC + 0x0CC */ | |
71 | u32 x_status; /* FEC + 0x0D0 */ | |
72 | u32 x_mib; /* FEC + 0x0D4 */ | |
73 | u32 x_test; /* FEC + 0x0D8 */ | |
74 | u32 fdxfc_da1; /* FEC + 0x0DC */ | |
75 | u32 fdxfc_da2; /* FEC + 0x0E0 */ | |
76 | u32 paddr1; /* FEC + 0x0E4 */ | |
77 | u32 paddr2; /* FEC + 0x0E8 */ | |
78 | u32 op_pause; /* FEC + 0x0EC */ | |
79 | ||
80 | u32 reserved5[4]; /* FEC + 0x0F0-0FC */ | |
81 | u32 instr_reg; /* FEC + 0x100 */ | |
82 | u32 context_reg; /* FEC + 0x104 */ | |
83 | u32 test_cntrl; /* FEC + 0x108 */ | |
84 | u32 acc_reg; /* FEC + 0x10C */ | |
85 | u32 ones; /* FEC + 0x110 */ | |
86 | u32 zeros; /* FEC + 0x114 */ | |
87 | u32 iaddr1; /* FEC + 0x118 */ | |
88 | u32 iaddr2; /* FEC + 0x11C */ | |
89 | u32 gaddr1; /* FEC + 0x120 */ | |
90 | u32 gaddr2; /* FEC + 0x124 */ | |
91 | u32 random; /* FEC + 0x128 */ | |
92 | u32 rand1; /* FEC + 0x12C */ | |
93 | u32 tmp; /* FEC + 0x130 */ | |
94 | ||
95 | u32 reserved6[3]; /* FEC + 0x134-13C */ | |
96 | u32 fifo_id; /* FEC + 0x140 */ | |
97 | u32 x_wmrk; /* FEC + 0x144 */ | |
98 | u32 fcntrl; /* FEC + 0x148 */ | |
99 | u32 r_bound; /* FEC + 0x14C */ | |
100 | u32 r_fstart; /* FEC + 0x150 */ | |
101 | u32 r_count; /* FEC + 0x154 */ | |
102 | u32 r_lag; /* FEC + 0x158 */ | |
103 | u32 r_read; /* FEC + 0x15C */ | |
104 | u32 r_write; /* FEC + 0x160 */ | |
105 | u32 x_count; /* FEC + 0x164 */ | |
106 | u32 x_lag; /* FEC + 0x168 */ | |
107 | u32 x_retry; /* FEC + 0x16C */ | |
108 | u32 x_write; /* FEC + 0x170 */ | |
109 | u32 x_read; /* FEC + 0x174 */ | |
110 | ||
111 | u32 reserved7[2]; /* FEC + 0x178-17C */ | |
112 | u32 fm_cntrl; /* FEC + 0x180 */ | |
113 | u32 rfifo_data; /* FEC + 0x184 */ | |
114 | u32 rfifo_status; /* FEC + 0x188 */ | |
115 | u32 rfifo_cntrl; /* FEC + 0x18C */ | |
116 | u32 rfifo_lrf_ptr; /* FEC + 0x190 */ | |
117 | u32 rfifo_lwf_ptr; /* FEC + 0x194 */ | |
118 | u32 rfifo_alarm; /* FEC + 0x198 */ | |
119 | u32 rfifo_rdptr; /* FEC + 0x19C */ | |
120 | u32 rfifo_wrptr; /* FEC + 0x1A0 */ | |
121 | u32 tfifo_data; /* FEC + 0x1A4 */ | |
122 | u32 tfifo_status; /* FEC + 0x1A8 */ | |
123 | u32 tfifo_cntrl; /* FEC + 0x1AC */ | |
124 | u32 tfifo_lrf_ptr; /* FEC + 0x1B0 */ | |
125 | u32 tfifo_lwf_ptr; /* FEC + 0x1B4 */ | |
126 | u32 tfifo_alarm; /* FEC + 0x1B8 */ | |
127 | u32 tfifo_rdptr; /* FEC + 0x1BC */ | |
128 | u32 tfifo_wrptr; /* FEC + 0x1C0 */ | |
129 | ||
130 | u32 reset_cntrl; /* FEC + 0x1C4 */ | |
131 | u32 xmit_fsm; /* FEC + 0x1C8 */ | |
132 | ||
133 | u32 reserved8[3]; /* FEC + 0x1CC-1D4 */ | |
134 | u32 rdes_data0; /* FEC + 0x1D8 */ | |
135 | u32 rdes_data1; /* FEC + 0x1DC */ | |
136 | u32 r_length; /* FEC + 0x1E0 */ | |
137 | u32 x_length; /* FEC + 0x1E4 */ | |
138 | u32 x_addr; /* FEC + 0x1E8 */ | |
139 | u32 cdes_data; /* FEC + 0x1EC */ | |
140 | u32 status; /* FEC + 0x1F0 */ | |
141 | u32 dma_control; /* FEC + 0x1F4 */ | |
142 | u32 des_cmnd; /* FEC + 0x1F8 */ | |
143 | u32 data; /* FEC + 0x1FC */ | |
144 | ||
145 | u32 rmon_t_drop; /* FEC + 0x200 */ | |
146 | u32 rmon_t_packets; /* FEC + 0x204 */ | |
147 | u32 rmon_t_bc_pkt; /* FEC + 0x208 */ | |
148 | u32 rmon_t_mc_pkt; /* FEC + 0x20C */ | |
149 | u32 rmon_t_crc_align; /* FEC + 0x210 */ | |
150 | u32 rmon_t_undersize; /* FEC + 0x214 */ | |
151 | u32 rmon_t_oversize; /* FEC + 0x218 */ | |
152 | u32 rmon_t_frag; /* FEC + 0x21C */ | |
153 | u32 rmon_t_jab; /* FEC + 0x220 */ | |
154 | u32 rmon_t_col; /* FEC + 0x224 */ | |
155 | u32 rmon_t_p64; /* FEC + 0x228 */ | |
156 | u32 rmon_t_p65to127; /* FEC + 0x22C */ | |
157 | u32 rmon_t_p128to255; /* FEC + 0x230 */ | |
158 | u32 rmon_t_p256to511; /* FEC + 0x234 */ | |
159 | u32 rmon_t_p512to1023; /* FEC + 0x238 */ | |
160 | u32 rmon_t_p1024to2047; /* FEC + 0x23C */ | |
161 | u32 rmon_t_p_gte2048; /* FEC + 0x240 */ | |
162 | u32 rmon_t_octets; /* FEC + 0x244 */ | |
163 | u32 ieee_t_drop; /* FEC + 0x248 */ | |
164 | u32 ieee_t_frame_ok; /* FEC + 0x24C */ | |
165 | u32 ieee_t_1col; /* FEC + 0x250 */ | |
166 | u32 ieee_t_mcol; /* FEC + 0x254 */ | |
167 | u32 ieee_t_def; /* FEC + 0x258 */ | |
168 | u32 ieee_t_lcol; /* FEC + 0x25C */ | |
169 | u32 ieee_t_excol; /* FEC + 0x260 */ | |
170 | u32 ieee_t_macerr; /* FEC + 0x264 */ | |
171 | u32 ieee_t_cserr; /* FEC + 0x268 */ | |
172 | u32 ieee_t_sqe; /* FEC + 0x26C */ | |
173 | u32 t_fdxfc; /* FEC + 0x270 */ | |
174 | u32 ieee_t_octets_ok; /* FEC + 0x274 */ | |
175 | ||
176 | u32 reserved9[2]; /* FEC + 0x278-27C */ | |
177 | u32 rmon_r_drop; /* FEC + 0x280 */ | |
178 | u32 rmon_r_packets; /* FEC + 0x284 */ | |
179 | u32 rmon_r_bc_pkt; /* FEC + 0x288 */ | |
180 | u32 rmon_r_mc_pkt; /* FEC + 0x28C */ | |
181 | u32 rmon_r_crc_align; /* FEC + 0x290 */ | |
182 | u32 rmon_r_undersize; /* FEC + 0x294 */ | |
183 | u32 rmon_r_oversize; /* FEC + 0x298 */ | |
184 | u32 rmon_r_frag; /* FEC + 0x29C */ | |
185 | u32 rmon_r_jab; /* FEC + 0x2A0 */ | |
186 | ||
187 | u32 rmon_r_resvd_0; /* FEC + 0x2A4 */ | |
188 | ||
189 | u32 rmon_r_p64; /* FEC + 0x2A8 */ | |
190 | u32 rmon_r_p65to127; /* FEC + 0x2AC */ | |
191 | u32 rmon_r_p128to255; /* FEC + 0x2B0 */ | |
192 | u32 rmon_r_p256to511; /* FEC + 0x2B4 */ | |
193 | u32 rmon_r_p512to1023; /* FEC + 0x2B8 */ | |
194 | u32 rmon_r_p1024to2047; /* FEC + 0x2BC */ | |
195 | u32 rmon_r_p_gte2048; /* FEC + 0x2C0 */ | |
196 | u32 rmon_r_octets; /* FEC + 0x2C4 */ | |
197 | u32 ieee_r_drop; /* FEC + 0x2C8 */ | |
198 | u32 ieee_r_frame_ok; /* FEC + 0x2CC */ | |
199 | u32 ieee_r_crc; /* FEC + 0x2D0 */ | |
200 | u32 ieee_r_align; /* FEC + 0x2D4 */ | |
201 | u32 r_macerr; /* FEC + 0x2D8 */ | |
202 | u32 r_fdxfc; /* FEC + 0x2DC */ | |
203 | u32 ieee_r_octets_ok; /* FEC + 0x2E0 */ | |
204 | ||
205 | u32 reserved10[7]; /* FEC + 0x2E4-2FC */ | |
206 | ||
207 | u32 reserved11[64]; /* FEC + 0x300-3FF */ | |
208 | }; | |
209 | ||
210 | #define FEC_MIB_DISABLE 0x80000000 | |
211 | ||
212 | #define FEC_IEVENT_HBERR 0x80000000 | |
213 | #define FEC_IEVENT_BABR 0x40000000 | |
214 | #define FEC_IEVENT_BABT 0x20000000 | |
215 | #define FEC_IEVENT_GRA 0x10000000 | |
216 | #define FEC_IEVENT_TFINT 0x08000000 | |
217 | #define FEC_IEVENT_MII 0x00800000 | |
218 | #define FEC_IEVENT_LATE_COL 0x00200000 | |
219 | #define FEC_IEVENT_COL_RETRY_LIM 0x00100000 | |
220 | #define FEC_IEVENT_XFIFO_UN 0x00080000 | |
221 | #define FEC_IEVENT_XFIFO_ERROR 0x00040000 | |
222 | #define FEC_IEVENT_RFIFO_ERROR 0x00020000 | |
223 | ||
224 | #define FEC_IMASK_HBERR 0x80000000 | |
225 | #define FEC_IMASK_BABR 0x40000000 | |
226 | #define FEC_IMASK_BABT 0x20000000 | |
227 | #define FEC_IMASK_GRA 0x10000000 | |
228 | #define FEC_IMASK_MII 0x00800000 | |
229 | #define FEC_IMASK_LATE_COL 0x00200000 | |
230 | #define FEC_IMASK_COL_RETRY_LIM 0x00100000 | |
231 | #define FEC_IMASK_XFIFO_UN 0x00080000 | |
232 | #define FEC_IMASK_XFIFO_ERROR 0x00040000 | |
233 | #define FEC_IMASK_RFIFO_ERROR 0x00020000 | |
234 | ||
235 | /* all but MII, which is enabled separately */ | |
236 | #define FEC_IMASK_ENABLE (FEC_IMASK_HBERR | FEC_IMASK_BABR | \ | |
237 | FEC_IMASK_BABT | FEC_IMASK_GRA | FEC_IMASK_LATE_COL | \ | |
238 | FEC_IMASK_COL_RETRY_LIM | FEC_IMASK_XFIFO_UN | \ | |
239 | FEC_IMASK_XFIFO_ERROR | FEC_IMASK_RFIFO_ERROR) | |
240 | ||
241 | #define FEC_RCNTRL_MAX_FL_SHIFT 16 | |
242 | #define FEC_RCNTRL_LOOP 0x01 | |
243 | #define FEC_RCNTRL_DRT 0x02 | |
244 | #define FEC_RCNTRL_MII_MODE 0x04 | |
245 | #define FEC_RCNTRL_PROM 0x08 | |
246 | #define FEC_RCNTRL_BC_REJ 0x10 | |
247 | #define FEC_RCNTRL_FCE 0x20 | |
248 | ||
249 | #define FEC_TCNTRL_GTS 0x00000001 | |
250 | #define FEC_TCNTRL_HBC 0x00000002 | |
251 | #define FEC_TCNTRL_FDEN 0x00000004 | |
252 | #define FEC_TCNTRL_TFC_PAUSE 0x00000008 | |
253 | #define FEC_TCNTRL_RFC_PAUSE 0x00000010 | |
254 | ||
255 | #define FEC_ECNTRL_RESET 0x00000001 | |
256 | #define FEC_ECNTRL_ETHER_EN 0x00000002 | |
257 | ||
258 | #define FEC_MII_DATA_ST 0x40000000 /* Start frame */ | |
259 | #define FEC_MII_DATA_OP_RD 0x20000000 /* Perform read */ | |
260 | #define FEC_MII_DATA_OP_WR 0x10000000 /* Perform write */ | |
261 | #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address mask */ | |
262 | #define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register mask */ | |
263 | #define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ | |
264 | #define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data mask */ | |
265 | ||
266 | #define FEC_MII_READ_FRAME (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA) | |
267 | #define FEC_MII_WRITE_FRAME (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | FEC_MII_DATA_TA) | |
268 | ||
269 | #define FEC_MII_DATA_RA_SHIFT 0x12 /* MII reg addr bits */ | |
270 | #define FEC_MII_DATA_PA_SHIFT 0x17 /* MII PHY addr bits */ | |
271 | ||
272 | #define FEC_PADDR2_TYPE 0x8808 | |
273 | ||
274 | #define FEC_OP_PAUSE_OPCODE 0x00010000 | |
275 | ||
276 | #define FEC_FIFO_WMRK_256B 0x3 | |
277 | ||
278 | #define FEC_FIFO_STATUS_ERR 0x00400000 | |
279 | #define FEC_FIFO_STATUS_UF 0x00200000 | |
280 | #define FEC_FIFO_STATUS_OF 0x00100000 | |
281 | ||
282 | #define FEC_FIFO_CNTRL_FRAME 0x08000000 | |
283 | #define FEC_FIFO_CNTRL_LTG_7 0x07000000 | |
284 | ||
285 | #define FEC_RESET_CNTRL_RESET_FIFO 0x02000000 | |
286 | #define FEC_RESET_CNTRL_ENABLE_IS_RESET 0x01000000 | |
287 | ||
288 | #define FEC_XMIT_FSM_APPEND_CRC 0x02000000 | |
289 | #define FEC_XMIT_FSM_ENABLE_CRC 0x01000000 | |
290 | ||
291 | ||
292 | extern struct of_platform_driver mpc52xx_fec_mdio_driver; | |
293 | ||
294 | #endif /* __DRIVERS_NET_MPC52XX_FEC_H__ */ |