projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8cdc3f6c TI |
1 | /* |
| 2 | * FUJITSU Extended Socket Network Device driver | |
| 3 | * Copyright (c) 2015 FUJITSU LIMITED | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms and conditions of the GNU General Public License, | |
| 7 | * version 2, as published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License along with | |
| 15 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
| 16 | * | |
| 17 | * The full GNU General Public License is included in this distribution in | |
| 18 | * the file called "COPYING". | |
| 19 | * | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef FJES_REGS_H_ | |
| 23 | #define FJES_REGS_H_ | |
| 24 | ||
| 25 | #include <linux/bitops.h> | |
| 26 | ||
| 27 | #define XSCT_DEVICE_REGISTER_SIZE 0x1000 | |
| 28 | ||
| 29 | /* register offset */ | |
| 30 | /* Information registers */ | |
| 31 | #define XSCT_OWNER_EPID 0x0000 /* Owner EPID */ | |
| 32 | #define XSCT_MAX_EP 0x0004 /* Maximum EP */ | |
| 33 | ||
| 34 | /* Device Control registers */ | |
| 35 | #define XSCT_DCTL 0x0010 /* Device Control */ | |
| 36 | ||
| 37 | /* Command Control registers */ | |
| 38 | #define XSCT_SHSTSAL 0x0028 /* Share status address Low */ | |
| 39 | #define XSCT_SHSTSAH 0x002C /* Share status address High */ | |
| 40 | ||
| 41 | #define XSCT_REQBL 0x0034 /* Request Buffer length */ | |
| 42 | #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */ | |
| 43 | #define XSCT_REQBAH 0x003C /* Request Buffer Address High */ | |
| 44 | ||
| 45 | #define XSCT_RESPBL 0x0044 /* Response Buffer Length */ | |
| 46 | #define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */ | |
| 47 | #define XSCT_RESPBAH 0x004C /* Response Buffer Address High */ | |
| 48 | ||
| 49 | /* Interrupt Control registers */ | |
| 50 | #define XSCT_IMS 0x0084 /* Interrupt mask set */ | |
| 51 | #define XSCT_IMC 0x0088 /* Interrupt mask clear */ | |
| 52 | ||
| 53 | /* register structure */ | |
| 54 | /* Information registers */ | |
| 55 | union REG_OWNER_EPID { | |
| 56 | struct { | |
| 57 | __le32 epid:16; | |
| 58 | __le32:16; | |
| 59 | } bits; | |
| 60 | __le32 reg; | |
| 61 | }; | |
| 62 | ||
| 63 | union REG_MAX_EP { | |
| 64 | struct { | |
| 65 | __le32 maxep:16; | |
| 66 | __le32:16; | |
| 67 | } bits; | |
| 68 | __le32 reg; | |
| 69 | }; | |
| 70 | ||
| 71 | /* Device Control registers */ | |
| 72 | union REG_DCTL { | |
| 73 | struct { | |
| 74 | __le32 reset:1; | |
| 75 | __le32 rsv0:15; | |
| 76 | __le32 rsv1:16; | |
| 77 | } bits; | |
| 78 | __le32 reg; | |
| 79 | }; | |
| 80 | ||
| 81 | enum REG_ICTL_MASK { | |
| 82 | REG_ICTL_MASK_INFO_UPDATE = 1 << 20, | |
| 83 | REG_ICTL_MASK_DEV_STOP_REQ = 1 << 19, | |
| 84 | REG_ICTL_MASK_TXRX_STOP_REQ = 1 << 18, | |
| 85 | REG_ICTL_MASK_TXRX_STOP_DONE = 1 << 17, | |
| 86 | REG_ICTL_MASK_RX_DATA = 1 << 16, | |
| 87 | REG_ICTL_MASK_ALL = GENMASK(20, 16), | |
| 88 | }; | |
| 89 | ||
| 90 | struct fjes_hw; | |
| 91 | ||
| 92 | u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg); | |
| 93 | ||
| 94 | #define wr32(reg, val) \ | |
| 95 | do { \ | |
| 96 | u8 *base = hw->base; \ | |
| 97 | writel((val), &base[(reg)]); \ | |
| 98 | } while (0) | |
| 99 | ||
| 100 | #define rd32(reg) (fjes_hw_rd32(hw, reg)) | |
| 101 | ||
| 102 | #endif /* FJES_REGS_H_ */ |