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fs_enet: Include linux/string.h from linux/fs_enet_pd.h
[deliverable/linux.git] / drivers / net / fs_enet / mac-fcc.c
CommitLineData
48257c4f
PA		 1/*
2 * FCC driver for Motorola MPC82xx (PQ2).
3 *
9b8ee8e7 4 * Copyright (c) 2003 Intracom S.A.
48257c4f
PA		 5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
9b8ee8e7 7 * 2005 (c) MontaVista Software, Inc.
48257c4f
PA		 8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
9b8ee8e7
VB		 10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
48257c4f
PA		 12 * kind, whether express or implied.
13 */
14
48257c4f
PA		 15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
48257c4f
PA		 18#include <linux/string.h>
19#include <linux/ptrace.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/interrupt.h>
48257c4f
PA		 24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/spinlock.h>
30#include <linux/mii.h>
31#include <linux/ethtool.h>
32#include <linux/bitops.h>
33#include <linux/fs.h>
f7b99969 34#include <linux/platform_device.h>
5b4b8454 35#include <linux/phy.h>
48257c4f
PA		 36
37#include <asm/immap_cpm2.h>
38#include <asm/mpc8260.h>
39#include <asm/cpm2.h>
40
41#include <asm/pgtable.h>
42#include <asm/irq.h>
43#include <asm/uaccess.h>
44
45#include "fs_enet.h"
46
47/*************************************************/
48
49/* FCC access macros */
50
51#define __fcc_out32(addr, x) out_be32((unsigned *)addr, x)
52#define __fcc_out16(addr, x) out_be16((unsigned short *)addr, x)
53#define __fcc_out8(addr, x) out_8((unsigned char *)addr, x)
54#define __fcc_in32(addr) in_be32((unsigned *)addr)
55#define __fcc_in16(addr) in_be16((unsigned short *)addr)
56#define __fcc_in8(addr) in_8((unsigned char *)addr)
57
58/* parameter space */
59
60/* write, read, set bits, clear bits */
61#define W32(_p, _m, _v) __fcc_out32(&(_p)->_m, (_v))
62#define R32(_p, _m) __fcc_in32(&(_p)->_m)
63#define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
64#define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
65
66#define W16(_p, _m, _v) __fcc_out16(&(_p)->_m, (_v))
67#define R16(_p, _m) __fcc_in16(&(_p)->_m)
68#define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
69#define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
70
71#define W8(_p, _m, _v) __fcc_out8(&(_p)->_m, (_v))
72#define R8(_p, _m) __fcc_in8(&(_p)->_m)
73#define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
74#define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
75
76/*************************************************/
77
78#define FCC_MAX_MULTICAST_ADDRS 64
79
80#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
81#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
82#define mk_mii_end 0
83
84#define MAX_CR_CMD_LOOPS 10000
85
86static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 mcn, u32 op)
87{
88 const struct fs_platform_info *fpi = fep->fpi;
48257c4f
PA		 89 cpm2_map_t *immap = fs_enet_immap;
90 cpm_cpm2_t *cpmp = &immap->im_cpm;
91 u32 v;
92 int i;
93
9b8ee8e7 94 /* Currently I don't know what feature call will look like. But
48257c4f
PA		 95 I guess there'd be something like do_cpm_cmd() which will require page & sblock */
96 v = mk_cr_cmd(fpi->cp_page, fpi->cp_block, mcn, op);
97 W32(cpmp, cp_cpcr, v | CPM_CR_FLG);
98 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
99 if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
100 break;
101
102 if (i >= MAX_CR_CMD_LOOPS) {
103 printk(KERN_ERR "%s(): Not able to issue CPM command\n",
104 __FUNCTION__);
105 return 1;
106 }
107
108 return 0;
109}
110
111static int do_pd_setup(struct fs_enet_private *fep)
112{
113 struct platform_device *pdev = to_platform_device(fep->dev);
114 struct resource *r;
115
116 /* Fill out IRQ field */
117 fep->interrupt = platform_get_irq(pdev, 0);
48944738
DV		 118 if (fep->interrupt < 0)
119 return -EINVAL;
48257c4f
PA		 120
121 /* Attach the memory for the FCC Parameter RAM */
122 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
5b4b8454 123 fep->fcc.ep = (void *)ioremap(r->start, r->end - r->start + 1);
48257c4f
PA		 124 if (fep->fcc.ep == NULL)
125 return -EINVAL;
126
127 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
5b4b8454 128 fep->fcc.fccp = (void *)ioremap(r->start, r->end - r->start + 1);
48257c4f
PA		 129 if (fep->fcc.fccp == NULL)
130 return -EINVAL;
131
5b4b8454
VB		 132 if (fep->fpi->fcc_regs_c) {
133
134 fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
135 } else {
136 r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
137 "fcc_regs_c");
138 fep->fcc.fcccp = (void *)ioremap(r->start,
139 r->end - r->start + 1);
140 }
48257c4f
PA		 141
142 if (fep->fcc.fcccp == NULL)
143 return -EINVAL;
144
5b4b8454
VB		 145 fep->fcc.mem = (void *)fep->fpi->mem_offset;
146 if (fep->fcc.mem == NULL)
147 return -EINVAL;
148
48257c4f
PA		 149 return 0;
150}
151
152#define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
153#define FCC_RX_EVENT (FCC_ENET_RXF)
154#define FCC_TX_EVENT (FCC_ENET_TXB)
155#define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY)
156
157static int setup_data(struct net_device *dev)
158{
159 struct fs_enet_private *fep = netdev_priv(dev);
160 const struct fs_platform_info *fpi = fep->fpi;
161
162 fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
163 if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
164 return -EINVAL;
165
48257c4f
PA		 166 if (do_pd_setup(fep) != 0)
167 return -EINVAL;
168
169 fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
170 fep->ev_rx = FCC_RX_EVENT;
171 fep->ev_tx = FCC_TX_EVENT;
172 fep->ev_err = FCC_ERR_EVENT_MSK;
173
174 return 0;
175}
176
177static int allocate_bd(struct net_device *dev)
178{
179 struct fs_enet_private *fep = netdev_priv(dev);
180 const struct fs_platform_info *fpi = fep->fpi;
181
182 fep->ring_base = dma_alloc_coherent(fep->dev,
183 (fpi->tx_ring + fpi->rx_ring) *
184 sizeof(cbd_t), &fep->ring_mem_addr,
185 GFP_KERNEL);
186 if (fep->ring_base == NULL)
187 return -ENOMEM;
188
189 return 0;
190}
191
192static void free_bd(struct net_device *dev)
193{
194 struct fs_enet_private *fep = netdev_priv(dev);
195 const struct fs_platform_info *fpi = fep->fpi;
196
197 if (fep->ring_base)
198 dma_free_coherent(fep->dev,
199 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
200 fep->ring_base, fep->ring_mem_addr);
201}
202
203static void cleanup_data(struct net_device *dev)
204{
205 /* nothing */
206}
207
208static void set_promiscuous_mode(struct net_device *dev)
209{
210 struct fs_enet_private *fep = netdev_priv(dev);
211 fcc_t *fccp = fep->fcc.fccp;
212
213 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
214}
215
216static void set_multicast_start(struct net_device *dev)
217{
218 struct fs_enet_private *fep = netdev_priv(dev);
219 fcc_enet_t *ep = fep->fcc.ep;
220
221 W32(ep, fen_gaddrh, 0);
222 W32(ep, fen_gaddrl, 0);
223}
224
225static void set_multicast_one(struct net_device *dev, const u8 *mac)
226{
227 struct fs_enet_private *fep = netdev_priv(dev);
228 fcc_enet_t *ep = fep->fcc.ep;
229 u16 taddrh, taddrm, taddrl;
230
231 taddrh = ((u16)mac[5] << 8) | mac[4];
232 taddrm = ((u16)mac[3] << 8) | mac[2];
233 taddrl = ((u16)mac[1] << 8) | mac[0];
234
235 W16(ep, fen_taddrh, taddrh);
236 W16(ep, fen_taddrm, taddrm);
237 W16(ep, fen_taddrl, taddrl);
238 fcc_cr_cmd(fep, 0x0C, CPM_CR_SET_GADDR);
239}
240
241static void set_multicast_finish(struct net_device *dev)
242{
243 struct fs_enet_private *fep = netdev_priv(dev);
244 fcc_t *fccp = fep->fcc.fccp;
245 fcc_enet_t *ep = fep->fcc.ep;
246
247 /* clear promiscuous always */
248 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
249
250 /* if all multi or too many multicasts; just enable all */
251 if ((dev->flags & IFF_ALLMULTI) != 0 ||
252 dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
253
254 W32(ep, fen_gaddrh, 0xffffffff);
255 W32(ep, fen_gaddrl, 0xffffffff);
256 }
257
258 /* read back */
259 fep->fcc.gaddrh = R32(ep, fen_gaddrh);
260 fep->fcc.gaddrl = R32(ep, fen_gaddrl);
261}
262
263static void set_multicast_list(struct net_device *dev)
264{
265 struct dev_mc_list *pmc;
266
267 if ((dev->flags & IFF_PROMISC) == 0) {
268 set_multicast_start(dev);
269 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
270 set_multicast_one(dev, pmc->dmi_addr);
271 set_multicast_finish(dev);
272 } else
273 set_promiscuous_mode(dev);
274}
275
276static void restart(struct net_device *dev)
277{
278 struct fs_enet_private *fep = netdev_priv(dev);
279 const struct fs_platform_info *fpi = fep->fpi;
280 fcc_t *fccp = fep->fcc.fccp;
281 fcc_c_t *fcccp = fep->fcc.fcccp;
282 fcc_enet_t *ep = fep->fcc.ep;
283 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
284 u16 paddrh, paddrm, paddrl;
285 u16 mem_addr;
286 const unsigned char *mac;
287 int i;
288
289 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
290
291 /* clear everything (slow & steady does it) */
292 for (i = 0; i < sizeof(*ep); i++)
293 __fcc_out8((char *)ep + i, 0);
294
295 /* get physical address */
296 rx_bd_base_phys = fep->ring_mem_addr;
297 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
298
299 /* point to bds */
300 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
301 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
302
303 /* Set maximum bytes per receive buffer.
304 * It must be a multiple of 32.
305 */
306 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
307
308 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
309 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
310
311 /* Allocate space in the reserved FCC area of DPRAM for the
312 * internal buffers. No one uses this space (yet), so we
313 * can do this. Later, we will add resource management for
314 * this area.
315 */
316
317 mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
318
319 W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
320 W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
321 W16(ep, fen_padptr, mem_addr + 64);
322
323 /* fill with special symbol... */
324 memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
325
326 W32(ep, fen_genfcc.fcc_rbptr, 0);
327 W32(ep, fen_genfcc.fcc_tbptr, 0);
328 W32(ep, fen_genfcc.fcc_rcrc, 0);
329 W32(ep, fen_genfcc.fcc_tcrc, 0);
330 W16(ep, fen_genfcc.fcc_res1, 0);
331 W32(ep, fen_genfcc.fcc_res2, 0);
332
333 /* no CAM */
334 W32(ep, fen_camptr, 0);
335
336 /* Set CRC preset and mask */
337 W32(ep, fen_cmask, 0xdebb20e3);
338 W32(ep, fen_cpres, 0xffffffff);
339
340 W32(ep, fen_crcec, 0); /* CRC Error counter */
341 W32(ep, fen_alec, 0); /* alignment error counter */
342 W32(ep, fen_disfc, 0); /* discard frame counter */
343 W16(ep, fen_retlim, 15); /* Retry limit threshold */
344 W16(ep, fen_pper, 0); /* Normal persistence */
345
346 /* set group address */
347 W32(ep, fen_gaddrh, fep->fcc.gaddrh);
348 W32(ep, fen_gaddrl, fep->fcc.gaddrh);
349
350 /* Clear hash filter tables */
351 W32(ep, fen_iaddrh, 0);
352 W32(ep, fen_iaddrl, 0);
353
354 /* Clear the Out-of-sequence TxBD */
355 W16(ep, fen_tfcstat, 0);
356 W16(ep, fen_tfclen, 0);
357 W32(ep, fen_tfcptr, 0);
358
359 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
360 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
361
362 /* set address */
363 mac = dev->dev_addr;
364 paddrh = ((u16)mac[5] << 8) | mac[4];
365 paddrm = ((u16)mac[3] << 8) | mac[2];
366 paddrl = ((u16)mac[1] << 8) | mac[0];
367
368 W16(ep, fen_paddrh, paddrh);
369 W16(ep, fen_paddrm, paddrm);
370 W16(ep, fen_paddrl, paddrl);
371
372 W16(ep, fen_taddrh, 0);
373 W16(ep, fen_taddrm, 0);
374 W16(ep, fen_taddrl, 0);
375
376 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
377 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
378
379 /* Clear stat counters, in case we ever enable RMON */
380 W32(ep, fen_octc, 0);
381 W32(ep, fen_colc, 0);
382 W32(ep, fen_broc, 0);
383 W32(ep, fen_mulc, 0);
384 W32(ep, fen_uspc, 0);
385 W32(ep, fen_frgc, 0);
386 W32(ep, fen_ospc, 0);
387 W32(ep, fen_jbrc, 0);
388 W32(ep, fen_p64c, 0);
389 W32(ep, fen_p65c, 0);
390 W32(ep, fen_p128c, 0);
391 W32(ep, fen_p256c, 0);
392 W32(ep, fen_p512c, 0);
393 W32(ep, fen_p1024c, 0);
394
395 W16(ep, fen_rfthr, 0); /* Suggested by manual */
396 W16(ep, fen_rfcnt, 0);
397 W16(ep, fen_cftype, 0);
398
399 fs_init_bds(dev);
400
401 /* adjust to speed (for RMII mode) */
402 if (fpi->use_rmii) {
5b4b8454 403 if (fep->phydev->speed == 100)
48257c4f
PA		 404 C8(fcccp, fcc_gfemr, 0x20);
405 else
406 S8(fcccp, fcc_gfemr, 0x20);
407 }
408
409 fcc_cr_cmd(fep, 0x0c, CPM_CR_INIT_TRX);
410
411 /* clear events */
412 W16(fccp, fcc_fcce, 0xffff);
413
414 /* Enable interrupts we wish to service */
415 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
416
417 /* Set GFMR to enable Ethernet operating mode */
418 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
419
420 /* set sync/delimiters */
421 W16(fccp, fcc_fdsr, 0xd555);
422
423 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
424
425 if (fpi->use_rmii)
426 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
427
428 /* adjust to duplex mode */
5b4b8454 429 if (fep->phydev->duplex)
48257c4f
PA		 430 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
431 else
432 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
433
434 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
435}
436
437static void stop(struct net_device *dev)
438{
439 struct fs_enet_private *fep = netdev_priv(dev);
440 fcc_t *fccp = fep->fcc.fccp;
441
442 /* stop ethernet */
443 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
444
445 /* clear events */
446 W16(fccp, fcc_fcce, 0xffff);
447
448 /* clear interrupt mask */
449 W16(fccp, fcc_fccm, 0);
450
451 fs_cleanup_bds(dev);
452}
453
454static void pre_request_irq(struct net_device *dev, int irq)
455{
456 /* nothing */
457}
458
459static void post_free_irq(struct net_device *dev, int irq)
460{
461 /* nothing */
462}
463
464static void napi_clear_rx_event(struct net_device *dev)
465{
466 struct fs_enet_private *fep = netdev_priv(dev);
467 fcc_t *fccp = fep->fcc.fccp;
468
469 W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
470}
471
472static void napi_enable_rx(struct net_device *dev)
473{
474 struct fs_enet_private *fep = netdev_priv(dev);
475 fcc_t *fccp = fep->fcc.fccp;
476
477 S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
478}
479
480static void napi_disable_rx(struct net_device *dev)
481{
482 struct fs_enet_private *fep = netdev_priv(dev);
483 fcc_t *fccp = fep->fcc.fccp;
484
485 C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
486}
487
488static void rx_bd_done(struct net_device *dev)
489{
490 /* nothing */
491}
492
493static void tx_kickstart(struct net_device *dev)
494{
5b4b8454
VB		 495 struct fs_enet_private *fep = netdev_priv(dev);
496 fcc_t *fccp = fep->fcc.fccp;
497
498 S32(fccp, fcc_ftodr, 0x80);
48257c4f
PA		 499}
500
501static u32 get_int_events(struct net_device *dev)
502{
503 struct fs_enet_private *fep = netdev_priv(dev);
504 fcc_t *fccp = fep->fcc.fccp;
505
506 return (u32)R16(fccp, fcc_fcce);
507}
508
509static void clear_int_events(struct net_device *dev, u32 int_events)
510{
511 struct fs_enet_private *fep = netdev_priv(dev);
512 fcc_t *fccp = fep->fcc.fccp;
513
514 W16(fccp, fcc_fcce, int_events & 0xffff);
515}
516
517static void ev_error(struct net_device *dev, u32 int_events)
518{
519 printk(KERN_WARNING DRV_MODULE_NAME
520 ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
521}
522
523int get_regs(struct net_device *dev, void *p, int *sizep)
524{
525 struct fs_enet_private *fep = netdev_priv(dev);
526
527 if (*sizep < sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t))
528 return -EINVAL;
529
530 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
531 p = (char *)p + sizeof(fcc_t);
532
533 memcpy_fromio(p, fep->fcc.fcccp, sizeof(fcc_c_t));
534 p = (char *)p + sizeof(fcc_c_t);
535
536 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
537
538 return 0;
539}
540
541int get_regs_len(struct net_device *dev)
542{
543 return sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t);
544}
545
546/* Some transmit errors cause the transmitter to shut
547 * down. We now issue a restart transmit. Since the
548 * errors close the BD and update the pointers, the restart
549 * _should_ pick up without having to reset any of our
9b8ee8e7 550 * pointers either. Also, To workaround 8260 device erratum
48257c4f
PA		 551 * CPM37, we must disable and then re-enable the transmitter
552 * following a Late Collision, Underrun, or Retry Limit error.
553 */
554void tx_restart(struct net_device *dev)
555{
556 struct fs_enet_private *fep = netdev_priv(dev);
557 fcc_t *fccp = fep->fcc.fccp;
558
559 C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
560 udelay(10);
561 S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
562
563 fcc_cr_cmd(fep, 0x0C, CPM_CR_RESTART_TX);
564}
565
566/*************************************************************************/
567
568const struct fs_ops fs_fcc_ops = {
569 .setup_data = setup_data,
570 .cleanup_data = cleanup_data,
571 .set_multicast_list = set_multicast_list,
572 .restart = restart,
573 .stop = stop,
574 .pre_request_irq = pre_request_irq,
575 .post_free_irq = post_free_irq,
576 .napi_clear_rx_event = napi_clear_rx_event,
577 .napi_enable_rx = napi_enable_rx,
578 .napi_disable_rx = napi_disable_rx,
579 .rx_bd_done = rx_bd_done,
580 .tx_kickstart = tx_kickstart,
581 .get_int_events = get_int_events,
582 .clear_int_events = clear_int_events,
583 .ev_error = ev_error,
584 .get_regs = get_regs,
585 .get_regs_len = get_regs_len,
586 .tx_restart = tx_restart,
587 .allocate_bd = allocate_bd,
588 .free_bd = free_bd,
589};
Linux kernel - Deliverables
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