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[PATCH] handle errors returned by platform_get_irq*()
[deliverable/linux.git] / drivers / net / fs_enet / mac-fec.c
CommitLineData
48257c4f
PA		 1/*
2 * Freescale Ethernet controllers
3 *
4 * Copyright (c) 2005 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15#include <linux/config.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/ptrace.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/slab.h>
25#include <linux/interrupt.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/spinlock.h>
33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/bitops.h>
36#include <linux/fs.h>
f7b99969 37#include <linux/platform_device.h>
48257c4f
PA		 38
39#include <asm/irq.h>
40#include <asm/uaccess.h>
41
42#ifdef CONFIG_8xx
43#include <asm/8xx_immap.h>
44#include <asm/pgtable.h>
45#include <asm/mpc8xx.h>
46#include <asm/commproc.h>
47#endif
48
49#include "fs_enet.h"
50
51/*************************************************/
52
53#if defined(CONFIG_CPM1)
54/* for a CPM1 __raw_xxx's are sufficient */
55#define __fs_out32(addr, x) __raw_writel(x, addr)
56#define __fs_out16(addr, x) __raw_writew(x, addr)
57#define __fs_in32(addr) __raw_readl(addr)
58#define __fs_in16(addr) __raw_readw(addr)
59#else
60/* for others play it safe */
61#define __fs_out32(addr, x) out_be32(addr, x)
62#define __fs_out16(addr, x) out_be16(addr, x)
63#define __fs_in32(addr) in_be32(addr)
64#define __fs_in16(addr) in_be16(addr)
65#endif
66
67/* write */
68#define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
69
70/* read */
71#define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
72
73/* set bits */
74#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
75
76/* clear bits */
77#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
78
79
80/* CRC polynomium used by the FEC for the multicast group filtering */
81#define FEC_CRC_POLY 0x04C11DB7
82
83#define FEC_MAX_MULTICAST_ADDRS 64
84
85/* Interrupt events/masks.
86*/
87#define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
88#define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
89#define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
90#define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
91#define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
92#define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
93#define FEC_ENET_RXF 0x02000000U /* Full frame received */
94#define FEC_ENET_RXB 0x01000000U /* A buffer was received */
95#define FEC_ENET_MII 0x00800000U /* MII interrupt */
96#define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
97
98#define FEC_ECNTRL_PINMUX 0x00000004
99#define FEC_ECNTRL_ETHER_EN 0x00000002
100#define FEC_ECNTRL_RESET 0x00000001
101
102#define FEC_RCNTRL_BC_REJ 0x00000010
103#define FEC_RCNTRL_PROM 0x00000008
104#define FEC_RCNTRL_MII_MODE 0x00000004
105#define FEC_RCNTRL_DRT 0x00000002
106#define FEC_RCNTRL_LOOP 0x00000001
107
108#define FEC_TCNTRL_FDEN 0x00000004
109#define FEC_TCNTRL_HBC 0x00000002
110#define FEC_TCNTRL_GTS 0x00000001
111
112
113/* Make MII read/write commands for the FEC.
114*/
115#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
116#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
117#define mk_mii_end 0
118
119#define FEC_MII_LOOPS 10000
120
121/*
122 * Delay to wait for FEC reset command to complete (in us)
123 */
124#define FEC_RESET_DELAY 50
125
126static int whack_reset(fec_t * fecp)
127{
128 int i;
129
130 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
131 for (i = 0; i < FEC_RESET_DELAY; i++) {
132 if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
133 return 0; /* OK */
134 udelay(1);
135 }
136
137 return -1;
138}
139
140static int do_pd_setup(struct fs_enet_private *fep)
141{
142 struct platform_device *pdev = to_platform_device(fep->dev);
143 struct resource *r;
144
145 /* Fill out IRQ field */
146 fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
48944738
DV		 147 if (fep->interrupt < 0)
148 return -EINVAL;
48257c4f
PA		 149
150 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
151 fep->fec.fecp =(void*)r->start;
152
153 if(fep->fec.fecp == NULL)
154 return -EINVAL;
155
156 return 0;
157
158}
159
160#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
161#define FEC_RX_EVENT (FEC_ENET_RXF)
162#define FEC_TX_EVENT (FEC_ENET_TXF)
163#define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
164 FEC_ENET_BABT | FEC_ENET_EBERR)
165
166static int setup_data(struct net_device *dev)
167{
168 struct fs_enet_private *fep = netdev_priv(dev);
169
170 if (do_pd_setup(fep) != 0)
171 return -EINVAL;
172
173 fep->fec.hthi = 0;
174 fep->fec.htlo = 0;
175
176 fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
177 fep->ev_rx = FEC_RX_EVENT;
178 fep->ev_tx = FEC_TX_EVENT;
179 fep->ev_err = FEC_ERR_EVENT_MSK;
180
181 return 0;
182}
183
184static int allocate_bd(struct net_device *dev)
185{
186 struct fs_enet_private *fep = netdev_priv(dev);
187 const struct fs_platform_info *fpi = fep->fpi;
188
189 fep->ring_base = dma_alloc_coherent(fep->dev,
190 (fpi->tx_ring + fpi->rx_ring) *
191 sizeof(cbd_t), &fep->ring_mem_addr,
192 GFP_KERNEL);
193 if (fep->ring_base == NULL)
194 return -ENOMEM;
195
196 return 0;
197}
198
199static void free_bd(struct net_device *dev)
200{
201 struct fs_enet_private *fep = netdev_priv(dev);
202 const struct fs_platform_info *fpi = fep->fpi;
203
204 if(fep->ring_base)
205 dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
206 * sizeof(cbd_t),
207 fep->ring_base,
208 fep->ring_mem_addr);
209}
210
211static void cleanup_data(struct net_device *dev)
212{
213 /* nothing */
214}
215
216static void set_promiscuous_mode(struct net_device *dev)
217{
218 struct fs_enet_private *fep = netdev_priv(dev);
219 fec_t *fecp = fep->fec.fecp;
220
221 FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
222}
223
224static void set_multicast_start(struct net_device *dev)
225{
226 struct fs_enet_private *fep = netdev_priv(dev);
227
228 fep->fec.hthi = 0;
229 fep->fec.htlo = 0;
230}
231
232static void set_multicast_one(struct net_device *dev, const u8 *mac)
233{
234 struct fs_enet_private *fep = netdev_priv(dev);
235 int temp, hash_index, i, j;
236 u32 crc, csrVal;
237 u8 byte, msb;
238
239 crc = 0xffffffff;
240 for (i = 0; i < 6; i++) {
241 byte = mac[i];
242 for (j = 0; j < 8; j++) {
243 msb = crc >> 31;
244 crc <<= 1;
245 if (msb ^ (byte & 0x1))
246 crc ^= FEC_CRC_POLY;
247 byte >>= 1;
248 }
249 }
250
251 temp = (crc & 0x3f) >> 1;
252 hash_index = ((temp & 0x01) << 4) |
253 ((temp & 0x02) << 2) |
254 ((temp & 0x04)) |
255 ((temp & 0x08) >> 2) |
256 ((temp & 0x10) >> 4);
257 csrVal = 1 << hash_index;
258 if (crc & 1)
259 fep->fec.hthi |= csrVal;
260 else
261 fep->fec.htlo |= csrVal;
262}
263
264static void set_multicast_finish(struct net_device *dev)
265{
266 struct fs_enet_private *fep = netdev_priv(dev);
267 fec_t *fecp = fep->fec.fecp;
268
269 /* if all multi or too many multicasts; just enable all */
270 if ((dev->flags & IFF_ALLMULTI) != 0 ||
271 dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
272 fep->fec.hthi = 0xffffffffU;
273 fep->fec.htlo = 0xffffffffU;
274 }
275
276 FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
277 FW(fecp, hash_table_high, fep->fec.hthi);
278 FW(fecp, hash_table_low, fep->fec.htlo);
279}
280
281static void set_multicast_list(struct net_device *dev)
282{
283 struct dev_mc_list *pmc;
284
285 if ((dev->flags & IFF_PROMISC) == 0) {
286 set_multicast_start(dev);
287 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
288 set_multicast_one(dev, pmc->dmi_addr);
289 set_multicast_finish(dev);
290 } else
291 set_promiscuous_mode(dev);
292}
293
294static void restart(struct net_device *dev)
295{
296#ifdef CONFIG_DUET
297 immap_t *immap = fs_enet_immap;
298 u32 cptr;
299#endif
300 struct fs_enet_private *fep = netdev_priv(dev);
301 fec_t *fecp = fep->fec.fecp;
302 const struct fs_platform_info *fpi = fep->fpi;
303 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
304 int r;
305 u32 addrhi, addrlo;
306
307 r = whack_reset(fep->fec.fecp);
308 if (r != 0)
309 printk(KERN_ERR DRV_MODULE_NAME
310 ": %s FEC Reset FAILED!\n", dev->name);
311
312 /*
313 * Set station address.
314 */
315 addrhi = ((u32) dev->dev_addr[0] << 24) |
316 ((u32) dev->dev_addr[1] << 16) |
317 ((u32) dev->dev_addr[2] << 8) |
318 (u32) dev->dev_addr[3];
319 addrlo = ((u32) dev->dev_addr[4] << 24) |
320 ((u32) dev->dev_addr[5] << 16);
321 FW(fecp, addr_low, addrhi);
322 FW(fecp, addr_high, addrlo);
323
324 /*
325 * Reset all multicast.
326 */
327 FW(fecp, hash_table_high, fep->fec.hthi);
328 FW(fecp, hash_table_low, fep->fec.htlo);
329
330 /*
331 * Set maximum receive buffer size.
332 */
333 FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
334 FW(fecp, r_hash, PKT_MAXBUF_SIZE);
335
336 /* get physical address */
337 rx_bd_base_phys = fep->ring_mem_addr;
338 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
339
340 /*
341 * Set receive and transmit descriptor base.
342 */
343 FW(fecp, r_des_start, rx_bd_base_phys);
344 FW(fecp, x_des_start, tx_bd_base_phys);
345
346 fs_init_bds(dev);
347
348 /*
349 * Enable big endian and don't care about SDMA FC.
350 */
351 FW(fecp, fun_code, 0x78000000);
352
353 /*
354 * Set MII speed.
355 */
356 FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
357
358 /*
359 * Clear any outstanding interrupt.
360 */
361 FW(fecp, ievent, 0xffc0);
362 FW(fecp, ivec, (fep->interrupt / 2) << 29);
363
364
365 /*
366 * adjust to speed (only for DUET & RMII)
367 */
368#ifdef CONFIG_DUET
369 if (fpi->use_rmii) {
370 cptr = in_be32(&immap->im_cpm.cp_cptr);
371 switch (fs_get_fec_index(fpi->fs_no)) {
372 case 0:
373 cptr |= 0x100;
374 if (fep->speed == 10)
375 cptr |= 0x0000010;
376 else if (fep->speed == 100)
377 cptr &= ~0x0000010;
378 break;
379 case 1:
380 cptr |= 0x80;
381 if (fep->speed == 10)
382 cptr |= 0x0000008;
383 else if (fep->speed == 100)
384 cptr &= ~0x0000008;
385 break;
386 default:
387 BUG(); /* should never happen */
388 break;
389 }
390 out_be32(&immap->im_cpm.cp_cptr, cptr);
391 }
392#endif
393
394 FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
395 /*
396 * adjust to duplex mode
397 */
398 if (fep->duplex) {
399 FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
400 FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
401 } else {
402 FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
403 FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
404 }
405
406 /*
407 * Enable interrupts we wish to service.
408 */
409 FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
410 FEC_ENET_RXF | FEC_ENET_RXB);
411
412 /*
413 * And last, enable the transmit and receive processing.
414 */
415 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
416 FW(fecp, r_des_active, 0x01000000);
417}
418
419static void stop(struct net_device *dev)
420{
421 struct fs_enet_private *fep = netdev_priv(dev);
422 fec_t *fecp = fep->fec.fecp;
423 struct fs_enet_mii_bus *bus = fep->mii_bus;
424 const struct fs_mii_bus_info *bi = bus->bus_info;
425 int i;
426
427 if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
428 return; /* already down */
429
430 FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
431 for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
432 i < FEC_RESET_DELAY; i++)
433 udelay(1);
434
435 if (i == FEC_RESET_DELAY)
436 printk(KERN_WARNING DRV_MODULE_NAME
437 ": %s FEC timeout on graceful transmit stop\n",
438 dev->name);
439 /*
440 * Disable FEC. Let only MII interrupts.
441 */
442 FW(fecp, imask, 0);
443 FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
444
445 fs_cleanup_bds(dev);
446
447 /* shut down FEC1? that's where the mii bus is */
448 if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
449 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
450 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
451 FW(fecp, ievent, FEC_ENET_MII);
452 FW(fecp, mii_speed, bus->fec.mii_speed);
453 }
454}
455
456static void pre_request_irq(struct net_device *dev, int irq)
457{
458 immap_t *immap = fs_enet_immap;
459 u32 siel;
460
461 /* SIU interrupt */
462 if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
463
464 siel = in_be32(&immap->im_siu_conf.sc_siel);
465 if ((irq & 1) == 0)
466 siel |= (0x80000000 >> irq);
467 else
468 siel &= ~(0x80000000 >> (irq & ~1));
469 out_be32(&immap->im_siu_conf.sc_siel, siel);
470 }
471}
472
473static void post_free_irq(struct net_device *dev, int irq)
474{
475 /* nothing */
476}
477
478static void napi_clear_rx_event(struct net_device *dev)
479{
480 struct fs_enet_private *fep = netdev_priv(dev);
481 fec_t *fecp = fep->fec.fecp;
482
483 FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
484}
485
486static void napi_enable_rx(struct net_device *dev)
487{
488 struct fs_enet_private *fep = netdev_priv(dev);
489 fec_t *fecp = fep->fec.fecp;
490
491 FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
492}
493
494static void napi_disable_rx(struct net_device *dev)
495{
496 struct fs_enet_private *fep = netdev_priv(dev);
497 fec_t *fecp = fep->fec.fecp;
498
499 FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
500}
501
502static void rx_bd_done(struct net_device *dev)
503{
504 struct fs_enet_private *fep = netdev_priv(dev);
505 fec_t *fecp = fep->fec.fecp;
506
507 FW(fecp, r_des_active, 0x01000000);
508}
509
510static void tx_kickstart(struct net_device *dev)
511{
512 struct fs_enet_private *fep = netdev_priv(dev);
513 fec_t *fecp = fep->fec.fecp;
514
515 FW(fecp, x_des_active, 0x01000000);
516}
517
518static u32 get_int_events(struct net_device *dev)
519{
520 struct fs_enet_private *fep = netdev_priv(dev);
521 fec_t *fecp = fep->fec.fecp;
522
523 return FR(fecp, ievent) & FR(fecp, imask);
524}
525
526static void clear_int_events(struct net_device *dev, u32 int_events)
527{
528 struct fs_enet_private *fep = netdev_priv(dev);
529 fec_t *fecp = fep->fec.fecp;
530
531 FW(fecp, ievent, int_events);
532}
533
534static void ev_error(struct net_device *dev, u32 int_events)
535{
536 printk(KERN_WARNING DRV_MODULE_NAME
537 ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
538}
539
540int get_regs(struct net_device *dev, void *p, int *sizep)
541{
542 struct fs_enet_private *fep = netdev_priv(dev);
543
544 if (*sizep < sizeof(fec_t))
545 return -EINVAL;
546
547 memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
548
549 return 0;
550}
551
552int get_regs_len(struct net_device *dev)
553{
554 return sizeof(fec_t);
555}
556
557void tx_restart(struct net_device *dev)
558{
559 /* nothing */
560}
561
562/*************************************************************************/
563
564const struct fs_ops fs_fec_ops = {
565 .setup_data = setup_data,
566 .cleanup_data = cleanup_data,
567 .set_multicast_list = set_multicast_list,
568 .restart = restart,
569 .stop = stop,
570 .pre_request_irq = pre_request_irq,
571 .post_free_irq = post_free_irq,
572 .napi_clear_rx_event = napi_clear_rx_event,
573 .napi_enable_rx = napi_enable_rx,
574 .napi_disable_rx = napi_disable_rx,
575 .rx_bd_done = rx_bd_done,
576 .tx_kickstart = tx_kickstart,
577 .get_int_events = get_int_events,
578 .clear_int_events = clear_int_events,
579 .ev_error = ev_error,
580 .get_regs = get_regs,
581 .get_regs_len = get_regs_len,
582 .tx_restart = tx_restart,
583 .allocate_bd = allocate_bd,
584 .free_bd = free_bd,
585};
586
587/***********************************************************************/
588
589static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
590{
591 fec_t *fecp = bus->fec.fecp;
592 int i, ret = -1;
593
594 if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
595 BUG();
596
597 /* Add PHY address to register command. */
598 FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
599
600 for (i = 0; i < FEC_MII_LOOPS; i++)
601 if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
602 break;
603
604 if (i < FEC_MII_LOOPS) {
605 FW(fecp, ievent, FEC_ENET_MII);
606 ret = FR(fecp, mii_data) & 0xffff;
607 }
608
609 return ret;
610}
611
612static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
613{
614 fec_t *fecp = bus->fec.fecp;
615 int i;
616
617 /* this must never happen */
618 if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
619 BUG();
620
621 /* Add PHY address to register command. */
622 FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
623
624 for (i = 0; i < FEC_MII_LOOPS; i++)
625 if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
626 break;
627
628 if (i < FEC_MII_LOOPS)
629 FW(fecp, ievent, FEC_ENET_MII);
630}
631
632int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
633{
634 bd_t *bd = (bd_t *)__res;
635 const struct fs_mii_bus_info *bi = bus->bus_info;
636 fec_t *fecp;
637
638 if (bi->id != 0)
639 return -1;
640
641 bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
642 bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
643 & 0x3F) << 1;
644
645 fecp = bus->fec.fecp;
646
647 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
648 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
649 FW(fecp, ievent, FEC_ENET_MII);
650 FW(fecp, mii_speed, bus->fec.mii_speed);
651
652 bus->mii_read = mii_read;
653 bus->mii_write = mii_write;
654
655 return 0;
656}
Linux kernel - Deliverables
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