[deliverable/linux.git] / drivers / net / fs_enet / mac-fec.c

/*
 * Freescale Ethernet controllers
 *
 * Copyright (c) 2005 Intracom S.A.
 *  by Pantelis Antoniou <panto@intracom.gr>
 *
 * 2005 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/fs.h>
#include <linux/platform_device.h>

#include <asm/irq.h>
#include <asm/uaccess.h>

#ifdef CONFIG_8xx
#include <asm/8xx_immap.h>
#include <asm/pgtable.h>
#include <asm/mpc8xx.h>
#include <asm/commproc.h>
#endif

#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <asm/of_device.h>
#endif

#include "fs_enet.h"
#include "fec.h"

/*************************************************/

#if defined(CONFIG_CPM1)
/* for a CPM1 __raw_xxx's are sufficient */
#define __fs_out32(addr, x)	__raw_writel(x, addr)
#define __fs_out16(addr, x)	__raw_writew(x, addr)
#define __fs_in32(addr)	__raw_readl(addr)
#define __fs_in16(addr)	__raw_readw(addr)
#else
/* for others play it safe */
#define __fs_out32(addr, x)	out_be32(addr, x)
#define __fs_out16(addr, x)	out_be16(addr, x)
#define __fs_in32(addr)	in_be32(addr)
#define __fs_in16(addr)	in_be16(addr)
#endif

/* write */
#define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))

/* read */
#define FR(_fecp, _reg)	__fs_in32(&(_fecp)->fec_ ## _reg)

/* set bits */
#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))

/* clear bits */
#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))

/*
 * Delay to wait for FEC reset command to complete (in us)
 */
#define FEC_RESET_DELAY		50

static int whack_reset(fec_t * fecp)
{
	int i;

	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
	for (i = 0; i < FEC_RESET_DELAY; i++) {
		if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
			return 0;	/* OK */
		udelay(1);
	}

	return -1;
}

static int do_pd_setup(struct fs_enet_private *fep)
{
#ifdef CONFIG_PPC_CPM_NEW_BINDING
	struct of_device *ofdev = to_of_device(fep->dev);

	fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
	if (fep->interrupt == NO_IRQ)
		return -EINVAL;

	fep->fec.fecp = of_iomap(ofdev->node, 0);
	if (!fep->fcc.fccp)
		return -EINVAL;

	return 0;
#else
	struct platform_device *pdev = to_platform_device(fep->dev);
	struct resource	*r;

	/* Fill out IRQ field */
	fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
	if (fep->interrupt < 0)
		return -EINVAL;

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	fep->fec.fecp = ioremap(r->start, r->end - r->start + 1);

	if(fep->fec.fecp == NULL)
		return -EINVAL;

	return 0;
#endif
}

#define FEC_NAPI_RX_EVENT_MSK	(FEC_ENET_RXF | FEC_ENET_RXB)
#define FEC_RX_EVENT		(FEC_ENET_RXF)
#define FEC_TX_EVENT		(FEC_ENET_TXF)
#define FEC_ERR_EVENT_MSK	(FEC_ENET_HBERR | FEC_ENET_BABR | \
				 FEC_ENET_BABT | FEC_ENET_EBERR)

static int setup_data(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);

	if (do_pd_setup(fep) != 0)
		return -EINVAL;

	fep->fec.hthi = 0;
	fep->fec.htlo = 0;

	fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
	fep->ev_rx = FEC_RX_EVENT;
	fep->ev_tx = FEC_TX_EVENT;
	fep->ev_err = FEC_ERR_EVENT_MSK;

	return 0;
}

static int allocate_bd(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	const struct fs_platform_info *fpi = fep->fpi;

	fep->ring_base = dma_alloc_coherent(fep->dev,
					    (fpi->tx_ring + fpi->rx_ring) *
					    sizeof(cbd_t), &fep->ring_mem_addr,
					    GFP_KERNEL);
	if (fep->ring_base == NULL)
		return -ENOMEM;

	return 0;
}

static void free_bd(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	const struct fs_platform_info *fpi = fep->fpi;

	if(fep->ring_base)
		dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
					* sizeof(cbd_t),
					fep->ring_base,
					fep->ring_mem_addr);
}

static void cleanup_data(struct net_device *dev)
{
	/* nothing */
}

static void set_promiscuous_mode(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
}

static void set_multicast_start(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);

	fep->fec.hthi = 0;
	fep->fec.htlo = 0;
}

static void set_multicast_one(struct net_device *dev, const u8 *mac)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	int temp, hash_index, i, j;
	u32 crc, csrVal;
	u8 byte, msb;

	crc = 0xffffffff;
	for (i = 0; i < 6; i++) {
		byte = mac[i];
		for (j = 0; j < 8; j++) {
			msb = crc >> 31;
			crc <<= 1;
			if (msb ^ (byte & 0x1))
				crc ^= FEC_CRC_POLY;
			byte >>= 1;
		}
	}

	temp = (crc & 0x3f) >> 1;
	hash_index = ((temp & 0x01) << 4) |
		     ((temp & 0x02) << 2) |
		     ((temp & 0x04)) |
		     ((temp & 0x08) >> 2) |
		     ((temp & 0x10) >> 4);
	csrVal = 1 << hash_index;
	if (crc & 1)
		fep->fec.hthi |= csrVal;
	else
		fep->fec.htlo |= csrVal;
}

static void set_multicast_finish(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	/* if all multi or too many multicasts; just enable all */
	if ((dev->flags & IFF_ALLMULTI) != 0 ||
	    dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
		fep->fec.hthi = 0xffffffffU;
		fep->fec.htlo = 0xffffffffU;
	}

	FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
	FW(fecp, hash_table_high, fep->fec.hthi);
	FW(fecp, hash_table_low, fep->fec.htlo);
}

static void set_multicast_list(struct net_device *dev)
{
	struct dev_mc_list *pmc;

	if ((dev->flags & IFF_PROMISC) == 0) {
		set_multicast_start(dev);
		for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
			set_multicast_one(dev, pmc->dmi_addr);
		set_multicast_finish(dev);
	} else
		set_promiscuous_mode(dev);
}

static void restart(struct net_device *dev)
{
#ifdef CONFIG_DUET
	immap_t *immap = fs_enet_immap;
	u32 cptr;
#endif
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;
	const struct fs_platform_info *fpi = fep->fpi;
	dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
	int r;
	u32 addrhi, addrlo;

	struct mii_bus* mii = fep->phydev->bus;
	struct fec_info* fec_inf = mii->priv;

	r = whack_reset(fep->fec.fecp);
	if (r != 0)
		printk(KERN_ERR DRV_MODULE_NAME
				": %s FEC Reset FAILED!\n", dev->name);
	/*
	 * Set station address.
	 */
	addrhi = ((u32) dev->dev_addr[0] << 24) |
		 ((u32) dev->dev_addr[1] << 16) |
		 ((u32) dev->dev_addr[2] <<  8) |
		  (u32) dev->dev_addr[3];
	addrlo = ((u32) dev->dev_addr[4] << 24) |
		 ((u32) dev->dev_addr[5] << 16);
	FW(fecp, addr_low, addrhi);
	FW(fecp, addr_high, addrlo);

	/*
	 * Reset all multicast.
	 */
	FW(fecp, hash_table_high, fep->fec.hthi);
	FW(fecp, hash_table_low, fep->fec.htlo);

	/*
	 * Set maximum receive buffer size.
	 */
	FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
	FW(fecp, r_hash, PKT_MAXBUF_SIZE);

	/* get physical address */
	rx_bd_base_phys = fep->ring_mem_addr;
	tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;

	/*
	 * Set receive and transmit descriptor base.
	 */
	FW(fecp, r_des_start, rx_bd_base_phys);
	FW(fecp, x_des_start, tx_bd_base_phys);

	fs_init_bds(dev);

	/*
	 * Enable big endian and don't care about SDMA FC.
	 */
	FW(fecp, fun_code, 0x78000000);

	/*
	 * Set MII speed.
	 */
	FW(fecp, mii_speed, fec_inf->mii_speed);

	/*
	 * Clear any outstanding interrupt.
	 */
	FW(fecp, ievent, 0xffc0);
#ifndef CONFIG_PPC_MERGE
	FW(fecp, ivec, (fep->interrupt / 2) << 29);
#else
	FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
#endif

	/*
	 * adjust to speed (only for DUET & RMII)
	 */
#ifdef CONFIG_DUET
	if (fpi->use_rmii) {
		cptr = in_be32(&immap->im_cpm.cp_cptr);
		switch (fs_get_fec_index(fpi->fs_no)) {
		case 0:
			cptr |= 0x100;
			if (fep->speed == 10)
				cptr |= 0x0000010;
			else if (fep->speed == 100)
				cptr &= ~0x0000010;
			break;
		case 1:
			cptr |= 0x80;
			if (fep->speed == 10)
				cptr |= 0x0000008;
			else if (fep->speed == 100)
				cptr &= ~0x0000008;
			break;
		default:
			BUG();	/* should never happen */
			break;
		}
		out_be32(&immap->im_cpm.cp_cptr, cptr);
	}
#endif


	FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);	/* MII enable */
	/*
	 * adjust to duplex mode
	 */
	if (fep->phydev->duplex) {
		FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
		FS(fecp, x_cntrl, FEC_TCNTRL_FDEN);	/* FD enable */
	} else {
		FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
		FC(fecp, x_cntrl, FEC_TCNTRL_FDEN);	/* FD disable */
	}

	/*
	 * Enable interrupts we wish to service.
	 */
	FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
	   FEC_ENET_RXF | FEC_ENET_RXB);

	/*
	 * And last, enable the transmit and receive processing.
	 */
	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
	FW(fecp, r_des_active, 0x01000000);
}

static void stop(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	const struct fs_platform_info *fpi = fep->fpi;
	fec_t *fecp = fep->fec.fecp;

	struct fec_info* feci= fep->phydev->bus->priv;

	int i;

	if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
		return;		/* already down */

	FW(fecp, x_cntrl, 0x01);	/* Graceful transmit stop */
	for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
	     i < FEC_RESET_DELAY; i++)
		udelay(1);

	if (i == FEC_RESET_DELAY)
		printk(KERN_WARNING DRV_MODULE_NAME
		       ": %s FEC timeout on graceful transmit stop\n",
		       dev->name);
	/*
	 * Disable FEC. Let only MII interrupts.
	 */
	FW(fecp, imask, 0);
	FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);

	fs_cleanup_bds(dev);

	/* shut down FEC1? that's where the mii bus is */
	if (fpi->has_phy) {
		FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);	/* MII enable */
		FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
		FW(fecp, ievent, FEC_ENET_MII);
		FW(fecp, mii_speed, feci->mii_speed);
	}
}

static void pre_request_irq(struct net_device *dev, int irq)
{
#ifndef CONFIG_PPC_MERGE
	immap_t *immap = fs_enet_immap;
	u32 siel;

	/* SIU interrupt */
	if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {

		siel = in_be32(&immap->im_siu_conf.sc_siel);
		if ((irq & 1) == 0)
			siel |= (0x80000000 >> irq);
		else
			siel &= ~(0x80000000 >> (irq & ~1));
		out_be32(&immap->im_siu_conf.sc_siel, siel);
	}
#endif
}

static void post_free_irq(struct net_device *dev, int irq)
{
	/* nothing */
}

static void napi_clear_rx_event(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
}

static void napi_enable_rx(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
}

static void napi_disable_rx(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
}

static void rx_bd_done(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FW(fecp, r_des_active, 0x01000000);
}

static void tx_kickstart(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FW(fecp, x_des_active, 0x01000000);
}

static u32 get_int_events(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	return FR(fecp, ievent) & FR(fecp, imask);
}

static void clear_int_events(struct net_device *dev, u32 int_events)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fec_t *fecp = fep->fec.fecp;

	FW(fecp, ievent, int_events);
}

static void ev_error(struct net_device *dev, u32 int_events)
{
	printk(KERN_WARNING DRV_MODULE_NAME
	       ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
}

int get_regs(struct net_device *dev, void *p, int *sizep)
{
	struct fs_enet_private *fep = netdev_priv(dev);

	if (*sizep < sizeof(fec_t))
		return -EINVAL;

	memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));

	return 0;
}

int get_regs_len(struct net_device *dev)
{
	return sizeof(fec_t);
}

void tx_restart(struct net_device *dev)
{
	/* nothing */
}

/*************************************************************************/

const struct fs_ops fs_fec_ops = {
	.setup_data		= setup_data,
	.cleanup_data		= cleanup_data,
	.set_multicast_list	= set_multicast_list,
	.restart		= restart,
	.stop			= stop,
	.pre_request_irq	= pre_request_irq,
	.post_free_irq		= post_free_irq,
	.napi_clear_rx_event	= napi_clear_rx_event,
	.napi_enable_rx		= napi_enable_rx,
	.napi_disable_rx	= napi_disable_rx,
	.rx_bd_done		= rx_bd_done,
	.tx_kickstart		= tx_kickstart,
	.get_int_events		= get_int_events,
	.clear_int_events	= clear_int_events,
	.ev_error		= ev_error,
	.get_regs		= get_regs,
	.get_regs_len		= get_regs_len,
	.tx_restart		= tx_restart,
	.allocate_bd		= allocate_bd,
	.free_bd		= free_bd,
};
Commit	Line	Data
48257c4f PA	1	/*
	2	* Freescale Ethernet controllers
	3	*
9b8ee8e7	4	* Copyright (c) 2005 Intracom S.A.
48257c4f PA	5	* by Pantelis Antoniou <panto@intracom.gr>
48257c4f PA	6	*
9b8ee8e7	7	* 2005 (c) MontaVista Software, Inc.
48257c4f PA	8	* Vitaly Bordug <vbordug@ru.mvista.com>
48257c4f PA	9	*
9b8ee8e7 VB	10	* This file is licensed under the terms of the GNU General Public License
9b8ee8e7 VB	11	* version 2. This program is licensed "as is" without any warranty of any
48257c4f PA	12	* kind, whether express or implied.
	13	*/
	14
48257c4f PA	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/types.h>
48257c4f PA	18	#include <linux/string.h>
	19	#include <linux/ptrace.h>
	20	#include <linux/errno.h>
	21	#include <linux/ioport.h>
	22	#include <linux/slab.h>
	23	#include <linux/interrupt.h>
48257c4f PA	24	#include <linux/init.h>
	25	#include <linux/delay.h>
	26	#include <linux/netdevice.h>
	27	#include <linux/etherdevice.h>
	28	#include <linux/skbuff.h>
	29	#include <linux/spinlock.h>
	30	#include <linux/mii.h>
	31	#include <linux/ethtool.h>
	32	#include <linux/bitops.h>
	33	#include <linux/fs.h>
f7b99969	34	#include <linux/platform_device.h>
48257c4f PA	35
	36	#include <asm/irq.h>
	37	#include <asm/uaccess.h>
	38
	39	#ifdef CONFIG_8xx
	40	#include <asm/8xx_immap.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/mpc8xx.h>
	43	#include <asm/commproc.h>
	44	#endif
	45
976de6a8 SW	46	#ifdef CONFIG_PPC_CPM_NEW_BINDING
	47	#include <asm/of_device.h>
	48	#endif
	49
48257c4f	50	#include "fs_enet.h"
5b4b8454	51	#include "fec.h"
48257c4f PA	52
	53	/*************************************************/
	54
	55	#if defined(CONFIG_CPM1)
	56	/* for a CPM1 __raw_xxx's are sufficient */
	57	#define __fs_out32(addr, x) __raw_writel(x, addr)
	58	#define __fs_out16(addr, x) __raw_writew(x, addr)
	59	#define __fs_in32(addr) __raw_readl(addr)
	60	#define __fs_in16(addr) __raw_readw(addr)
	61	#else
	62	/* for others play it safe */
	63	#define __fs_out32(addr, x) out_be32(addr, x)
	64	#define __fs_out16(addr, x) out_be16(addr, x)
	65	#define __fs_in32(addr) in_be32(addr)
	66	#define __fs_in16(addr) in_be16(addr)
	67	#endif
	68
	69	/* write */
	70	#define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
	71
	72	/* read */
	73	#define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
	74
	75	/* set bits */
	76	#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) \| (_v))
	77
	78	/* clear bits */
	79	#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
	80
48257c4f	81	/*
5b4b8454	82	* Delay to wait for FEC reset command to complete (in us)
48257c4f PA	83	*/
	84	#define FEC_RESET_DELAY 50
	85
	86	static int whack_reset(fec_t * fecp)
	87	{
	88	int i;
	89
	90	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX \| FEC_ECNTRL_RESET);
	91	for (i = 0; i < FEC_RESET_DELAY; i++) {
	92	if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
	93	return 0; /* OK */
	94	udelay(1);
	95	}
	96
	97	return -1;
	98	}
	99
	100	static int do_pd_setup(struct fs_enet_private *fep)
	101	{
976de6a8 SW	102	#ifdef CONFIG_PPC_CPM_NEW_BINDING
	103	struct of_device *ofdev = to_of_device(fep->dev);
	104
	105	fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
	106	if (fep->interrupt == NO_IRQ)
	107	return -EINVAL;
	108
	109	fep->fec.fecp = of_iomap(ofdev->node, 0);
	110	if (!fep->fcc.fccp)
	111	return -EINVAL;
	112
	113	return 0;
	114	#else
9b8ee8e7	115	struct platform_device *pdev = to_platform_device(fep->dev);
48257c4f	116	struct resource *r;
9b8ee8e7	117
48257c4f PA	118	/* Fill out IRQ field */
48257c4f PA	119	fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
48944738 DV	120	if (fep->interrupt < 0)
48944738 DV	121	return -EINVAL;
b1f54ba3	122
48257c4f	123	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
b1f54ba3	124	fep->fec.fecp = ioremap(r->start, r->end - r->start + 1);
48257c4f PA	125
	126	if(fep->fec.fecp == NULL)
	127	return -EINVAL;
	128
	129	return 0;
976de6a8	130	#endif
48257c4f PA	131	}
	132
	133	#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF \| FEC_ENET_RXB)
	134	#define FEC_RX_EVENT (FEC_ENET_RXF)
	135	#define FEC_TX_EVENT (FEC_ENET_TXF)
	136	#define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR \| FEC_ENET_BABR \| \
	137	FEC_ENET_BABT \| FEC_ENET_EBERR)
	138
	139	static int setup_data(struct net_device *dev)
	140	{
	141	struct fs_enet_private *fep = netdev_priv(dev);
	142
	143	if (do_pd_setup(fep) != 0)
	144	return -EINVAL;
	145
	146	fep->fec.hthi = 0;
	147	fep->fec.htlo = 0;
	148
	149	fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
	150	fep->ev_rx = FEC_RX_EVENT;
	151	fep->ev_tx = FEC_TX_EVENT;
	152	fep->ev_err = FEC_ERR_EVENT_MSK;
	153
	154	return 0;
	155	}
	156
	157	static int allocate_bd(struct net_device *dev)
	158	{
	159	struct fs_enet_private *fep = netdev_priv(dev);
	160	const struct fs_platform_info *fpi = fep->fpi;
9b8ee8e7	161
48257c4f PA	162	fep->ring_base = dma_alloc_coherent(fep->dev,
	163	(fpi->tx_ring + fpi->rx_ring) *
	164	sizeof(cbd_t), &fep->ring_mem_addr,
	165	GFP_KERNEL);
	166	if (fep->ring_base == NULL)
	167	return -ENOMEM;
	168
	169	return 0;
	170	}
	171
	172	static void free_bd(struct net_device *dev)
	173	{
	174	struct fs_enet_private *fep = netdev_priv(dev);
	175	const struct fs_platform_info *fpi = fep->fpi;
	176
	177	if(fep->ring_base)
	178	dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
	179	* sizeof(cbd_t),
	180	fep->ring_base,
	181	fep->ring_mem_addr);
	182	}
	183
	184	static void cleanup_data(struct net_device *dev)
	185	{
	186	/* nothing */
	187	}
	188
	189	static void set_promiscuous_mode(struct net_device *dev)
	190	{
	191	struct fs_enet_private *fep = netdev_priv(dev);
	192	fec_t *fecp = fep->fec.fecp;
	193
	194	FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
	195	}
	196
	197	static void set_multicast_start(struct net_device *dev)
	198	{
	199	struct fs_enet_private *fep = netdev_priv(dev);
	200
	201	fep->fec.hthi = 0;
	202	fep->fec.htlo = 0;
	203	}
	204
	205	static void set_multicast_one(struct net_device dev, const u8 mac)
	206	{
	207	struct fs_enet_private *fep = netdev_priv(dev);
	208	int temp, hash_index, i, j;
	209	u32 crc, csrVal;
	210	u8 byte, msb;
	211
	212	crc = 0xffffffff;
	213	for (i = 0; i < 6; i++) {
	214	byte = mac[i];
	215	for (j = 0; j < 8; j++) {
	216	msb = crc >> 31;
	217	crc <<= 1;
	218	if (msb ^ (byte & 0x1))
	219	crc ^= FEC_CRC_POLY;
	220	byte >>= 1;
	221	}
	222	}
	223
	224	temp = (crc & 0x3f) >> 1;
	225	hash_index = ((temp & 0x01) << 4) \|
226	((temp & 0x02) << 2) \|
227	((temp & 0x04)) \|
228	((temp & 0x08) >> 2) \|
229	((temp & 0x10) >> 4);
230	csrVal = 1 << hash_index;
231	if (crc & 1)
232	fep->fec.hthi \|= csrVal;
233	else
234	fep->fec.htlo \|= csrVal;
235	}
236
237	static void set_multicast_finish(struct net_device *dev)
238	{
239	struct fs_enet_private *fep = netdev_priv(dev);
240	fec_t *fecp = fep->fec.fecp;
241
242	/* if all multi or too many multicasts; just enable all */
243	if ((dev->flags & IFF_ALLMULTI) != 0 \|\|
244	dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
245	fep->fec.hthi = 0xffffffffU;
246	fep->fec.htlo = 0xffffffffU;
247	}
248
249	FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
250	FW(fecp, hash_table_high, fep->fec.hthi);
251	FW(fecp, hash_table_low, fep->fec.htlo);
252	}
253
254	static void set_multicast_list(struct net_device *dev)
255	{
256	struct dev_mc_list *pmc;
257
258	if ((dev->flags & IFF_PROMISC) == 0) {
259	set_multicast_start(dev);
260	for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
261	set_multicast_one(dev, pmc->dmi_addr);
262	set_multicast_finish(dev);
263	} else
264	set_promiscuous_mode(dev);
265	}
266
267	static void restart(struct net_device *dev)
268	{
269	#ifdef CONFIG_DUET
270	immap_t *immap = fs_enet_immap;
271	u32 cptr;
272	#endif
273	struct fs_enet_private *fep = netdev_priv(dev);
274	fec_t *fecp = fep->fec.fecp;
275	const struct fs_platform_info *fpi = fep->fpi;
276	dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
277	int r;
278	u32 addrhi, addrlo;
279
5b4b8454 VB	280	struct mii_bus* mii = fep->phydev->bus;
	281	struct fec_info* fec_inf = mii->priv;
	282
48257c4f PA	283	r = whack_reset(fep->fec.fecp);
	284	if (r != 0)
	285	printk(KERN_ERR DRV_MODULE_NAME
	286	": %s FEC Reset FAILED!\n", dev->name);
48257c4f	287	/*
5b4b8454	288	* Set station address.
48257c4f PA	289	*/
	290	addrhi = ((u32) dev->dev_addr[0] << 24) \|
	291	((u32) dev->dev_addr[1] << 16) \|
	292	((u32) dev->dev_addr[2] << 8) \|
	293	(u32) dev->dev_addr[3];
	294	addrlo = ((u32) dev->dev_addr[4] << 24) \|
	295	((u32) dev->dev_addr[5] << 16);
	296	FW(fecp, addr_low, addrhi);
	297	FW(fecp, addr_high, addrlo);
	298
	299	/*
9b8ee8e7	300	* Reset all multicast.
48257c4f PA	301	*/
	302	FW(fecp, hash_table_high, fep->fec.hthi);
	303	FW(fecp, hash_table_low, fep->fec.htlo);
	304
	305	/*
9b8ee8e7	306	* Set maximum receive buffer size.
48257c4f PA	307	*/
	308	FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
	309	FW(fecp, r_hash, PKT_MAXBUF_SIZE);
	310
	311	/* get physical address */
	312	rx_bd_base_phys = fep->ring_mem_addr;
	313	tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
	314
	315	/*
9b8ee8e7	316	* Set receive and transmit descriptor base.
48257c4f PA	317	*/
	318	FW(fecp, r_des_start, rx_bd_base_phys);
	319	FW(fecp, x_des_start, tx_bd_base_phys);
	320
	321	fs_init_bds(dev);
	322
	323	/*
9b8ee8e7	324	* Enable big endian and don't care about SDMA FC.
48257c4f PA	325	*/
	326	FW(fecp, fun_code, 0x78000000);
	327
	328	/*
5b4b8454	329	* Set MII speed.
48257c4f	330	*/
5b4b8454	331	FW(fecp, mii_speed, fec_inf->mii_speed);
48257c4f PA	332
48257c4f PA	333	/*
5b4b8454	334	* Clear any outstanding interrupt.
48257c4f PA	335	*/
48257c4f PA	336	FW(fecp, ievent, 0xffc0);
b1f54ba3	337	#ifndef CONFIG_PPC_MERGE
48257c4f	338	FW(fecp, ivec, (fep->interrupt / 2) << 29);
b1f54ba3 VB	339	#else
	340	FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
	341	#endif
48257c4f PA	342
48257c4f PA	343	/*
b1f54ba3	344	* adjust to speed (only for DUET & RMII)
48257c4f PA	345	*/
	346	#ifdef CONFIG_DUET
	347	if (fpi->use_rmii) {
	348	cptr = in_be32(&immap->im_cpm.cp_cptr);
	349	switch (fs_get_fec_index(fpi->fs_no)) {
	350	case 0:
	351	cptr \|= 0x100;
	352	if (fep->speed == 10)
	353	cptr \|= 0x0000010;
	354	else if (fep->speed == 100)
	355	cptr &= ~0x0000010;
	356	break;
	357	case 1:
	358	cptr \|= 0x80;
	359	if (fep->speed == 10)
	360	cptr \|= 0x0000008;
	361	else if (fep->speed == 100)
	362	cptr &= ~0x0000008;
	363	break;
	364	default:
	365	BUG(); /* should never happen */
	366	break;
	367	}
	368	out_be32(&immap->im_cpm.cp_cptr, cptr);
	369	}
	370	#endif
	371
5b4b8454	372
48257c4f PA	373	FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
48257c4f PA	374	/*
5b4b8454	375	* adjust to duplex mode
48257c4f	376	*/
5b4b8454	377	if (fep->phydev->duplex) {
48257c4f PA	378	FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
	379	FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
	380	} else {
	381	FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
	382	FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
	383	}
	384
	385	/*
9b8ee8e7	386	* Enable interrupts we wish to service.
48257c4f PA	387	*/
	388	FW(fecp, imask, FEC_ENET_TXF \| FEC_ENET_TXB \|
	389	FEC_ENET_RXF \| FEC_ENET_RXB);
	390
	391	/*
9b8ee8e7	392	* And last, enable the transmit and receive processing.
48257c4f PA	393	*/
	394	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX \| FEC_ECNTRL_ETHER_EN);
	395	FW(fecp, r_des_active, 0x01000000);
	396	}
	397
	398	static void stop(struct net_device *dev)
	399	{
	400	struct fs_enet_private *fep = netdev_priv(dev);
5b4b8454	401	const struct fs_platform_info *fpi = fep->fpi;
48257c4f	402	fec_t *fecp = fep->fec.fecp;
5b4b8454 VB	403
	404	struct fec_info* feci= fep->phydev->bus->priv;
	405
48257c4f PA	406	int i;
	407
	408	if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
	409	return; /* already down */
	410
	411	FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
	412	for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
	413	i < FEC_RESET_DELAY; i++)
	414	udelay(1);
	415
	416	if (i == FEC_RESET_DELAY)
	417	printk(KERN_WARNING DRV_MODULE_NAME
	418	": %s FEC timeout on graceful transmit stop\n",
	419	dev->name);
	420	/*
9b8ee8e7	421	* Disable FEC. Let only MII interrupts.
48257c4f PA	422	*/
	423	FW(fecp, imask, 0);
	424	FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
	425
	426	fs_cleanup_bds(dev);
	427
	428	/* shut down FEC1? that's where the mii bus is */
5b4b8454	429	if (fpi->has_phy) {
48257c4f PA	430	FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
	431	FS(fecp, ecntrl, FEC_ECNTRL_PINMUX \| FEC_ECNTRL_ETHER_EN);
	432	FW(fecp, ievent, FEC_ENET_MII);
5b4b8454	433	FW(fecp, mii_speed, feci->mii_speed);
48257c4f PA	434	}
	435	}
	436
	437	static void pre_request_irq(struct net_device *dev, int irq)
	438	{
b1f54ba3	439	#ifndef CONFIG_PPC_MERGE
48257c4f PA	440	immap_t *immap = fs_enet_immap;
	441	u32 siel;
	442
	443	/* SIU interrupt */
	444	if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
	445
	446	siel = in_be32(&immap->im_siu_conf.sc_siel);
	447	if ((irq & 1) == 0)
	448	siel \|= (0x80000000 >> irq);
	449	else
	450	siel &= ~(0x80000000 >> (irq & ~1));
	451	out_be32(&immap->im_siu_conf.sc_siel, siel);
	452	}
b1f54ba3	453	#endif
48257c4f PA	454	}
	455
	456	static void post_free_irq(struct net_device *dev, int irq)
	457	{
	458	/* nothing */
	459	}
	460
	461	static void napi_clear_rx_event(struct net_device *dev)
	462	{
	463	struct fs_enet_private *fep = netdev_priv(dev);
	464	fec_t *fecp = fep->fec.fecp;
	465
	466	FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
	467	}
	468
	469	static void napi_enable_rx(struct net_device *dev)
	470	{
	471	struct fs_enet_private *fep = netdev_priv(dev);
	472	fec_t *fecp = fep->fec.fecp;
	473
	474	FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
	475	}
	476
	477	static void napi_disable_rx(struct net_device *dev)
	478	{
	479	struct fs_enet_private *fep = netdev_priv(dev);
	480	fec_t *fecp = fep->fec.fecp;
	481
	482	FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
	483	}
	484
	485	static void rx_bd_done(struct net_device *dev)
	486	{
	487	struct fs_enet_private *fep = netdev_priv(dev);
	488	fec_t *fecp = fep->fec.fecp;
	489
	490	FW(fecp, r_des_active, 0x01000000);
	491	}
	492
	493	static void tx_kickstart(struct net_device *dev)
	494	{
	495	struct fs_enet_private *fep = netdev_priv(dev);
	496	fec_t *fecp = fep->fec.fecp;
	497
	498	FW(fecp, x_des_active, 0x01000000);
	499	}
	500
	501	static u32 get_int_events(struct net_device *dev)
	502	{
	503	struct fs_enet_private *fep = netdev_priv(dev);
	504	fec_t *fecp = fep->fec.fecp;
	505
	506	return FR(fecp, ievent) & FR(fecp, imask);
	507	}
	508
	509	static void clear_int_events(struct net_device *dev, u32 int_events)
	510	{
	511	struct fs_enet_private *fep = netdev_priv(dev);
	512	fec_t *fecp = fep->fec.fecp;
	513
	514	FW(fecp, ievent, int_events);
	515	}
	516
	517	static void ev_error(struct net_device *dev, u32 int_events)
518	{
519	printk(KERN_WARNING DRV_MODULE_NAME
520	": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
521	}
522
523	int get_regs(struct net_device dev, void p, int *sizep)
524	{
525	struct fs_enet_private *fep = netdev_priv(dev);
526
527	if (*sizep < sizeof(fec_t))
528	return -EINVAL;
529
530	memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
531
532	return 0;
533	}
534
535	int get_regs_len(struct net_device *dev)
536	{
537	return sizeof(fec_t);
538	}
539
540	void tx_restart(struct net_device *dev)
541	{
542	/* nothing */
543	}
544
545	/*************************************************************************/
546
547	const struct fs_ops fs_fec_ops = {
548	.setup_data = setup_data,
549	.cleanup_data = cleanup_data,
550	.set_multicast_list = set_multicast_list,
551	.restart = restart,
552	.stop = stop,
553	.pre_request_irq = pre_request_irq,
554	.post_free_irq = post_free_irq,
555	.napi_clear_rx_event = napi_clear_rx_event,
556	.napi_enable_rx = napi_enable_rx,
557	.napi_disable_rx = napi_disable_rx,
558	.rx_bd_done = rx_bd_done,
559	.tx_kickstart = tx_kickstart,
560	.get_int_events = get_int_events,
561	.clear_int_events = clear_int_events,
562	.ev_error = ev_error,
563	.get_regs = get_regs,
564	.get_regs_len = get_regs_len,
565	.tx_restart = tx_restart,
566	.allocate_bd = allocate_bd,
567	.free_bd = free_bd,
568	};
569