[deliverable/linux.git] / drivers / net / fs_enet / mii-fec.c

/*
 * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
 *
 * Copyright (c) 2003 Intracom S.A.
 *  by Pantelis Antoniou <panto@intracom.gr>
 *
 * 2005 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>

#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mpc5xxx.h>

#include "fs_enet.h"
#include "fec.h"

/* Make MII read/write commands for the FEC.
*/
#define mk_mii_read(REG)	(0x60020000 | ((REG & 0x1f) << 18))
#define mk_mii_write(REG, VAL)	(0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
#define mk_mii_end		0

#define FEC_MII_LOOPS	10000

static int fs_enet_fec_mii_read(struct mii_bus *bus , int phy_id, int location)
{
	struct fec_info* fec = bus->priv;
	struct fec __iomem *fecp = fec->fecp;
	int i, ret = -1;

	BUG_ON((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0);

	/* Add PHY address to register command.  */
	out_be32(&fecp->fec_mii_data, (phy_id << 23) | mk_mii_read(location));

	for (i = 0; i < FEC_MII_LOOPS; i++)
		if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0)
			break;

	if (i < FEC_MII_LOOPS) {
		out_be32(&fecp->fec_ievent, FEC_ENET_MII);
		ret = in_be32(&fecp->fec_mii_data) & 0xffff;
	}

	return ret;
}

static int fs_enet_fec_mii_write(struct mii_bus *bus, int phy_id, int location, u16 val)
{
	struct fec_info* fec = bus->priv;
	struct fec __iomem *fecp = fec->fecp;
	int i;

	/* this must never happen */
	BUG_ON((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0);

	/* Add PHY address to register command.  */
	out_be32(&fecp->fec_mii_data, (phy_id << 23) | mk_mii_write(location, val));

	for (i = 0; i < FEC_MII_LOOPS; i++)
		if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0)
			break;

	if (i < FEC_MII_LOOPS)
		out_be32(&fecp->fec_ievent, FEC_ENET_MII);

	return 0;

}

static int fs_enet_fec_mii_reset(struct mii_bus *bus)
{
	/* nothing here - for now */
	return 0;
}

static int __devinit fs_enet_mdio_probe(struct platform_device *ofdev)
{
	struct resource res;
	struct mii_bus *new_bus;
	struct fec_info *fec;
	int (*get_bus_freq)(struct device_node *);
	int ret = -ENOMEM, clock, speed;

	if (!ofdev->dev.of_match)
		return -EINVAL;
	get_bus_freq = ofdev->dev.of_match->data;

	new_bus = mdiobus_alloc();
	if (!new_bus)
		goto out;

	fec = kzalloc(sizeof(struct fec_info), GFP_KERNEL);
	if (!fec)
		goto out_mii;

	new_bus->priv = fec;
	new_bus->name = "FEC MII Bus";
	new_bus->read = &fs_enet_fec_mii_read;
	new_bus->write = &fs_enet_fec_mii_write;
	new_bus->reset = &fs_enet_fec_mii_reset;

	ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
	if (ret)
		goto out_res;

	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);

	fec->fecp = ioremap(res.start, res.end - res.start + 1);
	if (!fec->fecp)
		goto out_fec;

	if (get_bus_freq) {
		clock = get_bus_freq(ofdev->dev.of_node);
		if (!clock) {
			/* Use maximum divider if clock is unknown */
			dev_warn(&ofdev->dev, "could not determine IPS clock\n");
			clock = 0x3F * 5000000;
		}
	} else
		clock = ppc_proc_freq;

	/*
	 * Scale for a MII clock <= 2.5 MHz
	 * Note that only 6 bits (25:30) are available for MII speed.
	 */
	speed = (clock + 4999999) / 5000000;
	if (speed > 0x3F) {
		speed = 0x3F;
		dev_err(&ofdev->dev,
			"MII clock (%d Hz) exceeds max (2.5 MHz)\n",
			clock / speed);
	}

	fec->mii_speed = speed << 1;

	setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
	setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX |
	                                  FEC_ECNTRL_ETHER_EN);
	out_be32(&fec->fecp->fec_ievent, FEC_ENET_MII);
	clrsetbits_be32(&fec->fecp->fec_mii_speed, 0x7E, fec->mii_speed);

	new_bus->phy_mask = ~0;
	new_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
	if (!new_bus->irq)
		goto out_unmap_regs;

	new_bus->parent = &ofdev->dev;
	dev_set_drvdata(&ofdev->dev, new_bus);

	ret = of_mdiobus_register(new_bus, ofdev->dev.of_node);
	if (ret)
		goto out_free_irqs;

	return 0;

out_free_irqs:
	dev_set_drvdata(&ofdev->dev, NULL);
	kfree(new_bus->irq);
out_unmap_regs:
	iounmap(fec->fecp);
out_res:
out_fec:
	kfree(fec);
out_mii:
	mdiobus_free(new_bus);
out:
	return ret;
}

static int fs_enet_mdio_remove(struct platform_device *ofdev)
{
	struct mii_bus *bus = dev_get_drvdata(&ofdev->dev);
	struct fec_info *fec = bus->priv;

	mdiobus_unregister(bus);
	dev_set_drvdata(&ofdev->dev, NULL);
	kfree(bus->irq);
	iounmap(fec->fecp);
	kfree(fec);
	mdiobus_free(bus);

	return 0;
}

static struct of_device_id fs_enet_mdio_fec_match[] = {
	{
		.compatible = "fsl,pq1-fec-mdio",
	},
#if defined(CONFIG_PPC_MPC512x)
	{
		.compatible = "fsl,mpc5121-fec-mdio",
		.data = mpc5xxx_get_bus_frequency,
	},
#endif
	{},
};
MODULE_DEVICE_TABLE(of, fs_enet_mdio_fec_match);

static struct platform_driver fs_enet_fec_mdio_driver = {
	.driver = {
		.name = "fsl-fec-mdio",
		.owner = THIS_MODULE,
		.of_match_table = fs_enet_mdio_fec_match,
	},
	.probe = fs_enet_mdio_probe,
	.remove = fs_enet_mdio_remove,
};

static int fs_enet_mdio_fec_init(void)
{
	return platform_driver_register(&fs_enet_fec_mdio_driver);
}

static void fs_enet_mdio_fec_exit(void)
{
	platform_driver_unregister(&fs_enet_fec_mdio_driver);
}

module_init(fs_enet_mdio_fec_init);
module_exit(fs_enet_mdio_fec_exit);
Commit	Line	Data
5b4b8454 VB	1	/*
	2	* Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
	3	*
	4	* Copyright (c) 2003 Intracom S.A.
	5	* by Pantelis Antoniou <panto@intracom.gr>
	6	*
	7	* 2005 (c) MontaVista Software, Inc.
	8	* Vitaly Bordug <vbordug@ru.mvista.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public License
	11	* version 2. This program is licensed "as is" without any warranty of any
	12	* kind, whether express or implied.
	13	*/
	14
5b4b8454 VB	15	#include <linux/module.h>
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
5b4b8454 VB	18	#include <linux/string.h>
	19	#include <linux/ptrace.h>
	20	#include <linux/errno.h>
	21	#include <linux/ioport.h>
	22	#include <linux/slab.h>
	23	#include <linux/interrupt.h>
5b4b8454 VB	24	#include <linux/init.h>
	25	#include <linux/delay.h>
	26	#include <linux/netdevice.h>
	27	#include <linux/etherdevice.h>
	28	#include <linux/skbuff.h>
	29	#include <linux/spinlock.h>
	30	#include <linux/mii.h>
	31	#include <linux/ethtool.h>
	32	#include <linux/bitops.h>
	33	#include <linux/platform_device.h>
b219108c	34	#include <linux/of_platform.h>
5b4b8454 VB	35
	36	#include <asm/pgtable.h>
	37	#include <asm/irq.h>
	38	#include <asm/uaccess.h>
652f6787	39	#include <asm/mpc5xxx.h>
5b4b8454 VB	40
	41	#include "fs_enet.h"
	42	#include "fec.h"
	43
	44	/* Make MII read/write commands for the FEC.
	45	*/
	46	#define mk_mii_read(REG) (0x60020000 \| ((REG & 0x1f) << 18))
	47	#define mk_mii_write(REG, VAL) (0x50020000 \| ((REG & 0x1f) << 18) \| (VAL & 0xffff))
	48	#define mk_mii_end 0
	49
	50	#define FEC_MII_LOOPS 10000
	51
5b4b8454 VB	52	static int fs_enet_fec_mii_read(struct mii_bus *bus , int phy_id, int location)
	53	{
	54	struct fec_info* fec = bus->priv;
60ab4361	55	struct fec __iomem *fecp = fec->fecp;
5b4b8454 VB	56	int i, ret = -1;
5b4b8454 VB	57
0ee904c3	58	BUG_ON((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0);
5b4b8454 VB	59
	60	/* Add PHY address to register command. */
	61	out_be32(&fecp->fec_mii_data, (phy_id << 23) \| mk_mii_read(location));
	62
	63	for (i = 0; i < FEC_MII_LOOPS; i++)
	64	if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0)
	65	break;
	66
	67	if (i < FEC_MII_LOOPS) {
	68	out_be32(&fecp->fec_ievent, FEC_ENET_MII);
	69	ret = in_be32(&fecp->fec_mii_data) & 0xffff;
	70	}
	71
	72	return ret;
5b4b8454 VB	73	}
	74
	75	static int fs_enet_fec_mii_write(struct mii_bus *bus, int phy_id, int location, u16 val)
	76	{
	77	struct fec_info* fec = bus->priv;
60ab4361	78	struct fec __iomem *fecp = fec->fecp;
5b4b8454 VB	79	int i;
	80
	81	/* this must never happen */
0ee904c3	82	BUG_ON((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0);
5b4b8454 VB	83
	84	/* Add PHY address to register command. */
	85	out_be32(&fecp->fec_mii_data, (phy_id << 23) \| mk_mii_write(location, val));
	86
	87	for (i = 0; i < FEC_MII_LOOPS; i++)
	88	if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0)
	89	break;
	90
	91	if (i < FEC_MII_LOOPS)
	92	out_be32(&fecp->fec_ievent, FEC_ENET_MII);
	93
	94	return 0;
	95
	96	}
	97
	98	static int fs_enet_fec_mii_reset(struct mii_bus *bus)
	99	{
	100	/* nothing here - for now */
	101	return 0;
	102	}
	103
74888760	104	static int __devinit fs_enet_mdio_probe(struct platform_device *ofdev)
976de6a8	105	{
976de6a8 SW	106	struct resource res;
	107	struct mii_bus *new_bus;
	108	struct fec_info *fec;
74888760	109	int (get_bus_freq)(struct device_node );
652f6787	110	int ret = -ENOMEM, clock, speed;
976de6a8	111
74888760 GL	112	if (!ofdev->dev.of_match)
	113	return -EINVAL;
	114	get_bus_freq = ofdev->dev.of_match->data;
	115
298cf9be	116	new_bus = mdiobus_alloc();
976de6a8 SW	117	if (!new_bus)
	118	goto out;
	119
	120	fec = kzalloc(sizeof(struct fec_info), GFP_KERNEL);
	121	if (!fec)
	122	goto out_mii;
	123
	124	new_bus->priv = fec;
	125	new_bus->name = "FEC MII Bus";
	126	new_bus->read = &fs_enet_fec_mii_read;
	127	new_bus->write = &fs_enet_fec_mii_write;
	128	new_bus->reset = &fs_enet_fec_mii_reset;
	129
61c7a080	130	ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
976de6a8	131	if (ret)
a86e2cbe	132	goto out_res;
976de6a8	133
9d9326d3	134	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
976de6a8 SW	135
	136	fec->fecp = ioremap(res.start, res.end - res.start + 1);
	137	if (!fec->fecp)
	138	goto out_fec;
	139
652f6787	140	if (get_bus_freq) {
61c7a080	141	clock = get_bus_freq(ofdev->dev.of_node);
652f6787 WD	142	if (!clock) {
	143	/* Use maximum divider if clock is unknown */
	144	dev_warn(&ofdev->dev, "could not determine IPS clock\n");
	145	clock = 0x3F * 5000000;
	146	}
	147	} else
	148	clock = ppc_proc_freq;
	149
	150	/*
	151	* Scale for a MII clock <= 2.5 MHz
	152	* Note that only 6 bits (25:30) are available for MII speed.
	153	*/
	154	speed = (clock + 4999999) / 5000000;
	155	if (speed > 0x3F) {
	156	speed = 0x3F;
	157	dev_err(&ofdev->dev,
	158	"MII clock (%d Hz) exceeds max (2.5 MHz)\n",
	159	clock / speed);
	160	}
	161
	162	fec->mii_speed = speed << 1;
976de6a8 SW	163
	164	setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
	165	setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX \|
	166	FEC_ECNTRL_ETHER_EN);
	167	out_be32(&fec->fecp->fec_ievent, FEC_ENET_MII);
652f6787	168	clrsetbits_be32(&fec->fecp->fec_mii_speed, 0x7E, fec->mii_speed);
976de6a8 SW	169
	170	new_bus->phy_mask = ~0;
	171	new_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
	172	if (!new_bus->irq)
	173	goto out_unmap_regs;
	174
18ee49dd	175	new_bus->parent = &ofdev->dev;
976de6a8 SW	176	dev_set_drvdata(&ofdev->dev, new_bus);
976de6a8 SW	177
61c7a080	178	ret = of_mdiobus_register(new_bus, ofdev->dev.of_node);
976de6a8 SW	179	if (ret)
	180	goto out_free_irqs;
	181
	182	return 0;
	183
	184	out_free_irqs:
	185	dev_set_drvdata(&ofdev->dev, NULL);
	186	kfree(new_bus->irq);
	187	out_unmap_regs:
	188	iounmap(fec->fecp);
a86e2cbe	189	out_res:
976de6a8 SW	190	out_fec:
	191	kfree(fec);
	192	out_mii:
298cf9be	193	mdiobus_free(new_bus);
976de6a8 SW	194	out:
	195	return ret;
	196	}
	197
2dc11581	198	static int fs_enet_mdio_remove(struct platform_device *ofdev)
976de6a8 SW	199	{
	200	struct mii_bus *bus = dev_get_drvdata(&ofdev->dev);
	201	struct fec_info *fec = bus->priv;
	202
	203	mdiobus_unregister(bus);
	204	dev_set_drvdata(&ofdev->dev, NULL);
	205	kfree(bus->irq);
	206	iounmap(fec->fecp);
	207	kfree(fec);
298cf9be	208	mdiobus_free(bus);
976de6a8 SW	209
	210	return 0;
	211	}
	212
	213	static struct of_device_id fs_enet_mdio_fec_match[] = {
	214	{
	215	.compatible = "fsl,pq1-fec-mdio",
	216	},
652f6787 WD	217	#if defined(CONFIG_PPC_MPC512x)
	218	{
	219	.compatible = "fsl,mpc5121-fec-mdio",
	220	.data = mpc5xxx_get_bus_frequency,
	221	},
	222	#endif
976de6a8 SW	223	{},
976de6a8 SW	224	};
e72701ac	225	MODULE_DEVICE_TABLE(of, fs_enet_mdio_fec_match);
976de6a8	226
74888760	227	static struct platform_driver fs_enet_fec_mdio_driver = {
4018294b GL	228	.driver = {
	229	.name = "fsl-fec-mdio",
	230	.owner = THIS_MODULE,
	231	.of_match_table = fs_enet_mdio_fec_match,
	232	},
976de6a8 SW	233	.probe = fs_enet_mdio_probe,
	234	.remove = fs_enet_mdio_remove,
	235	};
	236
	237	static int fs_enet_mdio_fec_init(void)
	238	{
74888760	239	return platform_driver_register(&fs_enet_fec_mdio_driver);
976de6a8 SW	240	}
	241
	242	static void fs_enet_mdio_fec_exit(void)
	243	{
74888760	244	platform_driver_unregister(&fs_enet_fec_mdio_driver);
976de6a8 SW	245	}
	246
	247	module_init(fs_enet_mdio_fec_init);
	248	module_exit(fs_enet_mdio_fec_exit);